Add phy subsystem support for the xilinx-nwl PCIe controller. This
series also includes several small fixes and improvements.
Sean Anderson (7):
dt-bindings: pci: xilinx-nwl: Add phys
PCI: xilinx-nwl: Fix off-by-one
PCI: xilinx-nwl: Fix register misspelling
PCI: xilinx-nwl: Rate-limit misc interrupt messages
PCI: xilinx-nwl: Clean up clock on probe failure/removal
PCI: xilinx-nwl: Add phy support
[RFT] arm64: zynqmp: Add PCIe phys
.../bindings/pci/xlnx,nwl-pcie.yaml | 8 ++
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +
drivers/pci/controller/pcie-xilinx-nwl.c | 124 ++++++++++++++----
3 files changed, 111 insertions(+), 23 deletions(-)
--
2.35.1.1320.gc452695387.dirty
Add phys properties so Linux can power-on/configure the GTR
transcievers.
Signed-off-by: Sean Anderson <[email protected]>
---
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
index 426f90a47f35..02315669b831 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
@@ -61,6 +61,14 @@ properties:
interrupt-map:
maxItems: 4
+ phys:
+ maxItems: 4
+
+ phy-names:
+ maxItems: 4
+ items:
+ - pattern: '^pcie-phy[0-3]$'
+
power-domains:
maxItems: 1
--
2.35.1.1320.gc452695387.dirty
MSIC -> MISC
Fixes: c2a7ff18edcd ("PCI: xilinx-nwl: Expand error logging")
Signed-off-by: Sean Anderson <[email protected]>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 437927e3bcca..ce881baac6d8 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -80,8 +80,8 @@
#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
#define MSGF_MISC_SR_FATAL_DEV BIT(23)
#define MSGF_MISC_SR_LINK_DOWN BIT(24)
-#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
-#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
+#define MSGF_MISC_SR_LINK_AUTO_BWIDTH BIT(25)
+#define MSGF_MISC_SR_LINK_BWIDTH BIT(26)
#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
MSGF_MISC_SR_RXMSG_OVER | \
@@ -96,8 +96,8 @@
MSGF_MISC_SR_NON_FATAL_DEV | \
MSGF_MISC_SR_FATAL_DEV | \
MSGF_MISC_SR_LINK_DOWN | \
- MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
- MSGF_MSIC_SR_LINK_BWIDTH)
+ MSGF_MISC_SR_LINK_AUTO_BWIDTH | \
+ MSGF_MISC_SR_LINK_BWIDTH)
/* Legacy interrupt status mask bits */
#define MSGF_LEG_SR_INTA BIT(0)
@@ -299,10 +299,10 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
dev_err(dev, "Fatal Error Detected\n");
- if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
+ if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH)
dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
- if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
+ if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH)
dev_info(dev, "Link Bandwidth Management Status bit set\n");
/* Clear misc interrupt status */
--
2.35.1.1320.gc452695387.dirty
The conditions logged by the misc interrupt can occur repeatedly and
continuously. Avoid rendering the console unusable by rate-limiting
these messages.
Signed-off-by: Sean Anderson <[email protected]>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index ce881baac6d8..c0a60cebdb2e 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -267,37 +267,37 @@ static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
return IRQ_NONE;
if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
- dev_err(dev, "Received Message FIFO Overflow\n");
+ dev_err_ratelimited(dev, "Received Message FIFO Overflow\n");
if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
- dev_err(dev, "Slave error\n");
+ dev_err_ratelimited(dev, "Slave error\n");
if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
- dev_err(dev, "Master error\n");
+ dev_err_ratelimited(dev, "Master error\n");
if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
- dev_err(dev, "In Misc Ingress address translation error\n");
+ dev_err_ratelimited(dev, "In Misc Ingress address translation error\n");
if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
- dev_err(dev, "In Misc Egress address translation error\n");
+ dev_err_ratelimited(dev, "In Misc Egress address translation error\n");
if (misc_stat & MSGF_MISC_SR_FATAL_AER)
- dev_err(dev, "Fatal Error in AER Capability\n");
+ dev_err_ratelimited(dev, "Fatal Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
- dev_err(dev, "Non-Fatal Error in AER Capability\n");
+ dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_CORR_AER)
- dev_err(dev, "Correctable Error in AER Capability\n");
+ dev_err_ratelimited(dev, "Correctable Error in AER Capability\n");
if (misc_stat & MSGF_MISC_SR_UR_DETECT)
- dev_err(dev, "Unsupported request Detected\n");
+ dev_err_ratelimited(dev, "Unsupported request Detected\n");
if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
- dev_err(dev, "Non-Fatal Error Detected\n");
+ dev_err_ratelimited(dev, "Non-Fatal Error Detected\n");
if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
- dev_err(dev, "Fatal Error Detected\n");
+ dev_err_ratelimited(dev, "Fatal Error Detected\n");
if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH)
dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
--
2.35.1.1320.gc452695387.dirty
Make sure we turn off the clock on probe failure and device removal.
Fixes: de0a01f52966 ("PCI: xilinx-nwl: Enable the clock through CCF")
Signed-off-by: Sean Anderson <[email protected]>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index c0a60cebdb2e..424cc5a1b4d1 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -779,6 +779,7 @@ static int nwl_pcie_probe(struct platform_device *pdev)
return -ENODEV;
pcie = pci_host_bridge_priv(bridge);
+ platform_set_drvdata(pdev, pcie);
pcie->dev = dev;
@@ -801,13 +802,13 @@ static int nwl_pcie_probe(struct platform_device *pdev)
err = nwl_pcie_bridge_init(pcie);
if (err) {
dev_err(dev, "HW Initialization failed\n");
- return err;
+ goto err_clk;
}
err = nwl_pcie_init_irq_domain(pcie);
if (err) {
dev_err(dev, "Failed creating IRQ Domain\n");
- return err;
+ goto err_clk;
}
bridge->sysdata = pcie;
@@ -817,11 +818,23 @@ static int nwl_pcie_probe(struct platform_device *pdev)
err = nwl_pcie_enable_msi(pcie);
if (err < 0) {
dev_err(dev, "failed to enable MSI support: %d\n", err);
- return err;
+ goto err_clk;
}
}
- return pci_host_probe(bridge);
+ err = pci_host_probe(bridge);
+
+err_clk:
+ if (err)
+ clk_disable_unprepare(pcie->clk);
+ return err;
+}
+
+static void nwl_pcie_remove(struct platform_device *pdev)
+{
+ struct nwl_pcie *pcie = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(pcie->clk);
}
static struct platform_driver nwl_pcie_driver = {
@@ -831,5 +844,6 @@ static struct platform_driver nwl_pcie_driver = {
.of_match_table = nwl_pcie_of_match,
},
.probe = nwl_pcie_probe,
+ .remove_new = nwl_pcie_remove,
};
builtin_platform_driver(nwl_pcie_driver);
--
2.35.1.1320.gc452695387.dirty
Add support for enabling/disabling PCIe phys. We can't really do
anything about failures in the disable/remove path, so just warn.
Signed-off-by: Sean Anderson <[email protected]>
---
drivers/pci/controller/pcie-xilinx-nwl.c | 70 +++++++++++++++++++++++-
1 file changed, 67 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 424cc5a1b4d1..19a0ff105401 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -19,6 +19,7 @@
#include <linux/of_platform.h>
#include <linux/pci.h>
#include <linux/pci-ecam.h>
+#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/irqchip/chained_irq.h>
@@ -157,6 +158,7 @@ struct nwl_pcie {
void __iomem *breg_base;
void __iomem *pcireg_base;
void __iomem *ecam_base;
+ struct phy *phy[4];
phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
phys_addr_t phys_ecam_base; /* Physical Configuration Base */
@@ -521,6 +523,43 @@ static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
return 0;
}
+static int nwl_pcie_phy_enable(struct nwl_pcie *pcie)
+{
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
+ ret = phy_init(pcie->phy[i]);
+ if (ret)
+ goto err;
+
+ ret = phy_power_on(pcie->phy[i]);
+ if (ret) {
+ WARN_ON(phy_exit(pcie->phy[i]));
+ goto err;
+ }
+ }
+
+ return 0;
+
+err:
+ while (--i) {
+ WARN_ON(phy_power_off(pcie->phy[i]));
+ WARN_ON(phy_exit(pcie->phy[i]));
+ }
+
+ return ret;
+}
+
+static void nwl_pcie_phy_disable(struct nwl_pcie *pcie)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
+ WARN_ON(phy_power_off(pcie->phy[i]));
+ WARN_ON(phy_exit(pcie->phy[i]));
+ }
+}
+
static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
{
struct device *dev = pcie->dev;
@@ -732,6 +771,7 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
{
struct device *dev = pcie->dev;
struct resource *res;
+ int i;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
pcie->breg_base = devm_ioremap_resource(dev, res);
@@ -759,6 +799,20 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
irq_set_chained_handler_and_data(pcie->irq_intx,
nwl_pcie_leg_handler, pcie);
+ for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
+ char name[16];
+
+ snprintf(name, sizeof(name), "pcie-phy%d", i);
+ pcie->phy[i] = devm_phy_get(dev, name);
+ if (PTR_ERR(pcie->phy[i]) == -ENODEV) {
+ pcie->phy[i] = NULL;
+ break;
+ }
+
+ if (IS_ERR(pcie->phy[i]))
+ return PTR_ERR(pcie->phy[i]);
+ }
+
return 0;
}
@@ -799,16 +853,22 @@ static int nwl_pcie_probe(struct platform_device *pdev)
return err;
}
+ err = nwl_pcie_phy_enable(pcie);
+ if (err) {
+ dev_err(dev, "could not enable PHYs\n");
+ goto err_clk;
+ }
+
err = nwl_pcie_bridge_init(pcie);
if (err) {
dev_err(dev, "HW Initialization failed\n");
- goto err_clk;
+ goto err_phy;
}
err = nwl_pcie_init_irq_domain(pcie);
if (err) {
dev_err(dev, "Failed creating IRQ Domain\n");
- goto err_clk;
+ goto err_phy;
}
bridge->sysdata = pcie;
@@ -818,12 +878,15 @@ static int nwl_pcie_probe(struct platform_device *pdev)
err = nwl_pcie_enable_msi(pcie);
if (err < 0) {
dev_err(dev, "failed to enable MSI support: %d\n", err);
- goto err_clk;
+ goto err_phy;
}
}
err = pci_host_probe(bridge);
+err_phy:
+ if (err)
+ nwl_pcie_phy_disable(pcie);
err_clk:
if (err)
clk_disable_unprepare(pcie->clk);
@@ -834,6 +897,7 @@ static void nwl_pcie_remove(struct platform_device *pdev)
{
struct nwl_pcie *pcie = platform_get_drvdata(pdev);
+ nwl_pcie_phy_disable(pcie);
clk_disable_unprepare(pcie->clk);
}
--
2.35.1.1320.gc452695387.dirty
Add PCIe phy bindings for the ZCU102.
Signed-off-by: Sean Anderson <[email protected]>
---
I don't have a ZCU102, so please test this.
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
index ad8f23a0ec67..68fe53685351 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -941,6 +941,8 @@ conf-pull-none {
&pcie {
status = "okay";
+ phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
+ phy-names = "pcie-phy0";
};
&psgtr {
--
2.35.1.1320.gc452695387.dirty
On Mon, 22 Apr 2024 15:58:58 -0400, Sean Anderson wrote:
> Add phys properties so Linux can power-on/configure the GTR
> transcievers.
>
> Signed-off-by: Sean Anderson <[email protected]>
> ---
>
> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml: properties:phy-names: {'maxItems': 4, 'items': [{'pattern': '^pcie-phy[0-3]$'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On 4/22/24 17:28, Rob Herring wrote:
>
> On Mon, 22 Apr 2024 15:58:58 -0400, Sean Anderson wrote:
>> Add phys properties so Linux can power-on/configure the GTR
>> transcievers.
>>
>> Signed-off-by: Sean Anderson <[email protected]>
>> ---
>>
>> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml: properties:phy-names: {'maxItems': 4, 'items': [{'pattern': '^pcie-phy[0-3]$'}]} should not be valid under {'required': ['maxItems']}
> hint: "maxItems" is not needed with an "items" list
> from schema $id: http://devicetree.org/meta-schemas/items.yaml#
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>
This warning is invalid, since I am using pattern with items.
--Sean
Hi Bharat,
On 4/22/24 21:59, Sean Anderson wrote:
> Add PCIe phy bindings for the ZCU102.
>
> Signed-off-by: Sean Anderson <[email protected]>
> ---
> I don't have a ZCU102, so please test this.
>
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> index ad8f23a0ec67..68fe53685351 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -941,6 +941,8 @@ conf-pull-none {
>
> &pcie {
> status = "okay";
> + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
> + phy-names = "pcie-phy0";
> };
>
> &psgtr {
Please review and test this series.
Thanks,
Michal
On Mon, Apr 22, 2024 at 05:30:06PM -0400, Sean Anderson wrote:
> On 4/22/24 17:28, Rob Herring wrote:
> >
> > On Mon, 22 Apr 2024 15:58:58 -0400, Sean Anderson wrote:
> >> Add phys properties so Linux can power-on/configure the GTR
> >> transcievers.
> >>
> >> Signed-off-by: Sean Anderson <[email protected]>
> >> ---
> >>
> >> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
> >> 1 file changed, 8 insertions(+)
> >>
> >
> > My bot found errors running 'make dt_binding_check' on your patch:
> >
> > yamllint warnings/errors:
> >
> > dtschema/dtc warnings/errors:
> > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml: properties:phy-names: {'maxItems': 4, 'items': [{'pattern': '^pcie-phy[0-3]$'}]} should not be valid under {'required': ['maxItems']}
> > hint: "maxItems" is not needed with an "items" list
> > from schema $id: http://devicetree.org/meta-schemas/items.yaml#
> >
> > doc reference errors (make refcheckdocs):
> >
> > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
> >
> > The base for the series is generally the latest rc1. A different dependency
> > should be noted in *this* patch.
> >
> > If you already ran 'make dt_binding_check' and didn't see the above
> > error(s), then make sure 'yamllint' is installed and dt-schema is up to
> > date:
> >
> > pip3 install dtschema --upgrade
> >
> > Please check and re-submit after running the above command yourself. Note
> > that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> > your schema. However, it must be unset to test all examples with your schema.
> >
>
> This warning is invalid, since I am using pattern with items.
It is valid. You need to make 'items' a schema not a list (i.e. drop the
'-').
Rob
On Mon, Apr 22, 2024 at 03:58:58PM -0400, Sean Anderson wrote:
> Add phys properties so Linux can power-on/configure the GTR
> transcievers.
>
> Signed-off-by: Sean Anderson <[email protected]>
> ---
>
> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> index 426f90a47f35..02315669b831 100644
> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> @@ -61,6 +61,14 @@ properties:
> interrupt-map:
> maxItems: 4
>
> + phys:
> + maxItems: 4
> +
> + phy-names:
> + maxItems: 4
> + items:
> + - pattern: '^pcie-phy[0-3]$'
The names here are pointless and redundant. Names are local to the
device, so 'pcie' is redundant. They only refer to PHYs, so 'phy' is
redundant too. All you are left with is the index of the entry.
Now if PCIe can work on only lanes 2 and 3 or similar, then maybe
-names becomes useful.
Rob
On 4/23/24 08:44, Rob Herring wrote:
> On Mon, Apr 22, 2024 at 03:58:58PM -0400, Sean Anderson wrote:
>> Add phys properties so Linux can power-on/configure the GTR
>> transcievers.
>>
>> Signed-off-by: Sean Anderson <[email protected]>
>> ---
>>
>> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> index 426f90a47f35..02315669b831 100644
>> --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
>> @@ -61,6 +61,14 @@ properties:
>> interrupt-map:
>> maxItems: 4
>>
>> + phys:
>> + maxItems: 4
>> +
>> + phy-names:
>> + maxItems: 4
>> + items:
>> + - pattern: '^pcie-phy[0-3]$'
>
> The names here are pointless and redundant. Names are local to the
> device, so 'pcie' is redundant. They only refer to PHYs, so 'phy' is
> redundant too. All you are left with is the index of the entry.
>
> Now if PCIe can work on only lanes 2 and 3 or similar, then maybe
> -names becomes useful.
OK, I'll just remove them...
--Sean
Hi Sean,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus xilinx-xlnx/master robh/for-next linus/master v6.9-rc5 next-20240423]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Sean-Anderson/dt-bindings-pci-xilinx-nwl-Add-phys/20240423-040215
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20240422195904.3591683-2-sean.anderson%40linux.dev
patch subject: [PATCH 1/7] dt-bindings: pci: xilinx-nwl: Add phys
compiler: loongarch64-linux-gcc (GCC) 13.2.0
dtschema version: 2024.4
reproduce: (https://download.01.org/0day-ci/archive/20240424/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
dtcheck warnings: (new ones prefixed by >>)
>> Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml: properties:phy-names: {'maxItems': 4, 'items': [{'pattern': '^pcie-phy[0-3]$'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Michal,
> -----Original Message-----
> From: Simek, Michal <[email protected]>
> Sent: Tuesday, April 23, 2024 11:46 AM
> To: Sean Anderson <[email protected]>; Lorenzo Pieralisi
> <[email protected]>; Krzysztof Wilczyński <[email protected]>; Rob Herring
> <[email protected]>; [email protected]; Gogada, Bharat Kumar
> <[email protected]>
> Cc: [email protected]; [email protected]; Havalige,
> Thippeswamy <[email protected]>; Bjorn Helgaas
> <[email protected]>
> Subject: Re: [PATCH 7/7] [RFT] arm64: zynqmp: Add PCIe phys
>
> Hi Bharat,
>
> On 4/22/24 21:59, Sean Anderson wrote:
> > Add PCIe phy bindings for the ZCU102.
> >
> > Signed-off-by: Sean Anderson <[email protected]>
> > ---
> > I don't have a ZCU102, so please test this.
> >
> > arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> > index ad8f23a0ec67..68fe53685351 100644
> > --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> > @@ -941,6 +941,8 @@ conf-pull-none {
> >
> > &pcie {
> > status = "okay";
> > + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
> > + phy-names = "pcie-phy0";
> > };
> >
> > &psgtr {
>
> Please review and test this series.
>
> Thanks,
> Michal
Reviewed and tested the patch.
Regards,
Thippeswamy H
On 4/24/24 11:11, Havalige, Thippeswamy wrote:
> Hi Michal,
>
>> -----Original Message-----
>> From: Simek, Michal <[email protected]>
>> Sent: Tuesday, April 23, 2024 11:46 AM
>> To: Sean Anderson <[email protected]>; Lorenzo Pieralisi
>> <[email protected]>; Krzysztof Wilczyński <[email protected]>; Rob Herring
>> <[email protected]>; [email protected]; Gogada, Bharat Kumar
>> <[email protected]>
>> Cc: [email protected]; [email protected]; Havalige,
>> Thippeswamy <[email protected]>; Bjorn Helgaas
>> <[email protected]>
>> Subject: Re: [PATCH 7/7] [RFT] arm64: zynqmp: Add PCIe phys
>>
>> Hi Bharat,
>>
>> On 4/22/24 21:59, Sean Anderson wrote:
>>> Add PCIe phy bindings for the ZCU102.
>>>
>>> Signed-off-by: Sean Anderson <[email protected]>
>>> ---
>>> I don't have a ZCU102, so please test this.
>>>
>>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 ++
>>> 1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> index ad8f23a0ec67..68fe53685351 100644
>>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>>> @@ -941,6 +941,8 @@ conf-pull-none {
>>>
>>> &pcie {
>>> status = "okay";
>>> + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
>>> + phy-names = "pcie-phy0";
>>> };
>>>
>>> &psgtr {
>>
>> Please review and test this series.
>>
>> Thanks,
>> Michal
>
> Reviewed and tested the patch.
can you please provide proper Tested-by: line?
Thanks,
Michal
Tested-by: [email protected]
> -----Original Message-----
> From: Simek, Michal <[email protected]>
> Sent: Wednesday, April 24, 2024 4:57 PM
> To: Havalige, Thippeswamy <[email protected]>; Sean Anderson
> <[email protected]>; Lorenzo Pieralisi <[email protected]>; Krzysztof
> Wilczyński <[email protected]>; Rob Herring <[email protected]>; linux-
> [email protected]; Gogada, Bharat Kumar <[email protected]>
> Cc: [email protected]; [email protected]; Bjorn
> Helgaas <[email protected]>
> Subject: Re: [PATCH 7/7] [RFT] arm64: zynqmp: Add PCIe phys
>
>
>
> On 4/24/24 11:11, Havalige, Thippeswamy wrote:
> > Hi Michal,
> >
> >> -----Original Message-----
> >> From: Simek, Michal <[email protected]>
> >> Sent: Tuesday, April 23, 2024 11:46 AM
> >> To: Sean Anderson <[email protected]>; Lorenzo Pieralisi
> >> <[email protected]>; Krzysztof Wilczyński <[email protected]>; Rob
> >> Herring <[email protected]>; [email protected]; Gogada, Bharat
> >> Kumar <[email protected]>
> >> Cc: [email protected];
> >> [email protected]; Havalige, Thippeswamy
> >> <[email protected]>; Bjorn Helgaas <[email protected]>
> >> Subject: Re: [PATCH 7/7] [RFT] arm64: zynqmp: Add PCIe phys
> >>
> >> Hi Bharat,
> >>
> >> On 4/22/24 21:59, Sean Anderson wrote:
> >>> Add PCIe phy bindings for the ZCU102.
> >>>
> >>> Signed-off-by: Sean Anderson <[email protected]>
> >>> ---
> >>> I don't have a ZCU102, so please test this.
> >>>
> >>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 ++
> >>> 1 file changed, 2 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> >> b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> >>> index ad8f23a0ec67..68fe53685351 100644
> >>> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> >>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> >>> @@ -941,6 +941,8 @@ conf-pull-none {
> >>>
> >>> &pcie {
> >>> status = "okay";
> >>> + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
> >>> + phy-names = "pcie-phy0";
> >>> };
> >>>
> >>> &psgtr {
> >>
> >> Please review and test this series.
> >>
> >> Thanks,
> >> Michal
> >
> > Reviewed and tested the patch.
>
> can you please provide proper Tested-by: line?
>
> Thanks,
> Michal