This patch series aims to enable cpufreq for IPQ5332 and IPQ9574.
For IPQ5332, a minor enhancement to Stromer Plus ops and a safe
source switch is needed before cpu freq can be enabled.
These are also included in this series. Posting this as a single
series. Please let me know if this is not correct, will split in
the subsequent revisions.
Passed the following DT related validations
make W=1 ARCH=arm64 -j16 DT_CHECKER_FLAGS='-v -m' dt_binding_check DT_SCHEMA_FILES=qcom
make W=1 ARCH=arm64 -j16 CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check
For IPQ5332:
~~~~~~~~~~~
* This patch series introduces stromer plus ops which
builds on stromer ops and implements a different
set_rate and determine_rate.
A different set_rate is needed since stromer plus PLLs
do not support dynamic frequency scaling. To switch
between frequencies, we have to shut down the PLL,
configure the L and ALPHA values and turn on again. So
introduce the separate set of ops for Stromer Plus PLL.
* Update ipq_pll_stromer_plus to use clk_alpha_pll_stromer_plus_ops
instead of clk_alpha_pll_stromer_ops.
* Set 'l' value to a value that is supported on all SKUs.
* Provide safe source switch for a53pll
* Include IPQ5332 in cpufreq nvmem framework
* Add OPP details to device tree
For IPQ9574:
~~~~~~~~~~~
* Include IPQ9574 in cpufreq nvmem framework
* Add OPP details to device tree
Removed 2 patches from V1 as they have been merged
* dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ5332
* dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ9574
v4: Included a patch to fix 'kernel test robot' build error --
https://lore.kernel.org/r/[email protected]/
v5: Use devm_clk_notifier_register
Merge IPQ53xx and IPQ95xx cases with APQ8096 for speed bin selection
Add reviewed by tags
v6: Except these 2 patches, rest have been merged...
Rebased these to latest top as they don't apply cleanly
(https://lore.kernel.org/linux-arm-msm/20231025062508.vccrmkem45p3fnwe@vireshk-i7/)
Varadarajan Narayanan (2):
cpufreq: qti: Enable cpufreq for ipq53xx
cpufreq: qti: Introduce cpufreq for ipq95xx
drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
drivers/cpufreq/qcom-cpufreq-nvmem.c | 12 ++++++++++++
2 files changed, 14 insertions(+)
--
2.7.4
IPQ53xx have different OPPs available for the CPU based on
SoC variant. This can be determined through use of an eFuse
register present in the silicon.
Added support for ipq53xx on nvmem driver which helps to
determine OPPs at runtime based on the eFuse register which
has the CPU frequency limits. opp-supported-hw dt binding
can be used to indicate the available OPPs for each limit.
nvmem driver also creates the "cpufreq-dt" platform_device after
passing the version matching data to the OPP framework so that the
cpufreq-dt handles the actual cpufreq implementation.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v6: Rebase to top of tree
v5: Merge IPQ53xx with existing APQ8096 case
v2: Move IPQ53xx after APQ8096SG
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 0718191..53da255 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -180,6 +180,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "ti,am62a7", },
{ .compatible = "ti,am62p5", },
+ { .compatible = "qcom,ipq5332", },
{ .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,ipq8074", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 158c0e1..4f7af70 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -183,6 +183,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
switch (msm_id) {
case QCOM_ID_MSM8996:
case QCOM_ID_APQ8096:
+ case QCOM_ID_IPQ5332:
+ case QCOM_ID_IPQ5322:
+ case QCOM_ID_IPQ5312:
+ case QCOM_ID_IPQ5302:
+ case QCOM_ID_IPQ5300:
drv->versions = 1 << (unsigned int)(*speedbin);
break;
case QCOM_ID_MSM8996SG:
@@ -541,6 +546,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,msm8909", .data = &match_data_msm8909 },
{ .compatible = "qcom,msm8996", .data = &match_data_kryo },
{ .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
+ { .compatible = "qcom,ipq5332", .data = &match_data_kryo },
{ .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
{ .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
--
2.7.4
IPQ95xx SoCs have different OPPs available for the CPU based on
the SoC variant. This can be determined from an eFuse register
present in the silicon.
Added support for ipq95xx on nvmem driver which helps to
determine OPPs at runtime based on the eFuse register which
has the CPU frequency limits. opp-supported-hw dt binding
can be used to indicate the available OPPs for each limit.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Kathiravan T <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v6: Rebase to top of tree
v5: Merge IPQ95xx with APQ8096 case
v2: Simplify bin selection by tweaking the order in dts
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/qcom-cpufreq-nvmem.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 53da255..bd1e135 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -184,6 +184,7 @@ static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "qcom,ipq6018", },
{ .compatible = "qcom,ipq8064", },
{ .compatible = "qcom,ipq8074", },
+ { .compatible = "qcom,ipq9574", },
{ .compatible = "qcom,apq8064", },
{ .compatible = "qcom,msm8974", },
{ .compatible = "qcom,msm8960", },
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
index 4f7af70..6355a39 100644
--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
@@ -188,6 +188,11 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
case QCOM_ID_IPQ5312:
case QCOM_ID_IPQ5302:
case QCOM_ID_IPQ5300:
+ case QCOM_ID_IPQ9514:
+ case QCOM_ID_IPQ9550:
+ case QCOM_ID_IPQ9554:
+ case QCOM_ID_IPQ9570:
+ case QCOM_ID_IPQ9574:
drv->versions = 1 << (unsigned int)(*speedbin);
break;
case QCOM_ID_MSM8996SG:
@@ -551,6 +556,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
{ .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
{ .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
{ .compatible = "qcom,apq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq9574", .data = &match_data_kryo },
{ .compatible = "qcom,msm8974", .data = &match_data_krait },
{ .compatible = "qcom,msm8960", .data = &match_data_krait },
{},
--
2.7.4
On 31-10-23, 12:41, Varadarajan Narayanan wrote:
> This patch series aims to enable cpufreq for IPQ5332 and IPQ9574.
> For IPQ5332, a minor enhancement to Stromer Plus ops and a safe
> source switch is needed before cpu freq can be enabled.
>
> These are also included in this series. Posting this as a single
> series. Please let me know if this is not correct, will split in
> the subsequent revisions.
>
> Passed the following DT related validations
> make W=1 ARCH=arm64 -j16 DT_CHECKER_FLAGS='-v -m' dt_binding_check DT_SCHEMA_FILES=qcom
> make W=1 ARCH=arm64 -j16 CHECK_DTBS=y DT_SCHEMA_FILES=qcom dtbs_check
>
> For IPQ5332:
> ~~~~~~~~~~~
> * This patch series introduces stromer plus ops which
> builds on stromer ops and implements a different
> set_rate and determine_rate.
>
> A different set_rate is needed since stromer plus PLLs
> do not support dynamic frequency scaling. To switch
> between frequencies, we have to shut down the PLL,
> configure the L and ALPHA values and turn on again. So
> introduce the separate set of ops for Stromer Plus PLL.
>
> * Update ipq_pll_stromer_plus to use clk_alpha_pll_stromer_plus_ops
> instead of clk_alpha_pll_stromer_ops.
>
> * Set 'l' value to a value that is supported on all SKUs.
>
> * Provide safe source switch for a53pll
>
> * Include IPQ5332 in cpufreq nvmem framework
>
> * Add OPP details to device tree
>
> For IPQ9574:
> ~~~~~~~~~~~
> * Include IPQ9574 in cpufreq nvmem framework
>
> * Add OPP details to device tree
>
> Removed 2 patches from V1 as they have been merged
> * dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ5332
> * dt-bindings: cpufreq: qcom-cpufreq-nvmem: document IPQ9574
>
> v4: Included a patch to fix 'kernel test robot' build error --
> https://lore.kernel.org/r/[email protected]/
>
> v5: Use devm_clk_notifier_register
> Merge IPQ53xx and IPQ95xx cases with APQ8096 for speed bin selection
> Add reviewed by tags
>
> v6: Except these 2 patches, rest have been merged...
> Rebased these to latest top as they don't apply cleanly
> (https://lore.kernel.org/linux-arm-msm/20231025062508.vccrmkem45p3fnwe@vireshk-i7/)
>
> Varadarajan Narayanan (2):
> cpufreq: qti: Enable cpufreq for ipq53xx
> cpufreq: qti: Introduce cpufreq for ipq95xx
>
> drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
> drivers/cpufreq/qcom-cpufreq-nvmem.c | 12 ++++++++++++
> 2 files changed, 14 insertions(+)
Applied. Thanks.
--
viresh