This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2) and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
Weiyi Lu (5):
dt-bindings: soc: update MT2712 power dt-bindings
soc: mediatek: update power domain data of MT2712
dt-bindings: clock: add clocks for MT2712
arm64: dts: add clock device nodes of MT2712
clk: mediatek: update clock driver of MT2712
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 +++
drivers/clk/mediatek/clk-mt2712.c | 69 +++++--
drivers/soc/mediatek/mtk-scpsys.c | 42 ++++-
include/dt-bindings/clock/mt2712-clk.h | 294 +++++++++++++++---------------
include/dt-bindings/power/mt2712-power.h | 3 +
5 files changed, 277 insertions(+), 159 deletions(-)
1. split MFG power domain into MFG/MFG_SC1/MFG_SC2/MFG_SC3
according to MT2712 ECO design change
2. add subdomain support for MT2712
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 42 +++++++++++++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 59bd749c2f25..edf8fd6c2c85 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -664,12 +664,48 @@ static const struct scp_domain_data scp_domain_data_mt2712[] = {
.name = "mfg",
.sta_mask = PWR_STATUS_MFG,
.ctl_offs = SPM_MFG_PWR_CON,
- .sram_pdn_bits = GENMASK(11, 8),
- .sram_pdn_ack_bits = GENMASK(19, 16),
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(16, 16),
.clk_id = {CLK_MFG},
.bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
.active_wakeup = true,
},
+ [MT2712_POWER_DOMAIN_MFG_SC1] = {
+ .name = "mfg_sc1",
+ .sta_mask = BIT(22),
+ .ctl_offs = 0x02c0,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(16, 16),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_MFG_SC2] = {
+ .name = "mfg_sc2",
+ .sta_mask = BIT(23),
+ .ctl_offs = 0x02c4,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(16, 16),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+ [MT2712_POWER_DOMAIN_MFG_SC3] = {
+ .name = "mfg_sc3",
+ .sta_mask = BIT(30),
+ .ctl_offs = 0x01f8,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(16, 16),
+ .clk_id = {CLK_NONE},
+ .active_wakeup = true,
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt2712[] = {
+ {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VDEC},
+ {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VENC},
+ {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_ISP},
+ {MT2712_POWER_DOMAIN_MFG, MT2712_POWER_DOMAIN_MFG_SC1},
+ {MT2712_POWER_DOMAIN_MFG_SC1, MT2712_POWER_DOMAIN_MFG_SC2},
+ {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
};
/*
@@ -905,6 +941,8 @@ static const struct scp_soc_data mt2701_data = {
static const struct scp_soc_data mt2712_data = {
.domains = scp_domain_data_mt2712,
.num_domains = ARRAY_SIZE(scp_domain_data_mt2712),
+ .subdomains = scp_subdomain_mt2712,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
--
2.12.5
According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/clk-mt2712.c | 69 +++++++++++++++++++++++++++++++--------
1 file changed, 55 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 498d13799388..d4a7497a2417 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -141,6 +141,8 @@ static const struct mtk_fixed_factor top_divs[] = {
1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
2),
+ FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
+ 3),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
@@ -625,7 +627,7 @@ static const char * const ether_125m_parents[] = {
static const char * const ether_50m_parents[] = {
"clk26m",
"etherpll_50m",
- "univpll_d26",
+ "apll1_d3",
"univpll3_d4"
};
@@ -686,7 +688,7 @@ static const char * const i2c_parents[] = {
static const char * const msdc0p_aes_parents[] = {
"clk26m",
- "msdcpll_ck",
+ "syspll_d2",
"univpll_d3",
"vcodecpll_ck"
};
@@ -719,6 +721,17 @@ static const char * const aud_apll2_parents[] = {
"clkaud_ext_i_2"
};
+static const char * const apll1_ref_parents[] = {
+ "clkaud_ext_i_2",
+ "clkaud_ext_i_1",
+ "clki2si0_mck_i",
+ "clki2si1_mck_i",
+ "clki2si2_mck_i",
+ "clktdmin_mclk_i",
+ "clki2si2_mck_i",
+ "clktdmin_mclk_i"
+};
+
static const char * const audull_vtx_parents[] = {
"d2a_ulclk_6p5m",
"clkaud_ext_i_0"
@@ -884,6 +897,10 @@ static struct mtk_composite top_muxes[] = {
aud_apll1_parents, 0x134, 0, 1),
MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
aud_apll2_parents, 0x134, 1, 1),
+ MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
+ apll1_ref_parents, 0x134, 4, 3),
+ MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
+ apll1_ref_parents, 0x134, 7, 3),
MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
audull_vtx_parents, 0x134, 31, 1),
};
@@ -932,36 +949,56 @@ static const struct mtk_clk_divider top_adj_divs[] = {
DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
};
-static const struct mtk_gate_regs top_cg_regs = {
+static const struct mtk_gate_regs top0_cg_regs = {
.set_ofs = 0x120,
.clr_ofs = 0x120,
.sta_ofs = 0x120,
};
-#define GATE_TOP(_id, _name, _parent, _shift) { \
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x424,
+ .clr_ofs = 0x424,
+ .sta_ofs = 0x424,
+};
+
+#define GATE_TOP0(_id, _name, _parent, _shift) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
- .regs = &top_cg_regs, \
+ .regs = &top0_cg_regs, \
.shift = _shift, \
.ops = &mtk_clk_gate_ops_no_setclr, \
}
+#define GATE_TOP1(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+ }
+
static const struct mtk_gate top_clks[] = {
- GATE_TOP(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
- GATE_TOP(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
- GATE_TOP(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
- GATE_TOP(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
- GATE_TOP(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
- GATE_TOP(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
- GATE_TOP(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
- GATE_TOP(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
+ GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
+ GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
+ GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
};
static const struct mtk_gate_regs infra_cg_regs = {
.set_ofs = 0x40,
.clr_ofs = 0x44,
- .sta_ofs = 0x40,
+ .sta_ofs = 0x48,
};
#define GATE_INFRA(_id, _name, _parent, _shift) { \
@@ -1120,6 +1157,10 @@ static const struct mtk_gate peri_clks[] = {
"msdc50_0_h_sel", 4),
GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
"msdc50_3_h_sel", 5),
+ GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
+ "axi_sel", 6),
+ GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
+ "mem_sel", 7),
};
#define MT2712_PLL_FMAX (3000UL * MHZ)
--
2.12.5
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index fdf66f4fe7c3..d7688bc9db1b 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -199,6 +199,34 @@
clock-output-names = "clkaud_ext_i_2";
};
+ clki2si0_mck_i: oscillator@6 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clki2si0_mck_i";
+ };
+
+ clki2si1_mck_i: oscillator@7 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clki2si1_mck_i";
+ };
+
+ clki2si2_mck_i: oscillator@8 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clki2si2_mck_i";
+ };
+
+ clktdmin_mclk_i: oscillator@9 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clktdmin_mclk_i";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
--
2.12.5
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2) and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
Weiyi Lu (5):
dt-bindings: soc: update MT2712 power dt-bindings
soc: mediatek: update power domain data of MT2712
dt-bindings: clock: add clocks for MT2712
arm64: dts: add clock device nodes of MT2712
clk: mediatek: update clock driver of MT2712
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28 +++
drivers/clk/mediatek/clk-mt2712.c | 69 +++++--
drivers/soc/mediatek/mtk-scpsys.c | 42 ++++-
include/dt-bindings/clock/mt2712-clk.h | 294 +++++++++++++++---------------
include/dt-bindings/power/mt2712-power.h | 3 +
5 files changed, 277 insertions(+), 159 deletions(-)
--
2.12.5
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu <[email protected]>
---
include/dt-bindings/clock/mt2712-clk.h | 294 +++++++++++++++++----------------
1 file changed, 151 insertions(+), 143 deletions(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
index 48a8e797a617..0690f24391b3 100644
--- a/include/dt-bindings/clock/mt2712-clk.h
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -81,148 +81,154 @@
#define CLK_TOP_F_BUS_PLL2 42
#define CLK_TOP_APLL1 43
#define CLK_TOP_APLL1_D2 44
-#define CLK_TOP_APLL1_D4 45
-#define CLK_TOP_APLL1_D8 46
-#define CLK_TOP_APLL1_D16 47
-#define CLK_TOP_APLL2 48
-#define CLK_TOP_APLL2_D2 49
-#define CLK_TOP_APLL2_D4 50
-#define CLK_TOP_APLL2_D8 51
-#define CLK_TOP_APLL2_D16 52
-#define CLK_TOP_LVDSPLL 53
-#define CLK_TOP_LVDSPLL_D2 54
-#define CLK_TOP_LVDSPLL_D4 55
-#define CLK_TOP_LVDSPLL_D8 56
-#define CLK_TOP_LVDSPLL2 57
-#define CLK_TOP_LVDSPLL2_D2 58
-#define CLK_TOP_LVDSPLL2_D4 59
-#define CLK_TOP_LVDSPLL2_D8 60
-#define CLK_TOP_ETHERPLL_125M 61
-#define CLK_TOP_ETHERPLL_50M 62
-#define CLK_TOP_CVBS 63
-#define CLK_TOP_CVBS_D2 64
-#define CLK_TOP_SYS_26M 65
-#define CLK_TOP_MMPLL 66
-#define CLK_TOP_MMPLL_D2 67
-#define CLK_TOP_VENCPLL 68
-#define CLK_TOP_VENCPLL_D2 69
-#define CLK_TOP_VCODECPLL 70
-#define CLK_TOP_VCODECPLL_D2 71
-#define CLK_TOP_TVDPLL 72
-#define CLK_TOP_TVDPLL_D2 73
-#define CLK_TOP_TVDPLL_D4 74
-#define CLK_TOP_TVDPLL_D8 75
-#define CLK_TOP_TVDPLL_429M 76
-#define CLK_TOP_TVDPLL_429M_D2 77
-#define CLK_TOP_TVDPLL_429M_D4 78
-#define CLK_TOP_MSDCPLL 79
-#define CLK_TOP_MSDCPLL_D2 80
-#define CLK_TOP_MSDCPLL_D4 81
-#define CLK_TOP_MSDCPLL2 82
-#define CLK_TOP_MSDCPLL2_D2 83
-#define CLK_TOP_MSDCPLL2_D4 84
-#define CLK_TOP_CLK26M_D2 85
-#define CLK_TOP_D2A_ULCLK_6P5M 86
-#define CLK_TOP_VPLL3_DPIX 87
-#define CLK_TOP_VPLL_DPIX 88
-#define CLK_TOP_LTEPLL_FS26M 89
-#define CLK_TOP_DMPLL 90
-#define CLK_TOP_DSI0_LNTC 91
-#define CLK_TOP_DSI1_LNTC 92
-#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
-#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
-#define CLK_TOP_CLKRTC_EXT 95
-#define CLK_TOP_CLKRTC_INT 96
-#define CLK_TOP_CSI0 97
-#define CLK_TOP_CVBSPLL 98
-#define CLK_TOP_AXI_SEL 99
-#define CLK_TOP_MEM_SEL 100
-#define CLK_TOP_MM_SEL 101
-#define CLK_TOP_PWM_SEL 102
-#define CLK_TOP_VDEC_SEL 103
-#define CLK_TOP_VENC_SEL 104
-#define CLK_TOP_MFG_SEL 105
-#define CLK_TOP_CAMTG_SEL 106
-#define CLK_TOP_UART_SEL 107
-#define CLK_TOP_SPI_SEL 108
-#define CLK_TOP_USB20_SEL 109
-#define CLK_TOP_USB30_SEL 110
-#define CLK_TOP_MSDC50_0_HCLK_SEL 111
-#define CLK_TOP_MSDC50_0_SEL 112
-#define CLK_TOP_MSDC30_1_SEL 113
-#define CLK_TOP_MSDC30_2_SEL 114
-#define CLK_TOP_MSDC30_3_SEL 115
-#define CLK_TOP_AUDIO_SEL 116
-#define CLK_TOP_AUD_INTBUS_SEL 117
-#define CLK_TOP_PMICSPI_SEL 118
-#define CLK_TOP_DPILVDS1_SEL 119
-#define CLK_TOP_ATB_SEL 120
-#define CLK_TOP_NR_SEL 121
-#define CLK_TOP_NFI2X_SEL 122
-#define CLK_TOP_IRDA_SEL 123
-#define CLK_TOP_CCI400_SEL 124
-#define CLK_TOP_AUD_1_SEL 125
-#define CLK_TOP_AUD_2_SEL 126
-#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
-#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
-#define CLK_TOP_SCAM_SEL 129
-#define CLK_TOP_NFIECC_SEL 130
-#define CLK_TOP_PE2_MAC_P0_SEL 131
-#define CLK_TOP_PE2_MAC_P1_SEL 132
-#define CLK_TOP_DPILVDS_SEL 133
-#define CLK_TOP_MSDC50_3_HCLK_SEL 134
-#define CLK_TOP_HDCP_SEL 135
-#define CLK_TOP_HDCP_24M_SEL 136
-#define CLK_TOP_RTC_SEL 137
-#define CLK_TOP_SPINOR_SEL 138
-#define CLK_TOP_APLL_SEL 139
-#define CLK_TOP_APLL2_SEL 140
-#define CLK_TOP_A1SYS_HP_SEL 141
-#define CLK_TOP_A2SYS_HP_SEL 142
-#define CLK_TOP_ASM_L_SEL 143
-#define CLK_TOP_ASM_M_SEL 144
-#define CLK_TOP_ASM_H_SEL 145
-#define CLK_TOP_I2SO1_SEL 146
-#define CLK_TOP_I2SO2_SEL 147
-#define CLK_TOP_I2SO3_SEL 148
-#define CLK_TOP_TDMO0_SEL 149
-#define CLK_TOP_TDMO1_SEL 150
-#define CLK_TOP_I2SI1_SEL 151
-#define CLK_TOP_I2SI2_SEL 152
-#define CLK_TOP_I2SI3_SEL 153
-#define CLK_TOP_ETHER_125M_SEL 154
-#define CLK_TOP_ETHER_50M_SEL 155
-#define CLK_TOP_JPGDEC_SEL 156
-#define CLK_TOP_SPISLV_SEL 157
-#define CLK_TOP_ETHER_50M_RMII_SEL 158
-#define CLK_TOP_CAM2TG_SEL 159
-#define CLK_TOP_DI_SEL 160
-#define CLK_TOP_TVD_SEL 161
-#define CLK_TOP_I2C_SEL 162
-#define CLK_TOP_PWM_INFRA_SEL 163
-#define CLK_TOP_MSDC0P_AES_SEL 164
-#define CLK_TOP_CMSYS_SEL 165
-#define CLK_TOP_GCPU_SEL 166
-#define CLK_TOP_AUD_APLL1_SEL 167
-#define CLK_TOP_AUD_APLL2_SEL 168
-#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
-#define CLK_TOP_APLL_DIV0 170
-#define CLK_TOP_APLL_DIV1 171
-#define CLK_TOP_APLL_DIV2 172
-#define CLK_TOP_APLL_DIV3 173
-#define CLK_TOP_APLL_DIV4 174
-#define CLK_TOP_APLL_DIV5 175
-#define CLK_TOP_APLL_DIV6 176
-#define CLK_TOP_APLL_DIV7 177
-#define CLK_TOP_APLL_DIV_PDN0 178
-#define CLK_TOP_APLL_DIV_PDN1 179
-#define CLK_TOP_APLL_DIV_PDN2 180
-#define CLK_TOP_APLL_DIV_PDN3 181
-#define CLK_TOP_APLL_DIV_PDN4 182
-#define CLK_TOP_APLL_DIV_PDN5 183
-#define CLK_TOP_APLL_DIV_PDN6 184
-#define CLK_TOP_APLL_DIV_PDN7 185
-#define CLK_TOP_NR_CLK 186
+#define CLK_TOP_APLL1_D3 45
+#define CLK_TOP_APLL1_D4 46
+#define CLK_TOP_APLL1_D8 47
+#define CLK_TOP_APLL1_D16 48
+#define CLK_TOP_APLL2 49
+#define CLK_TOP_APLL2_D2 50
+#define CLK_TOP_APLL2_D4 51
+#define CLK_TOP_APLL2_D8 52
+#define CLK_TOP_APLL2_D16 53
+#define CLK_TOP_LVDSPLL 54
+#define CLK_TOP_LVDSPLL_D2 55
+#define CLK_TOP_LVDSPLL_D4 56
+#define CLK_TOP_LVDSPLL_D8 57
+#define CLK_TOP_LVDSPLL2 58
+#define CLK_TOP_LVDSPLL2_D2 59
+#define CLK_TOP_LVDSPLL2_D4 60
+#define CLK_TOP_LVDSPLL2_D8 61
+#define CLK_TOP_ETHERPLL_125M 62
+#define CLK_TOP_ETHERPLL_50M 63
+#define CLK_TOP_CVBS 64
+#define CLK_TOP_CVBS_D2 65
+#define CLK_TOP_SYS_26M 66
+#define CLK_TOP_MMPLL 67
+#define CLK_TOP_MMPLL_D2 68
+#define CLK_TOP_VENCPLL 69
+#define CLK_TOP_VENCPLL_D2 70
+#define CLK_TOP_VCODECPLL 71
+#define CLK_TOP_VCODECPLL_D2 72
+#define CLK_TOP_TVDPLL 73
+#define CLK_TOP_TVDPLL_D2 74
+#define CLK_TOP_TVDPLL_D4 75
+#define CLK_TOP_TVDPLL_D8 76
+#define CLK_TOP_TVDPLL_429M 77
+#define CLK_TOP_TVDPLL_429M_D2 78
+#define CLK_TOP_TVDPLL_429M_D4 79
+#define CLK_TOP_MSDCPLL 80
+#define CLK_TOP_MSDCPLL_D2 81
+#define CLK_TOP_MSDCPLL_D4 82
+#define CLK_TOP_MSDCPLL2 83
+#define CLK_TOP_MSDCPLL2_D2 84
+#define CLK_TOP_MSDCPLL2_D4 85
+#define CLK_TOP_CLK26M_D2 86
+#define CLK_TOP_D2A_ULCLK_6P5M 87
+#define CLK_TOP_VPLL3_DPIX 88
+#define CLK_TOP_VPLL_DPIX 89
+#define CLK_TOP_LTEPLL_FS26M 90
+#define CLK_TOP_DMPLL 91
+#define CLK_TOP_DSI0_LNTC 92
+#define CLK_TOP_DSI1_LNTC 93
+#define CLK_TOP_LVDSTX3_CLKDIG_CTS 94
+#define CLK_TOP_LVDSTX_CLKDIG_CTS 95
+#define CLK_TOP_CLKRTC_EXT 96
+#define CLK_TOP_CLKRTC_INT 97
+#define CLK_TOP_CSI0 98
+#define CLK_TOP_CVBSPLL 99
+#define CLK_TOP_AXI_SEL 100
+#define CLK_TOP_MEM_SEL 101
+#define CLK_TOP_MM_SEL 102
+#define CLK_TOP_PWM_SEL 103
+#define CLK_TOP_VDEC_SEL 104
+#define CLK_TOP_VENC_SEL 105
+#define CLK_TOP_MFG_SEL 106
+#define CLK_TOP_CAMTG_SEL 107
+#define CLK_TOP_UART_SEL 108
+#define CLK_TOP_SPI_SEL 109
+#define CLK_TOP_USB20_SEL 110
+#define CLK_TOP_USB30_SEL 111
+#define CLK_TOP_MSDC50_0_HCLK_SEL 112
+#define CLK_TOP_MSDC50_0_SEL 113
+#define CLK_TOP_MSDC30_1_SEL 114
+#define CLK_TOP_MSDC30_2_SEL 115
+#define CLK_TOP_MSDC30_3_SEL 116
+#define CLK_TOP_AUDIO_SEL 117
+#define CLK_TOP_AUD_INTBUS_SEL 118
+#define CLK_TOP_PMICSPI_SEL 119
+#define CLK_TOP_DPILVDS1_SEL 120
+#define CLK_TOP_ATB_SEL 121
+#define CLK_TOP_NR_SEL 122
+#define CLK_TOP_NFI2X_SEL 123
+#define CLK_TOP_IRDA_SEL 124
+#define CLK_TOP_CCI400_SEL 125
+#define CLK_TOP_AUD_1_SEL 126
+#define CLK_TOP_AUD_2_SEL 127
+#define CLK_TOP_MEM_MFG_IN_AS_SEL 128
+#define CLK_TOP_AXI_MFG_IN_AS_SEL 129
+#define CLK_TOP_SCAM_SEL 130
+#define CLK_TOP_NFIECC_SEL 131
+#define CLK_TOP_PE2_MAC_P0_SEL 132
+#define CLK_TOP_PE2_MAC_P1_SEL 133
+#define CLK_TOP_DPILVDS_SEL 134
+#define CLK_TOP_MSDC50_3_HCLK_SEL 135
+#define CLK_TOP_HDCP_SEL 136
+#define CLK_TOP_HDCP_24M_SEL 137
+#define CLK_TOP_RTC_SEL 138
+#define CLK_TOP_SPINOR_SEL 139
+#define CLK_TOP_APLL_SEL 140
+#define CLK_TOP_APLL2_SEL 141
+#define CLK_TOP_A1SYS_HP_SEL 142
+#define CLK_TOP_A2SYS_HP_SEL 143
+#define CLK_TOP_ASM_L_SEL 144
+#define CLK_TOP_ASM_M_SEL 145
+#define CLK_TOP_ASM_H_SEL 146
+#define CLK_TOP_I2SO1_SEL 147
+#define CLK_TOP_I2SO2_SEL 148
+#define CLK_TOP_I2SO3_SEL 149
+#define CLK_TOP_TDMO0_SEL 150
+#define CLK_TOP_TDMO1_SEL 151
+#define CLK_TOP_I2SI1_SEL 152
+#define CLK_TOP_I2SI2_SEL 153
+#define CLK_TOP_I2SI3_SEL 154
+#define CLK_TOP_ETHER_125M_SEL 155
+#define CLK_TOP_ETHER_50M_SEL 156
+#define CLK_TOP_JPGDEC_SEL 157
+#define CLK_TOP_SPISLV_SEL 158
+#define CLK_TOP_ETHER_50M_RMII_SEL 159
+#define CLK_TOP_CAM2TG_SEL 160
+#define CLK_TOP_DI_SEL 161
+#define CLK_TOP_TVD_SEL 162
+#define CLK_TOP_I2C_SEL 163
+#define CLK_TOP_PWM_INFRA_SEL 164
+#define CLK_TOP_MSDC0P_AES_SEL 165
+#define CLK_TOP_CMSYS_SEL 166
+#define CLK_TOP_GCPU_SEL 167
+#define CLK_TOP_AUD_APLL1_SEL 168
+#define CLK_TOP_AUD_APLL2_SEL 169
+#define CLK_TOP_APLL1_REF_SEL 170
+#define CLK_TOP_APLL2_REF_SEL 171
+#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 172
+#define CLK_TOP_APLL_DIV0 173
+#define CLK_TOP_APLL_DIV1 174
+#define CLK_TOP_APLL_DIV2 175
+#define CLK_TOP_APLL_DIV3 176
+#define CLK_TOP_APLL_DIV4 177
+#define CLK_TOP_APLL_DIV5 178
+#define CLK_TOP_APLL_DIV6 179
+#define CLK_TOP_APLL_DIV7 180
+#define CLK_TOP_APLL_DIV_PDN0 181
+#define CLK_TOP_APLL_DIV_PDN1 182
+#define CLK_TOP_APLL_DIV_PDN2 183
+#define CLK_TOP_APLL_DIV_PDN3 184
+#define CLK_TOP_APLL_DIV_PDN4 185
+#define CLK_TOP_APLL_DIV_PDN5 186
+#define CLK_TOP_APLL_DIV_PDN6 187
+#define CLK_TOP_APLL_DIV_PDN7 188
+#define CLK_TOP_NFI2X_EN 189
+#define CLK_TOP_NFIECC_EN 190
+#define CLK_TOP_NFI1X_CK_EN 191
+#define CLK_TOP_NR_CLK 192
/* INFRACFG */
@@ -281,7 +287,9 @@
#define CLK_PERI_MSDC30_3_EN 41
#define CLK_PERI_MSDC50_0_HCLK_EN 42
#define CLK_PERI_MSDC50_3_HCLK_EN 43
-#define CLK_PERI_NR_CLK 44
+#define CLK_PERI_MSDC30_0_QTR_EN 44
+#define CLK_PERI_MSDC30_3_QTR_EN 45
+#define CLK_PERI_NR_CLK 46
/* MCUCFG */
--
2.12.5
Add new power domains(MFG_SC1/MFG_SC2/MFG_SC3)
for MT2712 according to ECO design change.
Signed-off-by: Weiyi Lu <[email protected]>
---
include/dt-bindings/power/mt2712-power.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/power/mt2712-power.h b/include/dt-bindings/power/mt2712-power.h
index 92b46d772fae..2c147817efc2 100644
--- a/include/dt-bindings/power/mt2712-power.h
+++ b/include/dt-bindings/power/mt2712-power.h
@@ -22,5 +22,8 @@
#define MT2712_POWER_DOMAIN_USB 5
#define MT2712_POWER_DOMAIN_USB2 6
#define MT2712_POWER_DOMAIN_MFG 7
+#define MT2712_POWER_DOMAIN_MFG_SC1 8
+#define MT2712_POWER_DOMAIN_MFG_SC2 9
+#define MT2712_POWER_DOMAIN_MFG_SC3 10
#endif /* _DT_BINDINGS_POWER_MT2712_POWER_H */
--
2.12.5
On Thu, Feb 22, 2018 at 01:48:47PM +0800, Weiyi Lu wrote:
> Add new power domains(MFG_SC1/MFG_SC2/MFG_SC3)
> for MT2712 according to ECO design change.
>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
> include/dt-bindings/power/mt2712-power.h | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Rob Herring <[email protected]>
On Thu, Feb 22, 2018 at 01:48:49PM +0800, Weiyi Lu wrote:
> add new clocks according to ECO design change
>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
> include/dt-bindings/clock/mt2712-clk.h | 294 +++++++++++++++++----------------
> 1 file changed, 151 insertions(+), 143 deletions(-)
You can't just renumber your clocks. They are an ABI. Plus, for an ECO
there can't have been that much change.
>
> diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
> index 48a8e797a617..0690f24391b3 100644
> --- a/include/dt-bindings/clock/mt2712-clk.h
> +++ b/include/dt-bindings/clock/mt2712-clk.h
> @@ -81,148 +81,154 @@
> #define CLK_TOP_F_BUS_PLL2 42
> #define CLK_TOP_APLL1 43
> #define CLK_TOP_APLL1_D2 44
> -#define CLK_TOP_APLL1_D4 45
> -#define CLK_TOP_APLL1_D8 46
> -#define CLK_TOP_APLL1_D16 47
> -#define CLK_TOP_APLL2 48
> -#define CLK_TOP_APLL2_D2 49
> -#define CLK_TOP_APLL2_D4 50
> -#define CLK_TOP_APLL2_D8 51
> -#define CLK_TOP_APLL2_D16 52
> -#define CLK_TOP_LVDSPLL 53
> -#define CLK_TOP_LVDSPLL_D2 54
> -#define CLK_TOP_LVDSPLL_D4 55
> -#define CLK_TOP_LVDSPLL_D8 56
> -#define CLK_TOP_LVDSPLL2 57
> -#define CLK_TOP_LVDSPLL2_D2 58
> -#define CLK_TOP_LVDSPLL2_D4 59
> -#define CLK_TOP_LVDSPLL2_D8 60
> -#define CLK_TOP_ETHERPLL_125M 61
> -#define CLK_TOP_ETHERPLL_50M 62
> -#define CLK_TOP_CVBS 63
> -#define CLK_TOP_CVBS_D2 64
> -#define CLK_TOP_SYS_26M 65
> -#define CLK_TOP_MMPLL 66
> -#define CLK_TOP_MMPLL_D2 67
> -#define CLK_TOP_VENCPLL 68
> -#define CLK_TOP_VENCPLL_D2 69
> -#define CLK_TOP_VCODECPLL 70
> -#define CLK_TOP_VCODECPLL_D2 71
> -#define CLK_TOP_TVDPLL 72
> -#define CLK_TOP_TVDPLL_D2 73
> -#define CLK_TOP_TVDPLL_D4 74
> -#define CLK_TOP_TVDPLL_D8 75
> -#define CLK_TOP_TVDPLL_429M 76
> -#define CLK_TOP_TVDPLL_429M_D2 77
> -#define CLK_TOP_TVDPLL_429M_D4 78
> -#define CLK_TOP_MSDCPLL 79
> -#define CLK_TOP_MSDCPLL_D2 80
> -#define CLK_TOP_MSDCPLL_D4 81
> -#define CLK_TOP_MSDCPLL2 82
> -#define CLK_TOP_MSDCPLL2_D2 83
> -#define CLK_TOP_MSDCPLL2_D4 84
> -#define CLK_TOP_CLK26M_D2 85
> -#define CLK_TOP_D2A_ULCLK_6P5M 86
> -#define CLK_TOP_VPLL3_DPIX 87
> -#define CLK_TOP_VPLL_DPIX 88
> -#define CLK_TOP_LTEPLL_FS26M 89
> -#define CLK_TOP_DMPLL 90
> -#define CLK_TOP_DSI0_LNTC 91
> -#define CLK_TOP_DSI1_LNTC 92
> -#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
> -#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
> -#define CLK_TOP_CLKRTC_EXT 95
> -#define CLK_TOP_CLKRTC_INT 96
> -#define CLK_TOP_CSI0 97
> -#define CLK_TOP_CVBSPLL 98
> -#define CLK_TOP_AXI_SEL 99
> -#define CLK_TOP_MEM_SEL 100
> -#define CLK_TOP_MM_SEL 101
> -#define CLK_TOP_PWM_SEL 102
> -#define CLK_TOP_VDEC_SEL 103
> -#define CLK_TOP_VENC_SEL 104
> -#define CLK_TOP_MFG_SEL 105
> -#define CLK_TOP_CAMTG_SEL 106
> -#define CLK_TOP_UART_SEL 107
> -#define CLK_TOP_SPI_SEL 108
> -#define CLK_TOP_USB20_SEL 109
> -#define CLK_TOP_USB30_SEL 110
> -#define CLK_TOP_MSDC50_0_HCLK_SEL 111
> -#define CLK_TOP_MSDC50_0_SEL 112
> -#define CLK_TOP_MSDC30_1_SEL 113
> -#define CLK_TOP_MSDC30_2_SEL 114
> -#define CLK_TOP_MSDC30_3_SEL 115
> -#define CLK_TOP_AUDIO_SEL 116
> -#define CLK_TOP_AUD_INTBUS_SEL 117
> -#define CLK_TOP_PMICSPI_SEL 118
> -#define CLK_TOP_DPILVDS1_SEL 119
> -#define CLK_TOP_ATB_SEL 120
> -#define CLK_TOP_NR_SEL 121
> -#define CLK_TOP_NFI2X_SEL 122
> -#define CLK_TOP_IRDA_SEL 123
> -#define CLK_TOP_CCI400_SEL 124
> -#define CLK_TOP_AUD_1_SEL 125
> -#define CLK_TOP_AUD_2_SEL 126
> -#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
> -#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
> -#define CLK_TOP_SCAM_SEL 129
> -#define CLK_TOP_NFIECC_SEL 130
> -#define CLK_TOP_PE2_MAC_P0_SEL 131
> -#define CLK_TOP_PE2_MAC_P1_SEL 132
> -#define CLK_TOP_DPILVDS_SEL 133
> -#define CLK_TOP_MSDC50_3_HCLK_SEL 134
> -#define CLK_TOP_HDCP_SEL 135
> -#define CLK_TOP_HDCP_24M_SEL 136
> -#define CLK_TOP_RTC_SEL 137
> -#define CLK_TOP_SPINOR_SEL 138
> -#define CLK_TOP_APLL_SEL 139
> -#define CLK_TOP_APLL2_SEL 140
> -#define CLK_TOP_A1SYS_HP_SEL 141
> -#define CLK_TOP_A2SYS_HP_SEL 142
> -#define CLK_TOP_ASM_L_SEL 143
> -#define CLK_TOP_ASM_M_SEL 144
> -#define CLK_TOP_ASM_H_SEL 145
> -#define CLK_TOP_I2SO1_SEL 146
> -#define CLK_TOP_I2SO2_SEL 147
> -#define CLK_TOP_I2SO3_SEL 148
> -#define CLK_TOP_TDMO0_SEL 149
> -#define CLK_TOP_TDMO1_SEL 150
> -#define CLK_TOP_I2SI1_SEL 151
> -#define CLK_TOP_I2SI2_SEL 152
> -#define CLK_TOP_I2SI3_SEL 153
> -#define CLK_TOP_ETHER_125M_SEL 154
> -#define CLK_TOP_ETHER_50M_SEL 155
> -#define CLK_TOP_JPGDEC_SEL 156
> -#define CLK_TOP_SPISLV_SEL 157
> -#define CLK_TOP_ETHER_50M_RMII_SEL 158
> -#define CLK_TOP_CAM2TG_SEL 159
> -#define CLK_TOP_DI_SEL 160
> -#define CLK_TOP_TVD_SEL 161
> -#define CLK_TOP_I2C_SEL 162
> -#define CLK_TOP_PWM_INFRA_SEL 163
> -#define CLK_TOP_MSDC0P_AES_SEL 164
> -#define CLK_TOP_CMSYS_SEL 165
> -#define CLK_TOP_GCPU_SEL 166
> -#define CLK_TOP_AUD_APLL1_SEL 167
> -#define CLK_TOP_AUD_APLL2_SEL 168
> -#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
> -#define CLK_TOP_APLL_DIV0 170
> -#define CLK_TOP_APLL_DIV1 171
> -#define CLK_TOP_APLL_DIV2 172
> -#define CLK_TOP_APLL_DIV3 173
> -#define CLK_TOP_APLL_DIV4 174
> -#define CLK_TOP_APLL_DIV5 175
> -#define CLK_TOP_APLL_DIV6 176
> -#define CLK_TOP_APLL_DIV7 177
> -#define CLK_TOP_APLL_DIV_PDN0 178
> -#define CLK_TOP_APLL_DIV_PDN1 179
> -#define CLK_TOP_APLL_DIV_PDN2 180
> -#define CLK_TOP_APLL_DIV_PDN3 181
> -#define CLK_TOP_APLL_DIV_PDN4 182
> -#define CLK_TOP_APLL_DIV_PDN5 183
> -#define CLK_TOP_APLL_DIV_PDN6 184
> -#define CLK_TOP_APLL_DIV_PDN7 185
> -#define CLK_TOP_NR_CLK 186
> +#define CLK_TOP_APLL1_D3 45
> +#define CLK_TOP_APLL1_D4 46
> +#define CLK_TOP_APLL1_D8 47
> +#define CLK_TOP_APLL1_D16 48
> +#define CLK_TOP_APLL2 49
> +#define CLK_TOP_APLL2_D2 50
> +#define CLK_TOP_APLL2_D4 51
> +#define CLK_TOP_APLL2_D8 52
> +#define CLK_TOP_APLL2_D16 53
> +#define CLK_TOP_LVDSPLL 54
> +#define CLK_TOP_LVDSPLL_D2 55
> +#define CLK_TOP_LVDSPLL_D4 56
> +#define CLK_TOP_LVDSPLL_D8 57
> +#define CLK_TOP_LVDSPLL2 58
> +#define CLK_TOP_LVDSPLL2_D2 59
> +#define CLK_TOP_LVDSPLL2_D4 60
> +#define CLK_TOP_LVDSPLL2_D8 61
> +#define CLK_TOP_ETHERPLL_125M 62
> +#define CLK_TOP_ETHERPLL_50M 63
> +#define CLK_TOP_CVBS 64
> +#define CLK_TOP_CVBS_D2 65
> +#define CLK_TOP_SYS_26M 66
> +#define CLK_TOP_MMPLL 67
> +#define CLK_TOP_MMPLL_D2 68
> +#define CLK_TOP_VENCPLL 69
> +#define CLK_TOP_VENCPLL_D2 70
> +#define CLK_TOP_VCODECPLL 71
> +#define CLK_TOP_VCODECPLL_D2 72
> +#define CLK_TOP_TVDPLL 73
> +#define CLK_TOP_TVDPLL_D2 74
> +#define CLK_TOP_TVDPLL_D4 75
> +#define CLK_TOP_TVDPLL_D8 76
> +#define CLK_TOP_TVDPLL_429M 77
> +#define CLK_TOP_TVDPLL_429M_D2 78
> +#define CLK_TOP_TVDPLL_429M_D4 79
> +#define CLK_TOP_MSDCPLL 80
> +#define CLK_TOP_MSDCPLL_D2 81
> +#define CLK_TOP_MSDCPLL_D4 82
> +#define CLK_TOP_MSDCPLL2 83
> +#define CLK_TOP_MSDCPLL2_D2 84
> +#define CLK_TOP_MSDCPLL2_D4 85
> +#define CLK_TOP_CLK26M_D2 86
> +#define CLK_TOP_D2A_ULCLK_6P5M 87
> +#define CLK_TOP_VPLL3_DPIX 88
> +#define CLK_TOP_VPLL_DPIX 89
> +#define CLK_TOP_LTEPLL_FS26M 90
> +#define CLK_TOP_DMPLL 91
> +#define CLK_TOP_DSI0_LNTC 92
> +#define CLK_TOP_DSI1_LNTC 93
> +#define CLK_TOP_LVDSTX3_CLKDIG_CTS 94
> +#define CLK_TOP_LVDSTX_CLKDIG_CTS 95
> +#define CLK_TOP_CLKRTC_EXT 96
> +#define CLK_TOP_CLKRTC_INT 97
> +#define CLK_TOP_CSI0 98
> +#define CLK_TOP_CVBSPLL 99
> +#define CLK_TOP_AXI_SEL 100
> +#define CLK_TOP_MEM_SEL 101
> +#define CLK_TOP_MM_SEL 102
> +#define CLK_TOP_PWM_SEL 103
> +#define CLK_TOP_VDEC_SEL 104
> +#define CLK_TOP_VENC_SEL 105
> +#define CLK_TOP_MFG_SEL 106
> +#define CLK_TOP_CAMTG_SEL 107
> +#define CLK_TOP_UART_SEL 108
> +#define CLK_TOP_SPI_SEL 109
> +#define CLK_TOP_USB20_SEL 110
> +#define CLK_TOP_USB30_SEL 111
> +#define CLK_TOP_MSDC50_0_HCLK_SEL 112
> +#define CLK_TOP_MSDC50_0_SEL 113
> +#define CLK_TOP_MSDC30_1_SEL 114
> +#define CLK_TOP_MSDC30_2_SEL 115
> +#define CLK_TOP_MSDC30_3_SEL 116
> +#define CLK_TOP_AUDIO_SEL 117
> +#define CLK_TOP_AUD_INTBUS_SEL 118
> +#define CLK_TOP_PMICSPI_SEL 119
> +#define CLK_TOP_DPILVDS1_SEL 120
> +#define CLK_TOP_ATB_SEL 121
> +#define CLK_TOP_NR_SEL 122
> +#define CLK_TOP_NFI2X_SEL 123
> +#define CLK_TOP_IRDA_SEL 124
> +#define CLK_TOP_CCI400_SEL 125
> +#define CLK_TOP_AUD_1_SEL 126
> +#define CLK_TOP_AUD_2_SEL 127
> +#define CLK_TOP_MEM_MFG_IN_AS_SEL 128
> +#define CLK_TOP_AXI_MFG_IN_AS_SEL 129
> +#define CLK_TOP_SCAM_SEL 130
> +#define CLK_TOP_NFIECC_SEL 131
> +#define CLK_TOP_PE2_MAC_P0_SEL 132
> +#define CLK_TOP_PE2_MAC_P1_SEL 133
> +#define CLK_TOP_DPILVDS_SEL 134
> +#define CLK_TOP_MSDC50_3_HCLK_SEL 135
> +#define CLK_TOP_HDCP_SEL 136
> +#define CLK_TOP_HDCP_24M_SEL 137
> +#define CLK_TOP_RTC_SEL 138
> +#define CLK_TOP_SPINOR_SEL 139
> +#define CLK_TOP_APLL_SEL 140
> +#define CLK_TOP_APLL2_SEL 141
> +#define CLK_TOP_A1SYS_HP_SEL 142
> +#define CLK_TOP_A2SYS_HP_SEL 143
> +#define CLK_TOP_ASM_L_SEL 144
> +#define CLK_TOP_ASM_M_SEL 145
> +#define CLK_TOP_ASM_H_SEL 146
> +#define CLK_TOP_I2SO1_SEL 147
> +#define CLK_TOP_I2SO2_SEL 148
> +#define CLK_TOP_I2SO3_SEL 149
> +#define CLK_TOP_TDMO0_SEL 150
> +#define CLK_TOP_TDMO1_SEL 151
> +#define CLK_TOP_I2SI1_SEL 152
> +#define CLK_TOP_I2SI2_SEL 153
> +#define CLK_TOP_I2SI3_SEL 154
> +#define CLK_TOP_ETHER_125M_SEL 155
> +#define CLK_TOP_ETHER_50M_SEL 156
> +#define CLK_TOP_JPGDEC_SEL 157
> +#define CLK_TOP_SPISLV_SEL 158
> +#define CLK_TOP_ETHER_50M_RMII_SEL 159
> +#define CLK_TOP_CAM2TG_SEL 160
> +#define CLK_TOP_DI_SEL 161
> +#define CLK_TOP_TVD_SEL 162
> +#define CLK_TOP_I2C_SEL 163
> +#define CLK_TOP_PWM_INFRA_SEL 164
> +#define CLK_TOP_MSDC0P_AES_SEL 165
> +#define CLK_TOP_CMSYS_SEL 166
> +#define CLK_TOP_GCPU_SEL 167
> +#define CLK_TOP_AUD_APLL1_SEL 168
> +#define CLK_TOP_AUD_APLL2_SEL 169
> +#define CLK_TOP_APLL1_REF_SEL 170
> +#define CLK_TOP_APLL2_REF_SEL 171
> +#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 172
> +#define CLK_TOP_APLL_DIV0 173
> +#define CLK_TOP_APLL_DIV1 174
> +#define CLK_TOP_APLL_DIV2 175
> +#define CLK_TOP_APLL_DIV3 176
> +#define CLK_TOP_APLL_DIV4 177
> +#define CLK_TOP_APLL_DIV5 178
> +#define CLK_TOP_APLL_DIV6 179
> +#define CLK_TOP_APLL_DIV7 180
> +#define CLK_TOP_APLL_DIV_PDN0 181
> +#define CLK_TOP_APLL_DIV_PDN1 182
> +#define CLK_TOP_APLL_DIV_PDN2 183
> +#define CLK_TOP_APLL_DIV_PDN3 184
> +#define CLK_TOP_APLL_DIV_PDN4 185
> +#define CLK_TOP_APLL_DIV_PDN5 186
> +#define CLK_TOP_APLL_DIV_PDN6 187
> +#define CLK_TOP_APLL_DIV_PDN7 188
> +#define CLK_TOP_NFI2X_EN 189
> +#define CLK_TOP_NFIECC_EN 190
> +#define CLK_TOP_NFI1X_CK_EN 191
> +#define CLK_TOP_NR_CLK 192
>
> /* INFRACFG */
>
> @@ -281,7 +287,9 @@
> #define CLK_PERI_MSDC30_3_EN 41
> #define CLK_PERI_MSDC50_0_HCLK_EN 42
> #define CLK_PERI_MSDC50_3_HCLK_EN 43
> -#define CLK_PERI_NR_CLK 44
> +#define CLK_PERI_MSDC30_0_QTR_EN 44
> +#define CLK_PERI_MSDC30_3_QTR_EN 45
> +#define CLK_PERI_NR_CLK 46
>
> /* MCUCFG */
>
> --
> 2.12.5
>
On Thu, 2018-03-01 at 16:45 -0600, Rob Herring wrote:
> On Thu, Feb 22, 2018 at 01:48:49PM +0800, Weiyi Lu wrote:
> > add new clocks according to ECO design change
> >
> > Signed-off-by: Weiyi Lu <[email protected]>
> > ---
> > include/dt-bindings/clock/mt2712-clk.h | 294 +++++++++++++++++----------------
> > 1 file changed, 151 insertions(+), 143 deletions(-)
>
> You can't just renumber your clocks. They are an ABI. Plus, for an ECO
> there can't have been that much change.
>
Hi Rob,
Got it! Is it correct if I append those new added clocks at the bottom
of each own subsystem? If the answer is yes, I'll resend a new version.
> >
> > diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
> > index 48a8e797a617..0690f24391b3 100644
> > --- a/include/dt-bindings/clock/mt2712-clk.h
> > +++ b/include/dt-bindings/clock/mt2712-clk.h
> > @@ -81,148 +81,154 @@
> > #define CLK_TOP_F_BUS_PLL2 42
> > #define CLK_TOP_APLL1 43
> > #define CLK_TOP_APLL1_D2 44
> > -#define CLK_TOP_APLL1_D4 45
> > -#define CLK_TOP_APLL1_D8 46
> > -#define CLK_TOP_APLL1_D16 47
> > -#define CLK_TOP_APLL2 48
> > -#define CLK_TOP_APLL2_D2 49
> > -#define CLK_TOP_APLL2_D4 50
> > -#define CLK_TOP_APLL2_D8 51
> > -#define CLK_TOP_APLL2_D16 52
> > -#define CLK_TOP_LVDSPLL 53
> > -#define CLK_TOP_LVDSPLL_D2 54
> > -#define CLK_TOP_LVDSPLL_D4 55
> > -#define CLK_TOP_LVDSPLL_D8 56
> > -#define CLK_TOP_LVDSPLL2 57
> > -#define CLK_TOP_LVDSPLL2_D2 58
> > -#define CLK_TOP_LVDSPLL2_D4 59
> > -#define CLK_TOP_LVDSPLL2_D8 60
> > -#define CLK_TOP_ETHERPLL_125M 61
> > -#define CLK_TOP_ETHERPLL_50M 62
> > -#define CLK_TOP_CVBS 63
> > -#define CLK_TOP_CVBS_D2 64
> > -#define CLK_TOP_SYS_26M 65
> > -#define CLK_TOP_MMPLL 66
> > -#define CLK_TOP_MMPLL_D2 67
> > -#define CLK_TOP_VENCPLL 68
> > -#define CLK_TOP_VENCPLL_D2 69
> > -#define CLK_TOP_VCODECPLL 70
> > -#define CLK_TOP_VCODECPLL_D2 71
> > -#define CLK_TOP_TVDPLL 72
> > -#define CLK_TOP_TVDPLL_D2 73
> > -#define CLK_TOP_TVDPLL_D4 74
> > -#define CLK_TOP_TVDPLL_D8 75
> > -#define CLK_TOP_TVDPLL_429M 76
> > -#define CLK_TOP_TVDPLL_429M_D2 77
> > -#define CLK_TOP_TVDPLL_429M_D4 78
> > -#define CLK_TOP_MSDCPLL 79
> > -#define CLK_TOP_MSDCPLL_D2 80
> > -#define CLK_TOP_MSDCPLL_D4 81
> > -#define CLK_TOP_MSDCPLL2 82
> > -#define CLK_TOP_MSDCPLL2_D2 83
> > -#define CLK_TOP_MSDCPLL2_D4 84
> > -#define CLK_TOP_CLK26M_D2 85
> > -#define CLK_TOP_D2A_ULCLK_6P5M 86
> > -#define CLK_TOP_VPLL3_DPIX 87
> > -#define CLK_TOP_VPLL_DPIX 88
> > -#define CLK_TOP_LTEPLL_FS26M 89
> > -#define CLK_TOP_DMPLL 90
> > -#define CLK_TOP_DSI0_LNTC 91
> > -#define CLK_TOP_DSI1_LNTC 92
> > -#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
> > -#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
> > -#define CLK_TOP_CLKRTC_EXT 95
> > -#define CLK_TOP_CLKRTC_INT 96
> > -#define CLK_TOP_CSI0 97
> > -#define CLK_TOP_CVBSPLL 98
> > -#define CLK_TOP_AXI_SEL 99
> > -#define CLK_TOP_MEM_SEL 100
> > -#define CLK_TOP_MM_SEL 101
> > -#define CLK_TOP_PWM_SEL 102
> > -#define CLK_TOP_VDEC_SEL 103
> > -#define CLK_TOP_VENC_SEL 104
> > -#define CLK_TOP_MFG_SEL 105
> > -#define CLK_TOP_CAMTG_SEL 106
> > -#define CLK_TOP_UART_SEL 107
> > -#define CLK_TOP_SPI_SEL 108
> > -#define CLK_TOP_USB20_SEL 109
> > -#define CLK_TOP_USB30_SEL 110
> > -#define CLK_TOP_MSDC50_0_HCLK_SEL 111
> > -#define CLK_TOP_MSDC50_0_SEL 112
> > -#define CLK_TOP_MSDC30_1_SEL 113
> > -#define CLK_TOP_MSDC30_2_SEL 114
> > -#define CLK_TOP_MSDC30_3_SEL 115
> > -#define CLK_TOP_AUDIO_SEL 116
> > -#define CLK_TOP_AUD_INTBUS_SEL 117
> > -#define CLK_TOP_PMICSPI_SEL 118
> > -#define CLK_TOP_DPILVDS1_SEL 119
> > -#define CLK_TOP_ATB_SEL 120
> > -#define CLK_TOP_NR_SEL 121
> > -#define CLK_TOP_NFI2X_SEL 122
> > -#define CLK_TOP_IRDA_SEL 123
> > -#define CLK_TOP_CCI400_SEL 124
> > -#define CLK_TOP_AUD_1_SEL 125
> > -#define CLK_TOP_AUD_2_SEL 126
> > -#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
> > -#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
> > -#define CLK_TOP_SCAM_SEL 129
> > -#define CLK_TOP_NFIECC_SEL 130
> > -#define CLK_TOP_PE2_MAC_P0_SEL 131
> > -#define CLK_TOP_PE2_MAC_P1_SEL 132
> > -#define CLK_TOP_DPILVDS_SEL 133
> > -#define CLK_TOP_MSDC50_3_HCLK_SEL 134
> > -#define CLK_TOP_HDCP_SEL 135
> > -#define CLK_TOP_HDCP_24M_SEL 136
> > -#define CLK_TOP_RTC_SEL 137
> > -#define CLK_TOP_SPINOR_SEL 138
> > -#define CLK_TOP_APLL_SEL 139
> > -#define CLK_TOP_APLL2_SEL 140
> > -#define CLK_TOP_A1SYS_HP_SEL 141
> > -#define CLK_TOP_A2SYS_HP_SEL 142
> > -#define CLK_TOP_ASM_L_SEL 143
> > -#define CLK_TOP_ASM_M_SEL 144
> > -#define CLK_TOP_ASM_H_SEL 145
> > -#define CLK_TOP_I2SO1_SEL 146
> > -#define CLK_TOP_I2SO2_SEL 147
> > -#define CLK_TOP_I2SO3_SEL 148
> > -#define CLK_TOP_TDMO0_SEL 149
> > -#define CLK_TOP_TDMO1_SEL 150
> > -#define CLK_TOP_I2SI1_SEL 151
> > -#define CLK_TOP_I2SI2_SEL 152
> > -#define CLK_TOP_I2SI3_SEL 153
> > -#define CLK_TOP_ETHER_125M_SEL 154
> > -#define CLK_TOP_ETHER_50M_SEL 155
> > -#define CLK_TOP_JPGDEC_SEL 156
> > -#define CLK_TOP_SPISLV_SEL 157
> > -#define CLK_TOP_ETHER_50M_RMII_SEL 158
> > -#define CLK_TOP_CAM2TG_SEL 159
> > -#define CLK_TOP_DI_SEL 160
> > -#define CLK_TOP_TVD_SEL 161
> > -#define CLK_TOP_I2C_SEL 162
> > -#define CLK_TOP_PWM_INFRA_SEL 163
> > -#define CLK_TOP_MSDC0P_AES_SEL 164
> > -#define CLK_TOP_CMSYS_SEL 165
> > -#define CLK_TOP_GCPU_SEL 166
> > -#define CLK_TOP_AUD_APLL1_SEL 167
> > -#define CLK_TOP_AUD_APLL2_SEL 168
> > -#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
> > -#define CLK_TOP_APLL_DIV0 170
> > -#define CLK_TOP_APLL_DIV1 171
> > -#define CLK_TOP_APLL_DIV2 172
> > -#define CLK_TOP_APLL_DIV3 173
> > -#define CLK_TOP_APLL_DIV4 174
> > -#define CLK_TOP_APLL_DIV5 175
> > -#define CLK_TOP_APLL_DIV6 176
> > -#define CLK_TOP_APLL_DIV7 177
> > -#define CLK_TOP_APLL_DIV_PDN0 178
> > -#define CLK_TOP_APLL_DIV_PDN1 179
> > -#define CLK_TOP_APLL_DIV_PDN2 180
> > -#define CLK_TOP_APLL_DIV_PDN3 181
> > -#define CLK_TOP_APLL_DIV_PDN4 182
> > -#define CLK_TOP_APLL_DIV_PDN5 183
> > -#define CLK_TOP_APLL_DIV_PDN6 184
> > -#define CLK_TOP_APLL_DIV_PDN7 185
> > -#define CLK_TOP_NR_CLK 186
> > +#define CLK_TOP_APLL1_D3 45
> > +#define CLK_TOP_APLL1_D4 46
> > +#define CLK_TOP_APLL1_D8 47
> > +#define CLK_TOP_APLL1_D16 48
> > +#define CLK_TOP_APLL2 49
> > +#define CLK_TOP_APLL2_D2 50
> > +#define CLK_TOP_APLL2_D4 51
> > +#define CLK_TOP_APLL2_D8 52
> > +#define CLK_TOP_APLL2_D16 53
> > +#define CLK_TOP_LVDSPLL 54
> > +#define CLK_TOP_LVDSPLL_D2 55
> > +#define CLK_TOP_LVDSPLL_D4 56
> > +#define CLK_TOP_LVDSPLL_D8 57
> > +#define CLK_TOP_LVDSPLL2 58
> > +#define CLK_TOP_LVDSPLL2_D2 59
> > +#define CLK_TOP_LVDSPLL2_D4 60
> > +#define CLK_TOP_LVDSPLL2_D8 61
> > +#define CLK_TOP_ETHERPLL_125M 62
> > +#define CLK_TOP_ETHERPLL_50M 63
> > +#define CLK_TOP_CVBS 64
> > +#define CLK_TOP_CVBS_D2 65
> > +#define CLK_TOP_SYS_26M 66
> > +#define CLK_TOP_MMPLL 67
> > +#define CLK_TOP_MMPLL_D2 68
> > +#define CLK_TOP_VENCPLL 69
> > +#define CLK_TOP_VENCPLL_D2 70
> > +#define CLK_TOP_VCODECPLL 71
> > +#define CLK_TOP_VCODECPLL_D2 72
> > +#define CLK_TOP_TVDPLL 73
> > +#define CLK_TOP_TVDPLL_D2 74
> > +#define CLK_TOP_TVDPLL_D4 75
> > +#define CLK_TOP_TVDPLL_D8 76
> > +#define CLK_TOP_TVDPLL_429M 77
> > +#define CLK_TOP_TVDPLL_429M_D2 78
> > +#define CLK_TOP_TVDPLL_429M_D4 79
> > +#define CLK_TOP_MSDCPLL 80
> > +#define CLK_TOP_MSDCPLL_D2 81
> > +#define CLK_TOP_MSDCPLL_D4 82
> > +#define CLK_TOP_MSDCPLL2 83
> > +#define CLK_TOP_MSDCPLL2_D2 84
> > +#define CLK_TOP_MSDCPLL2_D4 85
> > +#define CLK_TOP_CLK26M_D2 86
> > +#define CLK_TOP_D2A_ULCLK_6P5M 87
> > +#define CLK_TOP_VPLL3_DPIX 88
> > +#define CLK_TOP_VPLL_DPIX 89
> > +#define CLK_TOP_LTEPLL_FS26M 90
> > +#define CLK_TOP_DMPLL 91
> > +#define CLK_TOP_DSI0_LNTC 92
> > +#define CLK_TOP_DSI1_LNTC 93
> > +#define CLK_TOP_LVDSTX3_CLKDIG_CTS 94
> > +#define CLK_TOP_LVDSTX_CLKDIG_CTS 95
> > +#define CLK_TOP_CLKRTC_EXT 96
> > +#define CLK_TOP_CLKRTC_INT 97
> > +#define CLK_TOP_CSI0 98
> > +#define CLK_TOP_CVBSPLL 99
> > +#define CLK_TOP_AXI_SEL 100
> > +#define CLK_TOP_MEM_SEL 101
> > +#define CLK_TOP_MM_SEL 102
> > +#define CLK_TOP_PWM_SEL 103
> > +#define CLK_TOP_VDEC_SEL 104
> > +#define CLK_TOP_VENC_SEL 105
> > +#define CLK_TOP_MFG_SEL 106
> > +#define CLK_TOP_CAMTG_SEL 107
> > +#define CLK_TOP_UART_SEL 108
> > +#define CLK_TOP_SPI_SEL 109
> > +#define CLK_TOP_USB20_SEL 110
> > +#define CLK_TOP_USB30_SEL 111
> > +#define CLK_TOP_MSDC50_0_HCLK_SEL 112
> > +#define CLK_TOP_MSDC50_0_SEL 113
> > +#define CLK_TOP_MSDC30_1_SEL 114
> > +#define CLK_TOP_MSDC30_2_SEL 115
> > +#define CLK_TOP_MSDC30_3_SEL 116
> > +#define CLK_TOP_AUDIO_SEL 117
> > +#define CLK_TOP_AUD_INTBUS_SEL 118
> > +#define CLK_TOP_PMICSPI_SEL 119
> > +#define CLK_TOP_DPILVDS1_SEL 120
> > +#define CLK_TOP_ATB_SEL 121
> > +#define CLK_TOP_NR_SEL 122
> > +#define CLK_TOP_NFI2X_SEL 123
> > +#define CLK_TOP_IRDA_SEL 124
> > +#define CLK_TOP_CCI400_SEL 125
> > +#define CLK_TOP_AUD_1_SEL 126
> > +#define CLK_TOP_AUD_2_SEL 127
> > +#define CLK_TOP_MEM_MFG_IN_AS_SEL 128
> > +#define CLK_TOP_AXI_MFG_IN_AS_SEL 129
> > +#define CLK_TOP_SCAM_SEL 130
> > +#define CLK_TOP_NFIECC_SEL 131
> > +#define CLK_TOP_PE2_MAC_P0_SEL 132
> > +#define CLK_TOP_PE2_MAC_P1_SEL 133
> > +#define CLK_TOP_DPILVDS_SEL 134
> > +#define CLK_TOP_MSDC50_3_HCLK_SEL 135
> > +#define CLK_TOP_HDCP_SEL 136
> > +#define CLK_TOP_HDCP_24M_SEL 137
> > +#define CLK_TOP_RTC_SEL 138
> > +#define CLK_TOP_SPINOR_SEL 139
> > +#define CLK_TOP_APLL_SEL 140
> > +#define CLK_TOP_APLL2_SEL 141
> > +#define CLK_TOP_A1SYS_HP_SEL 142
> > +#define CLK_TOP_A2SYS_HP_SEL 143
> > +#define CLK_TOP_ASM_L_SEL 144
> > +#define CLK_TOP_ASM_M_SEL 145
> > +#define CLK_TOP_ASM_H_SEL 146
> > +#define CLK_TOP_I2SO1_SEL 147
> > +#define CLK_TOP_I2SO2_SEL 148
> > +#define CLK_TOP_I2SO3_SEL 149
> > +#define CLK_TOP_TDMO0_SEL 150
> > +#define CLK_TOP_TDMO1_SEL 151
> > +#define CLK_TOP_I2SI1_SEL 152
> > +#define CLK_TOP_I2SI2_SEL 153
> > +#define CLK_TOP_I2SI3_SEL 154
> > +#define CLK_TOP_ETHER_125M_SEL 155
> > +#define CLK_TOP_ETHER_50M_SEL 156
> > +#define CLK_TOP_JPGDEC_SEL 157
> > +#define CLK_TOP_SPISLV_SEL 158
> > +#define CLK_TOP_ETHER_50M_RMII_SEL 159
> > +#define CLK_TOP_CAM2TG_SEL 160
> > +#define CLK_TOP_DI_SEL 161
> > +#define CLK_TOP_TVD_SEL 162
> > +#define CLK_TOP_I2C_SEL 163
> > +#define CLK_TOP_PWM_INFRA_SEL 164
> > +#define CLK_TOP_MSDC0P_AES_SEL 165
> > +#define CLK_TOP_CMSYS_SEL 166
> > +#define CLK_TOP_GCPU_SEL 167
> > +#define CLK_TOP_AUD_APLL1_SEL 168
> > +#define CLK_TOP_AUD_APLL2_SEL 169
> > +#define CLK_TOP_APLL1_REF_SEL 170
> > +#define CLK_TOP_APLL2_REF_SEL 171
> > +#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 172
> > +#define CLK_TOP_APLL_DIV0 173
> > +#define CLK_TOP_APLL_DIV1 174
> > +#define CLK_TOP_APLL_DIV2 175
> > +#define CLK_TOP_APLL_DIV3 176
> > +#define CLK_TOP_APLL_DIV4 177
> > +#define CLK_TOP_APLL_DIV5 178
> > +#define CLK_TOP_APLL_DIV6 179
> > +#define CLK_TOP_APLL_DIV7 180
> > +#define CLK_TOP_APLL_DIV_PDN0 181
> > +#define CLK_TOP_APLL_DIV_PDN1 182
> > +#define CLK_TOP_APLL_DIV_PDN2 183
> > +#define CLK_TOP_APLL_DIV_PDN3 184
> > +#define CLK_TOP_APLL_DIV_PDN4 185
> > +#define CLK_TOP_APLL_DIV_PDN5 186
> > +#define CLK_TOP_APLL_DIV_PDN6 187
> > +#define CLK_TOP_APLL_DIV_PDN7 188
> > +#define CLK_TOP_NFI2X_EN 189
> > +#define CLK_TOP_NFIECC_EN 190
> > +#define CLK_TOP_NFI1X_CK_EN 191
> > +#define CLK_TOP_NR_CLK 192
> >
> > /* INFRACFG */
> >
> > @@ -281,7 +287,9 @@
> > #define CLK_PERI_MSDC30_3_EN 41
> > #define CLK_PERI_MSDC50_0_HCLK_EN 42
> > #define CLK_PERI_MSDC50_3_HCLK_EN 43
> > -#define CLK_PERI_NR_CLK 44
> > +#define CLK_PERI_MSDC30_0_QTR_EN 44
> > +#define CLK_PERI_MSDC30_3_QTR_EN 45
> > +#define CLK_PERI_NR_CLK 46
> >
> > /* MCUCFG */
> >
> > --
> > 2.12.5
> >
On 03/02/2018 03:23 AM, Weiyi Lu wrote:
> On Thu, 2018-03-01 at 16:45 -0600, Rob Herring wrote:
>> On Thu, Feb 22, 2018 at 01:48:49PM +0800, Weiyi Lu wrote:
>>> add new clocks according to ECO design change
>>>
>>> Signed-off-by: Weiyi Lu <[email protected]>
>>> ---
>>> include/dt-bindings/clock/mt2712-clk.h | 294 +++++++++++++++++----------------
>>> 1 file changed, 151 insertions(+), 143 deletions(-)
>>
>> You can't just renumber your clocks. They are an ABI. Plus, for an ECO
>> there can't have been that much change.
>>
> Hi Rob,
> Got it! Is it correct if I append those new added clocks at the bottom
> of each own subsystem? If the answer is yes, I'll resend a new version.
Yes, that will work. Please do that and resubmit.
Thanks,
Matthias