From: Honghui Zhang <[email protected]>
MediaTek's PCIe host controller has two generation HWs, the new
generation HW has two root ports, it shares most probing flow with the
legacy controller. But the read/write config space logical is different
from the legacy controller. The per-port register must be touched for
read/write config space, And the per-port register base are in separate
address space.
This patchset abstract the common probing flow, and add support for the
new generation controller.
Changes since v2:
- Split the Gen2 training change to a separate patch.
- Simplify the config_read/write logical and get rid of mtk_pcie_find_port.
- Using bus->sysdata to simplify the code.
- Rebase to commit 65b83b13204a ("PCI: mediatek: Explicitly request exclusive
reset control")[1].
- Fix some misspells.
- Add review tags in commit message.
Changes since v1:
- Fix build warnings in arm arch.
- Using SoC specific compatible instead of generic compatible.
- Add devicetree binding example for mt7622.
- Unified the register define names with PCIE_ prefix.
- Cleanup some un-necessary condition determine when starup port.
- minor code cleanups.
[1] https://patchwork.kernel.org/patch/9852591/
Honghui Zhang (1):
PCI: mediatek: Add a structure to abstract the controller generations
Ryder Lee (5):
PCI: mediatek: Using readl_poll_timeout to wait Gen2 training
PCI: mediatek: switch to use platform_get_resource_byname()
dt-bindings: PCI: rename and cleanup MediaTek binding text
PCI: mediatek: Add new generation controller support
dt-bindings: PCI: add support for new generation controller
.../bindings/pci/mediatek,mt7623-pcie.txt | 130 -----
.../devicetree/bindings/pci/mediatek-pcie.txt | 284 ++++++++++
drivers/pci/host/Kconfig | 5 +-
drivers/pci/host/pcie-mediatek.c | 571 +++++++++++++++++++--
4 files changed, 812 insertions(+), 178 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
--
2.6.4
From: Ryder Lee <[email protected]>
In order to accommodate other SoC generations, this patch updates filename
to make it more generic, regroups specific properties by SoCs, and removes
redundant descriptions.
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Honghui Zhang <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
...{mediatek,mt7623-pcie.txt => mediatek-pcie.txt} | 32 +++++++++++-----------
1 file changed, 16 insertions(+), 16 deletions(-)
rename Documentation/devicetree/bindings/pci/{mediatek,mt7623-pcie.txt => mediatek-pcie.txt} (90%)
diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
similarity index 90%
rename from Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
rename to Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index fe80dda..0fdcb15 100644
--- a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -1,18 +1,13 @@
-MediaTek Gen2 PCIe controller which is available on MT7623 series SoCs
-
-PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
-ports supports a Gen2 1-lane Link and has PIPE interface to PHY.
+MediaTek Gen2 PCIe controller
Required properties:
-- compatible: Should contain "mediatek,mt7623-pcie".
+- compatible: Should contain one of the following strings:
+ "mediatek,mt2701-pcie"
+ "mediatek,mt7623-pcie"
- device_type: Must be "pci"
- reg: Base addresses and lengths of the PCIe controller.
- #address-cells: Address representation for root ports (must be 3)
- #size-cells: Size representation for root ports (must be 2)
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
@@ -20,12 +15,6 @@ Required properties:
- sys_ck0 :for clock of Port0
- sys_ck1 :for clock of Port1
- sys_ck2 :for clock of Port2
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - pcie-rst0 :port0 reset
- - pcie-rst1 :port1 reset
- - pcie-rst2 :port2 reset
- phys: List of PHY specifiers (used by generic PHY framework).
- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
@@ -34,6 +23,16 @@ Required properties:
- bus-range: Range of bus numbers associated with this controller.
- ranges: Ranges for the PCI memory and I/O regions.
+Required properties for MT7623/MT2701:
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+ Please refer to the standard PCI bus binding document for a more detailed
+ explanation.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
+ number of root ports.
+
In addition, the device tree node must have sub-nodes describing each
PCIe port interface, having the following mandatory properties:
@@ -85,7 +84,8 @@ Examples:
<&hifsys MT2701_HIFSYS_PCIE1_RST>,
<&hifsys MT2701_HIFSYS_PCIE2_RST>;
reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
- phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
+ <&pcie2_phy PHY_TYPE_PCIE>;
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
bus-range = <0x00 0xff>;
--
2.6.4
From: Ryder Lee <[email protected]>
This is a transitional patch. We currently use platfarm_get_resource() for
retrieving the IOMEM resources, but there might be some chips don't have
subsys/shared registers part, which depends on platform design, and these
will be introduced in further patches.
Switch this function to use the platform_get_resource_byname() so that the
binding can be agnostic of the resource order.
Signed-off-by: Ryder Lee <[email protected]>
---
drivers/pci/host/pcie-mediatek.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index 5d7f62e..63d300f 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -295,7 +295,8 @@ static int mtk_pcie_parse_ports(struct mtk_pcie *pcie,
return err;
}
- regs = platform_get_resource(pdev, IORESOURCE_MEM, index + 1);
+ snprintf(name, sizeof(name), "port%d", index);
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
port->base = devm_ioremap_resource(dev, regs);
if (IS_ERR(port->base)) {
dev_err(dev, "failed to map port%d base\n", index);
@@ -336,12 +337,14 @@ static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
struct resource *regs;
int err;
- /* get shared registers */
- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- pcie->base = devm_ioremap_resource(dev, regs);
- if (IS_ERR(pcie->base)) {
- dev_err(dev, "failed to map shared register\n");
- return PTR_ERR(pcie->base);
+ /* get shared registers, which are optional */
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
+ if (regs) {
+ pcie->base = devm_ioremap_resource(dev, regs);
+ if (IS_ERR(pcie->base)) {
+ dev_err(dev, "failed to map shared register\n");
+ return PTR_ERR(pcie->base);
+ }
}
pcie->free_ck = devm_clk_get(dev, "free_ck");
--
2.6.4
From: Ryder Lee <[email protected]>
MediaTek's PCIe host controller has two generation HWs, the new
generation HW has two root ports, it shares most probing flow with the
legacy controller. But the read/write config space logical is different
from the legacy controller. The per-port register must be touched for
read/write config space, And the per-port register base are in separate
address space.
Add support for new Gen2 controller which can be found on MT7622/MT2712.
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Honghui Zhang <[email protected]>
---
drivers/pci/host/Kconfig | 5 +-
drivers/pci/host/pcie-mediatek.c | 473 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 471 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 89d61c2..5b1ae9f 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -182,14 +182,13 @@ config PCIE_ROCKCHIP
config PCIE_MEDIATEK
bool "MediaTek PCIe controller"
- depends on ARM && (ARCH_MEDIATEK || COMPILE_TEST)
+ depends on (ARM || ARM64) && (ARCH_MEDIATEK || COMPILE_TEST)
depends on OF
depends on PCI
select PCIEPORTBUS
help
Say Y here if you want to enable PCIe controller support on
- MT7623 series SoCs. There is one single root complex with 3 root
- ports available. Each port supports Gen2 lane x1.
+ MediaTek SoCs.
config PCIE_TANGO_SMP8759
bool "Tango SMP8759 PCIe controller (DANGEROUS)"
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index 63d300f..91eb53b 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -3,6 +3,7 @@
*
* Copyright (c) 2017 MediaTek Inc.
* Author: Ryder Lee <[email protected]>
+ * Honghui Zhang <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -17,6 +18,8 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
@@ -64,16 +67,77 @@
#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
+/* PCIe V2 share registers */
+#define PCIE_SYS_CFG_V2 0x0
+#define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
+#define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
+
+/* PCIe V2 per-port registers */
+#define PCIE_INT_MASK 0x420
+#define INTX_MASK GENMASK(19, 16)
+#define INTX_SHIFT 16
+#define INTX_NUM 4
+#define PCIE_INT_STATUS 0x424
+
+#define PCIE_AHB_TRANS_BASE0_L 0x438
+#define PCIE_AHB_TRANS_BASE0_H 0x43c
+#define AHB2PCIE_BASEL(x) ((x) & GENMASK(31, 0))
+#define AHB2PCIE_BASEH(x) (((u64)(x) >> 32) & GENMASK(31, 0))
+#define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
+#define PCIE_AXI_WINDOW0 0x448
+#define WIN_ENABLE BIT(7)
+
+/* PCIe V2 Configuration Transaction Header */
+#define PCIE_CFG_HEADER0 0x460
+#define PCIE_CFG_HEADER1 0x464
+#define PCIE_CFG_HEADER2 0x468
+#define PCIE_CFG_WDATA 0x470
+#define PCIE_APP_TLP_REQ 0x488
+#define PCIE_CFG_RDATA 0x48c
+#define APP_CFG_REQ BIT(0)
+#define APP_CPL_STATUS GENMASK(7, 5)
+
+#define CFG_WRRD_TYPE_0 4
+#define CFG_WR_FMT 2
+#define CFG_RD_FMT 0
+
+#define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
+#define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
+#define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
+#define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
+#define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
+#define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
+#define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
+#define CFG_HEADER_DW0(type, fmt) \
+ (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
+#define CFG_HEADER_DW1(where, size) \
+ (GENMASK(((size) - 1), 0) << ((where) & 0x3))
+#define CFG_HEADER_DW2(regn, fun, dev, bus) \
+ (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
+ CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
+
+#define PCIE_RST_CTRL 0x510
+#define PCIE_PHY_RSTB BIT(0)
+#define PCIE_PIPE_SRSTB BIT(1)
+#define PCIE_MAC_SRSTB BIT(2)
+#define PCIE_CRSTB BIT(3)
+#define PCIE_PERSTB BIT(8)
+#define PCI_LINKDOWN_RST_EN GENMASK(15, 13)
+#define PCIE_LINK_STATUS_V2 0x804
+#define PCIE_PORT_LINKUP_V2 BIT(10)
+
struct mtk_pcie_port;
/**
* struct mtk_pcie_soc - differentiate between host generations
* @ops: pointer to configuration access functions
* @startup: pointer to controller setting functions
+ * @setup_irq: pointer to initialize IRQ functions
*/
struct mtk_pcie_soc {
struct pci_ops *ops;
int (*startup)(struct mtk_pcie_port *port);
+ int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
};
/**
@@ -82,10 +146,18 @@ struct mtk_pcie_soc {
* @list: port list
* @pcie: pointer to PCIe host info
* @reset: pointer to port reset control
- * @sys_ck: pointer to bus clock
- * @phy: pointer to phy control block
+ * @sys_ck: pointer to transaction/data link layer clock
+ * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
+ * and RC initiated MMIO access
+ * @axi_ck: pointer to application layer MMIO channel operating clock
+ * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
+ * when pcie_mac_ck/pcie_pipe_ck is turned off
+ * @obff_ck: pointer to OBFF functional block operating clock
+ * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
+ * @phy: pointer to PHY control block
* @lane: lane count
* @index: port index
+ * @irq_domain: legacy INTx IRQ domain
*/
struct mtk_pcie_port {
void __iomem *base;
@@ -93,9 +165,15 @@ struct mtk_pcie_port {
struct mtk_pcie *pcie;
struct reset_control *reset;
struct clk *sys_ck;
+ struct clk *ahb_ck;
+ struct clk *axi_ck;
+ struct clk *aux_ck;
+ struct clk *obff_ck;
+ struct clk *pipe_ck;
struct phy *phy;
u32 lane;
u32 index;
+ struct irq_domain *irq_domain;
};
/**
@@ -156,6 +234,12 @@ static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
phy_power_off(port->phy);
+ phy_exit(port->phy);
+ clk_disable_unprepare(port->pipe_ck);
+ clk_disable_unprepare(port->obff_ck);
+ clk_disable_unprepare(port->axi_ck);
+ clk_disable_unprepare(port->aux_ck);
+ clk_disable_unprepare(port->ahb_ck);
clk_disable_unprepare(port->sys_ck);
mtk_pcie_port_free(port);
}
@@ -163,6 +247,278 @@ static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
mtk_pcie_subsys_powerdown(pcie);
}
+static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
+{
+ u32 val;
+ int err;
+
+ err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
+ !(val & APP_CFG_REQ), 10,
+ 100 * USEC_PER_MSEC);
+ if (err)
+ return PCIBIOS_SET_FAILED;
+
+ if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
+ return PCIBIOS_SET_FAILED;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
+ int where, int size, u32 *val)
+{
+ int reg, shift = 8 * (where & 3);
+
+ /* Write PCIe Configuration Transaction Header for cfgrd */
+ writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
+ port->base + PCIE_CFG_HEADER0);
+ writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
+ writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
+ port->base + PCIE_CFG_HEADER2);
+
+ /* Trigger h/w to transmit Cfgrd TLP */
+ reg = readl(port->base + PCIE_APP_TLP_REQ);
+ writel(reg | APP_CFG_REQ, port->base + PCIE_APP_TLP_REQ);
+
+ /* Check completion status */
+ if (mtk_pcie_check_cfg_cpld(port))
+ return PCIBIOS_SET_FAILED;
+
+ /* Read cpld payload of Cfgrd */
+ *val = readl(port->base + PCIE_CFG_RDATA);
+
+ switch (size) {
+ case 4:
+ break;
+ case 3:
+ *val = (*val >> shift) & 0xffffff;
+ break;
+ case 2:
+ *val = (*val >> shift) & 0xffff;
+ break;
+ case 1:
+ *val = (*val >> shift) & 0xff;
+ break;
+ default:
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
+ int where, int size, u32 val)
+{
+ /* Write PCIe Configuration Transaction Header for Cfgwr */
+ writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
+ port->base + PCIE_CFG_HEADER0);
+ writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
+ writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
+ port->base + PCIE_CFG_HEADER2);
+
+ /* Write cfgwr data */
+ val = val << 8 * (where & 3);
+ writel(val, port->base + PCIE_CFG_WDATA);
+
+ /* Trigger h/w to transmit Cfgwr TLP */
+ val = readl(port->base + PCIE_APP_TLP_REQ);
+ val |= APP_CFG_REQ;
+ writel(val, port->base + PCIE_APP_TLP_REQ);
+
+ /* Check completion status */
+ return mtk_pcie_check_cfg_cpld(port);
+}
+
+static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct mtk_pcie_port *port = NULL, *iter, *tmp;
+ struct mtk_pcie *pcie = bus->sysdata;
+ u32 bn = bus->number;
+ int ret;
+
+ list_for_each_entry_safe(iter, tmp, &pcie->ports, list)
+ if (iter->index == PCI_SLOT(devfn)) {
+ port = iter;
+ break;
+ }
+
+ if (!port) {
+ *val = ~0;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+ ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
+ if (ret)
+ *val = ~0;
+
+ return ret;
+}
+
+static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ struct mtk_pcie_port *port = NULL, *iter, *tmp;
+ struct mtk_pcie *pcie = bus->sysdata;
+ u32 bn = bus->number;
+
+ list_for_each_entry_safe(iter, tmp, &pcie->ports, list)
+ if (iter->index == PCI_SLOT(devfn)) {
+ port = iter;
+ break;
+ }
+
+ if (!port)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
+}
+
+static struct pci_ops mtk_pcie_ops_v2 = {
+ .read = mtk_pcie_config_read,
+ .write = mtk_pcie_config_write,
+};
+
+static int mtk_pcie_startup_ports_v2(struct mtk_pcie_port *port)
+{
+ struct mtk_pcie *pcie = port->pcie;
+ struct resource *mem = &pcie->mem;
+ u32 val;
+ size_t size;
+ int err;
+
+ /* mt7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
+ if (pcie->base) {
+ val = readl(pcie->base + PCIE_SYS_CFG_V2);
+ val |= PCIE_CSR_LTSSM_EN(port->index) |
+ PCIE_CSR_ASPM_L1_EN(port->index);
+ writel(val, pcie->base + PCIE_SYS_CFG_V2);
+ }
+
+ /* Assert all reset signals */
+ writel(0, port->base + PCIE_RST_CTRL);
+
+ /*
+ * Enable PCIe link down reset, if link status changed from link up to
+ * link down, this will reset MAC control registers and configuration
+ * space.
+ */
+ writel(PCI_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
+
+ /* De-assert PHY, PE, PIPE, MAC and configuration reset */
+ val = readl(port->base + PCIE_RST_CTRL);
+ val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
+ PCIE_MAC_SRSTB | PCIE_CRSTB;
+ writel(val, port->base + PCIE_RST_CTRL);
+
+ /* PCIe v2.0 need at least 100ms delay to train from Gen1 to Gen2 */
+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
+ !!(val & PCIE_PORT_LINKUP_V2), 20,
+ 100 * USEC_PER_MSEC);
+ if (err)
+ return -ETIMEDOUT;
+
+ /* Set INTx mask */
+ val = readl(port->base + PCIE_INT_MASK);
+ val &= ~INTX_MASK;
+ writel(val, port->base + PCIE_INT_MASK);
+
+ /* Set AHB to PCIe translation windows */
+ size = mem->end - mem->start;
+ val = AHB2PCIE_BASEL(mem->start) | AHB2PCIE_SIZE(fls(size));
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
+
+ val = AHB2PCIE_BASEH(mem->start);
+ writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
+
+ /* Set PCIe to AXI translation memory space.*/
+ val = fls(0xffffffff) | WIN_ENABLE;
+ writel(val, port->base + PCIE_AXI_WINDOW0);
+
+ return 0;
+}
+
+static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
+ irq_set_chip_data(irq, domain->host_data);
+
+ return 0;
+}
+
+static const struct irq_domain_ops intx_domain_ops = {
+ .map = mtk_pcie_intx_map,
+};
+
+static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
+ struct device_node *node)
+{
+ struct device *dev = port->pcie->dev;
+ struct device_node *pcie_intc_node;
+
+ /* Setup INTx */
+ pcie_intc_node = of_get_next_child(node, NULL);
+ if (!pcie_intc_node) {
+ dev_err(dev, "No PCIe Intc node found\n");
+ return PTR_ERR(pcie_intc_node);
+ }
+
+ port->irq_domain = irq_domain_add_linear(pcie_intc_node, INTX_NUM,
+ &intx_domain_ops, port);
+ if (!port->irq_domain) {
+ dev_err(dev, "Failed to get INTx IRQ domain\n");
+ return PTR_ERR(port->irq_domain);
+ }
+
+ return 0;
+}
+
+static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
+{
+ struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
+ unsigned long status;
+ u32 virq;
+ u32 bit = INTX_SHIFT;
+
+ while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
+ for_each_set_bit_from(bit, &status, INTX_NUM + INTX_SHIFT) {
+ /* Clear the INTx */
+ writel(1 << bit, port->base + PCIE_INT_STATUS);
+ virq = irq_find_mapping(port->irq_domain,
+ bit - INTX_SHIFT);
+ generic_handle_irq(virq);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
+ struct device_node *node)
+{
+ struct mtk_pcie *pcie = port->pcie;
+ struct device *dev = pcie->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ int err, irq;
+
+ irq = platform_get_irq(pdev, port->index);
+ err = devm_request_irq(dev, irq, mtk_pcie_intr_handler,
+ IRQF_SHARED, "mtk-pcie", port);
+ if (err) {
+ dev_err(dev, "unable to request IRQ %d\n", irq);
+ return err;
+ }
+
+ err = mtk_pcie_init_irq_domain(port, node);
+ if (err) {
+ dev_err(dev, "failed to init PCIe legacy IRQ domain\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
unsigned int devfn, int where)
{
@@ -249,13 +605,49 @@ static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
err = clk_prepare_enable(port->sys_ck);
if (err) {
- dev_err(dev, "failed to enable port%d clock\n", port->index);
+ dev_err(dev, "failed to enable sys_ck%d\n", port->index);
goto err_sys_clk;
}
+ err = clk_prepare_enable(port->ahb_ck);
+ if (err) {
+ dev_err(dev, "failed to enable ahb_ck%d\n", port->index);
+ goto err_ahb_clk;
+ }
+
+ err = clk_prepare_enable(port->aux_ck);
+ if (err) {
+ dev_err(dev, "failed to enable aux_ck%d\n", port->index);
+ goto err_aux_clk;
+ }
+
+ err = clk_prepare_enable(port->axi_ck);
+ if (err) {
+ dev_err(dev, "failed to enable axi_ck%d\n", port->index);
+ goto err_axi_clk;
+ }
+
+ err = clk_prepare_enable(port->obff_ck);
+ if (err) {
+ dev_err(dev, "failed to enable obff_ck%d\n", port->index);
+ goto err_obff_clk;
+ }
+
+ err = clk_prepare_enable(port->pipe_ck);
+ if (err) {
+ dev_err(dev, "failed to enable pipe_ck%d\n", port->index);
+ goto err_pipe_clk;
+ }
+
reset_control_assert(port->reset);
reset_control_deassert(port->reset);
+ err = phy_init(port->phy);
+ if (err) {
+ dev_err(dev, "failed to initialize port%d phy\n", port->index);
+ goto err_phy_init;
+ }
+
err = phy_power_on(port->phy);
if (err) {
dev_err(dev, "failed to power on port%d phy\n", port->index);
@@ -269,6 +661,18 @@ static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
phy_power_off(port->phy);
err_phy_on:
+ phy_exit(port->phy);
+err_phy_init:
+ clk_disable_unprepare(port->pipe_ck);
+err_pipe_clk:
+ clk_disable_unprepare(port->obff_ck);
+err_obff_clk:
+ clk_disable_unprepare(port->axi_ck);
+err_axi_clk:
+ clk_disable_unprepare(port->aux_ck);
+err_aux_clk:
+ clk_disable_unprepare(port->ahb_ck);
+err_ahb_clk:
clk_disable_unprepare(port->sys_ck);
err_sys_clk:
mtk_pcie_port_free(port);
@@ -306,10 +710,56 @@ static int mtk_pcie_parse_ports(struct mtk_pcie *pcie,
snprintf(name, sizeof(name), "sys_ck%d", index);
port->sys_ck = devm_clk_get(dev, name);
if (IS_ERR(port->sys_ck)) {
- dev_err(dev, "failed to get port%d clock\n", index);
+ dev_err(dev, "failed to get sys_ck%d\n", index);
return PTR_ERR(port->sys_ck);
}
+ /* sys_ck might be divided into the following parts in some chips */
+ snprintf(name, sizeof(name), "ahb_ck%d", index);
+ port->ahb_ck = devm_clk_get(dev, name);
+ if (IS_ERR(port->ahb_ck)) {
+ if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ port->ahb_ck = NULL;
+ }
+
+ snprintf(name, sizeof(name), "axi_ck%d", index);
+ port->axi_ck = devm_clk_get(dev, name);
+ if (IS_ERR(port->axi_ck)) {
+ if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ port->axi_ck = NULL;
+ }
+
+ snprintf(name, sizeof(name), "aux_ck%d", index);
+ port->aux_ck = devm_clk_get(dev, name);
+ if (IS_ERR(port->aux_ck)) {
+ if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ port->aux_ck = NULL;
+ }
+
+ snprintf(name, sizeof(name), "obff_ck%d", index);
+ port->obff_ck = devm_clk_get(dev, name);
+ if (IS_ERR(port->obff_ck)) {
+ if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ port->obff_ck = NULL;
+ }
+
+ snprintf(name, sizeof(name), "pipe_ck%d", index);
+ port->pipe_ck = devm_clk_get(dev, name);
+ if (IS_ERR(port->pipe_ck)) {
+ if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ port->pipe_ck = NULL;
+ }
+
snprintf(name, sizeof(name), "pcie-rst%d", index);
port->reset = devm_reset_control_get_optional_exclusive(dev, name);
if (PTR_ERR(port->reset) == -EPROBE_DEFER)
@@ -324,6 +774,12 @@ static int mtk_pcie_parse_ports(struct mtk_pcie *pcie,
port->index = index;
port->pcie = pcie;
+ if (pcie->soc->setup_irq) {
+ err = pcie->soc->setup_irq(port, node);
+ if (err)
+ return err;
+ }
+
INIT_LIST_HEAD(&port->list);
list_add_tail(&port->list, &pcie->ports);
@@ -493,6 +949,7 @@ static int mtk_pcie_register_host(struct pci_host_bridge *host)
host->ops = pcie->soc->ops;
host->map_irq = of_irq_parse_and_map_pci;
host->swizzle_irq = pci_common_swizzle;
+ host->sysdata = pcie;
err = pci_scan_root_bus_bridge(host);
if (err < 0)
@@ -553,9 +1010,17 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
.startup = mtk_pcie_startup_ports,
};
+static const struct mtk_pcie_soc mtk_pcie_soc_v2 = {
+ .ops = &mtk_pcie_ops_v2,
+ .startup = mtk_pcie_startup_ports_v2,
+ .setup_irq = mtk_pcie_setup_irq,
+};
+
static const struct of_device_id mtk_pcie_ids[] = {
{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
+ { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_v2 },
+ { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_v2 },
{},
};
--
2.6.4
From: Ryder Lee <[email protected]>
Add support for MediaTek new generation controller and update related
properities.
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Honghui Zhang <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/pci/mediatek-pcie.txt | 168 ++++++++++++++++++++-
1 file changed, 161 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 0fdcb15..2e81742 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -3,18 +3,31 @@ MediaTek Gen2 PCIe controller
Required properties:
- compatible: Should contain one of the following strings:
"mediatek,mt2701-pcie"
+ "mediatek,mt2712-pcie"
+ "mediatek,mt7622-pcie"
"mediatek,mt7623-pcie"
- device_type: Must be "pci"
-- reg: Base addresses and lengths of the PCIe controller.
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource look-up.
- #address-cells: Address representation for root ports (must be 3)
- #size-cells: Size representation for root ports (must be 2)
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - free_ck :for reference clock of PCIe subsys
- - sys_ck0 :for clock of Port0
- - sys_ck1 :for clock of Port1
- - sys_ck2 :for clock of Port2
+- clock-names:
+ Mandatory entries:
+ - sys_ckN :transaction layer and data link layer clock
+ Required entries for MT2701/MT7623:
+ - free_ck :for reference clock of PCIe subsys
+ Required entries for MT2712/MT7622:
+ - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+ initiated MMIO access
+ Required entries for MT7622:
+ - axi_ckN :application layer MMIO channel operating clock
+ - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+ pcie_mac_ck/pcie_pipe_ck is turned off
+ - obff_ckN :OBFF functional block operating clock
+ - pipe_ckN :LTSSM and PHY/MAC layer operating clock
+ where N starting from 0 to one less than the number of root ports.
- phys: List of PHY specifiers (used by generic PHY framework).
- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
number of PHYs as specified in *phys* property.
@@ -33,6 +46,10 @@ Required properties for MT7623/MT2701:
- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
number of root ports.
+Required properties for MT2712/MT7622:
+-interrupts: A list of interrupt outputs of the controller, must have one
+ entry for each PCIe port
+
In addition, the device tree node must have sub-nodes describing each
PCIe port interface, having the following mandatory properties:
@@ -50,7 +67,7 @@ Required properties:
property is sufficient.
- num-lanes: Number of lanes to use for this port.
-Examples:
+Examples for MT7623:
hifsys: syscon@1a000000 {
compatible = "mediatek,mt7623-hifsys",
@@ -68,6 +85,7 @@ Examples:
<0 0x1a142000 0 0x1000>, /* Port0 registers */
<0 0x1a143000 0 0x1000>, /* Port1 registers */
<0 0x1a144000 0 0x1000>; /* Port2 registers */
+ reg-names = "subsys", "port0", "port1", "port2";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -128,3 +146,139 @@ Examples:
num-lanes = <1>;
};
};
+
+Examples for MT2712:
+ pcie: pcie@11700000 {
+ compatible = "mediatek,mt2712-pcie";
+ device_type = "pci";
+ reg = <0 0x11700000 0 0x1000>,
+ <0 0x112ff000 0 0x1000>;
+ reg-names = "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
+ <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
+ <&pericfg CLK_PERI_PCIE0>,
+ <&pericfg CLK_PERI_PCIE1>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+Examples for MT7622:
+ pcie: pcie@1a140000 {
+ compatible = "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0 0x1a140000 0 0x1000>,
+ <0 0x1a143000 0 0x1000>,
+ <0 0x1a145000 0 0x1000>;
+ reg-names = "subsys", "port0", "port1";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+ <&pciesys CLK_PCIE_P1_MAC_EN>,
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
+ <&pciesys CLK_PCIE_P1_AHB_EN>,
+ <&pciesys CLK_PCIE_P0_AUX_EN>,
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
+ <&pciesys CLK_PCIE_P0_AXI_EN>,
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
+ <&pciesys CLK_PCIE_P0_OBFF_EN>,
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
+ <&pciesys CLK_PCIE_P0_PIPE_EN>,
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
+ clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+ "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+ "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy0", "pcie-phy1";
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
+
+ pcie0: pcie@0,0 {
+ device_type = "pci";
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1,0 {
+ device_type = "pci";
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges;
+ num-lanes = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
--
2.6.4
From: Honghui Zhang <[email protected]>
Introduce a structure "mtk_pcie_soc" to abstract the differences between
controller generations, and the .startup() hook is used to encapsulate
some SoC-dependent related setting. In doing so, the common code which
will be reused by future chips.
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Honghui Zhang <[email protected]>
---
drivers/pci/host/pcie-mediatek.c | 31 ++++++++++++++++++++++++++-----
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index 0d46cda..5d7f62e 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -64,6 +64,18 @@
#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
+struct mtk_pcie_port;
+
+/**
+ * struct mtk_pcie_soc - differentiate between host generations
+ * @ops: pointer to configuration access functions
+ * @startup: pointer to controller setting functions
+ */
+struct mtk_pcie_soc {
+ struct pci_ops *ops;
+ int (*startup)(struct mtk_pcie_port *port);
+};
+
/**
* struct mtk_pcie_port - PCIe port information
* @base: IO mapped register base
@@ -97,6 +109,7 @@ struct mtk_pcie_port {
* @busn: bus range
* @offset: IO / Memory offset
* @ports: pointer to PCIe port information
+ * @soc: pointer to SoC-dependent operations
*/
struct mtk_pcie {
struct device *dev;
@@ -112,6 +125,7 @@ struct mtk_pcie {
resource_size_t io;
} offset;
struct list_head ports;
+ const struct mtk_pcie_soc *soc;
};
static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
@@ -229,7 +243,8 @@ static int mtk_pcie_startup_ports(struct mtk_pcie_port *port)
static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
{
- struct device *dev = port->pcie->dev;
+ struct mtk_pcie *pcie = port->pcie;
+ struct device *dev = pcie->dev;
int err;
err = clk_prepare_enable(port->sys_ck);
@@ -247,7 +262,7 @@ static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
goto err_phy_on;
}
- if (!mtk_pcie_startup_ports(port))
+ if (!pcie->soc->startup(port))
return;
dev_info(dev, "Port%d link down\n", port->index);
@@ -472,7 +487,7 @@ static int mtk_pcie_register_host(struct pci_host_bridge *host)
host->busnr = pcie->busn.start;
host->dev.parent = pcie->dev;
- host->ops = &mtk_pcie_ops;
+ host->ops = pcie->soc->ops;
host->map_irq = of_irq_parse_and_map_pci;
host->swizzle_irq = pci_common_swizzle;
@@ -505,6 +520,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
pcie = pci_host_bridge_priv(host);
pcie->dev = dev;
+ pcie->soc = of_device_get_match_data(dev);
platform_set_drvdata(pdev, pcie);
INIT_LIST_HEAD(&pcie->ports);
@@ -529,9 +545,14 @@ static int mtk_pcie_probe(struct platform_device *pdev)
return err;
}
+static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
+ .ops = &mtk_pcie_ops,
+ .startup = mtk_pcie_startup_ports,
+};
+
static const struct of_device_id mtk_pcie_ids[] = {
- { .compatible = "mediatek,mt7623-pcie"},
- { .compatible = "mediatek,mt2701-pcie"},
+ { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
+ { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
{},
};
--
2.6.4
From: Ryder Lee <[email protected]>
Wait Gen2 training by using readl_poll_timeout() calls, and simplify
the hardware assert logical by merge it into the new interface
mtk_pcie_startup_ports.
Signed-off-by: Ryder Lee <[email protected]>
Signed-off-by: Honghui Zhang <[email protected]>
---
drivers/pci/host/pcie-mediatek.c | 52 +++++++++++++++++-----------------------
1 file changed, 22 insertions(+), 30 deletions(-)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index 9c9f89b..0d46cda 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -16,6 +16,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_pci.h>
@@ -113,11 +114,6 @@ struct mtk_pcie {
struct list_head ports;
};
-static inline bool mtk_pcie_link_up(struct mtk_pcie_port *port)
-{
- return !!(readl(port->base + PCIE_LINK_STATUS) & PCIE_PORT_LINKUP);
-}
-
static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
{
struct device *dev = pcie->dev;
@@ -171,12 +167,30 @@ static struct pci_ops mtk_pcie_ops = {
.write = pci_generic_config_write,
};
-static void mtk_pcie_configure_rc(struct mtk_pcie_port *port)
+static int mtk_pcie_startup_ports(struct mtk_pcie_port *port)
{
struct mtk_pcie *pcie = port->pcie;
u32 func = PCI_FUNC(port->index << 3);
u32 slot = PCI_SLOT(port->index << 3);
u32 val;
+ int err;
+
+ /* assert port PERST_N */
+ val = readl(pcie->base + PCIE_SYS_CFG);
+ val |= PCIE_PORT_PERST(port->index);
+ writel(val, pcie->base + PCIE_SYS_CFG);
+
+ /* de-assert port PERST_N */
+ val = readl(pcie->base + PCIE_SYS_CFG);
+ val &= ~PCIE_PORT_PERST(port->index);
+ writel(val, pcie->base + PCIE_SYS_CFG);
+
+ /* 100ms timeout value should be enough for Gen1/2 training */
+ err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
+ !!(val & PCIE_PORT_LINKUP), 20,
+ 100 * USEC_PER_MSEC);
+ if (err)
+ return -ETIMEDOUT;
/* enable interrupt */
val = readl(pcie->base + PCIE_INT_ENABLE);
@@ -209,25 +223,8 @@ static void mtk_pcie_configure_rc(struct mtk_pcie_port *port)
writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
pcie->base + PCIE_CFG_ADDR);
writel(val, pcie->base + PCIE_CFG_DATA);
-}
-static void mtk_pcie_assert_ports(struct mtk_pcie_port *port)
-{
- struct mtk_pcie *pcie = port->pcie;
- u32 val;
-
- /* assert port PERST_N */
- val = readl(pcie->base + PCIE_SYS_CFG);
- val |= PCIE_PORT_PERST(port->index);
- writel(val, pcie->base + PCIE_SYS_CFG);
-
- /* de-assert port PERST_N */
- val = readl(pcie->base + PCIE_SYS_CFG);
- val &= ~PCIE_PORT_PERST(port->index);
- writel(val, pcie->base + PCIE_SYS_CFG);
-
- /* PCIe v2.0 need at least 100ms delay to train from Gen1 to Gen2 */
- msleep(100);
+ return 0;
}
static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
@@ -250,13 +247,8 @@ static void mtk_pcie_enable_ports(struct mtk_pcie_port *port)
goto err_phy_on;
}
- mtk_pcie_assert_ports(port);
-
- /* if link up, then setup root port configuration space */
- if (mtk_pcie_link_up(port)) {
- mtk_pcie_configure_rc(port);
+ if (!mtk_pcie_startup_ports(port))
return;
- }
dev_info(dev, "Port%d link down\n", port->index);
--
2.6.4
Hi Honghui,
If you plan to send next version, then I would suggest some minor
changes.
On Fri, 2017-08-04 at 20:06 +0800, [email protected] wrote:
> +#define PCIE_CRSTB BIT(3)
> +#define PCIE_PERSTB BIT(8)
> +#define PCI_LINKDOWN_RST_EN GENMASK(15, 13)
PCIE_LINKDOWN_RST_EN
> +#define PCIE_LINK_STATUS_V2 0x804
> +#define PCIE_PORT_LINKUP_V2 BIT(10)
> +
> +
> +static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
> + int where, int size, u32 *val)
> +{
> + int reg, shift = 8 * (where & 3);
int reg => u32
> + /* Write PCIe Configuration Transaction Header for cfgrd */
> + writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
> + port->base + PCIE_CFG_HEADER0);
> + writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
> + writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
> + port->base + PCIE_CFG_HEADER2);
> +
> + /* Trigger h/w to transmit Cfgrd TLP */
> + reg = readl(port->base + PCIE_APP_TLP_REQ);
> + writel(reg | APP_CFG_REQ, port->base + PCIE_APP_TLP_REQ);
> +
> + /* Check completion status */
> + if (mtk_pcie_check_cfg_cpld(port))
> + return PCIBIOS_SET_FAILED;
> +
> + /* Read cpld payload of Cfgrd */
> + *val = readl(port->base + PCIE_CFG_RDATA);
> +
> + switch (size) {
> + case 4:
> + break;
> + case 3:
> + *val = (*val >> shift) & 0xffffff;
> + break;
> + case 2:
> + *val = (*val >> shift) & 0xffff;
> + break;
> + case 1:
> + *val = (*val >> shift) & 0xff;
> + break;
> + default:
> + return PCIBIOS_BAD_REGISTER_NUMBER;
> + }
Do we really need case 3? I guess case 1, 2 or 4 should be enough.
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
> + int where, int size, u32 val)
> +{
> + /* Write PCIe Configuration Transaction Header for Cfgwr */
> + writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
> + port->base + PCIE_CFG_HEADER0);
> + writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
> + writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
> + port->base + PCIE_CFG_HEADER2);
> +
> + /* Write cfgwr data */
> + val = val << 8 * (where & 3);
> + writel(val, port->base + PCIE_CFG_WDATA);
> +
> + /* Trigger h/w to transmit Cfgwr TLP */
> + val = readl(port->base + PCIE_APP_TLP_REQ);
> + val |= APP_CFG_REQ;
> + writel(val, port->base + PCIE_APP_TLP_REQ);
> +
> + /* Check completion status */
> + return mtk_pcie_check_cfg_cpld(port);
> +}
> +
> +static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 *val)
> +{
> + struct mtk_pcie_port *port = NULL, *iter, *tmp;
> + struct mtk_pcie *pcie = bus->sysdata;
> + u32 bn = bus->number;
> + int ret;
> +
> + list_for_each_entry_safe(iter, tmp, &pcie->ports, list)
> + if (iter->index == PCI_SLOT(devfn)) {
> + port = iter;
> + break;
> + }
> +
> + if (!port) {
> + *val = ~0;
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + }
list_for_each_entry(), since you don't really remove or free something.
I know you need to find port->base to write/read configuration space. I
think it's better to move this part to another function. You can take a
look at pci-mvebu.c mvebu_pcie_find_portmvebu().
> + ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
> + if (ret)
> + *val = ~0;
> +
> + return ret;
> +}
> +
> +static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
> + int where, int size, u32 val)
> +{
> + struct mtk_pcie_port *port = NULL, *iter, *tmp;
> + struct mtk_pcie *pcie = bus->sysdata;
> + u32 bn = bus->number;
> +
> + list_for_each_entry_safe(iter, tmp, &pcie->ports, list)
> + if (iter->index == PCI_SLOT(devfn)) {
> + port = iter;
> + break;
> + }
> +
> + if (!port)
> + return PCIBIOS_DEVICE_NOT_FOUND;
Ditto.
> + return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
> +}
> +
> +static struct pci_ops mtk_pcie_ops_v2 = {
> + .read = mtk_pcie_config_read,
> + .write = mtk_pcie_config_write,
> +};
> +
> +static int mtk_pcie_startup_ports_v2(struct mtk_pcie_port *port)
> +{
> + struct mtk_pcie *pcie = port->pcie;
> + struct resource *mem = &pcie->mem;
> + u32 val;
> + size_t size;
> + int err;
> +
> + /* mt7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
> + if (pcie->base) {
> + val = readl(pcie->base + PCIE_SYS_CFG_V2);
> + val |= PCIE_CSR_LTSSM_EN(port->index) |
> + PCIE_CSR_ASPM_L1_EN(port->index);
> + writel(val, pcie->base + PCIE_SYS_CFG_V2);
> + }
> +
> + /* Assert all reset signals */
> + writel(0, port->base + PCIE_RST_CTRL);
> +
> + /*
> + * Enable PCIe link down reset, if link status changed from link up to
> + * link down, this will reset MAC control registers and configuration
> + * space.
> + */
> + writel(PCI_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
> +
> + /* De-assert PHY, PE, PIPE, MAC and configuration reset */
> + val = readl(port->base + PCIE_RST_CTRL);
> + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
> + PCIE_MAC_SRSTB | PCIE_CRSTB;
> + writel(val, port->base + PCIE_RST_CTRL);
> +
> + /* PCIe v2.0 need at least 100ms delay to train from Gen1 to Gen2 */
/* 100ms timeout value should be enough for Gen1/2 training */ for
consistency.
> + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
> + !!(val & PCIE_PORT_LINKUP_V2), 20,
> + 100 * USEC_PER_MSEC);
> + if (err)
> + return -ETIMEDOUT;
> +
> + /* Set INTx mask */
> + val = readl(port->base + PCIE_INT_MASK);
> + val &= ~INTX_MASK;
> + writel(val, port->base + PCIE_INT_MASK);
> +
> + /* Set AHB to PCIe translation windows */
> + size = mem->end - mem->start;
> + val = AHB2PCIE_BASEL(mem->start) | AHB2PCIE_SIZE(fls(size));
> + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
> +
> + val = AHB2PCIE_BASEH(mem->start);
> + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
> +
> + /* Set PCIe to AXI translation memory space.*/
> + val = fls(0xffffffff) | WIN_ENABLE;
> + writel(val, port->base + PCIE_AXI_WINDOW0);
> +
> + return 0;
> +}
Ryder
On Sun, 2017-08-06 at 10:06 +0800, Ryder Lee wrote:
> Hi Honghui,
>
> If you plan to send next version, then I would suggest some minor
> changes.
>
> On Fri, 2017-08-04 at 20:06 +0800, [email protected] wrote:
> > +#define PCIE_CRSTB BIT(3)
> > +#define PCIE_PERSTB BIT(8)
> > +#define PCI_LINKDOWN_RST_EN GENMASK(15, 13)
>
> PCIE_LINKDOWN_RST_EN
Thanks, I will change it in the next version.
>
> > +#define PCIE_LINK_STATUS_V2 0x804
> > +#define PCIE_PORT_LINKUP_V2 BIT(10)
> > +
> > +
> > +static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
> > + int where, int size, u32 *val)
> > +{
> > + int reg, shift = 8 * (where & 3);
>
> int reg => u32
sharp eyes, thanks.
>
> > + /* Write PCIe Configuration Transaction Header for cfgrd */
> > + writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
> > + port->base + PCIE_CFG_HEADER0);
> > + writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
> > + writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
> > + port->base + PCIE_CFG_HEADER2);
> > +
> > + /* Trigger h/w to transmit Cfgrd TLP */
> > + reg = readl(port->base + PCIE_APP_TLP_REQ);
> > + writel(reg | APP_CFG_REQ, port->base + PCIE_APP_TLP_REQ);
> > +
> > + /* Check completion status */
> > + if (mtk_pcie_check_cfg_cpld(port))
> > + return PCIBIOS_SET_FAILED;
> > +
> > + /* Read cpld payload of Cfgrd */
> > + *val = readl(port->base + PCIE_CFG_RDATA);
> > +
> > + switch (size) {
> > + case 4:
> > + break;
> > + case 3:
> > + *val = (*val >> shift) & 0xffffff;
> > + break;
> > + case 2:
> > + *val = (*val >> shift) & 0xffff;
> > + break;
> > + case 1:
> > + *val = (*val >> shift) & 0xff;
> > + break;
> > + default:
> > + return PCIBIOS_BAD_REGISTER_NUMBER;
> > + }
>
> Do we really need case 3? I guess case 1, 2 or 4 should be enough.
>
I will change this as the following snippet:
if (size == 1)
*val = (*val >> (8 * (where & 3))) & 0xff;
else if (size == 2)
*val = (*val >> (8 * (where & 3))) & 0xffff;
thanks.
> > + return PCIBIOS_SUCCESSFUL;
> > +}
> > +
> > +static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
> > + int where, int size, u32 val)
> > +{
> > + /* Write PCIe Configuration Transaction Header for Cfgwr */
> > + writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
> > + port->base + PCIE_CFG_HEADER0);
> > + writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
> > + writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
> > + port->base + PCIE_CFG_HEADER2);
> > +
> > + /* Write cfgwr data */
> > + val = val << 8 * (where & 3);
> > + writel(val, port->base + PCIE_CFG_WDATA);
> > +
> > + /* Trigger h/w to transmit Cfgwr TLP */
> > + val = readl(port->base + PCIE_APP_TLP_REQ);
> > + val |= APP_CFG_REQ;
> > + writel(val, port->base + PCIE_APP_TLP_REQ);
> > +
> > + /* Check completion status */
> > + return mtk_pcie_check_cfg_cpld(port);
> > +}
> > +
> > +static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
> > + int where, int size, u32 *val)
> > +{
> > + struct mtk_pcie_port *port = NULL, *iter, *tmp;
> > + struct mtk_pcie *pcie = bus->sysdata;
> > + u32 bn = bus->number;
> > + int ret;
> > +
> > + list_for_each_entry_safe(iter, tmp, &pcie->ports, list)
> > + if (iter->index == PCI_SLOT(devfn)) {
> > + port = iter;
> > + break;
> > + }
> > +
> > + if (!port) {
> > + *val = ~0;
> > + return PCIBIOS_DEVICE_NOT_FOUND;
> > + }
>
> list_for_each_entry(), since you don't really remove or free something.
>
> I know you need to find port->base to write/read configuration space. I
> think it's better to move this part to another function. You can take a
> look at pci-mvebu.c mvebu_pcie_find_portmvebu().
Sure, I will add the mtk_pcie_find_port interface, then the code is a
bit more readable.
thanks.
>
> > + ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
> > + if (ret)
> > + *val = ~0;
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
> > + int where, int size, u32 val)
> > +{
> > + struct mtk_pcie_port *port = NULL, *iter, *tmp;
> > + struct mtk_pcie *pcie = bus->sysdata;
> > + u32 bn = bus->number;
> > +
> > + list_for_each_entry_safe(iter, tmp, &pcie->ports, list)
> > + if (iter->index == PCI_SLOT(devfn)) {
> > + port = iter;
> > + break;
> > + }
> > +
> > + if (!port)
> > + return PCIBIOS_DEVICE_NOT_FOUND;
>
> Ditto.
>
> > + return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
> > +}
> > +
> > +static struct pci_ops mtk_pcie_ops_v2 = {
> > + .read = mtk_pcie_config_read,
> > + .write = mtk_pcie_config_write,
> > +};
> > +
> > +static int mtk_pcie_startup_ports_v2(struct mtk_pcie_port *port)
> > +{
> > + struct mtk_pcie *pcie = port->pcie;
> > + struct resource *mem = &pcie->mem;
> > + u32 val;
> > + size_t size;
> > + int err;
> > +
> > + /* mt7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
> > + if (pcie->base) {
> > + val = readl(pcie->base + PCIE_SYS_CFG_V2);
> > + val |= PCIE_CSR_LTSSM_EN(port->index) |
> > + PCIE_CSR_ASPM_L1_EN(port->index);
> > + writel(val, pcie->base + PCIE_SYS_CFG_V2);
> > + }
> > +
> > + /* Assert all reset signals */
> > + writel(0, port->base + PCIE_RST_CTRL);
> > +
> > + /*
> > + * Enable PCIe link down reset, if link status changed from link up to
> > + * link down, this will reset MAC control registers and configuration
> > + * space.
> > + */
> > + writel(PCI_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
> > +
> > + /* De-assert PHY, PE, PIPE, MAC and configuration reset */
> > + val = readl(port->base + PCIE_RST_CTRL);
> > + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
> > + PCIE_MAC_SRSTB | PCIE_CRSTB;
> > + writel(val, port->base + PCIE_RST_CTRL);
> > +
> > + /* PCIe v2.0 need at least 100ms delay to train from Gen1 to Gen2 */
>
> /* 100ms timeout value should be enough for Gen1/2 training */ for
> consistency.
>
> > + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
> > + !!(val & PCIE_PORT_LINKUP_V2), 20,
> > + 100 * USEC_PER_MSEC);
> > + if (err)
> > + return -ETIMEDOUT;
> > +
> > + /* Set INTx mask */
> > + val = readl(port->base + PCIE_INT_MASK);
> > + val &= ~INTX_MASK;
> > + writel(val, port->base + PCIE_INT_MASK);
> > +
> > + /* Set AHB to PCIe translation windows */
> > + size = mem->end - mem->start;
> > + val = AHB2PCIE_BASEL(mem->start) | AHB2PCIE_SIZE(fls(size));
> > + writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
> > +
> > + val = AHB2PCIE_BASEH(mem->start);
> > + writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
> > +
> > + /* Set PCIe to AXI translation memory space.*/
> > + val = fls(0xffffffff) | WIN_ENABLE;
> > + writel(val, port->base + PCIE_AXI_WINDOW0);
> > +
> > + return 0;
> > +}
>
> Ryder
>
On Fri, Aug 04, 2017 at 08:06:42PM +0800, [email protected] wrote:
> From: Ryder Lee <[email protected]>
>
> Add support for MediaTek new generation controller and update related
> properities.
When you update the series, can you update the subject and changelog
to be more specific than "new generation" controller?
Next year there will probably be another "new generation" controller,
so it's useful to be more specific here, e.g., include
"MT2701/MT7623", "MT2712/MT7622", or whatever is appropriate.
> Signed-off-by: Ryder Lee <[email protected]>
> Signed-off-by: Honghui Zhang <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
> .../devicetree/bindings/pci/mediatek-pcie.txt | 168 ++++++++++++++++++++-
> 1 file changed, 161 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> index 0fdcb15..2e81742 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> @@ -3,18 +3,31 @@ MediaTek Gen2 PCIe controller
> Required properties:
> - compatible: Should contain one of the following strings:
> "mediatek,mt2701-pcie"
> + "mediatek,mt2712-pcie"
> + "mediatek,mt7622-pcie"
> "mediatek,mt7623-pcie"
> - device_type: Must be "pci"
> -- reg: Base addresses and lengths of the PCIe controller.
> +- reg: Base addresses and lengths of the PCIe subsys and root ports.
> +- reg-names: Names of the above areas to use during resource look-up.
> - #address-cells: Address representation for root ports (must be 3)
> - #size-cells: Size representation for root ports (must be 2)
> - clocks: Must contain an entry for each entry in clock-names.
> See ../clocks/clock-bindings.txt for details.
> -- clock-names: Must include the following entries:
> - - free_ck :for reference clock of PCIe subsys
> - - sys_ck0 :for clock of Port0
> - - sys_ck1 :for clock of Port1
> - - sys_ck2 :for clock of Port2
> +- clock-names:
> + Mandatory entries:
> + - sys_ckN :transaction layer and data link layer clock
> + Required entries for MT2701/MT7623:
> + - free_ck :for reference clock of PCIe subsys
> + Required entries for MT2712/MT7622:
> + - ahb_ckN :AHB slave interface operating clock for CSR access and RC
> + initiated MMIO access
> + Required entries for MT7622:
> + - axi_ckN :application layer MMIO channel operating clock
> + - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
> + pcie_mac_ck/pcie_pipe_ck is turned off
> + - obff_ckN :OBFF functional block operating clock
> + - pipe_ckN :LTSSM and PHY/MAC layer operating clock
> + where N starting from 0 to one less than the number of root ports.
> - phys: List of PHY specifiers (used by generic PHY framework).
> - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> number of PHYs as specified in *phys* property.
> @@ -33,6 +46,10 @@ Required properties for MT7623/MT2701:
> - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
> number of root ports.
>
> +Required properties for MT2712/MT7622:
> +-interrupts: A list of interrupt outputs of the controller, must have one
> + entry for each PCIe port
> +
> In addition, the device tree node must have sub-nodes describing each
> PCIe port interface, having the following mandatory properties:
>
> @@ -50,7 +67,7 @@ Required properties:
> property is sufficient.
> - num-lanes: Number of lanes to use for this port.
>
> -Examples:
> +Examples for MT7623:
>
> hifsys: syscon@1a000000 {
> compatible = "mediatek,mt7623-hifsys",
> @@ -68,6 +85,7 @@ Examples:
> <0 0x1a142000 0 0x1000>, /* Port0 registers */
> <0 0x1a143000 0 0x1000>, /* Port1 registers */
> <0 0x1a144000 0 0x1000>; /* Port2 registers */
> + reg-names = "subsys", "port0", "port1", "port2";
> #address-cells = <3>;
> #size-cells = <2>;
> #interrupt-cells = <1>;
> @@ -128,3 +146,139 @@ Examples:
> num-lanes = <1>;
> };
> };
> +
> +Examples for MT2712:
> + pcie: pcie@11700000 {
> + compatible = "mediatek,mt2712-pcie";
> + device_type = "pci";
> + reg = <0 0x11700000 0 0x1000>,
> + <0 0x112ff000 0 0x1000>;
> + reg-names = "port0", "port1";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
> + <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
> + <&pericfg CLK_PERI_PCIE0>,
> + <&pericfg CLK_PERI_PCIE1>;
> + clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
> + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy0", "pcie-phy1";
> + bus-range = <0x00 0xff>;
> + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
> +
> + pcie0: pcie@0,0 {
> + device_type = "pci";
> + reg = <0x0000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + num-lanes = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> + <0 0 0 2 &pcie_intc0 1>,
> + <0 0 0 3 &pcie_intc0 2>,
> + <0 0 0 4 &pcie_intc0 3>;
> + pcie_intc0: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + pcie1: pcie@1,0 {
> + device_type = "pci";
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + num-lanes = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> + <0 0 0 2 &pcie_intc1 1>,
> + <0 0 0 3 &pcie_intc1 2>,
> + <0 0 0 4 &pcie_intc1 3>;
> + pcie_intc1: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> +Examples for MT7622:
> + pcie: pcie@1a140000 {
> + compatible = "mediatek,mt7622-pcie";
> + device_type = "pci";
> + reg = <0 0x1a140000 0 0x1000>,
> + <0 0x1a143000 0 0x1000>,
> + <0 0x1a145000 0 0x1000>;
> + reg-names = "subsys", "port0", "port1";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
> + <&pciesys CLK_PCIE_P1_MAC_EN>,
> + <&pciesys CLK_PCIE_P0_AHB_EN>,
> + <&pciesys CLK_PCIE_P1_AHB_EN>,
> + <&pciesys CLK_PCIE_P0_AUX_EN>,
> + <&pciesys CLK_PCIE_P1_AUX_EN>,
> + <&pciesys CLK_PCIE_P0_AXI_EN>,
> + <&pciesys CLK_PCIE_P1_AXI_EN>,
> + <&pciesys CLK_PCIE_P0_OBFF_EN>,
> + <&pciesys CLK_PCIE_P1_OBFF_EN>,
> + <&pciesys CLK_PCIE_P0_PIPE_EN>,
> + <&pciesys CLK_PCIE_P1_PIPE_EN>;
> + clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
> + "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
> + "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
> + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy0", "pcie-phy1";
> + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> + bus-range = <0x00 0xff>;
> + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
> +
> + pcie0: pcie@0,0 {
> + device_type = "pci";
> + reg = <0x0000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + num-lanes = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> + <0 0 0 2 &pcie_intc0 1>,
> + <0 0 0 3 &pcie_intc0 2>,
> + <0 0 0 4 &pcie_intc0 3>;
> + pcie_intc0: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + pcie1: pcie@1,0 {
> + device_type = "pci";
> + reg = <0x0800 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + ranges;
> + num-lanes = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> + <0 0 0 2 &pcie_intc1 1>,
> + <0 0 0 3 &pcie_intc1 2>,
> + <0 0 0 4 &pcie_intc1 3>;
> + pcie_intc1: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> --
> 2.6.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Fri, Aug 04, 2017 at 08:06:41PM +0800, [email protected] wrote:
> From: Ryder Lee <[email protected]>
>
> MediaTek's PCIe host controller has two generation HWs, the new
> generation HW has two root ports, it shares most probing flow with the
> legacy controller. But the read/write config space logical is different
> from the legacy controller. The per-port register must be touched for
> read/write config space, And the per-port register base are in separate
> address space.
Can you also include the new controller IDs ("MT7622/MT2712"?) in the
subject line of this patch?
> Add support for new Gen2 controller which can be found on MT7622/MT2712.