From: Lad Prabhakar <[email protected]>
Hi All,
The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
entry-class social infrastructure gateway control and industrial gateway
control.
This patch series adds initial SoC DTSi support for Renesas RZ/Five
(R9A07G043) SoC and updates the bindings for the same. Below is the list
of IP blocks added in the initial SoC DTSI which can be used to boot via
initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Patch series depends on:
-----------------------
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/[email protected]/
v2->v3:
-------
* Re-used RZ/G2UL SMARC EVK SoM and carrier DTSI
* Included RB tags
* Rebased patches on -next
v2: https://lore.kernel.org/all/[email protected]/
v1: https://lore.kernel.org/lkml/[email protected]/
Below are the logs from RZ/Five SMARC EVK:
------------------------------------------
/ # uname -ra
Linux (none) 6.0.0-rc5-next-20220915-00016-g0f0153102a13 #121 SMP Thu Sep 15 16:54:44 BST 2022 riscv64 GNU/Linux
/ # cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdc
mmu : sv39
uarch : andestech,ax45mp
mvendorid : 0x31e
marchid : 0x8000000000008a45
mimpid : 0x500
/ # cat /proc/interrupts
CPU0
1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
2: 0 SiFive PLIC 414 Level 1004b800.serial:rx full
3: 178 SiFive PLIC 415 Level 1004b800.serial:tx empty
4: 0 SiFive PLIC 413 Level 1004b800.serial:break
5: 1879569 RISC-V INTC 5 Edge riscv-timer
6: 37 SiFive PLIC 416 Level 1004b800.serial:rx ready
IPI0: 0 Rescheduling interrupts
IPI1: 0 Function call interrupts
IPI2: 0 CPU stop interrupts
IPI3: 0 IRQ work interrupts
IPI4: 0 Timer broadcast interrupts
/ # cat /proc/meminfo
MemTotal: 882356 kB
MemFree: 861740 kB
MemAvailable: 859488 kB
Buffers: 0 kB
Cached: 1796 kB
SwapCached: 0 kB
Active: 0 kB
Inactive: 80 kB
Active(anon): 0 kB
Inactive(anon): 80 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 1796 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 116 kB
Mapped: 1136 kB
Shmem: 0 kB
KReclaimable: 6732 kB
Slab: 11932 kB
SReclaimable: 6732 kB
SUnreclaim: 5200 kB
KernelStack: 540 kB
PageTables: 32 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 441176 kB
Committed_AS: 592 kB
VmallocTotal: 67108864 kB
VmallocUsed: 760 kB
VmallocChunk: 0 kB
Percpu: 84 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ #
Cheers,
Prabhakar
Lad Prabhakar (10):
dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
dt-bindings: riscv: Sort the CPU core list alphabetically
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
riscv: boot: dts: r9a07g043: Add placeholder nodes
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
MAINTAINERS: Add entry for Renesas RISC-V architecture
RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC
.../devicetree/bindings/riscv/cpus.yaml | 11 +-
.../{arm => soc/renesas}/renesas.yaml | 3 +-
MAINTAINERS | 4 +-
arch/riscv/Kconfig.socs | 14 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 297 ++++++++++++++++++
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 42 +++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 56 ++++
arch/riscv/configs/defconfig | 2 +
11 files changed, 451 insertions(+), 8 deletions(-)
rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (99%)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
--
2.25.1
From: Lad Prabhakar <[email protected]>
Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
board DTS/I.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1->v3
* New patch
---
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 177 +++++++++++++++++++++
1 file changed, 177 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
index fb6733f3cc2b..6d9db759a847 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -13,6 +13,14 @@ / {
#address-cells = <2>;
#size-cells = <2>;
+ audio_clk1: audio1-clk {
+ /* placeholder */
+ };
+
+ audio_clk2: audio2-clk {
+ /* placeholder */
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -54,6 +62,23 @@ soc: soc {
#size-cells = <2>;
ranges;
+ ssi1: ssi@1004a000 {
+ reg = <0 0x1004a000 0 0x400>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ spi1: spi@1004b000 {
+ reg = <0 0x1004b000 0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
@@ -73,6 +98,48 @@ scif0: serial@1004b800 {
status = "disabled";
};
+ canfd: can@10050000 {
+ reg = <0 0x10050000 0 0x8000>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ i2c0: i2c@10058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058000 0 0x400>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ i2c1: i2c@10058400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058400 0 0x400>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ adc: adc@10059000 {
+ reg = <0 0x10059000 0 0x400>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ sbc: spi@10060000 {
+ reg = <0 0x10060000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>,
+ <0 0x10070000 0 0x10000>;
+ reg-names = "regs", "dirmap", "wbuf";
+ status = "disabled";
+
+ /* placeholder */
+ };
+
cpg: clock-controller@11010000 {
compatible = "renesas,r9a07g043-cpg";
reg = <0 0x11010000 0 0x10000>;
@@ -104,6 +171,95 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A07G043_GPIO_SPARE_RESETN>;
};
+ sdhi0: mmc@11c00000 {
+ reg = <0x0 0x11c00000 0 0x10000>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ sdhi1: mmc@11c10000 {
+ reg = <0x0 0x11c10000 0 0x10000>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ eth0: ethernet@11c20000 {
+ reg = <0 0x11c20000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ eth1: ethernet@11c30000 {
+ reg = <0 0x11c30000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ phyrst: usbphy-ctrl@11c40000 {
+ reg = <0 0x11c40000 0 0x10000>;
+ #reset-cells = <1>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ ohci0: usb@11c50000 {
+ reg = <0 0x11c50000 0 0x100>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ ohci1: usb@11c70000 {
+ reg = <0 0x11c70000 0 0x100>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ ehci0: usb@11c50100 {
+ reg = <0 0x11c50100 0 0x100>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ ehci1: usb@11c70100 {
+ reg = <0 0x11c70100 0 0x100>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ reg = <0 0x11c50200 0 0x700>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ reg = <0 0x11c70200 0 0x700>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ hsusb: usb@11c60000 {
+ reg = <0 0x11c60000 0 0x10000>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
plic: interrupt-controller@12c00000 {
compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
#interrupt-cells = <2>;
@@ -116,5 +272,26 @@ plic: interrupt-controller@12c00000 {
resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
};
+
+ wdt0: watchdog@12800800 {
+ reg = <0 0x12800800 0 0x400>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ ostm1: timer@12801400 {
+ reg = <0x0 0x12801400 0x0 0x400>;
+ status = "disabled";
+
+ /* placeholder */
+ };
+
+ ostm2: timer@12801800 {
+ reg = <0x0 0x12801800 0x0 0x400>;
+ status = "disabled";
+
+ /* placeholder */
+ };
};
};
--
2.25.1
From: Lad Prabhakar <[email protected]>
Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.
Below are the blocks enabled:
- CPG
- CPU0
- DDR (memory regions)
- PINCTRL
- PLIC
- SCIF0
Note we have deleted the nodes from the DT for which support needs to be
added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
board DTS/I.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v2->v3
* Dropped RB tags from Conor and Geert
* Now re-using the SoM and carrier board DTS/I from RZ/G2UL
v1->v2
* New patch
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 42 ++++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 56 +++++++++++++++++++
5 files changed, 128 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..2d3f5751a649
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644
index 000000000000..9747f30c5db5
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
+ * Please change below macros according to SW1 setting on SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N 1
+
+#include "r9a07g043.dtsi"
+#include "rzfive-smarc-som.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043f01";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644
index 000000000000..8547c273f140
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ ethernet0;
+ /delete-property/ ethernet1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+};
+
+#if (SW_SW0_DEV_SEL)
+/delete-node/ &adc;
+#endif
+
+#if (!SW_ET0_EN_N)
+/delete-node/ ð0;
+#endif
+/delete-node/ ð1;
+
+/delete-node/ &ostm1;
+/delete-node/ &ostm2;
+
+/delete-node/ ®_1p8v;
+/delete-node/ ®_3p3v;
+
+/delete-node/ &sdhi0;
+
+#if !(SW_SW0_DEV_SEL)
+/delete-node/ &vccq_sdhi0;
+#endif
+
+/delete-node/ &wdt0;
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644
index 000000000000..3fde7192241e
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ i2c0;
+ /delete-property/ i2c1;
+ };
+};
+
+/delete-node/ &audio_clk1;
+/delete-node/ &audio_clk2;
+/delete-node/ &audio_mclock;
+
+/delete-node/ &canfd;
+
+/delete-node/ &cpu_dai;
+
+/delete-node/ &ehci0;
+/delete-node/ &ehci1;
+
+/delete-node/ &hsusb;
+
+/delete-node/ &i2c0;
+/delete-node/ &i2c1;
+
+/delete-node/ &ohci0;
+/delete-node/ &ohci1;
+
+&pinctrl {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+};
+
+/delete-node/ &phyrst;
+
+/delete-node/ &sdhi1;
+
+/delete-node/ &snd_rzg2l;
+
+/delete-node/ &spi1;
+
+/delete-node/ &ssi1;
+
+/delete-node/ &usb0_vbus_otg;
+
+/delete-node/ &usb2_phy0;
+/delete-node/ &usb2_phy1;
+
+/delete-node/ &vccq_sdhi1;
--
2.25.1
From: Lad Prabhakar <[email protected]>
Add RISC-V architecture as part of ARM/Renesas architecture, as they have
the same maintainers, use the same development collaboration
infrastructure, and share many files.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v2->v3
* Merged as part of ARM
v1->v2
* New patch
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index f5f17c50dac3..99483c13b91c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2665,7 +2665,7 @@ F: arch/arm/boot/dts/rtd*
F: arch/arm/mach-realtek/
F: arch/arm64/boot/dts/realtek/
-ARM/RENESAS ARCHITECTURE
+ARM/RISC-V/RENESAS ARCHITECTURE
M: Geert Uytterhoeven <[email protected]>
M: Magnus Damm <[email protected]>
L: [email protected]
@@ -2686,6 +2686,7 @@ F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
F: arch/arm/mach-shmobile/
F: arch/arm64/boot/dts/renesas/
+F: arch/riscv/boot/dts/renesas/
F: drivers/soc/renesas/
F: include/linux/soc/renesas/
--
2.25.1
On 15/09/2022 19:15, Prabhakar wrote:
> riscv: boot: dts: r9a07g043: Add placeholder nodes
nit: s/boot//
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Lad Prabhakar <[email protected]>
>
> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
Can you explain why do you need placeholder nodes for this and
cannot just directly include the other dtsis?
>
> This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> board DTS/I.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v1->v3
> * New patch
> ---
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 177 +++++++++++++++++++++
> 1 file changed, 177 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> index fb6733f3cc2b..6d9db759a847 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -13,6 +13,14 @@ / {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + audio_clk1: audio1-clk {
> + /* placeholder */
> + };
> +
> + audio_clk2: audio2-clk {
> + /* placeholder */
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -54,6 +62,23 @@ soc: soc {
> #size-cells = <2>;
> ranges;
>
> + ssi1: ssi@1004a000 {
> + reg = <0 0x1004a000 0 0x400>;
> + #sound-dai-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + spi1: spi@1004b000 {
> + reg = <0 0x1004b000 0 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> scif0: serial@1004b800 {
> compatible = "renesas,scif-r9a07g043",
> "renesas,scif-r9a07g044";
> @@ -73,6 +98,48 @@ scif0: serial@1004b800 {
> status = "disabled";
> };
>
> + canfd: can@10050000 {
> + reg = <0 0x10050000 0 0x8000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + i2c0: i2c@10058000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x10058000 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + i2c1: i2c@10058400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x10058400 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + adc: adc@10059000 {
> + reg = <0 0x10059000 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + sbc: spi@10060000 {
> + reg = <0 0x10060000 0 0x10000>,
> + <0 0x20000000 0 0x10000000>,
> + <0 0x10070000 0 0x10000>;
> + reg-names = "regs", "dirmap", "wbuf";
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> cpg: clock-controller@11010000 {
> compatible = "renesas,r9a07g043-cpg";
> reg = <0 0x11010000 0 0x10000>;
> @@ -104,6 +171,95 @@ pinctrl: pinctrl@11030000 {
> <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> };
>
> + sdhi0: mmc@11c00000 {
> + reg = <0x0 0x11c00000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + sdhi1: mmc@11c10000 {
> + reg = <0x0 0x11c10000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + eth0: ethernet@11c20000 {
> + reg = <0 0x11c20000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + eth1: ethernet@11c30000 {
> + reg = <0 0x11c30000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + phyrst: usbphy-ctrl@11c40000 {
> + reg = <0 0x11c40000 0 0x10000>;
> + #reset-cells = <1>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ohci0: usb@11c50000 {
> + reg = <0 0x11c50000 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ohci1: usb@11c70000 {
> + reg = <0 0x11c70000 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ehci0: usb@11c50100 {
> + reg = <0 0x11c50100 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ehci1: usb@11c70100 {
> + reg = <0 0x11c70100 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + usb2_phy0: usb-phy@11c50200 {
> + reg = <0 0x11c50200 0 0x700>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + usb2_phy1: usb-phy@11c70200 {
> + reg = <0 0x11c70200 0 0x700>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + hsusb: usb@11c60000 {
> + reg = <0 0x11c60000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> plic: interrupt-controller@12c00000 {
> compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> #interrupt-cells = <2>;
> @@ -116,5 +272,26 @@ plic: interrupt-controller@12c00000 {
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> };
> +
> + wdt0: watchdog@12800800 {
> + reg = <0 0x12800800 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ostm1: timer@12801400 {
> + reg = <0x0 0x12801400 0x0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ostm2: timer@12801800 {
> + reg = <0x0 0x12801800 0x0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> };
> };
> --
> 2.25.1
>
On 15/09/2022 19:15, Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Lad Prabhakar <[email protected]>
>
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Below are the blocks enabled:
> - CPG
> - CPU0
> - DDR (memory regions)
> - PINCTRL
> - PLIC
> - SCIF0
>
> Note we have deleted the nodes from the DT for which support needs to be
> added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> board DTS/I.
idk, I am not sure what to think of this approach.
What do you mean by "for which support needs to be added"? If the support
does not exist yet, then is surely you can just add the nodes and it will
be fine?
Confused,
Conor.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v2->v3
> * Dropped RB tags from Conor and Geert
> * Now re-using the SoM and carrier board DTS/I from RZ/G2UL
>
> v1->v2
> * New patch
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 42 ++++++++++++++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 56 +++++++++++++++++++
> 5 files changed, 128 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
> new file mode 100644
> index 000000000000..2d3f5751a649
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> new file mode 100644
> index 000000000000..9747f30c5db5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +/*
> + * DIP-Switch SW1 setting
> + * 1 : High; 0: Low
> + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
> + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
> + * Please change below macros according to SW1 setting on SoM
> + */
> +#define SW_SW0_DEV_SEL 1
> +#define SW_ET0_EN_N 1
> +
> +#include "r9a07g043.dtsi"
> +#include "rzfive-smarc-som.dtsi"
> +#include "rzfive-smarc.dtsi"
> +
> +/ {
> + model = "Renesas SMARC EVK based on r9a07g043f01";
> + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
> +};
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> new file mode 100644
> index 000000000000..8547c273f140
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK SOM
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ ethernet0;
> + /delete-property/ ethernet1;
> + };
> +
> + chosen {
> + bootargs = "ignore_loglevel";
> + };
> +};
> +
> +#if (SW_SW0_DEV_SEL)
> +/delete-node/ &adc;
> +#endif
> +
> +#if (!SW_ET0_EN_N)
> +/delete-node/ ð0;
> +#endif
> +/delete-node/ ð1;
> +
> +/delete-node/ &ostm1;
> +/delete-node/ &ostm2;
> +
> +/delete-node/ ®_1p8v;
> +/delete-node/ ®_3p3v;
> +
> +/delete-node/ &sdhi0;
> +
> +#if !(SW_SW0_DEV_SEL)
> +/delete-node/ &vccq_sdhi0;
> +#endif
> +
> +/delete-node/ &wdt0;
> diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> new file mode 100644
> index 000000000000..3fde7192241e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
> @@ -0,0 +1,56 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK carrier board
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ i2c0;
> + /delete-property/ i2c1;
> + };
> +};
> +
> +/delete-node/ &audio_clk1;
> +/delete-node/ &audio_clk2;
> +/delete-node/ &audio_mclock;
> +
> +/delete-node/ &canfd;
> +
> +/delete-node/ &cpu_dai;
> +
> +/delete-node/ &ehci0;
> +/delete-node/ &ehci1;
> +
> +/delete-node/ &hsusb;
> +
> +/delete-node/ &i2c0;
> +/delete-node/ &i2c1;
> +
> +/delete-node/ &ohci0;
> +/delete-node/ &ohci1;
> +
> +&pinctrl {
> + /delete-property/ pinctrl-0;
> + /delete-property/ pinctrl-names;
> +};
> +
> +/delete-node/ &phyrst;
> +
> +/delete-node/ &sdhi1;
> +
> +/delete-node/ &snd_rzg2l;
> +
> +/delete-node/ &spi1;
> +
> +/delete-node/ &ssi1;
> +
> +/delete-node/ &usb0_vbus_otg;
> +
> +/delete-node/ &usb2_phy0;
> +/delete-node/ &usb2_phy1;
> +
> +/delete-node/ &vccq_sdhi1;
> --
> 2.25.1
>
Hi Conor,
Thank you for the review.
On Thu, Sep 15, 2022 at 10:36 PM <[email protected]> wrote:
>
> On 15/09/2022 19:15, Prabhakar wrote:
> > riscv: boot: dts: r9a07g043: Add placeholder nodes
>
> nit: s/boot//
>
Will fix that.
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Lad Prabhakar <[email protected]>
> >
> > Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
>
> Can you explain why do you need placeholder nodes for this and
> cannot just directly include the other dtsis?
>
Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC
we have PLIC for interrupts. Also the interrupt numbering for RZ/Five
SoC differs from RZ/G2UL SoC hence we are not directly using the
RZ/G2UL SoC DTSI [0].
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5
For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and
[2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
I am re-using these when trying to compile the RZ/Five DTB I get
compilation errors since the nodes dont exist (and there is no way
currently we can delete the node reference when the actual node itself
isn't present) hence these place holders.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
Cheers,
Prabhakar
On 15/09/2022 23:41, Lad, Prabhakar wrote:
> Hi Conor,
>
> Thank you for the review.
>
> On Thu, Sep 15, 2022 at 10:56 PM <[email protected]> wrote:
>>
>> On 15/09/2022 19:15, Prabhakar wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Lad Prabhakar <[email protected]>
>>>
>>> Enable the minimal blocks required for booting the Renesas RZ/Five
>>> SMARC EVK with initramfs.
>>>
>>> Below are the blocks enabled:
>>> - CPG
>>> - CPU0
>>> - DDR (memory regions)
>>> - PINCTRL
>>> - PLIC
>>> - SCIF0
>>>
>>> Note we have deleted the nodes from the DT for which support needs to be
>>> added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
>>> board DTS/I.
>>
>> idk, I am not sure what to think of this approach.
>>
>> What do you mean by "for which support needs to be added"? If the support
>> does not exist yet, then is surely you can just add the nodes and it will
>> be fine?
>>
> As pointed out previously, I am re-using the below files [1] (SoM) and
> [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
> [1] and [2] enable almost all the peripherals (status = okay) on the
> RZ/G2UL SMARC EVK which are supported. For example [1] enables SDHI0/1
> this high speed block needs DMA and without cache management fixed on
> Andes core we cannot enable this on RZ/Five SoC so currently a
> placeholder is added for it in the RZ/FIve SoC DTSI and is deleted in
> the board DTS file.
>
> Below blocks suffer the cache management issue:
> - DMAC
> - ETH
> - SDHI
> - USB
>
> Rest of the blocks will be gradually enabled (as soon as this initial
> patchset is merged) along with the DT binding doc updates.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
Explanations are reasonable, but again - that information is important
and really needs to be included in the commit message etc.
Thanks,
Conor.
Hi Conor,
Thank you for the review.
On Thu, Sep 15, 2022 at 10:56 PM <[email protected]> wrote:
>
> On 15/09/2022 19:15, Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Lad Prabhakar <[email protected]>
> >
> > Enable the minimal blocks required for booting the Renesas RZ/Five
> > SMARC EVK with initramfs.
> >
> > Below are the blocks enabled:
> > - CPG
> > - CPU0
> > - DDR (memory regions)
> > - PINCTRL
> > - PLIC
> > - SCIF0
> >
> > Note we have deleted the nodes from the DT for which support needs to be
> > added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> > board DTS/I.
>
> idk, I am not sure what to think of this approach.
>
> What do you mean by "for which support needs to be added"? If the support
> does not exist yet, then is surely you can just add the nodes and it will
> be fine?
>
As pointed out previously, I am re-using the below files [1] (SoM) and
[2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
[1] and [2] enable almost all the peripherals (status = okay) on the
RZ/G2UL SMARC EVK which are supported. For example [1] enables SDHI0/1
this high speed block needs DMA and without cache management fixed on
Andes core we cannot enable this on RZ/Five SoC so currently a
placeholder is added for it in the RZ/FIve SoC DTSI and is deleted in
the board DTS file.
Below blocks suffer the cache management issue:
- DMAC
- ETH
- SDHI
- USB
Rest of the blocks will be gradually enabled (as soon as this initial
patchset is merged) along with the DT binding doc updates.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
[2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
Cheers,
Prabhakar
On 15/09/2022 23:26, Lad, Prabhakar wrote:
> Hi Conor,
>
> Thank you for the review.
>
> On Thu, Sep 15, 2022 at 10:36 PM <[email protected]> wrote:
>>
>> On 15/09/2022 19:15, Prabhakar wrote:
>>> riscv: boot: dts: r9a07g043: Add placeholder nodes
>>
>> nit: s/boot//
>>
> Will fix that.
>
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Lad Prabhakar <[email protected]>
>>>
>>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
>>
>> Can you explain why do you need placeholder nodes for this and
>> cannot just directly include the other dtsis?
>>
> Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC
> we have PLIC for interrupts. Also the interrupt numbering for RZ/Five
> SoC differs from RZ/G2UL SoC hence we are not directly using the
> RZ/G2UL SoC DTSI [0].
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5
>
> For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and
> [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
> I am re-using these when trying to compile the RZ/Five DTB I get
> compilation errors since the nodes dont exist (and there is no way
> currently we can delete the node reference when the actual node itself
> isn't present) hence these place holders.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
If this method is acceptable to Geert, this explanation 100% needs to
go into the commit message.
Thanks,
Conor.
On Thu, Sep 15, 2022 at 11:44 PM <[email protected]> wrote:
>
>
>
> On 15/09/2022 23:41, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> > Thank you for the review.
> >
> > On Thu, Sep 15, 2022 at 10:56 PM <[email protected]> wrote:
> >>
> >> On 15/09/2022 19:15, Prabhakar wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> From: Lad Prabhakar <[email protected]>
> >>>
> >>> Enable the minimal blocks required for booting the Renesas RZ/Five
> >>> SMARC EVK with initramfs.
> >>>
> >>> Below are the blocks enabled:
> >>> - CPG
> >>> - CPU0
> >>> - DDR (memory regions)
> >>> - PINCTRL
> >>> - PLIC
> >>> - SCIF0
> >>>
> >>> Note we have deleted the nodes from the DT for which support needs to be
> >>> added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> >>> board DTS/I.
> >>
> >> idk, I am not sure what to think of this approach.
> >>
> >> What do you mean by "for which support needs to be added"? If the support
> >> does not exist yet, then is surely you can just add the nodes and it will
> >> be fine?
> >>
> > As pointed out previously, I am re-using the below files [1] (SoM) and
> > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
> > [1] and [2] enable almost all the peripherals (status = okay) on the
> > RZ/G2UL SMARC EVK which are supported. For example [1] enables SDHI0/1
> > this high speed block needs DMA and without cache management fixed on
> > Andes core we cannot enable this on RZ/Five SoC so currently a
> > placeholder is added for it in the RZ/FIve SoC DTSI and is deleted in
> > the board DTS file.
> >
> > Below blocks suffer the cache management issue:
> > - DMAC
> > - ETH
> > - SDHI
> > - USB
> >
> > Rest of the blocks will be gradually enabled (as soon as this initial
> > patchset is merged) along with the DT binding doc updates.
> >
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
> > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
>
>
> Explanations are reasonable, but again - that information is important
> and really needs to be included in the commit message etc.
>
Sure, I will update the commit message while sending the v4.
Cheers,
Prabhakar
Hi Conor,
On Fri, Sep 16, 2022 at 12:40 AM Conor Dooley <[email protected]> wrote:
> On 15/09/2022 23:26, Lad, Prabhakar wrote:
> > On Thu, Sep 15, 2022 at 10:36 PM <[email protected]> wrote:
> >> On 15/09/2022 19:15, Prabhakar wrote:
> >>> riscv: boot: dts: r9a07g043: Add placeholder nodes
> >>> From: Lad Prabhakar <[email protected]>
> >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
> >> Can you explain why do you need placeholder nodes for this and
> >> cannot just directly include the other dtsis?
> >>
> > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC
> > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five
> > SoC differs from RZ/G2UL SoC hence we are not directly using the
> > RZ/G2UL SoC DTSI [0].
> >
> > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5
> >
> > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and
> > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
> > I am re-using these when trying to compile the RZ/Five DTB I get
> > compilation errors since the nodes dont exist (and there is no way
> > currently we can delete the node reference when the actual node itself
> > isn't present) hence these place holders.
> >
> > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
> > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
>
> If this method is acceptable to Geert, this explanation 100% needs to
> go into the commit message.
We've been using these placeholders a lot in Renesas SoC-specific
.dtsi files, as they allow us to introduce gradually support for a new SoC
that is mounted on an existing PCB, and thus shares a board-specific
.dtsi file. Hence I'm fine with this.
However, I think more properties can be dropped from the placeholders.
There is no need to have e.g. 'reg-names' and 'status = "disabled"'
(there is no compatible value, so no matching is done).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Sep 20, 2022 at 02:17:50PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Fri, Sep 16, 2022 at 12:40 AM Conor Dooley <[email protected]> wrote:
> > On 15/09/2022 23:26, Lad, Prabhakar wrote:
> > > On Thu, Sep 15, 2022 at 10:36 PM <[email protected]> wrote:
> > >> On 15/09/2022 19:15, Prabhakar wrote:
> > >>> riscv: boot: dts: r9a07g043: Add placeholder nodes
> > >>> From: Lad Prabhakar <[email protected]>
> > >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
> > >> Can you explain why do you need placeholder nodes for this and
> > >> cannot just directly include the other dtsis?
> > >>
> > > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC
> > > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five
> > > SoC differs from RZ/G2UL SoC hence we are not directly using the
> > > RZ/G2UL SoC DTSI [0].
> > >
> > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5
> > >
> > > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and
> > > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
> > > I am re-using these when trying to compile the RZ/Five DTB I get
> > > compilation errors since the nodes dont exist (and there is no way
> > > currently we can delete the node reference when the actual node itself
> > > isn't present) hence these place holders.
> > >
> > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
> > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
> >
> > If this method is acceptable to Geert, this explanation 100% needs to
> > go into the commit message.
>
> We've been using these placeholders a lot in Renesas SoC-specific
> .dtsi files, as they allow us to introduce gradually support for a new SoC
> that is mounted on an existing PCB, and thus shares a board-specific
> .dtsi file. Hence I'm fine with this.
Aye, if you're happy with it then I am too...
>
> However, I think more properties can be dropped from the placeholders.
> There is no need to have e.g. 'reg-names' and 'status = "disabled"'
> (there is no compatible value, so no matching is done).
...and this makes a lot of sense. I'd still like a comment in the
commit message though explaining why placeholder nodes are needed as
opposed to just leaving it blank etc.
Thanks,
Conor.
Hi Prabhakar,
On Thu, Sep 15, 2022 at 8:17 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> Enable the minimal blocks required for booting the Renesas RZ/Five
> SMARC EVK with initramfs.
>
> Below are the blocks enabled:
> - CPG
> - CPU0
> - DDR (memory regions)
> - PINCTRL
> - PLIC
> - SCIF0
>
> Note we have deleted the nodes from the DT for which support needs to be
> added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> board DTS/I.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v2->v3
> * Dropped RB tags from Conor and Geert
> * Now re-using the SoM and carrier board DTS/I from RZ/G2UL
Thanks for the update!
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +/*
> + * DIP-Switch SW1 setting
> + * 1 : High; 0: Low
> + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
> + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
> + * Please change below macros according to SW1 setting on SoM
"on the SoM" (like in r9a07g043u11-smarc.dts)?
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SMARC EVK SOM
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> +
> +/ {
> + aliases {
> + /delete-property/ ethernet0;
> + /delete-property/ ethernet1;
OK
> + };
> +
> + chosen {
> + bootargs = "ignore_loglevel";
> + };
> +};
> +
> +#if (SW_SW0_DEV_SEL)
> +/delete-node/ &adc;
> +#endif
> +
> +#if (!SW_ET0_EN_N)
> +/delete-node/ ð0;
> +#endif
> +/delete-node/ ð1;
> +
> +/delete-node/ &ostm1;
> +/delete-node/ &ostm2;
Given they are all placeholders, do you really need to delete them?
(more below)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, Sep 15, 2022 at 8:17 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> Add RISC-V architecture as part of ARM/Renesas architecture, as they have
> the same maintainers, use the same development collaboration
> infrastructure, and share many files.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v2->v3
> * Merged as part of ARM
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Conor and Geert,
On Tue, Sep 20, 2022 at 1:31 PM Conor Dooley <[email protected]> wrote:
>
> On Tue, Sep 20, 2022 at 02:17:50PM +0200, Geert Uytterhoeven wrote:
> > Hi Conor,
> >
> > On Fri, Sep 16, 2022 at 12:40 AM Conor Dooley <[email protected]> wrote:
> > > On 15/09/2022 23:26, Lad, Prabhakar wrote:
> > > > On Thu, Sep 15, 2022 at 10:36 PM <[email protected]> wrote:
> > > >> On 15/09/2022 19:15, Prabhakar wrote:
> > > >>> riscv: boot: dts: r9a07g043: Add placeholder nodes
> > > >>> From: Lad Prabhakar <[email protected]>
> > > >>> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
> > > >> Can you explain why do you need placeholder nodes for this and
> > > >> cannot just directly include the other dtsis?
> > > >>
> > > > Since the RZ/G2UL SoC is ARM64 where it has a GIC and on RZ/Five SoC
> > > > we have PLIC for interrupts. Also the interrupt numbering for RZ/Five
> > > > SoC differs from RZ/G2UL SoC hence we are not directly using the
> > > > RZ/G2UL SoC DTSI [0].
> > > >
> > > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=v6.0-rc5
> > > >
> > > > For the RZ/Five SMARC EVK I am re-using the below files [1] (SoM) and
> > > > [2] (Carrier board) as the RZ/Five SMARC EVK is pin compatible. Since
> > > > I am re-using these when trying to compile the RZ/Five DTB I get
> > > > compilation errors since the nodes dont exist (and there is no way
> > > > currently we can delete the node reference when the actual node itself
> > > > isn't present) hence these place holders.
> > > >
> > > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi?h=v6.0-rc5
> > > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi?h=v6.0-rc5
> > >
> > > If this method is acceptable to Geert, this explanation 100% needs to
> > > go into the commit message.
> >
> > We've been using these placeholders a lot in Renesas SoC-specific
> > .dtsi files, as they allow us to introduce gradually support for a new SoC
> > that is mounted on an existing PCB, and thus shares a board-specific
> > .dtsi file. Hence I'm fine with this.
>
> Aye, if you're happy with it then I am too...
> >
> > However, I think more properties can be dropped from the placeholders.
> > There is no need to have e.g. 'reg-names' and 'status = "disabled"'
> > (there is no compatible value, so no matching is done).
>
> ...and this makes a lot of sense. I'd still like a comment in the
> commit message though explaining why placeholder nodes are needed as
> opposed to just leaving it blank etc.
>
I will drop the status and reg-names properties and also update the
commit message while sending the v4
Cheers,
Prabhakar
Hi Geert,
Thank you for the review.
On Tue, Sep 20, 2022 at 1:32 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Thu, Sep 15, 2022 at 8:17 PM Prabhakar <[email protected]> wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Enable the minimal blocks required for booting the Renesas RZ/Five
> > SMARC EVK with initramfs.
> >
> > Below are the blocks enabled:
> > - CPG
> > - CPU0
> > - DDR (memory regions)
> > - PINCTRL
> > - PLIC
> > - SCIF0
> >
> > Note we have deleted the nodes from the DT for which support needs to be
> > added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> > board DTS/I.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > v2->v3
> > * Dropped RB tags from Conor and Geert
> > * Now re-using the SoM and carrier board DTS/I from RZ/G2UL
>
> Thanks for the update!
>
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SMARC EVK
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +/*
> > + * DIP-Switch SW1 setting
> > + * 1 : High; 0: Low
> > + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
> > + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
> > + * Please change below macros according to SW1 setting on SoM
>
> "on the SoM" (like in r9a07g043u11-smarc.dts)?
>
Agreed, I will update it.
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> > @@ -0,0 +1,42 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SMARC EVK SOM
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> > +
> > +/ {
> > + aliases {
> > + /delete-property/ ethernet0;
> > + /delete-property/ ethernet1;
>
> OK
>
I assume you are OK with dropping the above too?
> > + };
> > +
> > + chosen {
> > + bootargs = "ignore_loglevel";
> > + };
> > +};
> > +
> > +#if (SW_SW0_DEV_SEL)
> > +/delete-node/ &adc;
> > +#endif
> > +
> > +#if (!SW_ET0_EN_N)
> > +/delete-node/ ð0;
> > +#endif
> > +/delete-node/ ð1;
> > +
> > +/delete-node/ &ostm1;
> > +/delete-node/ &ostm2;
>
> Given they are all placeholders, do you really need to delete them?
> (more below)
>
I did retest without deleting the place holders and I dont see any
issues (or splat) while booting up so I'll drop them while sending the
v4.
Cheers,
Prabhakar
Hi Prabhakar,
On Tue, Sep 20, 2022 at 3:05 PM Lad, Prabhakar
<[email protected]> wrote:
> On Tue, Sep 20, 2022 at 1:32 PM Geert Uytterhoeven <[email protected]> wrote:
> > On Thu, Sep 15, 2022 at 8:17 PM Prabhakar <[email protected]> wrote:
> > > From: Lad Prabhakar <[email protected]>
> > >
> > > Enable the minimal blocks required for booting the Renesas RZ/Five
> > > SMARC EVK with initramfs.
> > >
> > > Below are the blocks enabled:
> > > - CPG
> > > - CPU0
> > > - DDR (memory regions)
> > > - PINCTRL
> > > - PLIC
> > > - SCIF0
> > >
> > > Note we have deleted the nodes from the DT for which support needs to be
> > > added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> > > board DTS/I.
> > >
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> > > @@ -0,0 +1,42 @@
> > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +/*
> > > + * Device Tree Source for the RZ/Five SMARC EVK SOM
> > > + *
> > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> > > +
> > > +/ {
> > > + aliases {
> > > + /delete-property/ ethernet0;
> > > + /delete-property/ ethernet1;
> >
> > OK
> >
> I assume you are OK with dropping the above too?
I did intend to delete these properties (hence the "OK"), as their
presence may confuse U-Boot.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Tue, Sep 20, 2022 at 4:07 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Tue, Sep 20, 2022 at 3:05 PM Lad, Prabhakar
> <[email protected]> wrote:
> > On Tue, Sep 20, 2022 at 1:32 PM Geert Uytterhoeven <[email protected]> wrote:
> > > On Thu, Sep 15, 2022 at 8:17 PM Prabhakar <[email protected]> wrote:
> > > > From: Lad Prabhakar <[email protected]>
> > > >
> > > > Enable the minimal blocks required for booting the Renesas RZ/Five
> > > > SMARC EVK with initramfs.
> > > >
> > > > Below are the blocks enabled:
> > > > - CPG
> > > > - CPU0
> > > > - DDR (memory regions)
> > > > - PINCTRL
> > > > - PLIC
> > > > - SCIF0
> > > >
> > > > Note we have deleted the nodes from the DT for which support needs to be
> > > > added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier
> > > > board DTS/I.
> > > >
> > > > Signed-off-by: Lad Prabhakar <[email protected]>
>
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> > > > @@ -0,0 +1,42 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +/*
> > > > + * Device Tree Source for the RZ/Five SMARC EVK SOM
> > > > + *
> > > > + * Copyright (C) 2022 Renesas Electronics Corp.
> > > > + */
> > > > +
> > > > +#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
> > > > +
> > > > +/ {
> > > > + aliases {
> > > > + /delete-property/ ethernet0;
> > > > + /delete-property/ ethernet1;
> > >
> > > OK
> > >
> > I assume you are OK with dropping the above too?
>
> I did intend to delete these properties (hence the "OK"), as their
> presence may confuse U-Boot.
>
Thank you for the clarification.
Cheers,
Prabhakar