Hi,
This is the v9 series to add some DRM bridge drivers support
for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
https://patchwork.kernel.org/project/dri-devel/list/?series=629908&state=%2A&archive=both
This series supports the following display pipes:
1) i.MX8qxp:
prefetch eng -> DPU -> pixel combiner -> pixel link ->
pixel link to DPI(PXL2DPI) -> LVDS display bridge(LDB)
2) i.MX8qm:
prefetch eng -> DPU -> pixel combiner -> pixel link -> LVDS display bridge(LDB)
Patch 1/14 and 2/14 add bus formats used by pixel combiner.
Patch 9/14 adds a helper for LDB bridge drivers.
Patch 3/14 ~ 8/14 and 10/14 ~ 12/14 add drm bridge drivers and
dt-bindings support for the bridges.
Patch 13/14 adds dt-binding for Control and Status Registers module(a syscon
used by PXL2DPI and LDB), which references the PXL2DPI and LDB schemas.
Patch 14/14 updates MAINTAINERS.
I've tested this series with a koe,tx26d202vm0bwa dual link LVDS panel and
a LVDS to HDMI bridge(with a downstream drm bridge driver).
Marcel Ziswiler has tested v6 with two LVDS panels(single link LT170410-2WHC
and dual link LP156WF1) on Toradex Colibri iMX8X.
Welcome comments, thanks.
v8->v9:
* Make the pixel link bridge driver(6/14) depend on IMX_SCU. (Laurent)
* Add and use 'fsl,dc-id' and 'fsl,dc-stream-id' properties in pixel link
binding. (Laurent)
v7->v8:
* Rebase upon v5.19-rc1.
* Use devm_drm_of_get_bridge() in patch 9/14 due to the rebase.
* Reorder the patch for adding dt-binding for Control and Status Registers
module as patch 13/14, as it references PXL2DPI and LDB schemas in this
series.
v6->v7:
* Fix complaints from 'checkpatch.pl --strict' on the LDB DRM bridge helper
driver(patch 10/14) and some DRM bridge drivers(patch 9/14, 12/14 and 13/14).
(Robert)
* Fix complaints from 'checkpatch --strict' on the rest DRM bridge
drivers(patch 4/14 and 6/14).
* A trivial indentation fix for patch 9/14. (Robert)
* Add Robert's R-b tags on patch 9/14, 10/14, 12/14, 13/14 and 14/14.
* Add Marcel's T-b tags on all DRM bridge drivers.
* Add Rob's R-b tag on patch 7/14 for CSR module dt-binding.
v5->v6:
* Fix data organizations in documentation(patch 2/14) for
MEDIA_BUS_FMT_RGB{666,888}_1X30-CPADLO. (Laurent)
* Add Laurent's R-b tags on patch 1/14 and 2/14.
* Drop 'select' schema from the CSR dt-binding documentation(patch 7/14). (Rob)
* Add Rob's R-b tag on patch 8/14.
v4->v5:
* Drop the patch 'phy: Add LVDS configuration options'. (Robert)
* Add Robert's R-b tags on patch 1/14, 2/14, 4/14 and 6/14.
* Drop the 'PC_BUF_PARA_REG' register definition from the pixel combiner bridge
driver(patch 4/14). (Robert)
* Make a comment occupy a line in the pixel link bridge driver(patch 6/14).
(Robert)
* Introduce a new patch(patch 7/14) to add dt-binding for Control and Status
Registers module. (Rob)
* Make imx-ldb-helper be a pure object to be linked with i.MX8qxp LDB bridge
driver and i.MX8qm LDB bridge driver, instead of a module. Correspondingly,
rename 'imx8{qm, qxp}-ldb.c' to 'imx8{qm, qxp}-ldb-drv.c'. (Robert)
* Move 'imx_ldb_helper.h' to 'drivers/gpu/drm/bridge/imx/imx-ldb-helper.h'.
(Robert)
* s/__FSL_IMX_LDB__/__IMX_LDB_HELPER__/ for 'imx-ldb-helper.h'.
v3->v4:
* Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with
the PXL2DPI instance instead of using alias ID. (Rob)
* Add Rob's R-b tag on patch 11/14.
v2->v3:
* Drop 'fsl,syscon' DT properties from fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml. (Rob)
* Mention the CSR module controls LDB and PXL2DPI in fsl,imx8qxp-ldb.yaml and
fsl,imx8qxp-pxl2dpi.yaml.
* Call syscon_node_to_regmap() to get regmaps from LDB bridge helper driver
and PXL2DPI bridger driver instead of syscon_regmap_lookup_by_phandle().
* Drop two macros from pixel link bridge driver which help define functions
and define them directly.
* Properly disable all pixel link controls to POR value by calling
imx8qxp_pixel_link_disable_all_controls() from
imx8qxp_pixel_link_bridge_probe().
* Add Rob's R-b tags on patch 4/14 and 6/14.
v1->v2:
* Rebase the series upon the latest drm-misc-next branch(5.11-rc2 based).
* Use graph schema in the dt-bindings of the bridges. (Laurent)
* Require all four pixel link output ports in fsl,imx8qxp-pixel-link.yaml.
(Laurent)
* Side note i.MX8qm/qxp LDB official name 'pixel mapper' in fsl,imx8qxp-ldb.yaml.
(Laurent)
* Mention pixel link is accessed via SCU firmware in fsl,imx8qxp-pixel-link.yaml.
(Rob)
* Use enum instead of oneOf + const for the reg property of pixel combiner
channels in fsl,imx8qxp-pixel-combiner.yaml. (Rob)
* Rewrite the function to find the next bridge in pixel link bridge driver
by properly using OF APIs and dropping unnecessary DT validation. (Rob)
* Drop unnecessary port availability check in i.MX8qxp pixel link to DPI
bridge driver.
* Drop unnecessary DT validation from i.MX8qxp LDB bridge driver.
* Use of_graph_get_endpoint_by_regs() and of_graph_get_remote_endpoint() to
get the input remote endpoint in imx8qxp_ldb_set_di_id() of i.MX8qxp LDB
bridge driver.
* Avoid using companion_port OF node after putting it in
imx8qxp_ldb_parse_dt_companion() of i.MX8qxp LDB bridge driver.
* Drop unnecessary check for maximum available LDB channels from
i.MX8qm LDB bridge driver.
* Mention i.MX8qm/qxp LDB official name 'pixel mapper' in i.MX8qm/qxp LDB
bridge drivers and Kconfig help messages.
Liu Ying (14):
media: uapi: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
media: docs: Add some RGB bus formats for i.MX8qm/qxp pixel combiner
dt-bindings: display: bridge: Add i.MX8qm/qxp pixel combiner binding
drm/bridge: imx: Add i.MX8qm/qxp pixel combiner support
dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link
binding
drm/bridge: imx: Add i.MX8qm/qxp display pixel link support
dt-bindings: display: bridge: Add i.MX8qxp pixel link to DPI binding
drm/bridge: imx: Add i.MX8qxp pixel link to DPI support
drm/bridge: imx: Add LDB driver helper support
dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge
binding
drm/bridge: imx: Add LDB support for i.MX8qxp
drm/bridge: imx: Add LDB support for i.MX8qm
dt-bindings: mfd: Add i.MX8qm/qxp Control and Status Registers module
binding
MAINTAINERS: add maintainer for DRM bridge drivers for i.MX SoCs
.../display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++
.../bridge/fsl,imx8qxp-pixel-combiner.yaml | 144 ++++
.../bridge/fsl,imx8qxp-pixel-link.yaml | 144 ++++
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml | 108 +++
.../bindings/mfd/fsl,imx8qxp-csr.yaml | 192 +++++
.../media/v4l/subdev-formats.rst | 156 ++++
MAINTAINERS | 10 +
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/imx/Kconfig | 43 ++
drivers/gpu/drm/bridge/imx/Makefile | 9 +
drivers/gpu/drm/bridge/imx/imx-ldb-helper.c | 220 ++++++
drivers/gpu/drm/bridge/imx/imx-ldb-helper.h | 96 +++
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c | 587 ++++++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c | 722 ++++++++++++++++++
.../drm/bridge/imx/imx8qxp-pixel-combiner.c | 448 +++++++++++
.../gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 429 +++++++++++
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 487 ++++++++++++
include/uapi/linux/media-bus-format.h | 6 +-
19 files changed, 3976 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
create mode 100644 drivers/gpu/drm/bridge/imx/Kconfig
create mode 100644 drivers/gpu/drm/bridge/imx/Makefile
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx-ldb-helper.h
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-ldb-drv.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
--
2.25.1
This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Add Rob's R-b tag.
v2->v3:
* Drop 'fsl,syscon' property. (Rob)
* Mention the CSR module controls LDB.
v1->v2:
* Use graph schema. (Laurent)
* Side note i.MX8qxp LDB official name 'pixel mapper'. (Laurent)
.../display/bridge/fsl,imx8qxp-ldb.yaml | 173 ++++++++++++++++++
1 file changed, 173 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
new file mode 100644
index 000000000000..94543006f5de
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp LVDS Display Bridge
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
+
+ The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
+ The CSR module, as a system controller, contains the LDB's configuration
+ registers.
+
+ For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
+ format and can map the input to VESA or JEIDA standards. The two channels
+ cannot be used simultaneously, that is to say, the user should pick one of
+ them to use. Two LDB channels from two LDB instances can work together in
+ LDB split mode to support a dual link LVDS display. The channel indexes
+ have to be different. Channel0 outputs odd pixels and channel1 outputs
+ even pixels.
+
+ For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
+ input color format. The two channels can be used simultaneously, either
+ in dual mode or split mode. In dual mode, the two channels output identical
+ data. In split mode, channel0 outputs odd pixels and channel1 outputs even
+ pixels.
+
+ A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
+ the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
+ i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming
+ consistency, this binding calls it LDB.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-ldb
+ - fsl,imx8qxp-ldb
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: pixel clock
+ - description: bypass clock
+
+ clock-names:
+ items:
+ - const: pixel
+ - const: bypass
+
+ power-domains:
+ maxItems: 1
+
+ fsl,companion-ldb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ A phandle which points to companion LDB which is used in LDB split mode.
+
+patternProperties:
+ "^channel@[0-1]$":
+ type: object
+ description: Represents a channel of LDB.
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ reg:
+ description: The channel index.
+ enum: [ 0, 1 ]
+
+ phys:
+ description: A phandle to the phy module representing the LVDS PHY.
+ maxItems: 1
+
+ phy-names:
+ const: lvds_phy
+
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input port of the channel.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output port of the channel.
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - reg
+ - phys
+ - phy-names
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - power-domains
+ - channel@0
+ - channel@1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qm-ldb
+ then:
+ properties:
+ fsl,companion-ldb: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+ };
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+ };
+ };
+ };
+ };
--
2.25.1
This patch adds a drm bridge driver for i.MX8qm LVDS display bridge(LDB)
which is officially named as pixel mapper. The LDB has two channels.
Each of them supports up to 30bpp parallel input color format and can
map the input to VESA or JEIDA standards. The two channels can be used
simultaneously, either in dual mode or split mode. In dual mode, the
two channels output identical data. In split mode, channel0 outputs
odd pixels and channel1 outputs even pixels. This patch supports the
LDB single mode and split mode.
Tested-by: Marcel Ziswiler <[email protected]> # Colibri iMX8X, LT170410-2WHC, LP156WF1
Reviewed-by: Robert Foss <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
Marcel, I add your T-b tag from v6, let me know if you want me to drop it, as
the checkpatch fix in v7 is trivial.
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* Fix below complaints from 'checkpatch.pl --strict'. (Robert)
- 'Prefer using the BIT macro'
- 'Alignment should match open parenthesis'
* Add Marcel's T-b tag.
* Add Robert's R-b tag.
v5->v6:
* No change.
v4->v5:
* Link with the imx-ldb-helper object. (Robert)
* Correspondingly, rename 'imx8qm-ldb.c' to 'imx8qm-ldb-drv.c'.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* Drop unnecessary check for maximum available LDB channels.
* Mention i.MX8qm LDB official name 'pixel mapper' in the bridge driver
and Kconfig help message.
drivers/gpu/drm/bridge/imx/Kconfig | 9 +
drivers/gpu/drm/bridge/imx/Makefile | 3 +
drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c | 587 ++++++++++++++++++++
3 files changed, 599 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index f33d67be54dc..212a7b0e64fd 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -1,3 +1,12 @@
+config DRM_IMX8QM_LDB
+ tristate "Freescale i.MX8QM LVDS display bridge"
+ depends on OF
+ depends on COMMON_CLK
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable the internal LVDS Display Bridge(LDB) found in
+ Freescale i.MX8qm processor. Official name of LDB is pixel mapper.
+
config DRM_IMX8QXP_LDB
tristate "Freescale i.MX8QXP LVDS display bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index 96d5d1e9659d..aa90ec8d5433 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,3 +1,6 @@
+imx8qm-ldb-objs := imx-ldb-helper.o imx8qm-ldb-drv.o
+obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
+
imx8qxp-ldb-objs := imx-ldb-helper.o imx8qxp-ldb-drv.o
obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
new file mode 100644
index 000000000000..29f8f36f814e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qm-ldb-drv.c
@@ -0,0 +1,587 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/phy/phy.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include "imx-ldb-helper.h"
+
+#define LDB_CH0_10BIT_EN BIT(22)
+#define LDB_CH1_10BIT_EN BIT(23)
+#define LDB_CH0_DATA_WIDTH_24BIT BIT(24)
+#define LDB_CH1_DATA_WIDTH_24BIT BIT(26)
+#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24)
+#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26)
+
+#define SS_CTRL 0x20
+#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
+#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
+#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
+#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
+
+#define DRIVER_NAME "imx8qm-ldb"
+
+struct imx8qm_ldb_channel {
+ struct ldb_channel base;
+ struct phy *phy;
+};
+
+struct imx8qm_ldb {
+ struct ldb base;
+ struct device *dev;
+ struct imx8qm_ldb_channel channel[MAX_LDB_CHAN_NUM];
+ struct clk *clk_pixel;
+ struct clk *clk_bypass;
+ int active_chno;
+};
+
+static inline struct imx8qm_ldb_channel *
+base_to_imx8qm_ldb_channel(struct ldb_channel *base)
+{
+ return container_of(base, struct imx8qm_ldb_channel, base);
+}
+
+static inline struct imx8qm_ldb *base_to_imx8qm_ldb(struct ldb *base)
+{
+ return container_of(base, struct imx8qm_ldb, base);
+}
+
+static void imx8qm_ldb_set_phy_cfg(struct imx8qm_ldb *imx8qm_ldb,
+ unsigned long di_clk,
+ bool is_split, bool is_slave,
+ struct phy_configure_opts_lvds *phy_cfg)
+{
+ phy_cfg->bits_per_lane_and_dclk_cycle = 7;
+ phy_cfg->lanes = 4;
+ phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk;
+ phy_cfg->is_slave = is_slave;
+}
+
+static int imx8qm_ldb_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct drm_display_mode *adj = &crtc_state->adjusted_mode;
+ unsigned long di_clk = adj->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ int ret;
+
+ ret = ldb_bridge_atomic_check_helper(bridge, bridge_state,
+ crtc_state, conn_state);
+ if (ret)
+ return ret;
+
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
+ ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
+ if (ret < 0) {
+ DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
+ "failed to validate PHY: %d\n", ret);
+ return ret;
+ }
+
+ if (is_split) {
+ imx8qm_ldb_ch =
+ &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
+ phy_cfg);
+ ret = phy_validate(imx8qm_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts);
+ if (ret < 0) {
+ DRM_DEV_DEBUG_DRIVER(imx8qm_ldb->dev,
+ "failed to validate slave PHY: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static void
+imx8qm_ldb_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ unsigned long di_clk = adjusted_mode->clock * 1000;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ union phy_configure_opts opts = { };
+ struct phy_configure_opts_lvds *phy_cfg = &opts.lvds;
+ u32 chno = ldb_ch->chno;
+ int ret;
+
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret);
+
+ ret = phy_init(imx8qm_ldb_ch->phy);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret);
+
+ clk_set_rate(imx8qm_ldb->clk_bypass, di_clk);
+ clk_set_rate(imx8qm_ldb->clk_pixel, di_clk);
+
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg);
+ ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret);
+
+ if (is_split) {
+ imx8qm_ldb_ch =
+ &imx8qm_ldb->channel[imx8qm_ldb->active_chno ^ 1];
+ imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true,
+ phy_cfg);
+ ret = phy_configure(imx8qm_ldb_ch->phy, &opts);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to configure slave PHY: %d\n",
+ ret);
+ }
+
+ /* input VSYNC signal from pixel link is active low */
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
+
+ switch (ldb_ch->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ if (ldb_ch->chno == 0 || is_split)
+ ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT;
+ if (ldb_ch->chno == 1 || is_split)
+ ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT;
+ break;
+ }
+
+ ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode);
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_VSYNC_M(chno), CH_PVSYNC(chno));
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0);
+ else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ regmap_update_bits(ldb->regmap, SS_CTRL,
+ CH_HSYNC_M(chno), CH_PHSYNC(chno));
+}
+
+static void
+imx8qm_ldb_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ clk_prepare_enable(imx8qm_ldb->clk_pixel);
+ clk_prepare_enable(imx8qm_ldb->clk_bypass);
+
+ /* both DI0 and DI1 connect with pixel link, so ok to use DI0 only */
+ if (ldb_ch->chno == 0 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
+ ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
+ }
+ if (ldb_ch->chno == 1 || is_split) {
+ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
+ ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
+ }
+
+ if (is_split) {
+ ret = phy_power_on(imx8qm_ldb->channel[0].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power on channel0 PHY: %d\n",
+ ret);
+
+ ret = phy_power_on(imx8qm_ldb->channel[1].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power on channel1 PHY: %d\n",
+ ret);
+ } else {
+ ret = phy_power_on(imx8qm_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret);
+ }
+
+ ldb_bridge_enable_helper(bridge);
+}
+
+static void
+imx8qm_ldb_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ struct ldb *ldb = ldb_ch->ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch =
+ base_to_imx8qm_ldb_channel(ldb_ch);
+ struct imx8qm_ldb *imx8qm_ldb = base_to_imx8qm_ldb(ldb);
+ struct device *dev = imx8qm_ldb->dev;
+ bool is_split = ldb_channel_is_split_link(ldb_ch);
+ int ret;
+
+ ldb_bridge_disable_helper(bridge);
+
+ if (is_split) {
+ ret = phy_power_off(imx8qm_ldb->channel[0].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power off channel0 PHY: %d\n",
+ ret);
+ ret = phy_power_off(imx8qm_ldb->channel[1].phy);
+ if (ret)
+ DRM_DEV_ERROR(dev,
+ "failed to power off channel1 PHY: %d\n",
+ ret);
+ } else {
+ ret = phy_power_off(imx8qm_ldb_ch->phy);
+ if (ret)
+ DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret);
+ }
+
+ clk_disable_unprepare(imx8qm_ldb->clk_bypass);
+ clk_disable_unprepare(imx8qm_ldb->clk_pixel);
+
+ ret = pm_runtime_put(dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(dev, "failed to put runtime PM: %d\n", ret);
+}
+
+static const u32 imx8qm_ldb_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
+ MEDIA_BUS_FMT_FIXED,
+};
+
+static bool imx8qm_ldb_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qm_ldb_bus_output_fmts); i++) {
+ if (imx8qm_ldb_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qm_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ struct drm_display_info *di;
+ const struct drm_format_info *finfo;
+ u32 *input_fmts;
+
+ if (!imx8qm_ldb_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_FIXED:
+ di = &conn_state->connector->display_info;
+
+ /*
+ * Look at the first bus format to determine input format.
+ * Default to MEDIA_BUS_FMT_RGB888_1X36_CPADLO, if no match.
+ */
+ if (di->num_bus_formats) {
+ finfo = drm_format_info(di->bus_formats[0]);
+
+ input_fmts[0] = finfo->depth == 18 ?
+ MEDIA_BUS_FMT_RGB666_1X36_CPADLO :
+ MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ } else {
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ }
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qm_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qm_ldb_bus_output_fmts);
+ return kmemdup(imx8qm_ldb_bus_output_fmts,
+ sizeof(imx8qm_ldb_bus_output_fmts), GFP_KERNEL);
+}
+
+static enum drm_mode_status
+imx8qm_ldb_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ struct ldb_channel *ldb_ch = bridge->driver_private;
+ bool is_single = ldb_channel_is_single_link(ldb_ch);
+
+ if (mode->clock > 300000)
+ return MODE_CLOCK_HIGH;
+
+ if (mode->clock > 150000 && is_single)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static const struct drm_bridge_funcs imx8qm_ldb_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .mode_valid = imx8qm_ldb_bridge_mode_valid,
+ .attach = ldb_bridge_attach_helper,
+ .atomic_check = imx8qm_ldb_bridge_atomic_check,
+ .mode_set = imx8qm_ldb_bridge_mode_set,
+ .atomic_enable = imx8qm_ldb_bridge_atomic_enable,
+ .atomic_disable = imx8qm_ldb_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qm_ldb_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qm_ldb_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qm_ldb_get_phy(struct imx8qm_ldb *imx8qm_ldb)
+{
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch;
+ struct ldb_channel *ldb_ch;
+ struct device *dev = imx8qm_ldb->dev;
+ int i, ret;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
+ ldb_ch = &imx8qm_ldb_ch->base;
+
+ if (!ldb_ch->is_available)
+ continue;
+
+ imx8qm_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np,
+ "lvds_phy");
+ if (IS_ERR(imx8qm_ldb_ch->phy)) {
+ ret = PTR_ERR(imx8qm_ldb_ch->phy);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get channel%d PHY: %d\n",
+ i, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int imx8qm_ldb_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct imx8qm_ldb *imx8qm_ldb;
+ struct imx8qm_ldb_channel *imx8qm_ldb_ch;
+ struct ldb *ldb;
+ struct ldb_channel *ldb_ch;
+ struct device_node *port1, *port2;
+ int pixel_order;
+ int ret, i;
+
+ imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL);
+ if (!imx8qm_ldb)
+ return -ENOMEM;
+
+ imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel");
+ if (IS_ERR(imx8qm_ldb->clk_pixel)) {
+ ret = PTR_ERR(imx8qm_ldb->clk_pixel);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get pixel clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass");
+ if (IS_ERR(imx8qm_ldb->clk_bypass)) {
+ ret = PTR_ERR(imx8qm_ldb->clk_bypass);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev,
+ "failed to get bypass clock: %d\n", ret);
+ return ret;
+ }
+
+ imx8qm_ldb->dev = dev;
+
+ ldb = &imx8qm_ldb->base;
+ ldb->dev = dev;
+ ldb->ctrl_reg = 0xe0;
+
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++)
+ ldb->channel[i] = &imx8qm_ldb->channel[i].base;
+
+ ret = ldb_init_helper(ldb);
+ if (ret)
+ return ret;
+
+ if (ldb->available_ch_cnt == 0) {
+ DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n");
+ return 0;
+ }
+
+ if (ldb->available_ch_cnt == 2) {
+ port1 = of_graph_get_port_by_id(ldb->channel[0]->np, 1);
+ port2 = of_graph_get_port_by_id(ldb->channel[1]->np, 1);
+ pixel_order =
+ drm_of_lvds_get_dual_link_pixel_order(port1, port2);
+ of_node_put(port1);
+ of_node_put(port2);
+
+ if (pixel_order != DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
+ DRM_DEV_ERROR(dev, "invalid dual link pixel order: %d\n",
+ pixel_order);
+ return -EINVAL;
+ }
+
+ imx8qm_ldb->active_chno = 0;
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[0];
+ ldb_ch = &imx8qm_ldb_ch->base;
+ ldb_ch->link_type = pixel_order;
+ } else {
+ for (i = 0; i < MAX_LDB_CHAN_NUM; i++) {
+ imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
+ ldb_ch = &imx8qm_ldb_ch->base;
+
+ if (ldb_ch->is_available) {
+ imx8qm_ldb->active_chno = ldb_ch->chno;
+ break;
+ }
+ }
+ }
+
+ ret = imx8qm_ldb_get_phy(imx8qm_ldb);
+ if (ret)
+ return ret;
+
+ ret = ldb_find_next_bridge_helper(ldb);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, imx8qm_ldb);
+ pm_runtime_enable(dev);
+
+ ldb_add_bridge_helper(ldb, &imx8qm_ldb_bridge_funcs);
+
+ return ret;
+}
+
+static int imx8qm_ldb_remove(struct platform_device *pdev)
+{
+ struct imx8qm_ldb *imx8qm_ldb = platform_get_drvdata(pdev);
+ struct ldb *ldb = &imx8qm_ldb->base;
+
+ ldb_remove_bridge_helper(ldb);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static int __maybe_unused imx8qm_ldb_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int __maybe_unused imx8qm_ldb_runtime_resume(struct device *dev)
+{
+ struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
+ struct ldb *ldb = &imx8qm_ldb->base;
+
+ /* disable LDB by resetting the control register to POR default */
+ regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
+
+ return 0;
+}
+
+static const struct dev_pm_ops imx8qm_ldb_pm_ops = {
+ SET_RUNTIME_PM_OPS(imx8qm_ldb_runtime_suspend,
+ imx8qm_ldb_runtime_resume, NULL)
+};
+
+static const struct of_device_id imx8qm_ldb_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-ldb" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids);
+
+static struct platform_driver imx8qm_ldb_driver = {
+ .probe = imx8qm_ldb_probe,
+ .remove = imx8qm_ldb_remove,
+ .driver = {
+ .pm = &imx8qm_ldb_pm_ops,
+ .name = DRIVER_NAME,
+ .of_match_table = imx8qm_ldb_dt_ids,
+ },
+};
+module_platform_driver(imx8qm_ldb_driver);
+
+MODULE_DESCRIPTION("i.MX8QM LVDS Display Bridge(LDB)/Pixel Mapper bridge driver");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.25.1
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a control interface.
Reviewed-by: Robert Foss <[email protected]>
Tested-by: Marcel Ziswiler <[email protected]> # Colibri iMX8X, LT170410-2WHC, LP156WF1
Signed-off-by: Liu Ying <[email protected]>
---
Robert, I keep your R-b tag from v5. Let me know if you want me to drop it, as
v7 contains a fix for checkpatch complaints and change in v9 is kinda trivial.
Marcel, as the v7 fix and v9 change are kinda trivial, I add your T-b tag. Let
me know if you want me to drop it.
v8->v9:
* Depend on IMX_SCU. (Laurent)
* Get DC index and DC stream index from 'fsl,dc-id' and 'fsl,dc-stream-id'
properties instead of OF alias. (Laurent)
v7->v8:
* No change.
v6->v7:
* Fix 'Alignment should match open parenthesis' complaints from
'checkpatch.pl --strict'.
* Add Marcel's T-b tag.
v5->v6:
* No change.
v4->v5:
* Make a comment occupy a line. (Robert)
* Add Robert's R-b tag.
v3->v4:
* No change.
v2->v3:
* Drop two macros which help define functions and define them directly.
* Properly disable all pixel link controls to POR value by calling
imx8qxp_pixel_link_disable_all_controls() from
imx8qxp_pixel_link_bridge_probe().
v1->v2:
* Rewrite the function to find the next bridge by properly using OF APIs
and dropping unnecessary DT validation. (Rob)
drivers/gpu/drm/bridge/imx/Kconfig | 9 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
.../gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 429 ++++++++++++++++++
3 files changed, 439 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index f1c91b6814a5..9f6ec601af37 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -6,3 +6,12 @@ config DRM_IMX8QXP_PIXEL_COMBINER
help
Choose this to enable pixel combiner found in
Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK
+ tristate "Freescale i.MX8QM/QXP display pixel link"
+ depends on OF
+ depends on IMX_SCU
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable display pixel link found in
+ Freescale i.MX8qm/qxp processors.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index 7d7c8d674bf0..c15469fb5789 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
new file mode 100644
index 000000000000..305c833f11ee
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020,2022 NXP
+ */
+
+#include <linux/firmware/imx/svc/misc.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_print.h>
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#define DRIVER_NAME "imx8qxp-display-pixel-link"
+#define PL_MAX_MST_ADDR 3
+#define PL_MAX_NEXT_BRIDGES 2
+
+struct imx8qxp_pixel_link {
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct device *dev;
+ struct imx_sc_ipc *ipc_handle;
+ u8 stream_id;
+ u8 dc_id;
+ u32 sink_rsc;
+ u32 mst_addr;
+ u8 mst_addr_ctrl;
+ u8 mst_en_ctrl;
+ u8 mst_vld_ctrl;
+ u8 sync_ctrl;
+};
+
+static void imx8qxp_pixel_link_enable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%u stream%u pixel link mst_en: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%u stream%u pixel link mst_vld: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static void imx8qxp_pixel_link_enable_sync(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->sync_ctrl, true);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to enable DC%u stream%u pixel link sync: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+}
+
+static int imx8qxp_pixel_link_disable_mst_en(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_en_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%u stream%u pixel link mst_en: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_disable_mst_vld(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->mst_vld_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%u stream%u pixel link mst_vld: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_disable_sync(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc,
+ pl->sync_ctrl, false);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to disable DC%u stream%u pixel link sync: %d\n",
+ pl->dc_id, pl->stream_id, ret);
+
+ return ret;
+}
+
+static void imx8qxp_pixel_link_set_mst_addr(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx_sc_misc_set_control(pl->ipc_handle,
+ pl->sink_rsc, pl->mst_addr_ctrl,
+ pl->mst_addr);
+ if (ret)
+ DRM_DEV_ERROR(pl->dev,
+ "failed to set DC%u stream%u pixel link mst addr(%u): %d\n",
+ pl->dc_id, pl->stream_id, pl->mst_addr, ret);
+}
+
+static int imx8qxp_pixel_link_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(pl->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(pl->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ pl->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static void
+imx8qxp_pixel_link_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_set_mst_addr(pl);
+}
+
+static void
+imx8qxp_pixel_link_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_enable_mst_en(pl);
+ imx8qxp_pixel_link_enable_mst_vld(pl);
+ imx8qxp_pixel_link_enable_sync(pl);
+}
+
+static void
+imx8qxp_pixel_link_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pixel_link *pl = bridge->driver_private;
+
+ imx8qxp_pixel_link_disable_mst_en(pl);
+ imx8qxp_pixel_link_disable_mst_vld(pl);
+ imx8qxp_pixel_link_disable_sync(pl);
+}
+
+static const u32 imx8qxp_pixel_link_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
+ MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
+};
+
+static bool imx8qxp_pixel_link_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts); i++) {
+ if (imx8qxp_pixel_link_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ if (!imx8qxp_pixel_link_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ input_fmts[0] = output_fmt;
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_pixel_link_bus_output_fmts);
+ return kmemdup(imx8qxp_pixel_link_bus_output_fmts,
+ sizeof(imx8qxp_pixel_link_bus_output_fmts), GFP_KERNEL);
+}
+
+static const struct drm_bridge_funcs imx8qxp_pixel_link_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = imx8qxp_pixel_link_bridge_attach,
+ .mode_set = imx8qxp_pixel_link_bridge_mode_set,
+ .atomic_enable = imx8qxp_pixel_link_bridge_atomic_enable,
+ .atomic_disable = imx8qxp_pixel_link_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_pixel_link_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_pixel_link_bridge_atomic_get_output_bus_fmts,
+};
+
+static int imx8qxp_pixel_link_disable_all_controls(struct imx8qxp_pixel_link *pl)
+{
+ int ret;
+
+ ret = imx8qxp_pixel_link_disable_mst_en(pl);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_pixel_link_disable_mst_vld(pl);
+ if (ret)
+ return ret;
+
+ return imx8qxp_pixel_link_disable_sync(pl);
+}
+
+static struct drm_bridge *
+imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl)
+{
+ struct device_node *np = pl->dev->of_node;
+ struct device_node *port, *remote;
+ struct drm_bridge *next_bridge[PL_MAX_NEXT_BRIDGES];
+ u32 port_id;
+ bool found_port = false;
+ int reg, ep_cnt = 0;
+ /* select the first next bridge by default */
+ int bridge_sel = 0;
+
+ for (port_id = 1; port_id <= PL_MAX_MST_ADDR + 1; port_id++) {
+ port = of_graph_get_port_by_id(np, port_id);
+ if (!port)
+ continue;
+
+ if (of_device_is_available(port)) {
+ found_port = true;
+ of_node_put(port);
+ break;
+ }
+
+ of_node_put(port);
+ }
+
+ if (!found_port) {
+ DRM_DEV_ERROR(pl->dev, "no available output port\n");
+ return ERR_PTR(-ENODEV);
+ }
+
+ for (reg = 0; reg < PL_MAX_NEXT_BRIDGES; reg++) {
+ remote = of_graph_get_remote_node(np, port_id, reg);
+ if (!remote)
+ continue;
+
+ if (!of_device_is_available(remote->parent)) {
+ DRM_DEV_DEBUG(pl->dev,
+ "port%u endpoint%u remote parent is not available\n",
+ port_id, reg);
+ of_node_put(remote);
+ continue;
+ }
+
+ next_bridge[ep_cnt] = of_drm_find_bridge(remote);
+ if (!next_bridge[ep_cnt]) {
+ of_node_put(remote);
+ return ERR_PTR(-EPROBE_DEFER);
+ }
+
+ /* specially select the next bridge with companion PXL2DPI */
+ if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL))
+ bridge_sel = ep_cnt;
+
+ ep_cnt++;
+
+ of_node_put(remote);
+ }
+
+ pl->mst_addr = port_id - 1;
+
+ return next_bridge[bridge_sel];
+}
+
+static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev)
+{
+ struct imx8qxp_pixel_link *pl;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ pl = devm_kzalloc(dev, sizeof(*pl), GFP_KERNEL);
+ if (!pl)
+ return -ENOMEM;
+
+ ret = imx_scu_get_handle(&pl->ipc_handle);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = of_property_read_u8(np, "fsl,dc-id", &pl->dc_id);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to get DC index: %d\n", ret);
+ return ret;
+ }
+
+ ret = of_property_read_u8(np, "fsl,dc-stream-id", &pl->stream_id);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to get DC stream index: %d\n", ret);
+ return ret;
+ }
+
+ pl->dev = dev;
+
+ pl->sink_rsc = pl->dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
+
+ if (pl->stream_id == 0) {
+ pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST1_ADDR;
+ pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST1_ENB;
+ pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST1_VLD;
+ pl->sync_ctrl = IMX_SC_C_SYNC_CTRL0;
+ } else {
+ pl->mst_addr_ctrl = IMX_SC_C_PXL_LINK_MST2_ADDR;
+ pl->mst_en_ctrl = IMX_SC_C_PXL_LINK_MST2_ENB;
+ pl->mst_vld_ctrl = IMX_SC_C_PXL_LINK_MST2_VLD;
+ pl->sync_ctrl = IMX_SC_C_SYNC_CTRL1;
+ }
+
+ /* disable all controls to POR default */
+ ret = imx8qxp_pixel_link_disable_all_controls(pl);
+ if (ret)
+ return ret;
+
+ pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl);
+ if (IS_ERR(pl->next_bridge)) {
+ ret = PTR_ERR(pl->next_bridge);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, pl);
+
+ pl->bridge.driver_private = pl;
+ pl->bridge.funcs = &imx8qxp_pixel_link_bridge_funcs;
+ pl->bridge.of_node = np;
+
+ drm_bridge_add(&pl->bridge);
+
+ return ret;
+}
+
+static int imx8qxp_pixel_link_bridge_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_pixel_link *pl = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&pl->bridge);
+
+ return 0;
+}
+
+static const struct of_device_id imx8qxp_pixel_link_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-dc-pixel-link", },
+ { .compatible = "fsl,imx8qxp-dc-pixel-link", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_pixel_link_dt_ids);
+
+static struct platform_driver imx8qxp_pixel_link_bridge_driver = {
+ .probe = imx8qxp_pixel_link_bridge_probe,
+ .remove = imx8qxp_pixel_link_bridge_remove,
+ .driver = {
+ .of_match_table = imx8qxp_pixel_link_dt_ids,
+ .name = DRIVER_NAME,
+ },
+};
+module_platform_driver(imx8qxp_pixel_link_bridge_driver);
+
+MODULE_DESCRIPTION("i.MX8QXP/QM display pixel link bridge driver");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.25.1
This patch adds bindings for i.MX8qm/qxp display pixel link.
Signed-off-by: Liu Ying <[email protected]>
---
v8->v9:
* Add 'fsl,dc-id' and 'fsl,dc-stream-id' properties. (Laurent)
* Drop Rob's R-b tag.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* Add Rob's R-b tag.
v1->v2:
* Use graph schema. (Laurent)
* Require all four pixel link output ports. (Laurent)
* Mention pixel link is accessed via SCU firmware. (Rob)
.../bridge/fsl,imx8qxp-pixel-link.yaml | 144 ++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
new file mode 100644
index 000000000000..38ecc7926fad
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Display Pixel Link
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
+ asynchronous linkage between pixel sources(display controller or
+ camera module) and pixel consumers(imaging or displays).
+ It consists of two distinct functions, a pixel transfer function and a
+ control interface. Multiple pixel channels can exist per one control channel.
+ This binding documentation is only for pixel links whose pixel sources are
+ display controllers.
+
+ The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
+ firmware.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-dc-pixel-link
+ - fsl,imx8qxp-dc-pixel-link
+
+ fsl,dc-id:
+ $ref: /schemas/types.yaml#/definitions/uint8
+ description: |
+ u8 value representing the display controller index that the pixel link
+ connects to.
+
+ fsl,dc-stream-id:
+ $ref: /schemas/types.yaml#/definitions/uint8
+ description: |
+ u8 value representing the display controller stream index that the pixel
+ link connects to.
+ enum: [0, 1]
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The pixel link input port node from upstream video source.
+
+ patternProperties:
+ "^port@[1-4]$":
+ $ref: /schemas/graph.yaml#/properties/port
+ description: The pixel link output port node to downstream bridge.
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - port@3
+ - port@4
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qxp-dc-pixel-link
+ then:
+ properties:
+ fsl,dc-id:
+ const: 0
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qm-dc-pixel-link
+ then:
+ properties:
+ fsl,dc-id:
+ enum: [0, 1]
+
+required:
+ - compatible
+ - fsl,dc-id
+ - fsl,dc-stream-id
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ dc0-pixel-link0 {
+ compatible = "fsl,imx8qxp-dc-pixel-link";
+ fsl,dc-id = /bits/ 8 <0>;
+ fsl,dc-stream-id = /bits/ 8 <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* from dc0 pixel combiner channel0 */
+ port@0 {
+ reg = <0>;
+
+ dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
+ remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
+ };
+ };
+
+ /* to PXL2DPIs in MIPI/LVDS combo subsystems */
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
+ };
+
+ dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
+ };
+ };
+
+ /* unused */
+ port@2 {
+ reg = <2>;
+ };
+
+ /* unused */
+ port@3 {
+ reg = <3>;
+ };
+
+ /* to imaging subsystem */
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
--
2.25.1
This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color codings between those modules. The PXL2DPI is purely
combinatorial.
Tested-by: Marcel Ziswiler <[email protected]> # Colibri iMX8X, LT170410-2WHC, LP156WF1
Reviewed-by: Robert Foss <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
Marcel, I add your T-b tag from v6, let me know if you want me to drop it, as
the checkpatch fix and indentation fix in v7 are trivial.
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* Fix below complaints from 'checkpatch.pl --strict'. (Robert)
- 'Alignment should match open parenthesis'
- 'ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP'
* A trivial indentation fix. (Robert)
* Add Marcel's T-b tag.
* Add Robert's R-b tag.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* Use 'fsl,sc-resource' DT property to get the SCU resource ID associated with
the PXL2DPI instance instead of using alias ID. (Rob)
v2->v3:
* Call syscon_node_to_regmap() to get regmap instead of
syscon_regmap_lookup_by_phandle().
v1->v2:
* Drop unnecessary port availability check.
drivers/gpu/drm/bridge/imx/Kconfig | 8 +
drivers/gpu/drm/bridge/imx/Makefile | 1 +
drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c | 487 +++++++++++++++++++
3 files changed, 496 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
diff --git a/drivers/gpu/drm/bridge/imx/Kconfig b/drivers/gpu/drm/bridge/imx/Kconfig
index 9f6ec601af37..53001650a61a 100644
--- a/drivers/gpu/drm/bridge/imx/Kconfig
+++ b/drivers/gpu/drm/bridge/imx/Kconfig
@@ -15,3 +15,11 @@ config DRM_IMX8QXP_PIXEL_LINK
help
Choose this to enable display pixel link found in
Freescale i.MX8qm/qxp processors.
+
+config DRM_IMX8QXP_PIXEL_LINK_TO_DPI
+ tristate "Freescale i.MX8QXP pixel link to display pixel interface"
+ depends on OF
+ select DRM_KMS_HELPER
+ help
+ Choose this to enable pixel link to display pixel interface(PXL2DPI)
+ found in Freescale i.MX8qxp processor.
diff --git a/drivers/gpu/drm/bridge/imx/Makefile b/drivers/gpu/drm/bridge/imx/Makefile
index c15469fb5789..e74dd6422e95 100644
--- a/drivers/gpu/drm/bridge/imx/Makefile
+++ b/drivers/gpu/drm/bridge/imx/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
+obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
new file mode 100644
index 000000000000..309f47a14cb6
--- /dev/null
+++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <linux/firmware/imx/svc/misc.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+#define PXL2DPI_CTRL 0x40
+#define CFG1_16BIT 0x0
+#define CFG2_16BIT 0x1
+#define CFG3_16BIT 0x2
+#define CFG1_18BIT 0x3
+#define CFG2_18BIT 0x4
+#define CFG_24BIT 0x5
+
+#define DRIVER_NAME "imx8qxp-pxl2dpi"
+
+struct imx8qxp_pxl2dpi {
+ struct regmap *regmap;
+ struct drm_bridge bridge;
+ struct drm_bridge *next_bridge;
+ struct drm_bridge *companion;
+ struct device *dev;
+ struct imx_sc_ipc *ipc_handle;
+ u32 sc_resource;
+ u32 in_bus_format;
+ u32 out_bus_format;
+ u32 pl_sel;
+};
+
+#define bridge_to_p2d(b) container_of(b, struct imx8qxp_pxl2dpi, bridge)
+
+static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ DRM_DEV_ERROR(p2d->dev,
+ "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ if (!bridge->encoder) {
+ DRM_DEV_ERROR(p2d->dev, "missing encoder\n");
+ return -ENODEV;
+ }
+
+ return drm_bridge_attach(bridge->encoder,
+ p2d->next_bridge, bridge,
+ DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static int
+imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+
+ p2d->in_bus_format = bridge_state->input_bus_cfg.format;
+ p2d->out_bus_format = bridge_state->output_bus_cfg.format;
+
+ return 0;
+}
+
+static void
+imx8qxp_pxl2dpi_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+ struct imx8qxp_pxl2dpi *companion_p2d;
+ int ret;
+
+ ret = pm_runtime_get_sync(p2d->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to get runtime PM sync: %d\n", ret);
+
+ ret = imx_sc_misc_set_control(p2d->ipc_handle, p2d->sc_resource,
+ IMX_SC_C_PXL_LINK_SEL, p2d->pl_sel);
+ if (ret)
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to set pixel link selection(%u): %d\n",
+ p2d->pl_sel, ret);
+
+ switch (p2d->out_bus_format) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG_24BIT);
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ regmap_write(p2d->regmap, PXL2DPI_CTRL, CFG2_18BIT);
+ break;
+ default:
+ DRM_DEV_ERROR(p2d->dev,
+ "unsupported output bus format 0x%08x\n",
+ p2d->out_bus_format);
+ }
+
+ if (p2d->companion) {
+ companion_p2d = bridge_to_p2d(p2d->companion);
+
+ companion_p2d->in_bus_format = p2d->in_bus_format;
+ companion_p2d->out_bus_format = p2d->out_bus_format;
+
+ p2d->companion->funcs->mode_set(p2d->companion, mode,
+ adjusted_mode);
+ }
+}
+
+static void
+imx8qxp_pxl2dpi_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
+{
+ struct imx8qxp_pxl2dpi *p2d = bridge->driver_private;
+ int ret;
+
+ ret = pm_runtime_put(p2d->dev);
+ if (ret < 0)
+ DRM_DEV_ERROR(p2d->dev, "failed to put runtime PM: %d\n", ret);
+
+ if (p2d->companion)
+ p2d->companion->funcs->atomic_disable(p2d->companion,
+ old_bridge_state);
+}
+
+static const u32 imx8qxp_pxl2dpi_bus_output_fmts[] = {
+ MEDIA_BUS_FMT_RGB888_1X24,
+ MEDIA_BUS_FMT_RGB666_1X24_CPADHI,
+};
+
+static bool imx8qxp_pxl2dpi_bus_output_fmt_supported(u32 fmt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts); i++) {
+ if (imx8qxp_pxl2dpi_bus_output_fmts[i] == fmt)
+ return true;
+ }
+
+ return false;
+}
+
+static u32 *
+imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ if (!imx8qxp_pxl2dpi_bus_output_fmt_supported(output_fmt))
+ return NULL;
+
+ *num_input_fmts = 1;
+
+ input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
+ if (!input_fmts)
+ return NULL;
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X36_CPADLO;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X36_CPADLO;
+ break;
+ default:
+ kfree(input_fmts);
+ input_fmts = NULL;
+ break;
+ }
+
+ return input_fmts;
+}
+
+static u32 *
+imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ unsigned int *num_output_fmts)
+{
+ *num_output_fmts = ARRAY_SIZE(imx8qxp_pxl2dpi_bus_output_fmts);
+ return kmemdup(imx8qxp_pxl2dpi_bus_output_fmts,
+ sizeof(imx8qxp_pxl2dpi_bus_output_fmts), GFP_KERNEL);
+}
+
+static const struct drm_bridge_funcs imx8qxp_pxl2dpi_bridge_funcs = {
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .attach = imx8qxp_pxl2dpi_bridge_attach,
+ .atomic_check = imx8qxp_pxl2dpi_bridge_atomic_check,
+ .mode_set = imx8qxp_pxl2dpi_bridge_mode_set,
+ .atomic_disable = imx8qxp_pxl2dpi_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts =
+ imx8qxp_pxl2dpi_bridge_atomic_get_input_bus_fmts,
+ .atomic_get_output_bus_fmts =
+ imx8qxp_pxl2dpi_bridge_atomic_get_output_bus_fmts,
+};
+
+static struct device_node *
+imx8qxp_pxl2dpi_get_available_ep_from_port(struct imx8qxp_pxl2dpi *p2d,
+ u32 port_id)
+{
+ struct device_node *port, *ep;
+ int ep_cnt;
+
+ port = of_graph_get_port_by_id(p2d->dev->of_node, port_id);
+ if (!port) {
+ DRM_DEV_ERROR(p2d->dev, "failed to get port@%u\n", port_id);
+ return ERR_PTR(-ENODEV);
+ }
+
+ ep_cnt = of_get_available_child_count(port);
+ if (ep_cnt == 0) {
+ DRM_DEV_ERROR(p2d->dev, "no available endpoints of port@%u\n",
+ port_id);
+ ep = ERR_PTR(-ENODEV);
+ goto out;
+ } else if (ep_cnt > 1) {
+ DRM_DEV_ERROR(p2d->dev,
+ "invalid available endpoints of port@%u\n",
+ port_id);
+ ep = ERR_PTR(-EINVAL);
+ goto out;
+ }
+
+ ep = of_get_next_available_child(port, NULL);
+ if (!ep) {
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to get available endpoint of port@%u\n",
+ port_id);
+ ep = ERR_PTR(-ENODEV);
+ goto out;
+ }
+out:
+ of_node_put(port);
+ return ep;
+}
+
+static struct drm_bridge *
+imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct device_node *ep, *remote;
+ struct drm_bridge *next_bridge;
+ int ret;
+
+ ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1);
+ if (IS_ERR(ep)) {
+ ret = PTR_ERR(ep);
+ return ERR_PTR(ret);
+ }
+
+ remote = of_graph_get_remote_port_parent(ep);
+ if (!remote || !of_device_is_available(remote)) {
+ DRM_DEV_ERROR(p2d->dev, "no available remote\n");
+ next_bridge = ERR_PTR(-ENODEV);
+ goto out;
+ } else if (!of_device_is_available(remote->parent)) {
+ DRM_DEV_ERROR(p2d->dev, "remote parent is not available\n");
+ next_bridge = ERR_PTR(-ENODEV);
+ goto out;
+ }
+
+ next_bridge = of_drm_find_bridge(remote);
+ if (!next_bridge) {
+ next_bridge = ERR_PTR(-EPROBE_DEFER);
+ goto out;
+ }
+out:
+ of_node_put(remote);
+ of_node_put(ep);
+
+ return next_bridge;
+}
+
+static int imx8qxp_pxl2dpi_set_pixel_link_sel(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct device_node *ep;
+ struct of_endpoint endpoint;
+ int ret;
+
+ ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 0);
+ if (IS_ERR(ep))
+ return PTR_ERR(ep);
+
+ ret = of_graph_parse_endpoint(ep, &endpoint);
+ if (ret) {
+ DRM_DEV_ERROR(p2d->dev,
+ "failed to parse endpoint of port@0: %d\n", ret);
+ goto out;
+ }
+
+ p2d->pl_sel = endpoint.id;
+out:
+ of_node_put(ep);
+
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d)
+{
+ struct imx8qxp_pxl2dpi *companion_p2d;
+ struct device *dev = p2d->dev;
+ struct device_node *companion;
+ struct device_node *port1, *port2;
+ const struct of_device_id *match;
+ int dual_link;
+ int ret = 0;
+
+ /* Locate the companion PXL2DPI for dual-link operation, if any. */
+ companion = of_parse_phandle(dev->of_node, "fsl,companion-pxl2dpi", 0);
+ if (!companion)
+ return 0;
+
+ if (!of_device_is_available(companion)) {
+ DRM_DEV_ERROR(dev, "companion PXL2DPI is not available\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ /*
+ * Sanity check: the companion bridge must have the same compatible
+ * string.
+ */
+ match = of_match_device(dev->driver->of_match_table, dev);
+ if (!of_device_is_compatible(companion, match->compatible)) {
+ DRM_DEV_ERROR(dev, "companion PXL2DPI is incompatible\n");
+ ret = -ENXIO;
+ goto out;
+ }
+
+ p2d->companion = of_drm_find_bridge(companion);
+ if (!p2d->companion) {
+ ret = -EPROBE_DEFER;
+ DRM_DEV_DEBUG_DRIVER(p2d->dev,
+ "failed to find companion bridge: %d\n",
+ ret);
+ goto out;
+ }
+
+ companion_p2d = bridge_to_p2d(p2d->companion);
+
+ /*
+ * We need to work out if the sink is expecting us to function in
+ * dual-link mode. We do this by looking at the DT port nodes that
+ * the next bridges are connected to. If they are marked as expecting
+ * even pixels and odd pixels than we need to use the companion PXL2DPI.
+ */
+ port1 = of_graph_get_port_by_id(p2d->next_bridge->of_node, 1);
+ port2 = of_graph_get_port_by_id(companion_p2d->next_bridge->of_node, 1);
+ dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2);
+ of_node_put(port1);
+ of_node_put(port2);
+
+ if (dual_link < 0) {
+ ret = dual_link;
+ DRM_DEV_ERROR(dev, "failed to get dual link pixel order: %d\n",
+ ret);
+ goto out;
+ }
+
+ DRM_DEV_DEBUG_DRIVER(dev,
+ "dual-link configuration detected (companion bridge %pOF)\n",
+ companion);
+out:
+ of_node_put(companion);
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev)
+{
+ struct imx8qxp_pxl2dpi *p2d;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ p2d = devm_kzalloc(dev, sizeof(*p2d), GFP_KERNEL);
+ if (!p2d)
+ return -ENOMEM;
+
+ p2d->regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(p2d->regmap)) {
+ ret = PTR_ERR(p2d->regmap);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get regmap: %d\n", ret);
+ return ret;
+ }
+
+ ret = imx_scu_get_handle(&p2d->ipc_handle);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to get SCU ipc handle: %d\n",
+ ret);
+ return ret;
+ }
+
+ p2d->dev = dev;
+
+ ret = of_property_read_u32(np, "fsl,sc-resource", &p2d->sc_resource);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "failed to get SC resource %d\n", ret);
+ return ret;
+ }
+
+ p2d->next_bridge = imx8qxp_pxl2dpi_find_next_bridge(p2d);
+ if (IS_ERR(p2d->next_bridge)) {
+ ret = PTR_ERR(p2d->next_bridge);
+ if (ret != -EPROBE_DEFER)
+ DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = imx8qxp_pxl2dpi_set_pixel_link_sel(p2d);
+ if (ret)
+ return ret;
+
+ ret = imx8qxp_pxl2dpi_parse_dt_companion(p2d);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, p2d);
+ pm_runtime_enable(dev);
+
+ p2d->bridge.driver_private = p2d;
+ p2d->bridge.funcs = &imx8qxp_pxl2dpi_bridge_funcs;
+ p2d->bridge.of_node = np;
+
+ drm_bridge_add(&p2d->bridge);
+
+ return ret;
+}
+
+static int imx8qxp_pxl2dpi_bridge_remove(struct platform_device *pdev)
+{
+ struct imx8qxp_pxl2dpi *p2d = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&p2d->bridge);
+
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id imx8qxp_pxl2dpi_dt_ids[] = {
+ { .compatible = "fsl,imx8qxp-pxl2dpi", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx8qxp_pxl2dpi_dt_ids);
+
+static struct platform_driver imx8qxp_pxl2dpi_bridge_driver = {
+ .probe = imx8qxp_pxl2dpi_bridge_probe,
+ .remove = imx8qxp_pxl2dpi_bridge_remove,
+ .driver = {
+ .of_match_table = imx8qxp_pxl2dpi_dt_ids,
+ .name = DRIVER_NAME,
+ },
+};
+module_platform_driver(imx8qxp_pxl2dpi_bridge_driver);
+
+MODULE_DESCRIPTION("i.MX8QXP pixel link to DPI bridge driver");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.25.1
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output bus(12-bit per component) to a pixel link.
Reviewed-by: Robert Foss <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* No change.
v5->v6:
* Add Laurent's R-b tag.
v4->v5:
* Add Robert's R-b tag.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
include/uapi/linux/media-bus-format.h | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h
index 0dfc11ee243a..ec3323dbb927 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -34,7 +34,7 @@
#define MEDIA_BUS_FMT_FIXED 0x0001
-/* RGB - next is 0x101e */
+/* RGB - next is 0x1022 */
#define MEDIA_BUS_FMT_RGB444_1X12 0x1016
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
@@ -59,9 +59,13 @@
#define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d
#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011
#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012
+#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e
+#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f
#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f
#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018
+#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020
+#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021
#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019
#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a
--
2.25.1
This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* Add Rob's R-b tag.
v5->v6:
* Drop 'select' schema. (Rob)
v4->v5:
* Newly introduced in v5. (Rob)
.../bindings/mfd/fsl,imx8qxp-csr.yaml | 192 ++++++++++++++++++
1 file changed, 192 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
diff --git a/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
new file mode 100644
index 000000000000..f09577105b50
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
@@ -0,0 +1,192 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qm/qxp Control and Status Registers Module Bindings
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ As a system controller, the Freescale i.MX8qm/qxp Control and Status
+ Registers(CSR) module represents a set of miscellaneous registers of a
+ specific subsystem. It may provide control and/or status report interfaces
+ to a mix of standalone hardware devices within that subsystem. One typical
+ use-case is for some other nodes to acquire a reference to the syscon node
+ by phandle, and the other typical use-case is that the operating system
+ should consider all subnodes of the CSR module as separate child devices.
+
+properties:
+ $nodename:
+ pattern: "^syscon@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - enum:
+ - fsl,imx8qxp-mipi-lvds-csr
+ - fsl,imx8qm-lvds-csr
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ipg
+
+patternProperties:
+ "^(ldb|phy|pxl2dpi)$":
+ type: object
+ description: The possible child devices of the CSR module.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qxp-mipi-lvds-csr
+ then:
+ required:
+ - pxl2dpi
+ - ldb
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8qm-lvds-csr
+ then:
+ required:
+ - phy
+ - ldb
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ mipi_lvds_0_csr: syscon@56221000 {
+ compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+ reg = <0x56221000 0x1000>;
+ clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+
+ mipi_lvds_0_pxl2dpi: pxl2dpi {
+ compatible = "fsl,imx8qxp-pxl2dpi";
+ fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+ };
+ };
+
+ mipi_lvds_0_ldb: ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+ };
+ };
+
+ mipi_lvds_0_phy: phy@56228300 {
+ compatible = "fsl,imx8qxp-mipi-dphy";
+ reg = <0x56228300 0x100>;
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ fsl,syscon = <&mipi_lvds_0_csr>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
--
2.25.1
Add myself as the maintainer of DRM bridge drivers for i.MX SoCs.
Reviewed-by: Robert Foss <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
v8->v9:
* No change.
v7->v8:
* No change.
v6->v7:
* Add Robert's R-b tag.
v5->v6:
* No change.
v4->v5:
* No change.
v3->v4:
* No change.
v2->v3:
* No change.
v1->v2:
* No change.
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d..033d4e8b838b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6654,6 +6654,16 @@ F: Documentation/devicetree/bindings/display/imx/
F: drivers/gpu/drm/imx/
F: drivers/gpu/ipu-v3/
+DRM DRIVERS FOR FREESCALE IMX BRIDGE
+M: Liu Ying <[email protected]>
+L: [email protected]
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-combiner.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
+F: Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pxl2dpi.yaml
+F: drivers/gpu/drm/bridge/imx/
+
DRM DRIVERS FOR GMA500 (Poulsbo, Moorestown and derivative chipsets)
M: Patrik Jakobsson <[email protected]>
L: [email protected]
--
2.25.1
On Sat, Jun 11, 2022 at 10:14:12PM +0800, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp display pixel link.
>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v8->v9:
> * Add 'fsl,dc-id' and 'fsl,dc-stream-id' properties. (Laurent)
Why? Isn't the graph sufficient for determining the connections? That's
what it is for.
> * Drop Rob's R-b tag.
>
> v7->v8:
> * No change.
>
> v6->v7:
> * No change.
>
> v5->v6:
> * No change.
>
> v4->v5:
> * No change.
>
> v3->v4:
> * No change.
>
> v2->v3:
> * Add Rob's R-b tag.
>
> v1->v2:
> * Use graph schema. (Laurent)
> * Require all four pixel link output ports. (Laurent)
> * Mention pixel link is accessed via SCU firmware. (Rob)
>
> .../bridge/fsl,imx8qxp-pixel-link.yaml | 144 ++++++++++++++++++
> 1 file changed, 144 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> new file mode 100644
> index 000000000000..38ecc7926fad
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml
> @@ -0,0 +1,144 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qm/qxp Display Pixel Link
> +
> +maintainers:
> + - Liu Ying <[email protected]>
> +
> +description: |
> + The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
> + asynchronous linkage between pixel sources(display controller or
> + camera module) and pixel consumers(imaging or displays).
> + It consists of two distinct functions, a pixel transfer function and a
> + control interface. Multiple pixel channels can exist per one control channel.
> + This binding documentation is only for pixel links whose pixel sources are
> + display controllers.
> +
> + The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
> + firmware.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8qm-dc-pixel-link
> + - fsl,imx8qxp-dc-pixel-link
> +
> + fsl,dc-id:
> + $ref: /schemas/types.yaml#/definitions/uint8
> + description: |
> + u8 value representing the display controller index that the pixel link
> + connects to.
> +
> + fsl,dc-stream-id:
> + $ref: /schemas/types.yaml#/definitions/uint8
> + description: |
> + u8 value representing the display controller stream index that the pixel
> + link connects to.
> + enum: [0, 1]
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The pixel link input port node from upstream video source.
> +
> + patternProperties:
> + "^port@[1-4]$":
> + $ref: /schemas/graph.yaml#/properties/port
> + description: The pixel link output port node to downstream bridge.
> +
> + required:
> + - port@0
> + - port@1
> + - port@2
> + - port@3
> + - port@4
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx8qxp-dc-pixel-link
> + then:
> + properties:
> + fsl,dc-id:
> + const: 0
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx8qm-dc-pixel-link
> + then:
> + properties:
> + fsl,dc-id:
> + enum: [0, 1]
> +
> +required:
> + - compatible
> + - fsl,dc-id
> + - fsl,dc-stream-id
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + dc0-pixel-link0 {
> + compatible = "fsl,imx8qxp-dc-pixel-link";
> + fsl,dc-id = /bits/ 8 <0>;
> + fsl,dc-stream-id = /bits/ 8 <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* from dc0 pixel combiner channel0 */
> + port@0 {
> + reg = <0>;
> +
> + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
> + remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
Isn't dc0 and link0 here the same information (if you get the port
number from the remote end).
Rob
On Tue, 2022-06-14 at 14:11 -0600, Rob Herring wrote:
> On Sat, Jun 11, 2022 at 10:14:12PM +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp display pixel link.
> >
> > Signed-off-by: Liu Ying <[email protected]>
> > ---
> > v8->v9:
> > * Add 'fsl,dc-id' and 'fsl,dc-stream-id' properties. (Laurent)
>
> Why? Isn't the graph sufficient for determining the connections?
> That's
> what it is for.
'fsl,dc-id' determines the SCU resource IMX_SC_R_DC_{0,1} used by the
pixel link. 'fsl,dc-stream-id' determines the SCU control codes, like
IMX_SC_C_PXL_LINK_MST{1,2}_ADDR.
The pixel combiner stands between the Display Controller(DPU) and the
pixel link. I doubt it'll be good to go through the graph in pixel link
driver to get DPU's output port index to set 'dc-stream-id'.
The graph doesn't tell 'dc-id' unless DPU's or pixel link's OF alias
ids are used. It looks that people don't like the idea of using the
pixel link's OF alias id in pixel link driver to set 'dc-id'(and 'dc-
stream-id'), just like previous versions do.
>
> > * Drop Rob's R-b tag.
> >
> > v7->v8:
> > * No change.
> >
> > v6->v7:
> > * No change.
> >
> > v5->v6:
> > * No change.
> >
> > v4->v5:
> > * No change.
> >
> > v3->v4:
> > * No change.
> >
> > v2->v3:
> > * Add Rob's R-b tag.
> >
> > v1->v2:
> > * Use graph schema. (Laurent)
> > * Require all four pixel link output ports. (Laurent)
> > * Mention pixel link is accessed via SCU firmware. (Rob)
> >
> > .../bridge/fsl,imx8qxp-pixel-link.yaml | 144
> > ++++++++++++++++++
> > 1 file changed, 144 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-
> > link.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-
> > pixel-link.yaml
> > b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-
> > pixel-link.yaml
> > new file mode 100644
> > index 000000000000..38ecc7926fad
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-
> > pixel-link.yaml
> > @@ -0,0 +1,144 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fbridge%2Ffsl%2Cimx8qxp-pixel-link.yaml%23&data=05%7C01%7Cvictor.liu%40nxp.com%7Cc8ba0853ca6446514fb408da4e421ec0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637908343136669762%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=ZLdEqO84HZMwOIjyo5t%2Fy%2BlcfliLr3J5mV2akOxPU5c%3D&reserved=0
> > +$schema:
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Cvictor.liu%40nxp.com%7Cc8ba0853ca6446514fb408da4e421ec0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637908343136669762%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=yL5Xi%2BWz4aX3yniTy8Jq0EhB%2FbLz59QOaCQpxP0AmDM%3D&reserved=0
> > +
> > +title: Freescale i.MX8qm/qxp Display Pixel Link
> > +
> > +maintainers:
> > + - Liu Ying <[email protected]>
> > +
> > +description: |
> > + The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a
> > standard
> > + asynchronous linkage between pixel sources(display controller or
> > + camera module) and pixel consumers(imaging or displays).
> > + It consists of two distinct functions, a pixel transfer function
> > and a
> > + control interface. Multiple pixel channels can exist per one
> > control channel.
> > + This binding documentation is only for pixel links whose pixel
> > sources are
> > + display controllers.
> > +
> > + The i.MX8qm/qxp Display Pixel Link is accessed via System
> > Controller Unit(SCU)
> > + firmware.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8qm-dc-pixel-link
> > + - fsl,imx8qxp-dc-pixel-link
> > +
> > + fsl,dc-id:
> > + $ref: /schemas/types.yaml#/definitions/uint8
> > + description: |
> > + u8 value representing the display controller index that the
> > pixel link
> > + connects to.
> > +
> > + fsl,dc-stream-id:
> > + $ref: /schemas/types.yaml#/definitions/uint8
> > + description: |
> > + u8 value representing the display controller stream index
> > that the pixel
> > + link connects to.
> > + enum: [0, 1]
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: The pixel link input port node from upstream
> > video source.
> > +
> > + patternProperties:
> > + "^port@[1-4]$":
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: The pixel link output port node to downstream
> > bridge.
> > +
> > + required:
> > + - port@0
> > + - port@1
> > + - port@2
> > + - port@3
> > + - port@4
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,imx8qxp-dc-pixel-link
> > + then:
> > + properties:
> > + fsl,dc-id:
> > + const: 0
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,imx8qm-dc-pixel-link
> > + then:
> > + properties:
> > + fsl,dc-id:
> > + enum: [0, 1]
> > +
> > +required:
> > + - compatible
> > + - fsl,dc-id
> > + - fsl,dc-stream-id
> > + - ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + dc0-pixel-link0 {
> > + compatible = "fsl,imx8qxp-dc-pixel-link";
> > + fsl,dc-id = /bits/ 8 <0>;
> > + fsl,dc-stream-id = /bits/ 8 <0>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + /* from dc0 pixel combiner channel0 */
> > + port@0 {
> > + reg = <0>;
> > +
> > + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
> > + remote-endpoint =
> > <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
>
> Isn't dc0 and link0 here the same information (if you get the port
> number from the remote end).
The remote end is the pixel combiner's channel@0 port@1.
Then, from the pixel combiner, we can reach DPU's output port.
Granted that dc0 and link0 here is the same information, but it seems
to be hard to get the 'dc-id' and 'dc-stream-id' information in the
pixel link driver.
Do you mean that we can parse the name of
'dcX_pixel_linkY_dc0_pixel_combiner_ch0' directly to get 'X' and 'Y' in
the pixel link driver? How??
Regards,
Liu Ying
On Sat, Jun 11, 2022 at 10:14:07PM +0800, Liu Ying wrote:
> Patch 1/14 and 2/14 add bus formats used by pixel combiner.
Thanks!
For these:
Acked-by: Sakari Ailus <[email protected]>
--
Sakari Ailus
On Thu, 16 Jun 2022 at 13:18, Sakari Ailus <[email protected]> wrote:
>
> On Sat, Jun 11, 2022 at 10:14:07PM +0800, Liu Ying wrote:
> > Patch 1/14 and 2/14 add bus formats used by pixel combiner.
>
> Thanks!
>
> For these:
>
> Acked-by: Sakari Ailus <[email protected]>
Applied to drm-misc-next.
On Sat, 11 Jun 2022, Liu Ying wrote:
> This patch adds bindings for i.MX8qm/qxp Control and Status Registers module.
>
> Reviewed-by: Rob Herring <[email protected]>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v8->v9:
> * No change.
>
> v7->v8:
> * No change.
>
> v6->v7:
> * Add Rob's R-b tag.
>
> v5->v6:
> * Drop 'select' schema. (Rob)
>
> v4->v5:
> * Newly introduced in v5. (Rob)
>
> .../bindings/mfd/fsl,imx8qxp-csr.yaml | 192 ++++++++++++++++++
> 1 file changed, 192 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/fsl,imx8qxp-csr.yaml
Applied, thanks.
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
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