A question came up recently about memory ordering in libata. Essentially
we have the classic case (ata_bmdma_setup in drivers/ata/libata-sff.c)
where we do some writes to memory (specifically the PRD table) and want
to make sure the device will see those writes before we poke it to go
and use that memory. Right now this is using an mb() (which seems like
overkill, even in the worst case it seems like only a wmb() should be
needed).
I just finished digging through the 2006 LKML discussion "Opinion on
ordering of writel vs. stores to RAM" which ironically failed to clearly
answer the question asked in its subject.
Documentation/memory-barriers.txt does not answer this question either.
The only thing it contains that seems to pertain to this question is the
following:
"Memory mapped I/O usually takes place through memory locations that are
part of a window in the CPU's memory space that has different properties
assigned than the usual RAM directed window.
Amongst these properties is usually the fact that such accesses bypass
the caching entirely and go directly to the device buses. This means
MMIO accesses may, in effect, overtake accesses to cached memory that
were emitted earlier. A memory barrier isn't sufficient in such a case,
but rather the cache must be flushed between the cached memory write and
the MMIO access if the two are in any way dependent."
This seems like BS to me.. Flush the cache? How is a driver supposed to
know how to do that? Furthermore, why should it need to worry about this
kind of detail? This seems wrong or at least a low-level detail that
normal code should not have to be concerned with.
From what I can vaguely infer from that 2006 discussion it seems like
powerpc was going to be fixed so that writel, etc. would provide the
expected ordering with respect to memory writes, however I don't know if
this is actually the case. The documentation that driver writers would
rely on should be updated to be explicit on this question...
> MMIO accesses may, in effect, overtake accesses to cached memory that
> were emitted earlier. A memory barrier isn't sufficient in such a case,
> but rather the cache must be flushed between the cached memory write and
> the MMIO access if the two are in any way dependent."
>
> This seems like BS to me.. Flush the cache? How is a driver supposed to
> know how to do that? Furthermore, why should it need to worry about this
> kind of detail? This seems wrong or at least a low-level detail that
> normal code should not have to be concerned with.
There isn't really much choice in the matter. However if you are using
the normal pci_map_ and pci_alloc_coherent functions then those have your
cache management built into them and all you have to watch is compiler
funnies.
Alan
Alan Cox wrote:
>> MMIO accesses may, in effect, overtake accesses to cached memory that
>> were emitted earlier. A memory barrier isn't sufficient in such a case,
>> but rather the cache must be flushed between the cached memory write and
>> the MMIO access if the two are in any way dependent."
>>
>> This seems like BS to me.. Flush the cache? How is a driver supposed to
>> know how to do that? Furthermore, why should it need to worry about this
>> kind of detail? This seems wrong or at least a low-level detail that
>> normal code should not have to be concerned with.
>
> There isn't really much choice in the matter. However if you are using
> the normal pci_map_ and pci_alloc_coherent functions then those have your
> cache management built into them and all you have to watch is compiler
> funnies.
What that documentation is suggesting is that MMIO writes to uncached
memory (what the normal mapping functions will give you) can pass
previous writes to cached memory. It doesn't indicate how this is to be
avoided, however.
The arch that was being discussed in that 2006 discussion was PPC, but
it appears that it's been changed to ensure that writeX, etc. will
provide the expected ordering (commit
f007cacffc8870702a1473d83ba5e4922d54e17c). I'm not sure what
architecture the author of those paragraphs in
Documentation/memory-barriers.txt had in mind, though. CCing David
Howells as he apparently wrote them..
> What that documentation is suggesting is that MMIO writes to uncached
> memory (what the normal mapping functions will give you) can pass
> previous writes to cached memory. It doesn't indicate how this is to be
> avoided, however.
They can. How you avoid it depends upon the bus but the problem is really
really rare as a corner case and almost the only device affected is
graphics because nobody uses cached memory on the PCI bus except graphics
cards and a couple of obscure other cases like I2O.
The graphics people implement various fencing operations and they are
generally tied down low level with AGP, GARTs and other places mere
mortals (ie most people except the DRI team) should not tread ;)
You need to distinguish between cachable memory remote on things like the
PCI bus (eg frame buffers) which are your problem and cachable memory in
the sense of main memory, which is handled by the pci_map functions or
kept coherent if allocated via the PCI coherent memory allocator - in
which case all you have to watch is the compiler and write buffers on the
CPU.