On Thu, Feb 22 2024 at 16:39, Yu Chien Peter Lin wrote:
> Add support for the Andes hart-level interrupt controller. This
> controller provides interrupt mask/unmask functions to access the
> custom register (SLIE) where the non-standard S-mode local interrupt
> enable bits are located. The base of custom interrupt number is set
> to 256.
>
> To share the riscv_intc_domain_map() with the generic RISC-V INTC and
> ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
> passed to the irq_domain_set_info() as a private data.
>
> Andes hart-level interrupt controller requires the "andestech,cpu-intc"
> compatible string to be present in interrupt-controller of cpu node to
> enable the use of custom local interrupt source.
> e.g.,
>
> cpu0: cpu@0 {
> compatible = "andestech,ax45mp", "riscv";
> ...
> cpu0-intc: interrupt-controller {
> #interrupt-cells = <0x01>;
> compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> interrupt-controller;
> };
> };
>
> Signed-off-by: Yu Chien Peter Lin <[email protected]>
> Reviewed-by: Randolph <[email protected]>
> Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Palmer, feel free to take this through the riscv tree. I have no other
changes pending against that driver.
Thanks,
tglx
On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
> Palmer, feel free to take this through the riscv tree. I have no other
> changes pending against that driver.
Aargh. Spoken too early. This conflicts with Anups AIA series.
https://lore.kernel.org/all/[email protected]
So I rather take the pile through my tree and deal with the conflicts
localy than inflicting it on next.
Palmer?
Thanks,
tglx
On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>> Palmer, feel free to take this through the riscv tree. I have no other
>> changes pending against that driver.
>
> Aargh. Spoken too early. This conflicts with Anups AIA series.
>
> https://lore.kernel.org/all/[email protected]
>
> So I rather take the pile through my tree and deal with the conflicts
> localy than inflicting it on next.
> Palmer?
Nah. I just apply the two intc patches localy and give you a tag to pull
from so we carry both the same commits. Then I can deal with the
conflicts on my side trivially.
Thanks,
tglx
On Fri, Feb 23 2024 at 09:54, Thomas Gleixner wrote:
> On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
>> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>>> Palmer, feel free to take this through the riscv tree. I have no other
>>> changes pending against that driver.
>>
>> Aargh. Spoken too early. This conflicts with Anups AIA series.
>>
>> https://lore.kernel.org/all/[email protected]
>>
>> So I rather take the pile through my tree and deal with the conflicts
>> localy than inflicting it on next.
>
>> Palmer?
>
> Nah. I just apply the two intc patches localy and give you a tag to pull
> from so we carry both the same commits. Then I can deal with the
> conflicts on my side trivially.
Here you go:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-for-riscv-02-23-24
Contains:
f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
on top of v6.8-rc1
Thanks,
tglx
On Fri, 23 Feb 2024 01:06:44 PST (-0800), [email protected] wrote:
> On Fri, Feb 23 2024 at 09:54, Thomas Gleixner wrote:
>> On Fri, Feb 23 2024 at 09:49, Thomas Gleixner wrote:
>>> On Thu, Feb 22 2024 at 22:36, Thomas Gleixner wrote:
>>>> Palmer, feel free to take this through the riscv tree. I have no other
>>>> changes pending against that driver.
>>>
>>> Aargh. Spoken too early. This conflicts with Anups AIA series.
>>>
>>> https://lore.kernel.org/all/[email protected]
>>>
>>> So I rather take the pile through my tree and deal with the conflicts
>>> localy than inflicting it on next.
>>
>>> Palmer?
>>
>> Nah. I just apply the two intc patches localy and give you a tag to pull
>> from so we carry both the same commits. Then I can deal with the
>> conflicts on my side trivially.
>
> Here you go:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-for-riscv-02-23-24
>
> Contains:
>
> f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
> 96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
>
> on top of v6.8-rc1
Sorry I missed this. I just merged this into my testing tree, it might
take a bit to show up because I've managed to break my VPN so I can't
poke the tester box right now...
>
> Thanks,
>
> tglx