This series aims at providing support for Raspberry Pi 4's PCIe
controller, which is also shared with the Broadcom STB family of
devices.
There was a previous attempt to upstream this some years ago[1] but was
blocked as most STB PCIe integrations have a sparse DMA mapping[2] which
is something currently not supported by the kernel. Luckily this is not
the case for the Raspberry Pi 4.
Note that the driver code is to be based on top of Rob Herring's series
simplifying inbound and outbound range parsing.
[1] https://patchwork.kernel.org/cover/10605933/
[2] https://patchwork.kernel.org/patch/10605957/
---
Jim Quinlan (3):
dt-bindings: pci: add bindings for brcmstb's PCIe device
PCI: brcmstb: add Broadcom STB PCIe host controller driver
PCI: brcmstb: add MSI capability
Nicolas Saenz Julienne (1):
ARM: dts: bcm2711: Enable PCIe controller
.../bindings/pci/brcm,stb-pcie.yaml | 116 ++
arch/arm/boot/dts/bcm2711.dtsi | 47 +
drivers/pci/controller/Kconfig | 12 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-brcmstb.c | 1302 +++++++++++++++++
5 files changed, 1478 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
create mode 100644 drivers/pci/controller/pcie-brcmstb.c
--
2.23.0
From: Jim Quinlan <[email protected]>
This commit adds the basic Broadcom STB PCIe controller. Missing is the
ability to process MSI. This functionality is added in a subsequent
commit.
The PCIe block contains an MDIO interface. This is a local interface
only accessible by the PCIe controller. It cannot be used or shared
by any other HW. As such, the small amount of code for this
controller is included in this driver as there is little upside to put
it elsewhere.
This is based on Jim's original submission[1] but adapted and tailored
specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
the rest of the brcmstb family will soon follow once we get support for
multiple dma-ranges in dma/direct.
[1] https://patchwork.kernel.org/patch/10605959/
Signed-off-by: Jim Quinlan <[email protected]>
Co-developed-by: Nicolas Saenz Julienne <[email protected]>
Signed-off-by: Nicolas Saenz Julienne <[email protected]>
---
drivers/pci/controller/Kconfig | 12 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
3 files changed, 986 insertions(+)
create mode 100644 drivers/pci/controller/pcie-brcmstb.c
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index f5de9119e8d3..8b3aae91d8af 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -281,6 +281,18 @@ config VMD
To compile this driver as a module, choose M here: the
module will be called vmd.
+config PCIE_BRCMSTB
+ bool "Broadcom Brcmstb PCIe host controller"
+ depends on ARCH_BRCMSTB || BMIPS_GENERIC
+ depends on OF
+ depends on SOC_BRCMSTB
+ default ARCH_BRCMSTB || BMIPS_GENERIC
+ help
+ Say Y here to enable PCIe host controller support for
+ Broadcom Settop Box SOCs. A Broadcom SOC will may have
+ multiple host controllers as opposed to a single host
+ controller with multiple ports.
+
config PCI_HYPERV_INTERFACE
tristate "Hyper-V PCI Interface"
depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index a2a22c9d91af..3fc0b0cf5b5b 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
obj-$(CONFIG_VMD) += vmd.o
+obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
obj-y += dwc/
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
new file mode 100644
index 000000000000..880ec11d06a1
--- /dev/null
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -0,0 +1,973 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2009 - 2019 Broadcom */
+
+#include <linux/clk.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/printk.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "../pci.h"
+
+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+/*
+ * Broadcom Settop Box PCIe Register Offsets. The names are from
+ * the chip's RDB and we use them here so that a script can correlate
+ * this code and the RDB to prevent discrepancies.
+ */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
+#define PCIE_RC_DL_MDIO_ADDR 0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
+#define PCIE_MISC_MISC_CTRL 0x4008
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define PCIE_MISC_PCIE_CTRL 0x4064
+#define PCIE_MISC_PCIE_STATUS 0x4068
+#define PCIE_MISC_REVISION 0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
+#define PCIE_INTR2_CPU_BASE 0x4300
+
+/*
+ * Broadcom Settop Box PCIe Register Field shift and mask info. The
+ * names are from the chip's RDB and we use them here so that a script
+ * can correlate this code and the RDB to prevent discrepancies.
+ */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
+#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
+#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
+#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
+
+#define BRCM_NUM_PCIE_OUT_WINS 0x4
+#define BRCM_MAX_SCB 0x4
+
+#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
+#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
+
+#define BURST_SIZE_128 0
+#define BURST_SIZE_256 1
+#define BURST_SIZE_512 2
+
+/* Offsets from PCIE_INTR2_CPU_BASE */
+#define STATUS 0x0
+#define SET 0x4
+#define CLR 0x8
+#define MASK_STATUS 0xc
+#define MASK_SET 0x10
+#define MASK_CLR 0x14
+
+#define PCIE_BUSNUM_SHIFT 20
+#define PCIE_SLOT_SHIFT 15
+#define PCIE_FUNC_SHIFT 12
+
+#if defined(__BIG_ENDIAN)
+#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */
+#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */
+#else
+#define DATA_ENDIAN 0
+#define MMIO_ENDIAN 0
+#endif
+
+#define MDIO_PORT0 0x0
+#define MDIO_DATA_MASK 0x7fffffff
+#define MDIO_DATA_SHIFT 0x0
+#define MDIO_PORT_MASK 0xf0000
+#define MDIO_PORT_SHIFT 0x16
+#define MDIO_REGAD_MASK 0xffff
+#define MDIO_REGAD_SHIFT 0x0
+#define MDIO_CMD_MASK 0xfff00000
+#define MDIO_CMD_SHIFT 0x14
+#define MDIO_CMD_READ 0x1
+#define MDIO_CMD_WRITE 0x0
+#define MDIO_DATA_DONE_MASK 0x80000000
+#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
+#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
+#define SSC_REGS_ADDR 0x1100
+#define SET_ADDR_OFFSET 0x1f
+#define SSC_CNTL_OFFSET 0x2
+#define SSC_CNTL_OVRD_EN_MASK 0x8000
+#define SSC_CNTL_OVRD_EN_SHIFT 0xf
+#define SSC_CNTL_OVRD_VAL_MASK 0x4000
+#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
+#define SSC_STATUS_OFFSET 0x1
+#define SSC_STATUS_SSC_MASK 0x400
+#define SSC_STATUS_SSC_SHIFT 0xa
+#define SSC_STATUS_PLL_LOCK_MASK 0x800
+#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
+
+#define IDX_ADDR(pcie) \
+ ((pcie)->reg_offsets[EXT_CFG_INDEX])
+#define DATA_ADDR(pcie) \
+ ((pcie)->reg_offsets[EXT_CFG_DATA])
+#define PCIE_RGR1_SW_INIT_1(pcie) \
+ ((pcie)->reg_offsets[RGR1_SW_INIT_1])
+
+enum {
+ RGR1_SW_INIT_1,
+ EXT_CFG_INDEX,
+ EXT_CFG_DATA,
+};
+
+enum {
+ RGR1_SW_INIT_1_INIT_MASK,
+ RGR1_SW_INIT_1_INIT_SHIFT,
+ RGR1_SW_INIT_1_PERST_MASK,
+ RGR1_SW_INIT_1_PERST_SHIFT,
+};
+
+enum pcie_type {
+ BCM2711,
+};
+
+struct brcm_window {
+ dma_addr_t pcie_addr;
+ phys_addr_t cpu_addr;
+ dma_addr_t size;
+};
+
+/* Internal PCIe Host Controller Information.*/
+struct brcm_pcie {
+ struct device *dev;
+ void __iomem *base;
+ int irq;
+ struct clk *clk;
+ struct pci_bus *root_bus;
+ struct device_node *dn;
+ int id;
+ bool suspended;
+ bool ssc;
+ int gen;
+ struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
+ unsigned int rev;
+ const int *reg_offsets;
+ const int *reg_field_info;
+ enum pcie_type type;
+};
+
+struct pcie_cfg_data {
+ const int *reg_field_info;
+ const int *offsets;
+ const enum pcie_type type;
+};
+
+static const int pcie_reg_field_info[] = {
+ [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
+ [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
+};
+
+static const int pcie_offset_bcm2711[] = {
+ [RGR1_SW_INIT_1] = 0x9210,
+ [EXT_CFG_INDEX] = 0x9000,
+ [EXT_CFG_DATA] = 0x8000,
+};
+
+static const struct pcie_cfg_data bcm2711_cfg = {
+ .reg_field_info = pcie_reg_field_info,
+ .offsets = pcie_offset_bcm2711,
+ .type = BCM2711,
+};
+
+static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
+ int where);
+
+static struct pci_ops brcm_pcie_ops = {
+ .map_bus = brcm_pcie_map_conf,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+};
+
+#define bcm_readl(a) readl(a)
+#define bcm_writel(d, a) writel(d, a)
+#define bcm_readw(a) readw(a)
+#define bcm_writew(d, a) writew(d, a)
+
+/* These macros extract/insert fields to host controller's register set. */
+#define RD_FLD(base, reg, field) \
+ rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
+#define WR_FLD(base, reg, field, val) \
+ wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
+#define WR_FLD_RB(base, reg, field, val) \
+ wr_fld_rb((base) + reg, reg##_##field##_MASK, \
+ reg##_##field##_SHIFT, val)
+#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
+ wr_fld((base) + reg + (off), reg##_##field##_MASK, \
+ reg##_##field##_SHIFT, val)
+#define EXTRACT_FIELD(val, reg, field) \
+ (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
+#define INSERT_FIELD(val, reg, field, field_val) \
+ (((val) & ~reg##_##field##_MASK) | \
+ (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
+
+static u32 rd_fld(void __iomem *p, u32 mask, int shift)
+{
+ return (bcm_readl(p) & mask) >> shift;
+}
+
+static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
+{
+ u32 reg = bcm_readl(p);
+
+ reg = (reg & ~mask) | ((val << shift) & mask);
+ bcm_writel(reg, p);
+}
+
+static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
+{
+ wr_fld(p, mask, shift, val);
+ (void)bcm_readl(p);
+}
+
+static const char *link_speed_to_str(int s)
+{
+ switch (s) {
+ case 1:
+ return "2.5";
+ case 2:
+ return "5.0";
+ case 3:
+ return "8.0";
+ default:
+ break;
+ }
+ return "???";
+}
+
+/*
+ * The roundup_pow_of_two() from log2.h invokes
+ * __roundup_pow_of_two(unsigned long), but we really need a
+ * such a function to take a native u64 since unsigned long
+ * is 32 bits on some configurations. So we provide this helper
+ * function below.
+ */
+static u64 roundup_pow_of_two_64(u64 n)
+{
+ return 1ULL << fls64(n - 1);
+}
+
+/*
+ * This is to convert the size of the inbound "BAR" region to the
+ * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
+ */
+int encode_ibar_size(u64 size)
+{
+ int log2_in = ilog2(size);
+
+ if (log2_in >= 12 && log2_in <= 15)
+ /* Covers 4KB to 32KB (inclusive) */
+ return (log2_in - 12) + 0x1c;
+ else if (log2_in >= 16 && log2_in <= 37)
+ /* Covers 64KB to 32GB, (inclusive) */
+ return log2_in - 15;
+ /* Something is awry so disable */
+ return 0;
+}
+
+static u32 mdio_form_pkt(int port, int regad, int cmd)
+{
+ u32 pkt = 0;
+
+ pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
+ pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
+ pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
+
+ return pkt;
+}
+
+/* negative return value indicates error */
+static int mdio_read(void __iomem *base, u8 port, u8 regad)
+{
+ int tries;
+ u32 data;
+
+ bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
+ base + PCIE_RC_DL_MDIO_ADDR);
+ bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
+
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+ for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
+ udelay(10);
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+ }
+
+ return MDIO_RD_DONE(data)
+ ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
+ : -EIO;
+}
+
+/* negative return value indicates error */
+static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
+{
+ int tries;
+ u32 data;
+
+ bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
+ base + PCIE_RC_DL_MDIO_ADDR);
+ bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
+ bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
+ base + PCIE_RC_DL_MDIO_WR_DATA);
+
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+ for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
+ udelay(10);
+ data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+ }
+
+ return MDIO_WT_DONE(data) ? 0 : -EIO;
+}
+
+/*
+ * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
+ * return value indicates error.
+ */
+static int set_ssc(void __iomem *base)
+{
+ int tmp;
+ u16 wrdata;
+ int pll, ssc;
+
+ tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
+ if (tmp < 0)
+ return tmp;
+
+ tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
+ if (tmp < 0)
+ return tmp;
+
+ wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
+ wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
+ tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
+ if (tmp < 0)
+ return tmp;
+
+ usleep_range(1000, 2000);
+ tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
+ if (tmp < 0)
+ return tmp;
+
+ ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
+ pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
+
+ return (ssc && pll) ? 0 : -EIO;
+}
+
+/* Limits operation to a specific generation (1, 2, or 3) */
+static void set_gen(void __iomem *base, int gen)
+{
+ u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
+ u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
+
+ lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
+ bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
+
+ lnkctl2 = (lnkctl2 & ~0xf) | gen;
+ bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
+}
+
+static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
+ unsigned int win, phys_addr_t cpu_addr,
+ dma_addr_t pcie_addr, dma_addr_t size)
+{
+ void __iomem *base = pcie->base;
+ phys_addr_t cpu_addr_mb, limit_addr_mb;
+ u32 tmp;
+
+ /* Set the base of the pcie_addr window */
+ bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
+ base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
+ bcm_writel(upper_32_bits(pcie_addr),
+ base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
+
+ cpu_addr_mb = cpu_addr >> 20;
+ limit_addr_mb = (cpu_addr + size - 1) >> 20;
+
+ /* Write the addr base low register */
+ WR_FLD_WITH_OFFSET(base, (win * 4),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
+ BASE, cpu_addr_mb);
+ /* Write the addr limit low register */
+ WR_FLD_WITH_OFFSET(base, (win * 4),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
+ LIMIT, limit_addr_mb);
+
+ /* Write the cpu addr high register */
+ tmp = (u32)(cpu_addr_mb >>
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
+ WR_FLD_WITH_OFFSET(base, (win * 8),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
+ BASE, tmp);
+ /* Write the cpu limit high register */
+ tmp = (u32)(limit_addr_mb >>
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
+ WR_FLD_WITH_OFFSET(base, (win * 8),
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
+ LIMIT, tmp);
+}
+
+/* Configuration space read/write support */
+static int cfg_index(int busnr, int devfn, int reg)
+{
+ return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
+ | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
+ | (busnr << PCIE_BUSNUM_SHIFT)
+ | (reg & ~3);
+}
+
+/* The controller is capable of serving in both RC and EP roles */
+static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
+
+ return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
+}
+
+static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
+ u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
+ u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
+
+ return (dla && plu) ? true : false;
+}
+
+static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
+ int where)
+{
+ struct brcm_pcie *pcie = bus->sysdata;
+ void __iomem *base = pcie->base;
+ int idx;
+
+ /* Accesses to the RC go right to the RC registers if slot==0 */
+ if (pci_is_root_bus(bus))
+ return PCI_SLOT(devfn) ? NULL : base + where;
+
+ /* For devices, write to the config space index register */
+ idx = cfg_index(bus->number, devfn, 0);
+ bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
+ return base + DATA_ADDR(pcie) + where;
+}
+
+static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
+ unsigned int val)
+{
+ unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
+ u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
+
+ wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
+}
+
+static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
+ unsigned int val)
+{
+ wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
+ PCIE_RGR1_SW_INIT_1_PERST_MASK,
+ PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
+}
+
+static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
+ u64 *rc_bar2_size,
+ u64 *rc_bar2_offset)
+{
+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
+ struct device *dev = pcie->dev;
+ struct resource_entry *entry;
+ u64 total_mem_size = 0;
+
+ *rc_bar2_offset = -1;
+
+ resource_list_for_each_entry(entry, &bridge->dma_ranges) {
+ /*
+ * We're promissed the RC will provide a contiguous view of
+ * memory to downstream devices. We can then infer the
+ * rc_bar2_offset from the lower avaiable dma-range offset.
+ */
+ if (entry->offset < *rc_bar2_offset)
+ *rc_bar2_offset = entry->offset;
+
+ total_mem_size += entry->res->end - entry->res->start + 1;
+ }
+
+ *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
+
+ /*
+ * Validate the results:
+ *
+ * The PCIe host controller by design must set the inbound viewport to
+ * be a contiguous arrangement of all of the system's memory. In
+ * addition, its size mut be a power of two. To further complicate
+ * matters, the viewport must start on a pcie-address that is aligned
+ * on a multiple of its size. If a portion of the viewport does not
+ * represent system memory -- e.g. 3GB of memory requires a 4GB
+ * viewport -- we can map the outbound memory in or after 3GB and even
+ * though the viewport will overlap the outbound memory the controller
+ * will know to send outbound memory downstream and everything else
+ * upstream.
+ *
+ * For example:
+ *
+ * - The best-case scenario, memory up to 3GB, is to place the inbound
+ * region in the first 4GB of pcie-space, as some legacy devices can
+ * only address 32bits. We would also like to put the MSI under 4GB
+ * as well, since some devices require a 32bit MSI target address.
+ *
+ * - If the system memory is 4GB or larger we cannot start the inbound
+ * region at location 0 (since we have to allow some space for
+ * outbound memory @ 3GB). So instead it will start at the 1x
+ * multiple of its size
+ */
+ if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
+ (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
+ dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
+ *rc_bar2_size, *rc_bar2_offset);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int brcm_pcie_setup(struct brcm_pcie *pcie)
+{
+ struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
+ u64 rc_bar2_offset, rc_bar2_size;
+ void __iomem *base = pcie->base;
+ struct resource_entry *entry;
+ unsigned int scb_size_val;
+ struct resource *res;
+ int num_out_wins = 0;
+ u32 tmp;
+ int i, j, ret, limit;
+ u16 nlw, cls, lnksta;
+ bool ssc_good = false;
+ struct device *dev = pcie->dev;
+
+ /* Reset the bridge */
+ brcm_pcie_bridge_sw_init_set(pcie, 1);
+
+ usleep_range(100, 200);
+
+ /* Take the bridge out of reset */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+ /* Wait for SerDes to be stable */
+ usleep_range(100, 200);
+
+ /* Grab the PCIe hw revision number */
+ tmp = bcm_readl(base + PCIE_MISC_REVISION);
+ pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
+
+ /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
+ tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
+ tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
+ tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
+ BURST_SIZE_128);
+ bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
+
+ ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
+ &rc_bar2_offset);
+ if (ret)
+ return ret;
+
+ tmp = lower_32_bits(rc_bar2_offset);
+ tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
+ encode_ibar_size(rc_bar2_size));
+ bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
+ bcm_writel(upper_32_bits(rc_bar2_offset),
+ base + PCIE_MISC_RC_BAR2_CONFIG_HI);
+
+ scb_size_val = rc_bar2_size ?
+ ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
+ WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
+
+ /* disable the PCIe->GISB memory window (RC_BAR1) */
+ WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
+
+ /* disable the PCIe->SCB memory window (RC_BAR3) */
+ WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
+
+ if (!pcie->suspended) {
+ /* clear any interrupts we find on boot */
+ bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
+ (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
+ }
+
+ /* Mask all interrupts since we are not handling any yet */
+ bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
+ (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
+
+ if (pcie->gen)
+ set_gen(base, pcie->gen);
+
+ /* Unassert the fundamental reset */
+ brcm_pcie_perst_set(pcie, 0);
+
+ /*
+ * Give the RC/EP time to wake up, before trying to configure RC.
+ * Intermittently check status for link-up, up to a total of 100ms
+ * when we don't know if the device is there, and up to 1000ms if
+ * we do know the device is there.
+ */
+ limit = pcie->suspended ? 1000 : 100;
+ for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
+ j += i, i = i * 2)
+ msleep(i + j > limit ? limit - j : i);
+
+ if (!brcm_pcie_link_up(pcie)) {
+ dev_info(dev, "link down\n");
+ return -ENODEV;
+ }
+
+ if (!brcm_pcie_rc_mode(pcie)) {
+ dev_err(dev, "PCIe misconfigured; is in EP mode\n");
+ return -EINVAL;
+ }
+
+ resource_list_for_each_entry(entry, &bridge->windows) {
+ res = entry->res;
+
+ if (resource_type(res) != IORESOURCE_MEM)
+ continue;
+
+ if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
+ dev_err(pcie->dev, "too many outbound wins\n");
+ return -EINVAL;
+ }
+
+ brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
+ res->start - entry->offset,
+ res->end - res->start + 1);
+ num_out_wins++;
+ }
+
+ /*
+ * For config space accesses on the RC, show the right class for
+ * a PCIe-PCIe bridge (the default setting is to be EP mode).
+ */
+ WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
+
+ if (pcie->ssc) {
+ ret = set_ssc(base);
+ if (ret == 0)
+ ssc_good = true;
+ else
+ dev_err(dev, "failed attempt to enter ssc mode\n");
+ }
+
+ lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
+ cls = lnksta & PCI_EXP_LNKSTA_CLS;
+ nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
+ dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
+ nlw, ssc_good ? "(SSC)" : "(!SSC)");
+
+ /* PCIe->SCB endian mode for BAR */
+ /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
+ WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
+ ENDIAN_MODE_BAR2, DATA_ENDIAN);
+
+ /*
+ * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
+ * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
+ */
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
+
+ return 0;
+}
+
+/* L23 is a low-power PCIe link state */
+static void enter_l23(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+ int l23, i;
+
+ /* assert request for L23 */
+ WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
+
+ /* Wait up to 30 msec for L23 */
+ l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
+ for (i = 0; i < 15 && !l23; i++) {
+ usleep_range(2000, 2400);
+ l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
+ }
+
+ if (!l23)
+ dev_err(pcie->dev, "failed to enter L23\n");
+}
+
+static void turn_off(struct brcm_pcie *pcie)
+{
+ void __iomem *base = pcie->base;
+
+ if (brcm_pcie_link_up(pcie))
+ enter_l23(pcie);
+ /* Assert fundamental reset */
+ brcm_pcie_perst_set(pcie, 1);
+ /* Deassert request for L23 in case it was asserted */
+ WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
+ /* Turn off SerDes */
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
+ /* Shutdown PCIe bridge */
+ brcm_pcie_bridge_sw_init_set(pcie, 1);
+}
+
+static int brcm_pcie_suspend(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+
+ turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+ pcie->suspended = true;
+
+ return 0;
+}
+
+static int brcm_pcie_resume(struct device *dev)
+{
+ struct brcm_pcie *pcie = dev_get_drvdata(dev);
+ void __iomem *base;
+ int ret;
+
+ base = pcie->base;
+ clk_prepare_enable(pcie->clk);
+
+ /* Take bridge out of reset so we can access the SerDes reg */
+ brcm_pcie_bridge_sw_init_set(pcie, 0);
+
+ /* Turn on SerDes */
+ WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
+ /* Wait for SerDes to be stable */
+ usleep_range(100, 200);
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ return ret;
+
+ pcie->suspended = false;
+
+ return 0;
+}
+
+static void _brcm_pcie_remove(struct brcm_pcie *pcie)
+{
+ turn_off(pcie);
+ clk_disable_unprepare(pcie->clk);
+ clk_put(pcie->clk);
+}
+
+static int brcm_pcie_remove(struct platform_device *pdev)
+{
+ struct brcm_pcie *pcie = platform_get_drvdata(pdev);
+
+ pci_stop_root_bus(pcie->root_bus);
+ pci_remove_root_bus(pcie->root_bus);
+ _brcm_pcie_remove(pcie);
+
+ return 0;
+}
+
+static const struct of_device_id brcm_pcie_match[] = {
+ { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
+ {},
+};
+MODULE_DEVICE_TABLE(of, brcm_pcie_match);
+
+static int brcm_pcie_probe(struct platform_device *pdev)
+{
+ struct device_node *dn = pdev->dev.of_node;
+ const struct of_device_id *of_id;
+ const struct pcie_cfg_data *data;
+ struct resource *res;
+ int ret;
+ struct brcm_pcie *pcie;
+ void __iomem *base;
+ struct pci_host_bridge *bridge;
+ struct pci_bus *child;
+
+ bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
+ if (!bridge)
+ return -ENOMEM;
+
+ pcie = pci_host_bridge_priv(bridge);
+
+ of_id = of_match_node(brcm_pcie_match, dn);
+ if (!of_id) {
+ dev_err(&pdev->dev, "failed to look up compatible string\n");
+ return -EINVAL;
+ }
+
+ data = of_id->data;
+ pcie->reg_offsets = data->offsets;
+ pcie->reg_field_info = data->reg_field_info;
+ pcie->type = data->type;
+ pcie->dn = dn;
+ pcie->dev = &pdev->dev;
+
+ /* We use the domain number as our controller number */
+ pcie->id = of_get_pci_domain_nr(dn);
+ if (pcie->id < 0)
+ return pcie->id;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
+
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
+ if (IS_ERR(pcie->clk)) {
+ dev_err(&pdev->dev, "could not get clock\n");
+ pcie->clk = NULL;
+ }
+ pcie->base = base;
+
+ ret = of_pci_get_max_link_speed(dn);
+ pcie->gen = (ret < 0) ? 0 : ret;
+
+ pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
+
+ ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
+ if (ret == 0)
+ /* keep going, as we don't use this intr yet */
+ dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
+ else
+ pcie->irq = ret;
+
+ ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
+ &bridge->dma_ranges, NULL);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(pcie->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "could not enable clock\n");
+ return ret;
+ }
+
+ ret = brcm_pcie_setup(pcie);
+ if (ret)
+ goto fail;
+
+ bridge->dev.parent = &pdev->dev;
+ bridge->busnr = 0;
+ bridge->ops = &brcm_pcie_ops;
+ bridge->sysdata = pcie;
+ bridge->map_irq = of_irq_parse_and_map_pci;
+ bridge->swizzle_irq = pci_common_swizzle;
+
+ ret = pci_scan_root_bus_bridge(bridge);
+ if (ret < 0) {
+ dev_err(pcie->dev, "Scanning root bridge failed\n");
+ goto fail;
+ }
+
+ pci_assign_unassigned_bus_resources(bridge->bus);
+ list_for_each_entry(child, &bridge->bus->children, node)
+ pcie_bus_configure_settings(child);
+ pci_bus_add_devices(bridge->bus);
+ platform_set_drvdata(pdev, pcie);
+ pcie->root_bus = bridge->bus;
+
+ return 0;
+
+fail:
+ _brcm_pcie_remove(pcie);
+ return ret;
+}
+
+static const struct dev_pm_ops brcm_pcie_pm_ops = {
+ .suspend_noirq = brcm_pcie_suspend,
+ .resume_noirq = brcm_pcie_resume,
+};
+
+static struct platform_driver brcm_pcie_driver = {
+ .probe = brcm_pcie_probe,
+ .remove = brcm_pcie_remove,
+ .driver = {
+ .name = "brcm-pcie",
+ .owner = THIS_MODULE,
+ .of_match_table = brcm_pcie_match,
+ .pm = &brcm_pcie_pm_ops,
+ },
+};
+
+module_platform_driver(brcm_pcie_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
+MODULE_AUTHOR("Broadcom");
--
2.23.0
From: Jim Quinlan <[email protected]>
This commit adds MSI to the Broadcom STB PCIe host controller. It does
not add MSIX since that functionality is not in the HW. The MSI
controller is physically located within the PCIe block, however, there
is no reason why the MSI controller could not be moved elsewhere in
the future.
Since the internal Brcmstb MSI controller is intertwined with the PCIe
controller, it is not its own platform device but rather part of the
PCIe platform device.
This is based on Jim's original submission[1] with some slight changes
regarding how pcie->msi_target_addr is decided.
[1] https://patchwork.kernel.org/patch/10605955/
Signed-off-by: Jim Quinlan <[email protected]>
Co-developed-by: Nicolas Saenz Julienne <[email protected]>
Signed-off-by: Nicolas Saenz Julienne <[email protected]>
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-brcmstb.c | 333 +++++++++++++++++++++++++-
2 files changed, 332 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 8b3aae91d8af..99b972ad3f2f 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -284,7 +284,7 @@ config VMD
config PCIE_BRCMSTB
bool "Broadcom Brcmstb PCIe host controller"
depends on ARCH_BRCMSTB || BMIPS_GENERIC
- depends on OF
+ depends on OF && PCI_MSI
depends on SOC_BRCMSTB
default ARCH_BRCMSTB || BMIPS_GENERIC
help
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 880ec11d06a1..26053e69b95f 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2009 - 2019 Broadcom */
+#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/compiler.h>
#include <linux/delay.h>
@@ -8,11 +9,13 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/log2.h>
#include <linux/module.h>
+#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
@@ -46,6 +49,9 @@
#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
+#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
#define PCIE_MISC_PCIE_CTRL 0x4064
#define PCIE_MISC_PCIE_STATUS 0x4068
#define PCIE_MISC_REVISION 0x406c
@@ -54,6 +60,7 @@
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
#define PCIE_INTR2_CPU_BASE 0x4300
+#define PCIE_MSI_INTR2_BASE 0x4500
/*
* Broadcom Settop Box PCIe Register Field shift and mask info. The
@@ -114,6 +121,8 @@
#define BRCM_NUM_PCIE_OUT_WINS 0x4
#define BRCM_MAX_SCB 0x4
+#define BRCM_INT_PCI_MSI_NR 32
+#define BRCM_PCIE_HW_REV_33 0x0303
#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
@@ -199,6 +208,33 @@ struct brcm_window {
dma_addr_t size;
};
+struct brcm_msi {
+ struct device *dev;
+ void __iomem *base;
+ struct device_node *dn;
+ struct irq_domain *msi_domain;
+ struct irq_domain *inner_domain;
+ struct mutex lock; /* guards the alloc/free operations */
+ u64 target_addr;
+ int irq;
+
+ /* intr_base is the base pointer for interrupt status/set/clr regs */
+ void __iomem *intr_base;
+
+ /* intr_legacy_mask indicates how many bits are MSI interrupts */
+ u32 intr_legacy_mask;
+
+ /*
+ * intr_legacy_offset indicates bit position of MSI_01. It is
+ * to map the register bit position to a hwirq that starts at 0.
+ */
+ u32 intr_legacy_offset;
+
+ /* used indicates which MSI interrupts have been alloc'd */
+ unsigned long used;
+ unsigned int rev;
+};
+
/* Internal PCIe Host Controller Information.*/
struct brcm_pcie {
struct device *dev;
@@ -211,7 +247,10 @@ struct brcm_pcie {
bool suspended;
bool ssc;
int gen;
+ u64 msi_target_addr;
struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
+ struct brcm_msi *msi;
+ bool msi_internal;
unsigned int rev;
const int *reg_offsets;
const int *reg_field_info;
@@ -477,6 +516,267 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
LIMIT, tmp);
}
+static struct irq_chip brcm_msi_irq_chip = {
+ .name = "Brcm_MSI",
+ .irq_mask = pci_msi_mask_irq,
+ .irq_unmask = pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info brcm_msi_domain_info = {
+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX),
+ .chip = &brcm_msi_irq_chip,
+};
+
+static void brcm_pcie_msi_isr(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct brcm_msi *msi;
+ unsigned long status, virq;
+ u32 mask, bit, hwirq;
+ struct device *dev;
+
+ chained_irq_enter(chip, desc);
+ msi = irq_desc_get_handler_data(desc);
+ mask = msi->intr_legacy_mask;
+ dev = msi->dev;
+
+ while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
+ for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
+ /* clear the interrupt */
+ bcm_writel(1 << bit, msi->intr_base + CLR);
+
+ /* Account for legacy interrupt offset */
+ hwirq = bit - msi->intr_legacy_offset;
+
+ virq = irq_find_mapping(msi->inner_domain, hwirq);
+ if (virq) {
+ if (msi->used & (1 << hwirq))
+ generic_handle_irq(virq);
+ else
+ dev_info(dev, "unhandled MSI %d\n",
+ hwirq);
+ } else {
+ /* Unknown MSI, just clear it */
+ dev_dbg(dev, "unexpected MSI\n");
+ }
+ }
+ }
+ chained_irq_exit(chip, desc);
+}
+
+static void brcm_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+ struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
+ u32 temp;
+
+ msg->address_lo = lower_32_bits(msi->target_addr);
+ msg->address_hi = upper_32_bits(msi->target_addr);
+ temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+ msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
+}
+
+static int brcm_msi_set_affinity(struct irq_data *irq_data,
+ const struct cpumask *mask, bool force)
+{
+ return -EINVAL;
+}
+
+static struct irq_chip brcm_msi_bottom_irq_chip = {
+ .name = "Brcm_MSI",
+ .irq_compose_msi_msg = brcm_compose_msi_msg,
+ .irq_set_affinity = brcm_msi_set_affinity,
+};
+
+static int brcm_msi_alloc(struct brcm_msi *msi)
+{
+ int bit, hwirq;
+
+ mutex_lock(&msi->lock);
+ bit = ~msi->used ? ffz(msi->used) : -1;
+
+ if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
+ msi->used |= (1 << bit);
+ hwirq = bit - msi->intr_legacy_offset;
+ } else {
+ hwirq = -ENOSPC;
+ }
+
+ mutex_unlock(&msi->lock);
+ return hwirq;
+}
+
+static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
+{
+ mutex_lock(&msi->lock);
+ msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
+ mutex_unlock(&msi->lock);
+}
+
+static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *args)
+{
+ struct brcm_msi *msi = domain->host_data;
+ int hwirq;
+
+ hwirq = brcm_msi_alloc(msi);
+
+ if (hwirq < 0)
+ return hwirq;
+
+ irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
+ &brcm_msi_bottom_irq_chip, domain->host_data,
+ handle_simple_irq, NULL, NULL);
+ return 0;
+}
+
+static void brcm_irq_domain_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
+
+ brcm_msi_free(msi, d->hwirq);
+}
+
+static void brcm_msi_set_regs(struct brcm_msi *msi)
+{
+ u32 data_val, msi_lo, msi_hi;
+
+ if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+ /*
+ * ffe0 -- least sig 5 bits are 0 indicating 32 msgs
+ * 6540 -- this is our arbitrary unique data value
+ */
+ data_val = 0xffe06540;
+ } else {
+ /*
+ * fff8 -- least sig 3 bits are 0 indicating 8 msgs
+ * 6540 -- this is our arbitrary unique data value
+ */
+ data_val = 0xfff86540;
+ }
+
+ /*
+ * Make sure we are not masking MSIs. Note that MSIs can be masked,
+ * but that occurs on the PCIe EP device
+ */
+ bcm_writel(0xffffffff & msi->intr_legacy_mask,
+ msi->intr_base + MASK_CLR);
+
+ msi_lo = lower_32_bits(msi->target_addr);
+ msi_hi = upper_32_bits(msi->target_addr);
+ /*
+ * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
+ * enable, which we set to 1.
+ */
+ bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
+ bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
+ bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
+}
+
+static const struct irq_domain_ops msi_domain_ops = {
+ .alloc = brcm_irq_domain_alloc,
+ .free = brcm_irq_domain_free,
+};
+
+static int brcm_allocate_domains(struct brcm_msi *msi)
+{
+ struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
+ struct device *dev = msi->dev;
+
+ msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
+ &msi_domain_ops, msi);
+ if (!msi->inner_domain) {
+ dev_err(dev, "failed to create IRQ domain\n");
+ return -ENOMEM;
+ }
+
+ msi->msi_domain = pci_msi_create_irq_domain(fwnode,
+ &brcm_msi_domain_info,
+ msi->inner_domain);
+ if (!msi->msi_domain) {
+ dev_err(dev, "failed to create MSI domain\n");
+ irq_domain_remove(msi->inner_domain);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static void brcm_free_domains(struct brcm_msi *msi)
+{
+ irq_domain_remove(msi->msi_domain);
+ irq_domain_remove(msi->inner_domain);
+}
+
+static void brcm_msi_remove(struct brcm_pcie *pcie)
+{
+ struct brcm_msi *msi = pcie->msi;
+
+ if (!msi)
+ return;
+ irq_set_chained_handler(msi->irq, NULL);
+ irq_set_handler_data(msi->irq, NULL);
+ brcm_free_domains(msi);
+}
+
+static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
+{
+ struct brcm_msi *msi;
+ int irq, ret;
+ struct device *dev = pcie->dev;
+
+ irq = irq_of_parse_and_map(dev->of_node, 1);
+ if (irq <= 0) {
+ dev_err(dev, "cannot map msi intr\n");
+ return -ENODEV;
+ }
+
+ msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
+ if (!msi)
+ return -ENOMEM;
+
+ msi->dev = dev;
+ msi->base = pcie->base;
+ msi->rev = pcie->rev;
+ msi->dn = pcie->dn;
+ msi->target_addr = pcie->msi_target_addr;
+ msi->irq = irq;
+
+ ret = brcm_allocate_domains(msi);
+ if (ret)
+ return ret;
+
+ irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
+
+ if (msi->rev >= BRCM_PCIE_HW_REV_33) {
+ msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
+ /*
+ * This version of PCIe hw has only 32 intr bits
+ * starting at bit position 0.
+ */
+ msi->intr_legacy_mask = 0xffffffff;
+ msi->intr_legacy_offset = 0x0;
+ msi->used = 0x0;
+
+ } else {
+ msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
+ /*
+ * This version of PCIe hw has only 8 intr bits starting
+ * at bit position 24.
+ */
+ msi->intr_legacy_mask = 0xff000000;
+ msi->intr_legacy_offset = 24;
+ msi->used = 0x00ffffff;
+ }
+
+ brcm_msi_set_regs(msi);
+ pcie->msi = msi;
+
+ return 0;
+}
+
/* Configuration space read/write support */
static int cfg_index(int busnr, int devfn, int reg)
{
@@ -643,6 +943,18 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
if (ret)
return ret;
+ /*
+ * We ideally want the MSI target address to be located in the 32bit
+ * addressable memory area. Some devices might depend on it. This is
+ * possible either when the inbound window is located above the lower
+ * 4GB or when the inbound and outbound areas fit in the lower 4GB of
+ * memory.
+ */
+ if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) <= SZ_4G)
+ pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
+ else
+ pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
+
tmp = lower_32_bits(rc_bar2_offset);
tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
encode_ibar_size(rc_bar2_size));
@@ -816,6 +1128,9 @@ static int brcm_pcie_resume(struct device *dev)
if (ret)
return ret;
+ if (pcie->msi && pcie->msi_internal)
+ brcm_msi_set_regs(pcie->msi);
+
pcie->suspended = false;
return 0;
@@ -823,6 +1138,7 @@ static int brcm_pcie_resume(struct device *dev)
static void _brcm_pcie_remove(struct brcm_pcie *pcie)
{
+ brcm_msi_remove(pcie);
turn_off(pcie);
clk_disable_unprepare(pcie->clk);
clk_put(pcie->clk);
@@ -847,7 +1163,7 @@ MODULE_DEVICE_TABLE(of, brcm_pcie_match);
static int brcm_pcie_probe(struct platform_device *pdev)
{
- struct device_node *dn = pdev->dev.of_node;
+ struct device_node *dn = pdev->dev.of_node, *msi_dn;
const struct of_device_id *of_id;
const struct pcie_cfg_data *data;
struct resource *res;
@@ -923,6 +1239,20 @@ static int brcm_pcie_probe(struct platform_device *pdev)
if (ret)
goto fail;
+ msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
+ /* Use the internal MSI if no msi-parent property */
+ if (!msi_dn)
+ msi_dn = pcie->dn;
+
+ if (pci_msi_enabled() && msi_dn == pcie->dn) {
+ ret = brcm_pcie_enable_msi(pcie);
+ if (ret)
+ dev_err(pcie->dev,
+ "probe of internal MSI failed: %d)", ret);
+ else
+ pcie->msi_internal = true;
+ }
+
bridge->dev.parent = &pdev->dev;
bridge->busnr = 0;
bridge->ops = &brcm_pcie_ops;
@@ -944,7 +1274,6 @@ static int brcm_pcie_probe(struct platform_device *pdev)
pcie->root_bus = bridge->bus;
return 0;
-
fail:
_brcm_pcie_remove(pcie);
return ret;
--
2.23.0
This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies
XHCI USB 3.0 controller.
Signed-off-by: Nicolas Saenz Julienne <[email protected]>
---
arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index a9d84e28f245..c7b2e7b57da6 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -288,6 +288,53 @@
arm,cpu-registers-not-fw-configured;
};
+ scb {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
+ <0x6 0x00000000 0x6 0x00000000 0x40000000>;
+
+ pcie_0: pcie@7d500000 {
+ compatible = "brcm,bcm2711-pcie";
+ reg = <0x0 0x7d500000 0x9310>;
+ msi-controller;
+ msi-parent = <&pcie_0>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ linux,pci-domain = <0>;
+ brcm,enable-ssc;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
+ IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &gicv2 GIC_SPI 144
+ IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &gicv2 GIC_SPI 145
+ IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &gicv2 GIC_SPI 146
+ IRQ_TYPE_LEVEL_HIGH>;
+
+ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
+ 0x0 0x04000000>;
+ /*
+ * The wrapper around the PCIe block has a bug
+ * preventing it from accessing beyond the first 3GB of
+ * memory. As the bus DMA mask is rounded up to the
+ * closest power of two of the dma-range size, we're
+ * forced to set the limit at 2GB. This can be
+ * harmlessly changed in the future once the DMA code
+ * handles non power of two DMA limits.
+ */
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
+ 0x0 0x80000000>;
+ };
+ };
+
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.23.0
From: Jim Quinlan <[email protected]>
The DT bindings description of the brcmstb PCIe device is described.
This node can only be used for now on the Raspberry Pi 4.
This was based on Jim's original submission[1], converted to yaml and
adapted to the RPi4 case.
[1] https://patchwork.kernel.org/patch/10605937/
Signed-off-by: Jim Quinlan <[email protected]>
Co-developed-by: Nicolas Saenz Julienne <[email protected]>
Signed-off-by: Nicolas Saenz Julienne <[email protected]>
---
.../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++
1 file changed, 116 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
new file mode 100644
index 000000000000..0b81c26f8568
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -0,0 +1,116 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Brcmstb PCIe Host Controller Device Tree Bindings
+
+maintainers:
+ - Nicolas Saenz Julienne <[email protected]>
+
+properties:
+ compatible:
+ const: brcm,bcm2711-pcie # The Raspberry Pi 4
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: PCIe host controller
+ - description: builtin MSI controller
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: pcie
+ - const: msi
+
+ "#address-cells":
+ const: 3
+
+ "#size-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-map-mask: true
+
+ interrupt-map: true
+
+ ranges: true
+
+ dma-ranges: true
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: sw_pcie
+
+ msi-controller:
+ description: Identifies the node as an MSI controller.
+ type: boolean
+
+ msi-parent:
+ description: MSI controller the device is capable of using.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ linux,pci-domain:
+ description: PCI domain ID. Should be unique for each host controller.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ brcm,enable-ssc:
+ description: Indicates usage of spread-spectrum clocking.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - "#interrupt-cells"
+ - interrupt-map-mask
+ - interrupt-map
+ - ranges
+ - dma-ranges
+ - linux,pci-domain
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ scb {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ pcie0: pcie@7d500000 {
+ compatible = "brcm,bcm2711-pcie";
+ reg = <0x0 0x7d500000 0x9310>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ msi-parent = <&pcie0>;
+ msi-controller;
+ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+ linux,pci-domain = <0>;
+ brcm,enable-ssc;
+ };
+ };
--
2.23.0
On 11/6/19 1:45 PM, Nicolas Saenz Julienne wrote:
> This series aims at providing support for Raspberry Pi 4's PCIe
> controller, which is also shared with the Broadcom STB family of
> devices.
>
> There was a previous attempt to upstream this some years ago[1] but was
> blocked as most STB PCIe integrations have a sparse DMA mapping[2] which
> is something currently not supported by the kernel. Luckily this is not
> the case for the Raspberry Pi 4.
>
> Note that the driver code is to be based on top of Rob Herring's series
> simplifying inbound and outbound range parsing.
>
> [1] https://patchwork.kernel.org/cover/10605933/
> [2] https://patchwork.kernel.org/patch/10605957/
Thanks for picking up on this Nicolas. Can you amend the MAINTAINERS
file with something along those lines such that PCIe binding and driver
changes are picked up by both the BCM2835 and BCM7XXX entries?
diff --git a/MAINTAINERS b/MAINTAINERS
index cba1095547fd..4276a30f3294 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3196,6 +3196,8 @@ S: Maintained
N: bcm2711
N: bcm2835
F: drivers/staging/vc04_services
+F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+F: drivers/pci/controller/pcie-brcmstb.c
BROADCOM BCM47XX MIPS ARCHITECTURE
M: Hauke Mehrtens <[email protected]>
@@ -3251,6 +3253,7 @@ F: drivers/bus/brcmstb_gisb.c
F: arch/arm/mm/cache-b15-rac.c
F: arch/arm/include/asm/hardware/cache-b15-rac.h
N: brcmstb
+F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
BROADCOM BMIPS CPUFREQ DRIVER
M: Markus Mayer <[email protected]>
--
Florian
On Wed, 2019-11-06 at 13:51 -0800, Florian Fainelli wrote:
> On 11/6/19 1:45 PM, Nicolas Saenz Julienne wrote:
> > This series aims at providing support for Raspberry Pi 4's PCIe
> > controller, which is also shared with the Broadcom STB family of
> > devices.
> >
> > There was a previous attempt to upstream this some years ago[1] but was
> > blocked as most STB PCIe integrations have a sparse DMA mapping[2] which
> > is something currently not supported by the kernel. Luckily this is not
> > the case for the Raspberry Pi 4.
> >
> > Note that the driver code is to be based on top of Rob Herring's series
> > simplifying inbound and outbound range parsing.
> >
> > [1] https://patchwork.kernel.org/cover/10605933/
> > [2] https://patchwork.kernel.org/patch/10605957/
>
> Thanks for picking up on this Nicolas. Can you amend the MAINTAINERS
> file with something along those lines such that PCIe binding and driver
> changes are picked up by both the BCM2835 and BCM7XXX entries?
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cba1095547fd..4276a30f3294 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3196,6 +3196,8 @@ S: Maintained
> N: bcm2711
> N: bcm2835
> F: drivers/staging/vc04_services
> +F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +F: drivers/pci/controller/pcie-brcmstb.c
>
> BROADCOM BCM47XX MIPS ARCHITECTURE
> M: Hauke Mehrtens <[email protected]>
> @@ -3251,6 +3253,7 @@ F: drivers/bus/brcmstb_gisb.c
> F: arch/arm/mm/cache-b15-rac.c
> F: arch/arm/include/asm/hardware/cache-b15-rac.h
> N: brcmstb
> +F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
>
> BROADCOM BMIPS CPUFREQ DRIVER
> M: Markus Mayer <[email protected]>
>
Ok, noted, I'll add that patch to v2.
On Wed, Nov 06, 2019 at 10:45:23PM +0100, Nicolas Saenz Julienne wrote:
> From: Jim Quinlan <[email protected]>
Nit: Looking at past git history, ideally the patch subject would be
'dt-bindings: *PCI*: *A*dd bindings for brcmstb's PCIe.
>
> The DT bindings description of the brcmstb PCIe device is described.
> This node can only be used for now on the Raspberry Pi 4.
>
> This was based on Jim's original submission[1], converted to yaml and
> adapted to the RPi4 case.
Thanks for picking this up.
>
> [1] https://patchwork.kernel.org/patch/10605937/
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> .../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++
> 1 file changed, 116 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> new file mode 100644
> index 000000000000..0b81c26f8568
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -0,0 +1,116 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Brcmstb PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> + - Nicolas Saenz Julienne <[email protected]>
> +
> +properties:
> + compatible:
> + const: brcm,bcm2711-pcie # The Raspberry Pi 4
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: PCIe host controller
> + - description: builtin MSI controller
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 2
> + items:
> + - const: pcie
> + - const: msi
> +
> + "#address-cells":
> + const: 3
> +
> + "#size-cells":
> + const: 2
> +
> + "#interrupt-cells":
> + const: 1
> +
> + interrupt-map-mask: true
> +
> + interrupt-map: true
> +
> + ranges: true
> +
> + dma-ranges: true
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: sw_pcie
> +
> + msi-controller:
> + description: Identifies the node as an MSI controller.
> + type: boolean
> +
> + msi-parent:
> + description: MSI controller the device is capable of using.
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> + linux,pci-domain:
> + description: PCI domain ID. Should be unique for each host controller.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + brcm,enable-ssc:
> + description: Indicates usage of spread-spectrum clocking.
> + type: boolean
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - "#interrupt-cells"
> + - interrupt-map-mask
> + - interrupt-map
> + - ranges
> + - dma-ranges
> + - linux,pci-domain
I don't think pci-domain is *required* is it?
Thanks,
Andrew Murray
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + scb {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + pcie0: pcie@7d500000 {
> + compatible = "brcm,bcm2711-pcie";
> + reg = <0x0 0x7d500000 0x9310>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pcie", "msi";
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + msi-parent = <&pcie0>;
> + msi-controller;
> + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
> + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
> + linux,pci-domain = <0>;
> + brcm,enable-ssc;
> + };
> + };
> --
> 2.23.0
>
On Wed, Nov 06, 2019 at 10:45:24PM +0100, Nicolas Saenz Julienne wrote:
> This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies
s/wich/which/
> XHCI USB 3.0 controller.
>
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> index a9d84e28f245..c7b2e7b57da6 100644
> --- a/arch/arm/boot/dts/bcm2711.dtsi
> +++ b/arch/arm/boot/dts/bcm2711.dtsi
> @@ -288,6 +288,53 @@
> arm,cpu-registers-not-fw-configured;
> };
>
> + scb {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
> + <0x6 0x00000000 0x6 0x00000000 0x40000000>;
> +
> + pcie_0: pcie@7d500000 {
> + compatible = "brcm,bcm2711-pcie";
> + reg = <0x0 0x7d500000 0x9310>;
> + msi-controller;
> + msi-parent = <&pcie_0>;
> + #address-cells = <3>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + linux,pci-domain = <0>;
pci-domain is unlikely to be needed here.
> + brcm,enable-ssc;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pcie", "msi";
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
> + IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 2 &gicv2 GIC_SPI 144
> + IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 3 &gicv2 GIC_SPI 145
> + IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 4 &gicv2 GIC_SPI 146
> + IRQ_TYPE_LEVEL_HIGH>;
> +
> + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
> + 0x0 0x04000000>;
Is legacy I/O supported by this controller?
> + /*
> + * The wrapper around the PCIe block has a bug
> + * preventing it from accessing beyond the first 3GB of
> + * memory. As the bus DMA mask is rounded up to the
> + * closest power of two of the dma-range size, we're
> + * forced to set the limit at 2GB. This can be
> + * harmlessly changed in the future once the DMA code
> + * handles non power of two DMA limits.
> + */
> + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
> + 0x0 0x80000000>;
> + };
> + };
Thanks,
Andrew Murray
> +
> cpus: cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.23.0
>
On Thu, 2019-11-07 at 10:32 +0000, Andrew Murray wrote:
> On Wed, Nov 06, 2019 at 10:45:23PM +0100, Nicolas Saenz Julienne wrote:
> > From: Jim Quinlan <[email protected]>
>
> Nit: Looking at past git history, ideally the patch subject would be
> 'dt-bindings: *PCI*: *A*dd bindings for brcmstb's PCIe.
Noted.
> > The DT bindings description of the brcmstb PCIe device is described.
> > This node can only be used for now on the Raspberry Pi 4.
> >
> > This was based on Jim's original submission[1], converted to yaml and
> > adapted to the RPi4 case.
>
> Thanks for picking this up.
>
> > [1] https://patchwork.kernel.org/patch/10605937/
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > .../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++
> > 1 file changed, 116 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > new file mode 100644
> > index 000000000000..0b81c26f8568
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > @@ -0,0 +1,116 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Brcmstb PCIe Host Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Nicolas Saenz Julienne <[email protected]>
> > +
> > +properties:
> > + compatible:
> > + const: brcm,bcm2711-pcie # The Raspberry Pi 4
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 2
> > + items:
> > + - description: PCIe host controller
> > + - description: builtin MSI controller
> > +
> > + interrupt-names:
> > + minItems: 1
> > + maxItems: 2
> > + items:
> > + - const: pcie
> > + - const: msi
> > +
> > + "#address-cells":
> > + const: 3
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > + "#interrupt-cells":
> > + const: 1
> > +
> > + interrupt-map-mask: true
> > +
> > + interrupt-map: true
> > +
> > + ranges: true
> > +
> > + dma-ranges: true
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + items:
> > + - const: sw_pcie
> > +
> > + msi-controller: /* We use the domain number as our controller number */
> > pcie->id = of_get_pci_domain_nr(dn);
> > if (pcie->id < 0)
> > return pcie->id;
> > + description: Identifies the node as an MSI controller.
> > + type: boolean
> > +
> > + msi-parent:
> > + description: MSI controller the device is capable of using.
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > +
> > + linux,pci-domain:
> > + description: PCI domain ID. Should be unique for each host controller.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + brcm,enable-ssc:
> > + description: Indicates usage of spread-spectrum clocking.
> > + type: boolean
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - "#address-cells"
> > + - "#size-cells"
> > + - "#interrupt-cells"
> > + - interrupt-map-mask
> > + - interrupt-map
> > + - ranges
> > + - dma-ranges
> > + - linux,pci-domain
>
> I don't think pci-domain is *required* is it?
You're right, I missed that one. It was needed on some of the STB devices but
not in the RPi4's case. I'll remove it in v2.
Regards,
Nicolas
Thanks for the patch, some initial feedback below, though I will give it a
more detailed review on your respin.
On Wed, Nov 06, 2019 at 10:45:25PM +0100, Nicolas Saenz Julienne wrote:
> From: Jim Quinlan <[email protected]>
>
> This commit adds the basic Broadcom STB PCIe controller. Missing is the
> ability to process MSI. This functionality is added in a subsequent
> commit.
>
> The PCIe block contains an MDIO interface. This is a local interface
> only accessible by the PCIe controller. It cannot be used or shared
> by any other HW. As such, the small amount of code for this
> controller is included in this driver as there is little upside to put
> it elsewhere.
>
> This is based on Jim's original submission[1] but adapted and tailored
> specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> the rest of the brcmstb family will soon follow once we get support for
> multiple dma-ranges in dma/direct.
This commit message is very informative and helpful, though I feel a lot
of this isn't relevant for a commit message (especially as much of it is
time based comments). Instead it would be better to simply describe what
the patch does provide, and any additional helpful notes can be provided
under the '---' after the signed off (which won't make it into git).
>
> [1] https://patchwork.kernel.org/patch/10605959/
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> drivers/pci/controller/Kconfig | 12 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> 3 files changed, 986 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-brcmstb.c
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index f5de9119e8d3..8b3aae91d8af 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -281,6 +281,18 @@ config VMD
> To compile this driver as a module, choose M here: the
> module will be called vmd.
>
> +config PCIE_BRCMSTB
> + bool "Broadcom Brcmstb PCIe host controller"
> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
I can't see what ARCH_BRCMSTB adds here. Given this also depends
on SOC_BRCMSTB. Are all of these depends really necessary?
Also should the bool be "Broadcom STB PCIe host contoller" ?
> + depends on OF
> + depends on SOC_BRCMSTB
> + default ARCH_BRCMSTB || BMIPS_GENERIC
Please also include COMPILE_TEST in here (look at the other controllers
in the file). This helps improve testing coverage by compiling all drivers
even if they can't be run.
> + help
> + Say Y here to enable PCIe host controller support for
> + Broadcom Settop Box SOCs. A Broadcom SOC will may have
s/Settop/Set top/ or s/Settop/STB/?
> + multiple host controllers as opposed to a single host
> + controller with multiple ports.
I'm sure many other SOCs may have multiple controllers instead of one
with multiple ports. I'm not sure what value this adds here. It's
always better to describe enough information so the user can determine
if this option will enable something they want on their hardware.
> +
> config PCI_HYPERV_INTERFACE
> tristate "Hyper-V PCI Interface"
> depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index a2a22c9d91af..3fc0b0cf5b5b 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> obj-y += dwc/
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> new file mode 100644
> index 000000000000..880ec11d06a1
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -0,0 +1,973 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright (C) 2009 - 2019 Broadcom */
> +
> +#include <linux/clk.h>
> +#include <linux/compiler.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/log2.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/printk.h>
> +#include <linux/sizes.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +
> +#include "../pci.h"
Is this last include needed? Sometimes controller drivers suffer from copy and
paste and this is often included when it isn't needed.
> +
> +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> +#define BRCM_PCIE_CAP_REGS 0x00ac
> +
> +/*
> + * Broadcom Settop Box PCIe Register Offsets. The names are from
> + * the chip's RDB and we use them here so that a script can correlate
> + * this code and the RDB to prevent discrepancies.
> + */
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> +#define PCIE_MISC_MISC_CTRL 0x4008
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> +#define PCIE_MISC_PCIE_CTRL 0x4064
> +#define PCIE_MISC_PCIE_STATUS 0x4068
> +#define PCIE_MISC_REVISION 0x406c
PCIE_MISC_REVISION can be removed as it shouldn't be needed
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> +#define PCIE_INTR2_CPU_BASE 0x4300
> +
> +/*
> + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> + * names are from the chip's RDB and we use them here so that a script
> + * can correlate this code and the RDB to prevent discrepancies.
> + */
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
Most of the above aren't used anywhere, please remove them.
> +
> +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> +#define BRCM_MAX_SCB 0x4
> +
> +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
These two aren't used.
> +
> +#define BURST_SIZE_128 0
> +#define BURST_SIZE_256 1
> +#define BURST_SIZE_512 2
> +
> +/* Offsets from PCIE_INTR2_CPU_BASE */
> +#define STATUS 0x0
> +#define SET 0x4
> +#define CLR 0x8
> +#define MASK_STATUS 0xc
> +#define MASK_SET 0x10
> +#define MASK_CLR 0x14
Some of the above are not used anywhere.
> +
> +#define PCIE_BUSNUM_SHIFT 20
> +#define PCIE_SLOT_SHIFT 15
> +#define PCIE_FUNC_SHIFT 12
> +
> +#if defined(__BIG_ENDIAN)
> +#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */
> +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */
> +#else
> +#define DATA_ENDIAN 0
> +#define MMIO_ENDIAN 0
> +#endif
> +
> +#define MDIO_PORT0 0x0
> +#define MDIO_DATA_MASK 0x7fffffff
> +#define MDIO_DATA_SHIFT 0x0
> +#define MDIO_PORT_MASK 0xf0000
> +#define MDIO_PORT_SHIFT 0x16
> +#define MDIO_REGAD_MASK 0xffff
> +#define MDIO_REGAD_SHIFT 0x0
> +#define MDIO_CMD_MASK 0xfff00000
> +#define MDIO_CMD_SHIFT 0x14
> +#define MDIO_CMD_READ 0x1
> +#define MDIO_CMD_WRITE 0x0
> +#define MDIO_DATA_DONE_MASK 0x80000000
> +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
> +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
> +#define SSC_REGS_ADDR 0x1100
> +#define SET_ADDR_OFFSET 0x1f
> +#define SSC_CNTL_OFFSET 0x2
> +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> +#define SSC_STATUS_OFFSET 0x1
> +#define SSC_STATUS_SSC_MASK 0x400
> +#define SSC_STATUS_SSC_SHIFT 0xa
> +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> +
> +#define IDX_ADDR(pcie) \
> + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> +#define DATA_ADDR(pcie) \
> + ((pcie)->reg_offsets[EXT_CFG_DATA])
> +#define PCIE_RGR1_SW_INIT_1(pcie) \
> + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> +
> +enum {
> + RGR1_SW_INIT_1,
> + EXT_CFG_INDEX,
> + EXT_CFG_DATA,
> +};
> +
> +enum {
> + RGR1_SW_INIT_1_INIT_MASK,
> + RGR1_SW_INIT_1_INIT_SHIFT,
> + RGR1_SW_INIT_1_PERST_MASK,
> + RGR1_SW_INIT_1_PERST_SHIFT,
> +};
> +
> +enum pcie_type {
> + BCM2711,
> +};
> +
> +struct brcm_window {
> + dma_addr_t pcie_addr;
> + phys_addr_t cpu_addr;
> + dma_addr_t size;
> +};
> +
> +/* Internal PCIe Host Controller Information.*/
> +struct brcm_pcie {
> + struct device *dev;
> + void __iomem *base;
> + int irq;
'irq' isn't used and can be removed.
> + struct clk *clk;
> + struct pci_bus *root_bus;
> + struct device_node *dn;
> + int id;
'id' isn't used and can be removed.
> + bool suspended;
> + bool ssc;
> + int gen;
> + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> + unsigned int rev;
'rev' isn't used and can be removed.
> + const int *reg_offsets;
> + const int *reg_field_info;
> + enum pcie_type type;
> +};
> +
> +struct pcie_cfg_data {
> + const int *reg_field_info;
> + const int *offsets;
> + const enum pcie_type type;
> +};
> +
> +static const int pcie_reg_field_info[] = {
> + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> +};
> +
> +static const int pcie_offset_bcm2711[] = {
> + [RGR1_SW_INIT_1] = 0x9210,
> + [EXT_CFG_INDEX] = 0x9000,
> + [EXT_CFG_DATA] = 0x8000,
> +};
> +
> +static const struct pcie_cfg_data bcm2711_cfg = {
> + .reg_field_info = pcie_reg_field_info,
> + .offsets = pcie_offset_bcm2711,
> + .type = BCM2711,
> +};
> +
> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> + int where);
> +
> +static struct pci_ops brcm_pcie_ops = {
> + .map_bus = brcm_pcie_map_conf,
> + .read = pci_generic_config_read,
> + .write = pci_generic_config_write,
> +};
> +
> +#define bcm_readl(a) readl(a)
> +#define bcm_writel(d, a) writel(d, a)
> +#define bcm_readw(a) readw(a)
> +#define bcm_writew(d, a) writew(d, a)
Is there much value in these macros?
> +
> +/* These macros extract/insert fields to host controller's register set. */
> +#define RD_FLD(base, reg, field) \
> + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> +#define WR_FLD(base, reg, field, val) \
> + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> +#define WR_FLD_RB(base, reg, field, val) \
> + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> + reg##_##field##_SHIFT, val)
> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> + reg##_##field##_SHIFT, val)
> +#define EXTRACT_FIELD(val, reg, field) \
> + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> +#define INSERT_FIELD(val, reg, field, field_val) \
> + (((val) & ~reg##_##field##_MASK) | \
> + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> +
> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> +{
> + return (bcm_readl(p) & mask) >> shift;
> +}
> +
> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> + u32 reg = bcm_readl(p);
> +
> + reg = (reg & ~mask) | ((val << shift) & mask);
> + bcm_writel(reg, p);
> +}
> +
> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> + wr_fld(p, mask, shift, val);
> + (void)bcm_readl(p);
> +}
> +
> +static const char *link_speed_to_str(int s)
> +{
> + switch (s) {
> + case 1:
> + return "2.5";
> + case 2:
> + return "5.0";
> + case 3:
> + return "8.0";
> + default:
> + break;
> + }
> + return "???";
> +}
> +
> +/*
> + * The roundup_pow_of_two() from log2.h invokes
> + * __roundup_pow_of_two(unsigned long), but we really need a
> + * such a function to take a native u64 since unsigned long
> + * is 32 bits on some configurations. So we provide this helper
> + * function below.
> + */
> +static u64 roundup_pow_of_two_64(u64 n)
> +{
> + return 1ULL << fls64(n - 1);
> +}
Given that you use this in one place and that it is a single line, I'd
suggest you just drop this function. Alternatively if you wanted to add
this function to log2.h then you already have a bunch of users ready to
be migrated to it:
$ git grep "<< fls64"
arch/sparc/mm/init_64.c: m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
drivers/net/ethernet/mellanox/mlx4/en_clock.c: u64 max_val_cycles_rounded = 1ULL << fls64(max_val_cycles - 1);
drivers/pci/controller/pcie-cadence-ep.c: sz = 1ULL << fls64(sz - 1);
drivers/pci/controller/pcie-cadence.c: u64 sz = 1ULL << fls64(size - 1);
drivers/pci/controller/pcie-rockchip-ep.c: u64 sz = 1ULL << fls64(size - 1);
drivers/pci/controller/pcie-rockchip-ep.c: sz = 1ULL << fls64(sz - 1);
> +
> +/*
> + * This is to convert the size of the inbound "BAR" region to the
> + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> + */
> +int encode_ibar_size(u64 size)
> +{
> + int log2_in = ilog2(size);
> +
> + if (log2_in >= 12 && log2_in <= 15)
> + /* Covers 4KB to 32KB (inclusive) */
> + return (log2_in - 12) + 0x1c;
> + else if (log2_in >= 16 && log2_in <= 37)
> + /* Covers 64KB to 32GB, (inclusive) */
2^37 != 32GB?
> + return log2_in - 15;
> + /* Something is awry so disable */
> + return 0;
> +}
> +
> +static u32 mdio_form_pkt(int port, int regad, int cmd)
> +{
> + u32 pkt = 0;
> +
> + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> +
> + return pkt;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> +{
> + int tries;
> + u32 data;
> +
> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> + base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> +
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> + udelay(10);
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> + }
> +
> + return MDIO_RD_DONE(data)
> + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> + : -EIO;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> +{
> + int tries;
> + u32 data;
> +
> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> + base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> + base + PCIE_RC_DL_MDIO_WR_DATA);
> +
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> + udelay(10);
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> + }
> +
> + return MDIO_WT_DONE(data) ? 0 : -EIO;
> +}
> +
> +/*
> + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> + * return value indicates error.
> + */
> +static int set_ssc(void __iomem *base)
Please prefix this with brcm_pcie_ (and other similar occurances)
> +{
> + int tmp;
> + u16 wrdata;
> + int pll, ssc;
> +
> + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> + if (tmp < 0)
> + return tmp;
> +
> + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> + if (tmp < 0)
> + return tmp;
> +
> + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> + if (tmp < 0)
> + return tmp;
> +
> + usleep_range(1000, 2000);
> + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> + if (tmp < 0)
> + return tmp;
> +
> + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> +
> + return (ssc && pll) ? 0 : -EIO;
> +}
> +
> +/* Limits operation to a specific generation (1, 2, or 3) */
> +static void set_gen(void __iomem *base, int gen)
> +{
> + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> +
> + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> +
> + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> +}
> +
> +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> + unsigned int win, phys_addr_t cpu_addr,
> + dma_addr_t pcie_addr, dma_addr_t size)
> +{
> + void __iomem *base = pcie->base;
> + phys_addr_t cpu_addr_mb, limit_addr_mb;
> + u32 tmp;
> +
> + /* Set the base of the pcie_addr window */
> + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> + bcm_writel(upper_32_bits(pcie_addr),
> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> +
> + cpu_addr_mb = cpu_addr >> 20;
> + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> +
> + /* Write the addr base low register */
> + WR_FLD_WITH_OFFSET(base, (win * 4),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> + BASE, cpu_addr_mb);
> + /* Write the addr limit low register */
> + WR_FLD_WITH_OFFSET(base, (win * 4),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> + LIMIT, limit_addr_mb);
> +
> + /* Write the cpu addr high register */
> + tmp = (u32)(cpu_addr_mb >>
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> + WR_FLD_WITH_OFFSET(base, (win * 8),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> + BASE, tmp);
> + /* Write the cpu limit high register */
> + tmp = (u32)(limit_addr_mb >>
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> + WR_FLD_WITH_OFFSET(base, (win * 8),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> + LIMIT, tmp);
> +}
> +
> +/* Configuration space read/write support */
> +static int cfg_index(int busnr, int devfn, int reg)
> +{
> + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> + | (busnr << PCIE_BUSNUM_SHIFT)
> + | (reg & ~3);
> +}
> +
> +/* The controller is capable of serving in both RC and EP roles */
> +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> +
> + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> +}
> +
> +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> +
> + return (dla && plu) ? true : false;
> +}
> +
> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> + int where)
> +{
> + struct brcm_pcie *pcie = bus->sysdata;
> + void __iomem *base = pcie->base;
> + int idx;
> +
> + /* Accesses to the RC go right to the RC registers if slot==0 */
> + if (pci_is_root_bus(bus))
> + return PCI_SLOT(devfn) ? NULL : base + where;
> +
> + /* For devices, write to the config space index register */
> + idx = cfg_index(bus->number, devfn, 0);
> + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> + return base + DATA_ADDR(pcie) + where;
> +}
> +
> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> + unsigned int val)
> +{
> + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> +
> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> +}
> +
> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> + unsigned int val)
> +{
> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> +}
> +
> +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> + u64 *rc_bar2_size,
> + u64 *rc_bar2_offset)
> +{
> + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> + struct device *dev = pcie->dev;
> + struct resource_entry *entry;
> + u64 total_mem_size = 0;
> +
> + *rc_bar2_offset = -1;
> +
> + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> + /*
> + * We're promissed the RC will provide a contiguous view of
s/promissed/promised/
> + * memory to downstream devices. We can then infer the
> + * rc_bar2_offset from the lower avaiable dma-range offset.
> + */
> + if (entry->offset < *rc_bar2_offset)
> + *rc_bar2_offset = entry->offset;
> +
> + total_mem_size += entry->res->end - entry->res->start + 1;
> + }
> +
> + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> +
> + /*
> + * Validate the results:
> + *
> + * The PCIe host controller by design must set the inbound viewport to
> + * be a contiguous arrangement of all of the system's memory. In
> + * addition, its size mut be a power of two. To further complicate
> + * matters, the viewport must start on a pcie-address that is aligned
> + * on a multiple of its size. If a portion of the viewport does not
> + * represent system memory -- e.g. 3GB of memory requires a 4GB
> + * viewport -- we can map the outbound memory in or after 3GB and even
> + * though the viewport will overlap the outbound memory the controller
> + * will know to send outbound memory downstream and everything else
> + * upstream.
> + *
> + * For example:
> + *
> + * - The best-case scenario, memory up to 3GB, is to place the inbound
> + * region in the first 4GB of pcie-space, as some legacy devices can
> + * only address 32bits. We would also like to put the MSI under 4GB
> + * as well, since some devices require a 32bit MSI target address.
> + *
> + * - If the system memory is 4GB or larger we cannot start the inbound
> + * region at location 0 (since we have to allow some space for
> + * outbound memory @ 3GB). So instead it will start at the 1x
> + * multiple of its size
> + */
> + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
> + *rc_bar2_size, *rc_bar2_offset);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> +{
> + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> + u64 rc_bar2_offset, rc_bar2_size;
> + void __iomem *base = pcie->base;
> + struct resource_entry *entry;
> + unsigned int scb_size_val;
> + struct resource *res;
> + int num_out_wins = 0;
> + u32 tmp;
> + int i, j, ret, limit;
> + u16 nlw, cls, lnksta;
> + bool ssc_good = false;
> + struct device *dev = pcie->dev;
> +
> + /* Reset the bridge */
> + brcm_pcie_bridge_sw_init_set(pcie, 1);
> +
> + usleep_range(100, 200);
> +
> + /* Take the bridge out of reset */
> + brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> + /* Wait for SerDes to be stable */
> + usleep_range(100, 200);
> +
> + /* Grab the PCIe hw revision number */
> + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
This isn't used anywhere
> +
> + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> + BURST_SIZE_128);
> + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> +
> + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> + &rc_bar2_offset);
> + if (ret)
> + return ret;
> +
> + tmp = lower_32_bits(rc_bar2_offset);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> + encode_ibar_size(rc_bar2_size));
> + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> + bcm_writel(upper_32_bits(rc_bar2_offset),
> + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> +
> + scb_size_val = rc_bar2_size ?
> + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> +
> + /* disable the PCIe->GISB memory window (RC_BAR1) */
> + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> +
> + /* disable the PCIe->SCB memory window (RC_BAR3) */
> + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> +
> + if (!pcie->suspended) {
> + /* clear any interrupts we find on boot */
> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> + }
> +
> + /* Mask all interrupts since we are not handling any yet */
> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> +
> + if (pcie->gen)
> + set_gen(base, pcie->gen);
> +
> + /* Unassert the fundamental reset */
> + brcm_pcie_perst_set(pcie, 0);
> +
> + /*
> + * Give the RC/EP time to wake up, before trying to configure RC.
> + * Intermittently check status for link-up, up to a total of 100ms
> + * when we don't know if the device is there, and up to 1000ms if
> + * we do know the device is there.
> + */
> + limit = pcie->suspended ? 1000 : 100;
> + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> + j += i, i = i * 2)
> + msleep(i + j > limit ? limit - j : i);
Does it need to be this complex? Also waiting a second during resume seems
like a long delay.
> +
> + if (!brcm_pcie_link_up(pcie)) {
> + dev_info(dev, "link down\n");
> + return -ENODEV;
> + }
> +
> + if (!brcm_pcie_rc_mode(pcie)) {
> + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> + return -EINVAL;
> + }
> +
> + resource_list_for_each_entry(entry, &bridge->windows) {
> + res = entry->res;
> +
> + if (resource_type(res) != IORESOURCE_MEM)
> + continue;
> +
> + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> + dev_err(pcie->dev, "too many outbound wins\n");
> + return -EINVAL;
> + }
> +
> + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> + res->start - entry->offset,
> + res->end - res->start + 1);
> + num_out_wins++;
> + }
> +
> + /*
> + * For config space accesses on the RC, show the right class for
> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> + */
> + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> +
> + if (pcie->ssc) {
> + ret = set_ssc(base);
> + if (ret == 0)
> + ssc_good = true;
> + else
> + dev_err(dev, "failed attempt to enter ssc mode\n");
> + }
> +
> + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> +
> + /* PCIe->SCB endian mode for BAR */
> + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> +
> + /*
> + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> + */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> +
> + return 0;
> +}
> +
> +/* L23 is a low-power PCIe link state */
> +static void enter_l23(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + int l23, i;
> +
> + /* assert request for L23 */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> +
> + /* Wait up to 30 msec for L23 */
> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> + for (i = 0; i < 15 && !l23; i++) {
> + usleep_range(2000, 2400);
> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> + }
> +
> + if (!l23)
> + dev_err(pcie->dev, "failed to enter L23\n");
> +}
> +
> +static void turn_off(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> +
> + if (brcm_pcie_link_up(pcie))
> + enter_l23(pcie);
> + /* Assert fundamental reset */
> + brcm_pcie_perst_set(pcie, 1);
> + /* Deassert request for L23 in case it was asserted */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> + /* Turn off SerDes */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> + /* Shutdown PCIe bridge */
> + brcm_pcie_bridge_sw_init_set(pcie, 1);
> +}
> +
> +static int brcm_pcie_suspend(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> +
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + pcie->suspended = true;
> +
> + return 0;
> +}
> +
> +static int brcm_pcie_resume(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> + void __iomem *base;
> + int ret;
> +
> + base = pcie->base;
> + clk_prepare_enable(pcie->clk);
> +
> + /* Take bridge out of reset so we can access the SerDes reg */
> + brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> + /* Turn on SerDes */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> + /* Wait for SerDes to be stable */
> + usleep_range(100, 200);
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + return ret;
> +
> + pcie->suspended = false;
> +
> + return 0;
> +}
> +
> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
I don't see the value in the first underscore here.
> +{
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + clk_put(pcie->clk);
> +}
> +
> +static int brcm_pcie_remove(struct platform_device *pdev)
> +{
> + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> +
> + pci_stop_root_bus(pcie->root_bus);
> + pci_remove_root_bus(pcie->root_bus);
> + _brcm_pcie_remove(pcie);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id brcm_pcie_match[] = {
> + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> +
> +static int brcm_pcie_probe(struct platform_device *pdev)
> +{
> + struct device_node *dn = pdev->dev.of_node;
> + const struct of_device_id *of_id;
> + const struct pcie_cfg_data *data;
> + struct resource *res;
> + int ret;
> + struct brcm_pcie *pcie;
> + void __iomem *base;
> + struct pci_host_bridge *bridge;
> + struct pci_bus *child;
> +
> + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> + if (!bridge)
> + return -ENOMEM;
> +
> + pcie = pci_host_bridge_priv(bridge);
> +
> + of_id = of_match_node(brcm_pcie_match, dn);
> + if (!of_id) {
> + dev_err(&pdev->dev, "failed to look up compatible string\n");
> + return -EINVAL;
> + }
> +
> + data = of_id->data;
Can you replace the above (from of_match_node to here) with the following?
data = of_device_get_match_data(pdev->dev)
> + pcie->reg_offsets = data->offsets;
> + pcie->reg_field_info = data->reg_field_info;
> + pcie->type = data->type;
> + pcie->dn = dn;
> + pcie->dev = &pdev->dev;
> +
> + /* We use the domain number as our controller number */
> + pcie->id = of_get_pci_domain_nr(dn);
> + if (pcie->id < 0)
> + return pcie->id;
We don't do anything with this, so you can remove this.
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -EINVAL;
The majority of controller drivers don't bother to check the return value
here and just pass res into devm_ioremap_resource.
> +
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> + if (IS_ERR(pcie->clk)) {
> + dev_err(&pdev->dev, "could not get clock\n");
> + pcie->clk = NULL;
> + }
Is this a good use-case for devm_clk_get_optional?
> + pcie->base = base;
> +
> + ret = of_pci_get_max_link_speed(dn);
> + pcie->gen = (ret < 0) ? 0 : ret;
There is no checking that gen isn't too large here, given that we pass
this into a register later we probably want to check it here.
> +
> + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> +
> + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> + if (ret == 0)
> + /* keep going, as we don't use this intr yet */
> + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> + else
> + pcie->irq = ret;
Given we don't use it yet, please remove it from this patch.
> +
> + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> + &bridge->dma_ranges, NULL);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(pcie->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "could not enable clock\n");
> + return ret;
> + }
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + goto fail;
> +
> + bridge->dev.parent = &pdev->dev;
> + bridge->busnr = 0;
> + bridge->ops = &brcm_pcie_ops;
> + bridge->sysdata = pcie;
> + bridge->map_irq = of_irq_parse_and_map_pci;
> + bridge->swizzle_irq = pci_common_swizzle;
> +
> + ret = pci_scan_root_bus_bridge(bridge);
> + if (ret < 0) {
> + dev_err(pcie->dev, "Scanning root bridge failed\n");
> + goto fail;
> + }
> +
> + pci_assign_unassigned_bus_resources(bridge->bus);
> + list_for_each_entry(child, &bridge->bus->children, node)
> + pcie_bus_configure_settings(child);
> + pci_bus_add_devices(bridge->bus);
> + platform_set_drvdata(pdev, pcie);
> + pcie->root_bus = bridge->bus;
> +
> + return 0;
> +
> +fail:
> + _brcm_pcie_remove(pcie);
> + return ret;
> +}
> +
> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> + .suspend_noirq = brcm_pcie_suspend,
> + .resume_noirq = brcm_pcie_resume,
> +};
> +
> +static struct platform_driver brcm_pcie_driver = {
> + .probe = brcm_pcie_probe,
> + .remove = brcm_pcie_remove,
> + .driver = {
> + .name = "brcm-pcie",
> + .owner = THIS_MODULE,
> + .of_match_table = brcm_pcie_match,
> + .pm = &brcm_pcie_pm_ops,
> + },
> +};
> +
> +module_platform_driver(brcm_pcie_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
> +MODULE_AUTHOR("Broadcom");
> --
> 2.23.0
>
On 2019-11-06 22:54, Nicolas Saenz Julienne wrote:
> From: Jim Quinlan <[email protected]>
>
> This commit adds MSI to the Broadcom STB PCIe host controller. It
> does
> not add MSIX since that functionality is not in the HW. The MSI
> controller is physically located within the PCIe block, however,
> there
> is no reason why the MSI controller could not be moved elsewhere in
> the future.
>
> Since the internal Brcmstb MSI controller is intertwined with the
> PCIe
> controller, it is not its own platform device but rather part of the
> PCIe platform device.
>
> This is based on Jim's original submission[1] with some slight
> changes
> regarding how pcie->msi_target_addr is decided.
>
> [1] https://patchwork.kernel.org/patch/10605955/
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> drivers/pci/controller/Kconfig | 2 +-
> drivers/pci/controller/pcie-brcmstb.c | 333
> +++++++++++++++++++++++++-
> 2 files changed, 332 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/Kconfig
> b/drivers/pci/controller/Kconfig
> index 8b3aae91d8af..99b972ad3f2f 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -284,7 +284,7 @@ config VMD
> config PCIE_BRCMSTB
> bool "Broadcom Brcmstb PCIe host controller"
> depends on ARCH_BRCMSTB || BMIPS_GENERIC
> - depends on OF
> + depends on OF && PCI_MSI
> depends on SOC_BRCMSTB
> default ARCH_BRCMSTB || BMIPS_GENERIC
> help
> diff --git a/drivers/pci/controller/pcie-brcmstb.c
> b/drivers/pci/controller/pcie-brcmstb.c
> index 880ec11d06a1..26053e69b95f 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /* Copyright (C) 2009 - 2019 Broadcom */
>
> +#include <linux/bitops.h>
> #include <linux/clk.h>
> #include <linux/compiler.h>
> #include <linux/delay.h>
> @@ -8,11 +9,13 @@
> #include <linux/interrupt.h>
> #include <linux/io.h>
> #include <linux/ioport.h>
> +#include <linux/irqchip/chained_irq.h>
> #include <linux/irqdomain.h>
> #include <linux/kernel.h>
> #include <linux/list.h>
> #include <linux/log2.h>
> #include <linux/module.h>
> +#include <linux/msi.h>
> #include <linux/of_address.h>
> #include <linux/of_irq.h>
> #include <linux/of_pci.h>
> @@ -46,6 +49,9 @@
> #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> +#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
> +#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
> +#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
> #define PCIE_MISC_PCIE_CTRL 0x4064
> #define PCIE_MISC_PCIE_STATUS 0x4068
> #define PCIE_MISC_REVISION 0x406c
> @@ -54,6 +60,7 @@
> #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> #define PCIE_INTR2_CPU_BASE 0x4300
> +#define PCIE_MSI_INTR2_BASE 0x4500
>
> /*
> * Broadcom Settop Box PCIe Register Field shift and mask info. The
> @@ -114,6 +121,8 @@
>
> #define BRCM_NUM_PCIE_OUT_WINS 0x4
> #define BRCM_MAX_SCB 0x4
> +#define BRCM_INT_PCI_MSI_NR 32
> +#define BRCM_PCIE_HW_REV_33 0x0303
>
> #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> @@ -199,6 +208,33 @@ struct brcm_window {
> dma_addr_t size;
> };
>
> +struct brcm_msi {
> + struct device *dev;
> + void __iomem *base;
> + struct device_node *dn;
> + struct irq_domain *msi_domain;
> + struct irq_domain *inner_domain;
> + struct mutex lock; /* guards the alloc/free operations */
> + u64 target_addr;
> + int irq;
> +
> + /* intr_base is the base pointer for interrupt status/set/clr regs
> */
> + void __iomem *intr_base;
> +
> + /* intr_legacy_mask indicates how many bits are MSI interrupts */
> + u32 intr_legacy_mask;
> +
> + /*
> + * intr_legacy_offset indicates bit position of MSI_01. It is
> + * to map the register bit position to a hwirq that starts at 0.
> + */
> + u32 intr_legacy_offset;
> +
> + /* used indicates which MSI interrupts have been alloc'd */
> + unsigned long used;
> + unsigned int rev;
> +};
> +
> /* Internal PCIe Host Controller Information.*/
> struct brcm_pcie {
> struct device *dev;
> @@ -211,7 +247,10 @@ struct brcm_pcie {
> bool suspended;
> bool ssc;
> int gen;
> + u64 msi_target_addr;
> struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> + struct brcm_msi *msi;
> + bool msi_internal;
Do you need both of these fields? Is there any case where msi is valid
and msi_internal is false?
> unsigned int rev;
> const int *reg_offsets;
> const int *reg_field_info;
> @@ -477,6 +516,267 @@ static void brcm_pcie_set_outbound_win(struct
> brcm_pcie *pcie,
> LIMIT, tmp);
> }
>
> +static struct irq_chip brcm_msi_irq_chip = {
> + .name = "Brcm_MSI",
> + .irq_mask = pci_msi_mask_irq,
> + .irq_unmask = pci_msi_unmask_irq,
> +};
> +
> +static struct msi_domain_info brcm_msi_domain_info = {
> + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> + MSI_FLAG_PCI_MSIX),
Is there a particular reason for not supporting MultiMSI? I won't miss
it, but it might be worth documenting the restriction if the HW cannot
support it (though I can't immediately see why).
> + .chip = &brcm_msi_irq_chip,
> +};
> +
> +static void brcm_pcie_msi_isr(struct irq_desc *desc)
> +{
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> + struct brcm_msi *msi;
> + unsigned long status, virq;
> + u32 mask, bit, hwirq;
> + struct device *dev;
> +
> + chained_irq_enter(chip, desc);
> + msi = irq_desc_get_handler_data(desc);
> + mask = msi->intr_legacy_mask;
> + dev = msi->dev;
> +
> + while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
Is this loop really worth it? If, as I imagine, this register is at the
end of a wet piece of string, this additional read (likely to return
zero)
will have a measurable latency impact...
> + for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
> + /* clear the interrupt */
> + bcm_writel(1 << bit, msi->intr_base + CLR);
> +
> + /* Account for legacy interrupt offset */
> + hwirq = bit - msi->intr_legacy_offset;
> +
> + virq = irq_find_mapping(msi->inner_domain, hwirq);
> + if (virq) {
> + if (msi->used & (1 << hwirq))
> + generic_handle_irq(virq);
> + else
> + dev_info(dev, "unhandled MSI %d\n",
> + hwirq);
Can this ever happen? If you've found the mapping in the irqdomain,
the MSI obviously has been allocated. Or am I missing something?
> + } else {
> + /* Unknown MSI, just clear it */
> + dev_dbg(dev, "unexpected MSI\n");
> + }
> + }
> + }
> + chained_irq_exit(chip, desc);
> +}
> +
> +static void brcm_compose_msi_msg(struct irq_data *data, struct
> msi_msg *msg)
> +{
> + struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
> + u32 temp;
> +
> + msg->address_lo = lower_32_bits(msi->target_addr);
> + msg->address_hi = upper_32_bits(msi->target_addr);
> + temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
Do you have to reload it from the HW?
> + msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
> +}
> +
> +static int brcm_msi_set_affinity(struct irq_data *irq_data,
> + const struct cpumask *mask, bool force)
> +{
> + return -EINVAL;
> +}
> +
> +static struct irq_chip brcm_msi_bottom_irq_chip = {
> + .name = "Brcm_MSI",
> + .irq_compose_msi_msg = brcm_compose_msi_msg,
> + .irq_set_affinity = brcm_msi_set_affinity,
> +};
> +
> +static int brcm_msi_alloc(struct brcm_msi *msi)
> +{
> + int bit, hwirq;
> +
> + mutex_lock(&msi->lock);
> + bit = ~msi->used ? ffz(msi->used) : -1;
> +
> + if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
> + msi->used |= (1 << bit);
> + hwirq = bit - msi->intr_legacy_offset;
> + } else {
> + hwirq = -ENOSPC;
> + }
Please consider using bitmap_find_free_region() and co, instead of
open coding your allocator.
> +
> + mutex_unlock(&msi->lock);
> + return hwirq;
> +}
> +
> +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
> +{
> + mutex_lock(&msi->lock);
> + msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
> + mutex_unlock(&msi->lock);
> +}
> +
> +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned
> int virq,
> + unsigned int nr_irqs, void *args)
> +{
> + struct brcm_msi *msi = domain->host_data;
> + int hwirq;
> +
> + hwirq = brcm_msi_alloc(msi);
> +
> + if (hwirq < 0)
> + return hwirq;
> +
> + irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
> + &brcm_msi_bottom_irq_chip, domain->host_data,
> + handle_simple_irq, NULL, NULL);
simple_irq doesn't quite match what this does. This really should
use an edge flow.
> + return 0;
> +}
> +
> +static void brcm_irq_domain_free(struct irq_domain *domain,
> + unsigned int virq, unsigned int nr_irqs)
> +{
> + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> + struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
> +
> + brcm_msi_free(msi, d->hwirq);
> +}
> +
> +static void brcm_msi_set_regs(struct brcm_msi *msi)
> +{
> + u32 data_val, msi_lo, msi_hi;
> +
> + if (msi->rev >= BRCM_PCIE_HW_REV_33) {
> + /*
> + * ffe0 -- least sig 5 bits are 0 indicating 32 msgs
> + * 6540 -- this is our arbitrary unique data value
> + */
> + data_val = 0xffe06540;
> + } else {
> + /*
> + * fff8 -- least sig 3 bits are 0 indicating 8 msgs
> + * 6540 -- this is our arbitrary unique data value
> + */
> + data_val = 0xfff86540;
> + }
> +
> + /*
> + * Make sure we are not masking MSIs. Note that MSIs can be
> masked,
> + * but that occurs on the PCIe EP device
That's not a guarantee, specially with plain MultiMSI. I'm actually
minded to move the masking to be purely local on the MSI controllers
I maintain.
> + */
> + bcm_writel(0xffffffff & msi->intr_legacy_mask,
> + msi->intr_base + MASK_CLR);
> +
> + msi_lo = lower_32_bits(msi->target_addr);
> + msi_hi = upper_32_bits(msi->target_addr);
> + /*
> + * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
> + * enable, which we set to 1.
> + */
> + bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
> + bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
> + bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
> +}
> +
> +static const struct irq_domain_ops msi_domain_ops = {
> + .alloc = brcm_irq_domain_alloc,
> + .free = brcm_irq_domain_free,
> +};
> +
> +static int brcm_allocate_domains(struct brcm_msi *msi)
> +{
> + struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
> + struct device *dev = msi->dev;
> +
> + msi->inner_domain = irq_domain_add_linear(NULL,
> BRCM_INT_PCI_MSI_NR,
> + &msi_domain_ops, msi);
> + if (!msi->inner_domain) {
> + dev_err(dev, "failed to create IRQ domain\n");
> + return -ENOMEM;
> + }
> +
> + msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> + &brcm_msi_domain_info,
> + msi->inner_domain);
> + if (!msi->msi_domain) {
> + dev_err(dev, "failed to create MSI domain\n");
> + irq_domain_remove(msi->inner_domain);
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> +static void brcm_free_domains(struct brcm_msi *msi)
> +{
> + irq_domain_remove(msi->msi_domain);
> + irq_domain_remove(msi->inner_domain);
> +}
> +
> +static void brcm_msi_remove(struct brcm_pcie *pcie)
> +{
> + struct brcm_msi *msi = pcie->msi;
> +
> + if (!msi)
> + return;
> + irq_set_chained_handler(msi->irq, NULL);
> + irq_set_handler_data(msi->irq, NULL);
> + brcm_free_domains(msi);
> +}
> +
> +static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
> +{
> + struct brcm_msi *msi;
> + int irq, ret;
> + struct device *dev = pcie->dev;
> +
> + irq = irq_of_parse_and_map(dev->of_node, 1);
> + if (irq <= 0) {
> + dev_err(dev, "cannot map msi intr\n");
> + return -ENODEV;
> + }
> +
> + msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
> + if (!msi)
> + return -ENOMEM;
> +
> + msi->dev = dev;
> + msi->base = pcie->base;
> + msi->rev = pcie->rev;
> + msi->dn = pcie->dn;
> + msi->target_addr = pcie->msi_target_addr;
> + msi->irq = irq;
> +
> + ret = brcm_allocate_domains(msi);
> + if (ret)
> + return ret;
You seem to rely on the devm_* allocators to cleanup on failure. But as
far
as I can see, failing to initialize the MSI subsystem doesn't translate
in
a PCIe init failure, hence keeping the memory around.
> +
> + irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
> +
> + if (msi->rev >= BRCM_PCIE_HW_REV_33) {
> + msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
> + /*
> + * This version of PCIe hw has only 32 intr bits
> + * starting at bit position 0.
> + */
> + msi->intr_legacy_mask = 0xffffffff;
> + msi->intr_legacy_offset = 0x0;
> + msi->used = 0x0;
> +
> + } else {
> + msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
> + /*
> + * This version of PCIe hw has only 8 intr bits starting
> + * at bit position 24.
> + */
> + msi->intr_legacy_mask = 0xff000000;
> + msi->intr_legacy_offset = 24;
> + msi->used = 0x00ffffff;
> + }
> +
> + brcm_msi_set_regs(msi);
> + pcie->msi = msi;
> +
> + return 0;
> +}
> +
> /* Configuration space read/write support */
> static int cfg_index(int busnr, int devfn, int reg)
> {
> @@ -643,6 +943,18 @@ static int brcm_pcie_setup(struct brcm_pcie
> *pcie)
> if (ret)
> return ret;
>
> + /*
> + * We ideally want the MSI target address to be located in the
> 32bit
> + * addressable memory area. Some devices might depend on it. This
> is
> + * possible either when the inbound window is located above the
> lower
> + * 4GB or when the inbound and outbound areas fit in the lower 4GB
> of
> + * memory.
> + */
> + if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) <=
> SZ_4G)
> + pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
> + else
> + pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
> +
> tmp = lower_32_bits(rc_bar2_offset);
> tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> encode_ibar_size(rc_bar2_size));
> @@ -816,6 +1128,9 @@ static int brcm_pcie_resume(struct device *dev)
> if (ret)
> return ret;
>
> + if (pcie->msi && pcie->msi_internal)
> + brcm_msi_set_regs(pcie->msi);
> +
> pcie->suspended = false;
>
> return 0;
> @@ -823,6 +1138,7 @@ static int brcm_pcie_resume(struct device *dev)
>
> static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> {
> + brcm_msi_remove(pcie);
> turn_off(pcie);
> clk_disable_unprepare(pcie->clk);
> clk_put(pcie->clk);
> @@ -847,7 +1163,7 @@ MODULE_DEVICE_TABLE(of, brcm_pcie_match);
>
> static int brcm_pcie_probe(struct platform_device *pdev)
> {
> - struct device_node *dn = pdev->dev.of_node;
> + struct device_node *dn = pdev->dev.of_node, *msi_dn;
> const struct of_device_id *of_id;
> const struct pcie_cfg_data *data;
> struct resource *res;
> @@ -923,6 +1239,20 @@ static int brcm_pcie_probe(struct
> platform_device *pdev)
> if (ret)
> goto fail;
>
> + msi_dn = of_parse_phandle(pcie->dn, "msi-parent", 0);
> + /* Use the internal MSI if no msi-parent property */
> + if (!msi_dn)
> + msi_dn = pcie->dn;
> +
> + if (pci_msi_enabled() && msi_dn == pcie->dn) {
> + ret = brcm_pcie_enable_msi(pcie);
> + if (ret)
> + dev_err(pcie->dev,
> + "probe of internal MSI failed: %d)", ret);
> + else
> + pcie->msi_internal = true;
> + }
> +
> bridge->dev.parent = &pdev->dev;
> bridge->busnr = 0;
> bridge->ops = &brcm_pcie_ops;
> @@ -944,7 +1274,6 @@ static int brcm_pcie_probe(struct
> platform_device *pdev)
> pcie->root_bus = bridge->bus;
>
> return 0;
> -
> fail:
> _brcm_pcie_remove(pcie);
> return ret;
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On Thu, Nov 7, 2019 at 10:05 AM Andrew Murray <[email protected]> wrote:
>
> Thanks for the patch, some initial feedback below, though I will give it a
> more detailed review on your respin.
>
> On Wed, Nov 06, 2019 at 10:45:25PM +0100, Nicolas Saenz Julienne wrote:
> > From: Jim Quinlan <[email protected]>
> >
> > This commit adds the basic Broadcom STB PCIe controller. Missing is the
> > ability to process MSI. This functionality is added in a subsequent
> > commit.
> >
> > The PCIe block contains an MDIO interface. This is a local interface
> > only accessible by the PCIe controller. It cannot be used or shared
> > by any other HW. As such, the small amount of code for this
> > controller is included in this driver as there is little upside to put
> > it elsewhere.
> >
> > This is based on Jim's original submission[1] but adapted and tailored
> > specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> > the rest of the brcmstb family will soon follow once we get support for
> > multiple dma-ranges in dma/direct.
>
> This commit message is very informative and helpful, though I feel a lot
> of this isn't relevant for a commit message (especially as much of it is
> time based comments). Instead it would be better to simply describe what
> the patch does provide, and any additional helpful notes can be provided
> under the '---' after the signed off (which won't make it into git).
>
> >
> > [1] https://patchwork.kernel.org/patch/10605959/
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > drivers/pci/controller/Kconfig | 12 +
> > drivers/pci/controller/Makefile | 1 +
> > drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> > 3 files changed, 986 insertions(+)
> > create mode 100644 drivers/pci/controller/pcie-brcmstb.c
> >
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index f5de9119e8d3..8b3aae91d8af 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -281,6 +281,18 @@ config VMD
> > To compile this driver as a module, choose M here: the
> > module will be called vmd.
> >
> > +config PCIE_BRCMSTB
> > + bool "Broadcom Brcmstb PCIe host controller"
> > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
>
> I can't see what ARCH_BRCMSTB adds here. Given this also depends
> on SOC_BRCMSTB. Are all of these depends really necessary?
>
> Also should the bool be "Broadcom STB PCIe host contoller" ?
>
> > + depends on OF
> > + depends on SOC_BRCMSTB
> > + default ARCH_BRCMSTB || BMIPS_GENERIC
>
> Please also include COMPILE_TEST in here (look at the other controllers
> in the file). This helps improve testing coverage by compiling all drivers
> even if they can't be run.
>
> > + help
> > + Say Y here to enable PCIe host controller support for
> > + Broadcom Settop Box SOCs. A Broadcom SOC will may have
>
> s/Settop/Set top/ or s/Settop/STB/?
>
> > + multiple host controllers as opposed to a single host
> > + controller with multiple ports.
>
> I'm sure many other SOCs may have multiple controllers instead of one
> with multiple ports. I'm not sure what value this adds here. It's
> always better to describe enough information so the user can determine
> if this option will enable something they want on their hardware.
>
> > +
> > config PCI_HYPERV_INTERFACE
> > tristate "Hyper-V PCI Interface"
> > depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> > index a2a22c9d91af..3fc0b0cf5b5b 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > obj-$(CONFIG_VMD) += vmd.o
> > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > obj-y += dwc/
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > new file mode 100644
> > index 000000000000..880ec11d06a1
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -0,0 +1,973 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* Copyright (C) 2009 - 2019 Broadcom */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/compiler.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/ioport.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/kernel.h>
> > +#include <linux/list.h>
> > +#include <linux/log2.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pci.h>
> > +#include <linux/printk.h>
> > +#include <linux/sizes.h>
> > +#include <linux/slab.h>
> > +#include <linux/string.h>
> > +#include <linux/types.h>
> > +
> > +#include "../pci.h"
>
> Is this last include needed? Sometimes controller drivers suffer from copy and
> paste and this is often included when it isn't needed.
>
> > +
> > +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> > +#define BRCM_PCIE_CAP_REGS 0x00ac
> > +
> > +/*
> > + * Broadcom Settop Box PCIe Register Offsets. The names are from
> > + * the chip's RDB and we use them here so that a script can correlate
> > + * this code and the RDB to prevent discrepancies.
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> > +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > +#define PCIE_MISC_MISC_CTRL 0x4008
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > +#define PCIE_MISC_PCIE_CTRL 0x4064
> > +#define PCIE_MISC_PCIE_STATUS 0x4068
> > +#define PCIE_MISC_REVISION 0x406c
>
> PCIE_MISC_REVISION can be removed as it shouldn't be needed
>
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > +#define PCIE_INTR2_CPU_BASE 0x4300
> > +
> > +/*
> > + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> > + * names are from the chip's RDB and we use them here so that a script
> > + * can correlate this code and the RDB to prevent discrepancies.
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> > +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> > +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> > +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
>
> Most of the above aren't used anywhere, please remove them.
>
> > +
> > +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> > +#define BRCM_MAX_SCB 0x4
> > +
> > +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
>
> These two aren't used.
>
> > +
> > +#define BURST_SIZE_128 0
> > +#define BURST_SIZE_256 1
> > +#define BURST_SIZE_512 2
> > +
> > +/* Offsets from PCIE_INTR2_CPU_BASE */
> > +#define STATUS 0x0
> > +#define SET 0x4
> > +#define CLR 0x8
> > +#define MASK_STATUS 0xc
> > +#define MASK_SET 0x10
> > +#define MASK_CLR 0x14
>
> Some of the above are not used anywhere.
>
> > +
> > +#define PCIE_BUSNUM_SHIFT 20
> > +#define PCIE_SLOT_SHIFT 15
> > +#define PCIE_FUNC_SHIFT 12
> > +
> > +#if defined(__BIG_ENDIAN)
> > +#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */
> > +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */
> > +#else
> > +#define DATA_ENDIAN 0
> > +#define MMIO_ENDIAN 0
> > +#endif
> > +
> > +#define MDIO_PORT0 0x0
> > +#define MDIO_DATA_MASK 0x7fffffff
> > +#define MDIO_DATA_SHIFT 0x0
> > +#define MDIO_PORT_MASK 0xf0000
> > +#define MDIO_PORT_SHIFT 0x16
> > +#define MDIO_REGAD_MASK 0xffff
> > +#define MDIO_REGAD_SHIFT 0x0
> > +#define MDIO_CMD_MASK 0xfff00000
> > +#define MDIO_CMD_SHIFT 0x14
> > +#define MDIO_CMD_READ 0x1
> > +#define MDIO_CMD_WRITE 0x0
> > +#define MDIO_DATA_DONE_MASK 0x80000000
> > +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
> > +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
> > +#define SSC_REGS_ADDR 0x1100
> > +#define SET_ADDR_OFFSET 0x1f
> > +#define SSC_CNTL_OFFSET 0x2
> > +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> > +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> > +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> > +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> > +#define SSC_STATUS_OFFSET 0x1
> > +#define SSC_STATUS_SSC_MASK 0x400
> > +#define SSC_STATUS_SSC_SHIFT 0xa
> > +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> > +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> > +
> > +#define IDX_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> > +#define DATA_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_DATA])
> > +#define PCIE_RGR1_SW_INIT_1(pcie) \
> > + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> > +
> > +enum {
> > + RGR1_SW_INIT_1,
> > + EXT_CFG_INDEX,
> > + EXT_CFG_DATA,
> > +};
> > +
> > +enum {
> > + RGR1_SW_INIT_1_INIT_MASK,
> > + RGR1_SW_INIT_1_INIT_SHIFT,
> > + RGR1_SW_INIT_1_PERST_MASK,
> > + RGR1_SW_INIT_1_PERST_SHIFT,
> > +};
> > +
> > +enum pcie_type {
> > + BCM2711,
> > +};
> > +
> > +struct brcm_window {
> > + dma_addr_t pcie_addr;
> > + phys_addr_t cpu_addr;
> > + dma_addr_t size;
> > +};
> > +
> > +/* Internal PCIe Host Controller Information.*/
> > +struct brcm_pcie {
> > + struct device *dev;
> > + void __iomem *base;
> > + int irq;
>
> 'irq' isn't used and can be removed.
>
> > + struct clk *clk;
> > + struct pci_bus *root_bus;
> > + struct device_node *dn;
> > + int id;
>
> 'id' isn't used and can be removed.
>
> > + bool suspended;
> > + bool ssc;
> > + int gen;
> > + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > + unsigned int rev;
>
> 'rev' isn't used and can be removed.
>
> > + const int *reg_offsets;
> > + const int *reg_field_info;
> > + enum pcie_type type;
> > +};
> > +
> > +struct pcie_cfg_data {
> > + const int *reg_field_info;
> > + const int *offsets;
> > + const enum pcie_type type;
> > +};
> > +
> > +static const int pcie_reg_field_info[] = {
> > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> > +};
> > +
> > +static const int pcie_offset_bcm2711[] = {
> > + [RGR1_SW_INIT_1] = 0x9210,
> > + [EXT_CFG_INDEX] = 0x9000,
> > + [EXT_CFG_DATA] = 0x8000,
> > +};
> > +
> > +static const struct pcie_cfg_data bcm2711_cfg = {
> > + .reg_field_info = pcie_reg_field_info,
> > + .offsets = pcie_offset_bcm2711,
> > + .type = BCM2711,
> > +};
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> > + int where);
> > +
> > +static struct pci_ops brcm_pcie_ops = {
> > + .map_bus = brcm_pcie_map_conf,
> > + .read = pci_generic_config_read,
> > + .write = pci_generic_config_write,
> > +};
> > +
> > +#define bcm_readl(a) readl(a)
> > +#define bcm_writel(d, a) writel(d, a)
> > +#define bcm_readw(a) readw(a)
> > +#define bcm_writew(d, a) writew(d, a)
>
> Is there much value in these macros?
>
> > +
> > +/* These macros extract/insert fields to host controller's register set. */
> > +#define RD_FLD(base, reg, field) \
> > + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> > +#define WR_FLD(base, reg, field, val) \
> > + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> > +#define WR_FLD_RB(base, reg, field, val) \
> > + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> > + reg##_##field##_SHIFT, val)
> > +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> > + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> > + reg##_##field##_SHIFT, val)
> > +#define EXTRACT_FIELD(val, reg, field) \
> > + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> > +#define INSERT_FIELD(val, reg, field, field_val) \
> > + (((val) & ~reg##_##field##_MASK) | \
> > + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> > +
> > +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> > +{
> > + return (bcm_readl(p) & mask) >> shift;
> > +}
> > +
> > +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + u32 reg = bcm_readl(p);
> > +
> > + reg = (reg & ~mask) | ((val << shift) & mask);
> > + bcm_writel(reg, p);
> > +}
> > +
> > +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + wr_fld(p, mask, shift, val);
> > + (void)bcm_readl(p);
> > +}
> > +
> > +static const char *link_speed_to_str(int s)
> > +{
> > + switch (s) {
> > + case 1:
> > + return "2.5";
> > + case 2:
> > + return "5.0";
> > + case 3:
> > + return "8.0";
> > + default:
> > + break;
> > + }
> > + return "???";
> > +}
> > +
> > +/*
> > + * The roundup_pow_of_two() from log2.h invokes
> > + * __roundup_pow_of_two(unsigned long), but we really need a
> > + * such a function to take a native u64 since unsigned long
> > + * is 32 bits on some configurations. So we provide this helper
> > + * function below.
> > + */
> > +static u64 roundup_pow_of_two_64(u64 n)
> > +{
> > + return 1ULL << fls64(n - 1);
> > +}
>
> Given that you use this in one place and that it is a single line, I'd
> suggest you just drop this function. Alternatively if you wanted to add
> this function to log2.h then you already have a bunch of users ready to
> be migrated to it:
>
> $ git grep "<< fls64"
> arch/sparc/mm/init_64.c: m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
> drivers/net/ethernet/mellanox/mlx4/en_clock.c: u64 max_val_cycles_rounded = 1ULL << fls64(max_val_cycles - 1);
> drivers/pci/controller/pcie-cadence-ep.c: sz = 1ULL << fls64(sz - 1);
> drivers/pci/controller/pcie-cadence.c: u64 sz = 1ULL << fls64(size - 1);
> drivers/pci/controller/pcie-rockchip-ep.c: u64 sz = 1ULL << fls64(size - 1);
> drivers/pci/controller/pcie-rockchip-ep.c: sz = 1ULL << fls64(sz - 1);
>
>
> > +
> > +/*
> > + * This is to convert the size of the inbound "BAR" region to the
> > + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> > + */
> > +int encode_ibar_size(u64 size)
> > +{
> > + int log2_in = ilog2(size);
> > +
> > + if (log2_in >= 12 && log2_in <= 15)
> > + /* Covers 4KB to 32KB (inclusive) */
> > + return (log2_in - 12) + 0x1c;
> > + else if (log2_in >= 16 && log2_in <= 37)
> > + /* Covers 64KB to 32GB, (inclusive) */
>
> 2^37 != 32GB?
Comment should be changed
/* Current chips implement 64KB to 32GB; allow up to 128GB for
future chips */
or the value should be changed:
s/37/35/;
>
> > + return log2_in - 15;
> > + /* Something is awry so disable */
> > + return 0;
> > +}
> > +
> > +static u32 mdio_form_pkt(int port, int regad, int cmd)
> > +{
> > + u32 pkt = 0;
> > +
> > + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> > + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> > + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> > +
> > + return pkt;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + }
> > +
> > + return MDIO_RD_DONE(data)
> > + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> > + : -EIO;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> > + base + PCIE_RC_DL_MDIO_WR_DATA);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + }
> > +
> > + return MDIO_WT_DONE(data) ? 0 : -EIO;
> > +}
> > +
> > +/*
> > + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> > + * return value indicates error.
> > + */
> > +static int set_ssc(void __iomem *base)
>
> Please prefix this with brcm_pcie_ (and other similar occurances)
>
> > +{
> > + int tmp;
> > + u16 wrdata;
> > + int pll, ssc;
> > +
> > + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> > + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> > + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + usleep_range(1000, 2000);
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> > + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> > +
> > + return (ssc && pll) ? 0 : -EIO;
> > +}
> > +
> > +/* Limits operation to a specific generation (1, 2, or 3) */
> > +static void set_gen(void __iomem *base, int gen)
> > +{
> > + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > +
> > + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> > + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > +
> > + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> > + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > +}
> > +
> > +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> > + unsigned int win, phys_addr_t cpu_addr,
> > + dma_addr_t pcie_addr, dma_addr_t size)
> > +{
> > + void __iomem *base = pcie->base;
> > + phys_addr_t cpu_addr_mb, limit_addr_mb;
> > + u32 tmp;
> > +
> > + /* Set the base of the pcie_addr window */
> > + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> > + bcm_writel(upper_32_bits(pcie_addr),
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> > +
> > + cpu_addr_mb = cpu_addr >> 20;
> > + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> > +
> > + /* Write the addr base low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + BASE, cpu_addr_mb);
> > + /* Write the addr limit low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + LIMIT, limit_addr_mb);
> > +
> > + /* Write the cpu addr high register */
> > + tmp = (u32)(cpu_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> > + BASE, tmp);
> > + /* Write the cpu limit high register */
> > + tmp = (u32)(limit_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> > + LIMIT, tmp);
> > +}
> > +
> > +/* Configuration space read/write support */
> > +static int cfg_index(int busnr, int devfn, int reg)
> > +{
> > + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> > + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> > + | (busnr << PCIE_BUSNUM_SHIFT)
> > + | (reg & ~3);
> > +}
> > +
> > +/* The controller is capable of serving in both RC and EP roles */
> > +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > +
> > + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> > +}
> > +
> > +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> > + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> > +
> > + return (dla && plu) ? true : false;
> > +}
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> > + int where)
> > +{
> > + struct brcm_pcie *pcie = bus->sysdata;
> > + void __iomem *base = pcie->base;
> > + int idx;
> > +
> > + /* Accesses to the RC go right to the RC registers if slot==0 */
> > + if (pci_is_root_bus(bus))
> > + return PCI_SLOT(devfn) ? NULL : base + where;
> > +
> > + /* For devices, write to the config space index register */
> > + idx = cfg_index(bus->number, devfn, 0);
> > + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> > + return base + DATA_ADDR(pcie) + where;
> > +}
> > +
> > +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> > + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > +
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> > +}
> > +
> > +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> > + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> > + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> > +}
> > +
> > +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> > + u64 *rc_bar2_size,
> > + u64 *rc_bar2_offset)
> > +{
> > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > + struct device *dev = pcie->dev;
> > + struct resource_entry *entry;
> > + u64 total_mem_size = 0;
> > +
> > + *rc_bar2_offset = -1;
> > +
> > + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> > + /*
> > + * We're promissed the RC will provide a contiguous view of
>
> s/promissed/promised/
>
> > + * memory to downstream devices. We can then infer the
> > + * rc_bar2_offset from the lower avaiable dma-range offset.
> > + */
> > + if (entry->offset < *rc_bar2_offset)
> > + *rc_bar2_offset = entry->offset;
> > +
> > + total_mem_size += entry->res->end - entry->res->start + 1;
> > + }
> > +
> > + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> > +
> > + /*
> > + * Validate the results:
> > + *
> > + * The PCIe host controller by design must set the inbound viewport to
> > + * be a contiguous arrangement of all of the system's memory. In
> > + * addition, its size mut be a power of two. To further complicate
> > + * matters, the viewport must start on a pcie-address that is aligned
> > + * on a multiple of its size. If a portion of the viewport does not
> > + * represent system memory -- e.g. 3GB of memory requires a 4GB
> > + * viewport -- we can map the outbound memory in or after 3GB and even
> > + * though the viewport will overlap the outbound memory the controller
> > + * will know to send outbound memory downstream and everything else
> > + * upstream.
> > + *
> > + * For example:
> > + *
> > + * - The best-case scenario, memory up to 3GB, is to place the inbound
> > + * region in the first 4GB of pcie-space, as some legacy devices can
> > + * only address 32bits. We would also like to put the MSI under 4GB
> > + * as well, since some devices require a 32bit MSI target address.
> > + *
> > + * - If the system memory is 4GB or larger we cannot start the inbound
> > + * region at location 0 (since we have to allow some space for
> > + * outbound memory @ 3GB). So instead it will start at the 1x
> > + * multiple of its size
> > + */
> > + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> > + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> > + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
> > + *rc_bar2_size, *rc_bar2_offset);
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > +{
> > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > + u64 rc_bar2_offset, rc_bar2_size;
> > + void __iomem *base = pcie->base;
> > + struct resource_entry *entry;
> > + unsigned int scb_size_val;
> > + struct resource *res;
> > + int num_out_wins = 0;
> > + u32 tmp;
> > + int i, j, ret, limit;
> > + u16 nlw, cls, lnksta;
> > + bool ssc_good = false;
> > + struct device *dev = pcie->dev;
> > +
> > + /* Reset the bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +
> > + usleep_range(100, 200);
> > +
> > + /* Take the bridge out of reset */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* Wait for SerDes to be stable */
> > + usleep_range(100, 200);
> > +
> > + /* Grab the PCIe hw revision number */
> > + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> > + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
>
> This isn't used anywhere
>
> > +
> > + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> > + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> > + BURST_SIZE_128);
> > + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> > +
> > + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> > + &rc_bar2_offset);
> > + if (ret)
> > + return ret;
> > +
> > + tmp = lower_32_bits(rc_bar2_offset);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> > + encode_ibar_size(rc_bar2_size));
> > + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> > + bcm_writel(upper_32_bits(rc_bar2_offset),
> > + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> > +
> > + scb_size_val = rc_bar2_size ?
> > + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> > +
> > + /* disable the PCIe->GISB memory window (RC_BAR1) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> > +
> > + /* disable the PCIe->SCB memory window (RC_BAR3) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> > +
> > + if (!pcie->suspended) {
> > + /* clear any interrupts we find on boot */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> > + }
> > +
> > + /* Mask all interrupts since we are not handling any yet */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > +
> > + if (pcie->gen)
> > + set_gen(base, pcie->gen);
> > +
> > + /* Unassert the fundamental reset */
> > + brcm_pcie_perst_set(pcie, 0);
> > +
> > + /*
> > + * Give the RC/EP time to wake up, before trying to configure RC.
> > + * Intermittently check status for link-up, up to a total of 100ms
> > + * when we don't know if the device is there, and up to 1000ms if
> > + * we do know the device is there.
> > + */
> > + limit = pcie->suspended ? 1000 : 100;
> > + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> > + j += i, i = i * 2)
> > + msleep(i + j > limit ? limit - j : i);
>
> Does it need to be this complex? Also waiting a second during resume seems
> like a long delay.
Agree on the complexity issue. But we've had EP chips that required
this much time on a resume for reasons unknown. Code could be
changed to something like
for (i = 0; i <= limit; i += 100)
if (brcm_pcie_link_up(pcie)
break;
else
msleep(100);
>
> > +
> > + if (!brcm_pcie_link_up(pcie)) {
> > + dev_info(dev, "link down\n");
> > + return -ENODEV;
> > + }
> > +
> > + if (!brcm_pcie_rc_mode(pcie)) {
> > + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> > + return -EINVAL;
> > + }
> > +
> > + resource_list_for_each_entry(entry, &bridge->windows) {
> > + res = entry->res;
> > +
> > + if (resource_type(res) != IORESOURCE_MEM)
> > + continue;
> > +
> > + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> > + dev_err(pcie->dev, "too many outbound wins\n");
> > + return -EINVAL;
> > + }
> > +
> > + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> > + res->start - entry->offset,
> > + res->end - res->start + 1);
> > + num_out_wins++;
> > + }
> > +
> > + /*
> > + * For config space accesses on the RC, show the right class for
> > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > + */
> > + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> > +
> > + if (pcie->ssc) {
> > + ret = set_ssc(base);
> > + if (ret == 0)
> > + ssc_good = true;
> > + else
> > + dev_err(dev, "failed attempt to enter ssc mode\n");
> > + }
> > +
> > + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> > + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> > + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> > + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> > +
> > + /* PCIe->SCB endian mode for BAR */
> > + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> > + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> > + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> > +
> > + /*
> > + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> > + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> > + */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> > +
> > + return 0;
> > +}
> > +
> > +/* L23 is a low-power PCIe link state */
> > +static void enter_l23(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + int l23, i;
> > +
> > + /* assert request for L23 */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > +
> > + /* Wait up to 30 msec for L23 */
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + for (i = 0; i < 15 && !l23; i++) {
> > + usleep_range(2000, 2400);
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + }
> > +
> > + if (!l23)
> > + dev_err(pcie->dev, "failed to enter L23\n");
> > +}
> > +
> > +static void turn_off(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > +
> > + if (brcm_pcie_link_up(pcie))
> > + enter_l23(pcie);
> > + /* Assert fundamental reset */
> > + brcm_pcie_perst_set(pcie, 1);
> > + /* Deassert request for L23 in case it was asserted */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > + /* Turn off SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > + /* Shutdown PCIe bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +}
> > +
> > +static int brcm_pcie_suspend(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > +
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + pcie->suspended = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_resume(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > + void __iomem *base;
> > + int ret;
> > +
> > + base = pcie->base;
> > + clk_prepare_enable(pcie->clk);
> > +
> > + /* Take bridge out of reset so we can access the SerDes reg */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + /* Turn on SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* Wait for SerDes to be stable */
> > + usleep_range(100, 200);
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + return ret;
> > +
> > + pcie->suspended = false;
> > +
> > + return 0;
> > +}
> > +
> > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>
> I don't see the value in the first underscore here.
We have a function _brcm_pcie_remove() and a function
brcm_pciie_remove(). The former is invoked by the latter, but the
former is also invoked later in the code as well.
Jim Quinlan
Broadcom
>
> > +{
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + clk_put(pcie->clk);
> > +}
> > +
> > +static int brcm_pcie_remove(struct platform_device *pdev)
> > +{
> > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > +
> > + pci_stop_root_bus(pcie->root_bus);
> > + pci_remove_root_bus(pcie->root_bus);
> > + _brcm_pcie_remove(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id brcm_pcie_match[] = {
> > + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > +
> > +static int brcm_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *dn = pdev->dev.of_node;
> > + const struct of_device_id *of_id;
> > + const struct pcie_cfg_data *data;
> > + struct resource *res;
> > + int ret;
> > + struct brcm_pcie *pcie;
> > + void __iomem *base;
> > + struct pci_host_bridge *bridge;
> > + struct pci_bus *child;
> > +
> > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > + if (!bridge)
> > + return -ENOMEM;
> > +
> > + pcie = pci_host_bridge_priv(bridge);
> > +
> > + of_id = of_match_node(brcm_pcie_match, dn);
> > + if (!of_id) {
> > + dev_err(&pdev->dev, "failed to look up compatible string\n");
> > + return -EINVAL;
> > + }
> > +
> > + data = of_id->data;
>
> Can you replace the above (from of_match_node to here) with the following?
>
> data = of_device_get_match_data(pdev->dev)
>
> > + pcie->reg_offsets = data->offsets;
> > + pcie->reg_field_info = data->reg_field_info;
> > + pcie->type = data->type;
> > + pcie->dn = dn;
> > + pcie->dev = &pdev->dev;
> > +
> > + /* We use the domain number as our controller number */
> > + pcie->id = of_get_pci_domain_nr(dn);
> > + if (pcie->id < 0)
> > + return pcie->id;
>
> We don't do anything with this, so you can remove this.
>
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -EINVAL;
>
> The majority of controller drivers don't bother to check the return value
> here and just pass res into devm_ioremap_resource.
>
> > +
> > + base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > + if (IS_ERR(pcie->clk)) {
> > + dev_err(&pdev->dev, "could not get clock\n");
> > + pcie->clk = NULL;
> > + }
>
> Is this a good use-case for devm_clk_get_optional?
>
> > + pcie->base = base;
> > +
> > + ret = of_pci_get_max_link_speed(dn);
> > + pcie->gen = (ret < 0) ? 0 : ret;
>
> There is no checking that gen isn't too large here, given that we pass
> this into a register later we probably want to check it here.
>
> > +
> > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > +
> > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > + if (ret == 0)
> > + /* keep going, as we don't use this intr yet */
> > + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> > + else
> > + pcie->irq = ret;
>
> Given we don't use it yet, please remove it from this patch.
>
> > +
> > + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> > + &bridge->dma_ranges, NULL);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_prepare_enable(pcie->clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "could not enable clock\n");
> > + return ret;
> > + }
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + goto fail;
> > +
> > + bridge->dev.parent = &pdev->dev;
> > + bridge->busnr = 0;
> > + bridge->ops = &brcm_pcie_ops;
> > + bridge->sysdata = pcie;
> > + bridge->map_irq = of_irq_parse_and_map_pci;
> > + bridge->swizzle_irq = pci_common_swizzle;
> > +
> > + ret = pci_scan_root_bus_bridge(bridge);
> > + if (ret < 0) {
> > + dev_err(pcie->dev, "Scanning root bridge failed\n");
> > + goto fail;
> > + }
> > +
> > + pci_assign_unassigned_bus_resources(bridge->bus);
> > + list_for_each_entry(child, &bridge->bus->children, node)
> > + pcie_bus_configure_settings(child);
> > + pci_bus_add_devices(bridge->bus);
> > + platform_set_drvdata(pdev, pcie);
> > + pcie->root_bus = bridge->bus;
> > +
> > + return 0;
> > +
> > +fail:
> > + _brcm_pcie_remove(pcie);
> > + return ret;
> > +}
> > +
> > +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> > + .suspend_noirq = brcm_pcie_suspend,
> > + .resume_noirq = brcm_pcie_resume,
> > +};
> > +
> > +static struct platform_driver brcm_pcie_driver = {
> > + .probe = brcm_pcie_probe,
> > + .remove = brcm_pcie_remove,
> > + .driver = {
> > + .name = "brcm-pcie",
> > + .owner = THIS_MODULE,
> > + .of_match_table = brcm_pcie_match,
> > + .pm = &brcm_pcie_pm_ops,
> > + },
> > +};
> > +
> > +module_platform_driver(brcm_pcie_driver);
> > +
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
> > +MODULE_AUTHOR("Broadcom");
> > --
> > 2.23.0
> >
Hi Andrew,
thanks for taking the time to review this.
On Thu, 2019-11-07 at 15:00 +0000, Andrew Murray wrote:
> Thanks for the patch, some initial feedback below, though I will give it a
> more detailed review on your respin.
>
> On Wed, Nov 06, 2019 at 10:45:25PM +0100, Nicolas Saenz Julienne wrote:
> > From: Jim Quinlan <[email protected]>
> >
> > This commit adds the basic Broadcom STB PCIe controller. Missing is the
> > ability to process MSI. This functionality is added in a subsequent
> > commit.
> >
> > The PCIe block contains an MDIO interface. This is a local interface
> > only accessible by the PCIe controller. It cannot be used or shared
> > by any other HW. As such, the small amount of code for this
> > controller is included in this driver as there is little upside to put
> > it elsewhere.
> >
> > This is based on Jim's original submission[1] but adapted and tailored
> > specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> > the rest of the brcmstb family will soon follow once we get support for
> > multiple dma-ranges in dma/direct.
>
> This commit message is very informative and helpful, though I feel a lot
> of this isn't relevant for a commit message (especially as much of it is
> time based comments). Instead it would be better to simply describe what
> the patch does provide, and any additional helpful notes can be provided
> under the '---' after the signed off (which won't make it into git).
Ok noted
> > [1] https://patchwork.kernel.org/patch/10605959/
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > drivers/pci/controller/Kconfig | 12 +
> > drivers/pci/controller/Makefile | 1 +
> > drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> > 3 files changed, 986 insertions(+)
> > create mode 100644 drivers/pci/controller/pcie-brcmstb.c
> >
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index f5de9119e8d3..8b3aae91d8af 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -281,6 +281,18 @@ config VMD
> > To compile this driver as a module, choose M here: the
> > module will be called vmd.
> >
> > +config PCIE_BRCMSTB
> > + bool "Broadcom Brcmstb PCIe host controller"
> > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
>
> I can't see what ARCH_BRCMSTB adds here. Given this also depends
> on SOC_BRCMSTB. Are all of these depends really necessary?
You're right, too many unnecessary depends. I missed this. For now only
ARCH_BCM2835 will do. I'll clean it up.
> Also should the bool be "Broadcom STB PCIe host contoller" ?
I'd rather keep the STB mention as it's the overall platform this is aimed for
(and it's on the driver name), but for the sake of clarity I'll update it to
something the likes of: "Bradcom STB & Raspberry Pi 4 PCIe host
controller"
> > + depends on OF
> > + depends on SOC_BRCMSTB
> > + default ARCH_BRCMSTB || BMIPS_GENERIC
>
> Please also include COMPILE_TEST in here (look at the other controllers
> in the file). This helps improve testing coverage by compiling all drivers
> even if they can't be run.
OK
> > + help
> > + Say Y here to enable PCIe host controller support for
> > + Broadcom Settop Box SOCs. A Broadcom SOC will may have
>
> s/Settop/Set top/ or s/Settop/STB/?
Let's default to STB. I'll look around for more offenders.
> > + multiple host controllers as opposed to a single host
> > + controller with multiple ports.
>
> I'm sure many other SOCs may have multiple controllers instead of one
> with multiple ports. I'm not sure what value this adds here. It's
> always better to describe enough information so the user can determine
> if this option will enable something they want on their hardware.
Agree, I'll remove that sentence.
> > +
> > config PCI_HYPERV_INTERFACE
> > tristate "Hyper-V PCI Interface"
> > depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> > diff --git a/drivers/pci/controller/Makefile
> > b/drivers/pci/controller/Makefile
> > index a2a22c9d91af..3fc0b0cf5b5b 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > obj-$(CONFIG_VMD) += vmd.o
> > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > obj-y += dwc/
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c
> > b/drivers/pci/controller/pcie-brcmstb.c
> > new file mode 100644
> > index 000000000000..880ec11d06a1
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -0,0 +1,973 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* Copyright (C) 2009 - 2019 Broadcom */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/compiler.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/ioport.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/kernel.h>
> > +#include <linux/list.h>
> > +#include <linux/log2.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pci.h>
> > +#include <linux/printk.h>
> > +#include <linux/sizes.h>
> > +#include <linux/slab.h>
> > +#include <linux/string.h>
> > +#include <linux/types.h>
> > +
> > +#include "../pci.h"
>
> Is this last include needed? Sometimes controller drivers suffer from copy and
> paste and this is often included when it isn't needed.
It's needed in order to call of_pci_get_max_link_speed().
> > +
> > +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> > +#define BRCM_PCIE_CAP_REGS 0x00ac
> > +
> > +/*
> > + * Broadcom Settop Box PCIe Register Offsets. The names are from
> > + * the chip's RDB and we use them here so that a script can correlate
> > + * this code and the RDB to prevent discrepancies.
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> > +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > +#define PCIE_MISC_MISC_CTRL 0x4008
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > +#define PCIE_MISC_PCIE_CTRL 0x4064
> > +#define PCIE_MISC_PCIE_STATUS 0x4068
> > +#define PCIE_MISC_REVISION 0x406c
>
> PCIE_MISC_REVISION can be removed as it shouldn't be needed
See my comment below regarding revision.
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > +#define PCIE_INTR2_CPU_BASE 0x4300
> > +
> > +/*
> > + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> > + * names are from the chip's RDB and we use them here so that a script
> > + * can correlate this code and the RDB to prevent discrepancies.
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK
> > 0xc
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT
> > 0x2
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> > +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> > +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff000
> > 00
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x080000
> > 00
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> > +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
>
> Most of the above aren't used anywhere, please remove them.
OK
> > +
> > +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> > +#define BRCM_MAX_SCB 0x4
> > +
> > +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
>
> These two aren't used.
As with the revision, this is only used once MSI is introduced, on the next
patch. I'll move it there if you prefer it.
> > +
> > +#define BURST_SIZE_128 0
> > +#define BURST_SIZE_256 1
> > +#define BURST_SIZE_512 2
> > +
> > +/* Offsets from PCIE_INTR2_CPU_BASE */
> > +#define STATUS 0x0
> > +#define SET 0x4
> > +#define CLR 0x8
> > +#define MASK_STATUS 0xc
> > +#define MASK_SET 0x10
> > +#define MASK_CLR 0x14
>
> Some of the above are not used anywhere.
OK
> > +
> > +#define PCIE_BUSNUM_SHIFT 20
> > +#define PCIE_SLOT_SHIFT 15
> > +#define PCIE_FUNC_SHIFT 12
> > +
> > +#if defined(__BIG_ENDIAN)
> > +#define DATA_ENDIAN 2 /* PCIe->DDR inbound
traffic
> > */
> > +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound
> > traffic */
> > +#else
> > +#define DATA_ENDIAN 0
> > +#define MMIO_ENDIAN 0
> > +#endif
> > +
> > +#define MDIO_PORT0 0x0
> > +#define MDIO_DATA_MASK 0x7fffffff
> > +#define MDIO_DATA_SHIFT 0x0
> > +#define MDIO_PORT_MASK 0xf0000
> > +#define MDIO_PORT_SHIFT 0x16
> > +#define MDIO_REGAD_MASK 0xffff
> > +#define MDIO_REGAD_SHIFT 0x0
> > +#define MDIO_CMD_MASK 0xfff00000
> > +#define MDIO_CMD_SHIFT 0x14
> > +#define MDIO_CMD_READ 0x1
> > +#define MDIO_CMD_WRITE 0x0
> > +#define MDIO_DATA_DONE_MASK 0x80000000
> > +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1
> > : 0)
> > +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0
> > : 1)
> > +#define SSC_REGS_ADDR 0x1100
> > +#define SET_ADDR_OFFSET 0x1f
> > +#define SSC_CNTL_OFFSET 0x2
> > +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> > +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> > +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> > +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> > +#define SSC_STATUS_OFFSET 0x1
> > +#define SSC_STATUS_SSC_MASK 0x400
> > +#define SSC_STATUS_SSC_SHIFT 0xa
> > +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> > +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> > +
> > +#define IDX_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> > +#define DATA_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_DATA])
> > +#define PCIE_RGR1_SW_INIT_1(pcie) \
> > + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> > +
> > +enum {
> > + RGR1_SW_INIT_1,
> > + EXT_CFG_INDEX,
> > + EXT_CFG_DATA,
> > +};
> > +
> > +enum {
> > + RGR1_SW_INIT_1_INIT_MASK,
> > + RGR1_SW_INIT_1_INIT_SHIFT,
> > + RGR1_SW_INIT_1_PERST_MASK,
> > + RGR1_SW_INIT_1_PERST_SHIFT,
> > +};
> > +
> > +enum pcie_type {
> > + BCM2711,
> > +};
> > +
> > +struct brcm_window {
> > + dma_addr_t pcie_addr;
> > + phys_addr_t cpu_addr;
> > + dma_addr_t size;
> > +};
> > +
> > +/* Internal PCIe Host Controller Information.*/
> > +struct brcm_pcie {
> > + struct device *dev;
> > + void __iomem *base;
> > + int irq;
>
> 'irq' isn't used and can be removed.
Yes
> > + struct clk *clk;
> > + struct pci_bus *root_bus;
> > + struct device_node *dn;
> > + int id;
>
> 'id' isn't used and can be removed.
Yes
> > + bool suspended;
> > + bool ssc;
> > + int gen;
> > + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > + unsigned int rev;
>
> 'rev' isn't used and can be removed.
It's used by the MSI code further down the line. If you want I'll move it to
that patch.
> > + const int *reg_offsets;
> > + const int *reg_field_info;
> > + enum pcie_type type;
> > +};
> > +
> > +struct pcie_cfg_data {
> > + const int *reg_field_info;
> > + const int *offsets;
> > + const enum pcie_type type;
> > +};
> > +
> > +static const int pcie_reg_field_info[] = {
> > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> > +};
> > +
> > +static const int pcie_offset_bcm2711[] = {
> > + [RGR1_SW_INIT_1] = 0x9210,
> > + [EXT_CFG_INDEX] = 0x9000,
> > + [EXT_CFG_DATA] = 0x8000,
> > +};
> > +
> > +static const struct pcie_cfg_data bcm2711_cfg = {
> > + .reg_field_info = pcie_reg_field_info,
> > + .offsets = pcie_offset_bcm2711,
> > + .type = BCM2711,
> > +};
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
> > devfn,
> > + int where);
> > +
> > +static struct pci_ops brcm_pcie_ops = {
> > + .map_bus = brcm_pcie_map_conf,
> > + .read = pci_generic_config_read,
> > + .write = pci_generic_config_write,
> > +};
> > +
> > +#define bcm_readl(a) readl(a)
> > +#define bcm_writel(d, a) writel(d, a)
> > +#define bcm_readw(a) readw(a)
> > +#define bcm_writew(d, a) writew(d, a)
>
> Is there much value in these macros?
Yes, once we introduce MIPS users, they'll need to use __raw_write*(). It'll
make the patch simpler.
> > +
> > +/* These macros extract/insert fields to host controller's register set. */
> > +#define RD_FLD(base, reg, field) \
> > + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> > +#define WR_FLD(base, reg, field, val) \
> > + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> > +#define WR_FLD_RB(base, reg, field, val) \
> > + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> > + reg##_##field##_SHIFT, val)
> > +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> > + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> > + reg##_##field##_SHIFT, val)
> > +#define EXTRACT_FIELD(val, reg, field) \
> > + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> > +#define INSERT_FIELD(val, reg, field, field_val) \
> > + (((val) & ~reg##_##field##_MASK) | \
> > + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> > +
> > +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> > +{
> > + return (bcm_readl(p) & mask) >> shift;
> > +}
> > +
> > +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + u32 reg = bcm_readl(p);
> > +
> > + reg = (reg & ~mask) | ((val << shift) & mask);
> > + bcm_writel(reg, p);
> > +}
> > +
> > +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + wr_fld(p, mask, shift, val);
> > + (void)bcm_readl(p);
> > +}
> > +
> > +static const char *link_speed_to_str(int s)
> > +{
> > + switch (s) {
> > + case 1:
> > + return "2.5";
> > + case 2:
> > + return "5.0";
> > + case 3:
> > + return "8.0";
> > + default:
> > + break;
> > + }
> > + return "???";
> > +}
> > +
> > +/*
> > + * The roundup_pow_of_two() from log2.h invokes
> > + * __roundup_pow_of_two(unsigned long), but we really need a
> > + * such a function to take a native u64 since unsigned long
> > + * is 32 bits on some configurations. So we provide this helper
> > + * function below.
> > + */
> > +static u64 roundup_pow_of_two_64(u64 n)
> > +{
> > + return 1ULL << fls64(n - 1);
> > +}
>
> Given that you use this in one place and that it is a single line, I'd
> suggest you just drop this function. Alternatively if you wanted to add
> this function to log2.h then you already have a bunch of users ready to
> be migrated to it:
>
> $ git grep "<<
> fls64"
> arch/sparc/mm/init_64.c: m_end += pa_start & ~((1ul << fls64(m_mask)) -
> 1);
> drivers/net/ethernet/mellanox/mlx4/en_clock.c: u64 max_val_cycles_rounded =
> 1ULL << fls64(max_val_cycles - 1);
> drivers/pci/controller/pcie-cadence-ep.c: sz = 1ULL << fls64(sz - 1);
> drivers/pci/controller/pcie-cadence.c: u64 sz = 1ULL << fls64(size - 1);
> drivers/pci/controller/pcie-rockchip-ep.c: u64 sz = 1ULL << fls64(size -
> 1);
> drivers/pci/controller/pcie-rockchip-ep.c: sz = 1ULL << fls64(sz - 1);
I'll add it to log2.h
> > +
> > +/*
> > + * This is to convert the size of the inbound "BAR" region to the
> > + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> > + */
> > +int encode_ibar_size(u64 size)
> > +{
> > + int log2_in = ilog2(size);
> > +
> > + if (log2_in >= 12 && log2_in <= 15)
> > + /* Covers 4KB to 32KB (inclusive) */
> > + return (log2_in - 12) + 0x1c;
> > + else if (log2_in >= 16 && log2_in <= 37)
> > + /* Covers 64KB to 32GB, (inclusive) */
>
> 2^37 != 32GB?
I picked up Jim's comment.
> > + return log2_in - 15;
> > + /* Something is awry so disable */
> > + return 0;
> > +}
> > +
> > +static u32 mdio_form_pkt(int port, int regad, int cmd)
> > +{
> > + u32 pkt = 0;
> > +
> > + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> > + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> > + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> > +
> > + return pkt;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + }
> > +
> > + return MDIO_RD_DONE(data)
> > + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> > + : -EIO;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> > + base + PCIE_RC_DL_MDIO_WR_DATA);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + }
> > +
> > + return MDIO_WT_DONE(data) ? 0 : -EIO;
> > +}
> > +
> > +/*
> > + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> > + * return value indicates error.
> > + */
> > +static int set_ssc(void __iomem *base)
>
> Please prefix this with brcm_pcie_ (and other similar occurances)
>
OK
> > +{
> > + int tmp;
> > + u16 wrdata;
> > + int pll, ssc;
> > +
> > + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> > + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> > + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + usleep_range(1000, 2000);
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> > + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> > +
> > + return (ssc && pll) ? 0 : -EIO;
> > +}
> > +
> > +/* Limits operation to a specific generation (1, 2, or 3) */
> > +static void set_gen(void __iomem *base, int gen)
> > +{
> > + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > +
> > + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> > + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > +
> > + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> > + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > +}
> > +
> > +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> > + unsigned int win, phys_addr_t cpu_addr,
> > + dma_addr_t pcie_addr, dma_addr_t size)
> > +{
> > + void __iomem *base = pcie->base;
> > + phys_addr_t cpu_addr_mb, limit_addr_mb;
> > + u32 tmp;
> > +
> > + /* Set the base of the pcie_addr window */
> > + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> > + bcm_writel(upper_32_bits(pcie_addr),
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> > +
> > + cpu_addr_mb = cpu_addr >> 20;
> > + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> > +
> > + /* Write the addr base low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + BASE, cpu_addr_mb);
> > + /* Write the addr limit low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + LIMIT, limit_addr_mb);
> > +
> > + /* Write the cpu addr high register */
> > + tmp = (u32)(cpu_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> > + BASE, tmp);
> > + /* Write the cpu limit high register */
> > + tmp = (u32)(limit_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> > + LIMIT, tmp);
> > +}
> > +
> > +/* Configuration space read/write support */
> > +static int cfg_index(int busnr, int devfn, int reg)
> > +{
> > + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> > + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> > + | (busnr << PCIE_BUSNUM_SHIFT)
> > + | (reg & ~3);
> > +}
> > +
> > +/* The controller is capable of serving in both RC and EP roles */
> > +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > +
> > + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> > +}
> > +
> > +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> > + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> > +
> > + return (dla && plu) ? true : false;
> > +}
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
> > devfn,
> > + int where)
> > +{
> > + struct brcm_pcie *pcie = bus->sysdata;
> > + void __iomem *base = pcie->base;
> > + int idx;
> > +
> > + /* Accesses to the RC go right to the RC registers if slot==0 */
> > + if (pci_is_root_bus(bus))
> > + return PCI_SLOT(devfn) ? NULL : base + where;
> > +
> > + /* For devices, write to the config space index register */
> > + idx = cfg_index(bus->number, devfn, 0);
> > + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> > + return base + DATA_ADDR(pcie) + where;
> > +}
> > +
> > +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> > + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > +
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> > +}
> > +
> > +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> > + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> > + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> > +}
> > +
> > +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie
> > *pcie,
> > + u64 *rc_bar2_size,
> > + u64 *rc_bar2_offset)
> > +{
> > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > + struct device *dev = pcie->dev;
> > + struct resource_entry *entry;
> > + u64 total_mem_size = 0;
> > +
> > + *rc_bar2_offset = -1;
> > +
> > + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> > + /*
> > + * We're promissed the RC will provide a contiguous view of
>
> s/promissed/promised/
Corrected
> > + * memory to downstream devices. We can then infer the
> > + * rc_bar2_offset from the lower avaiable dma-range offset.
> > + */
> > + if (entry->offset < *rc_bar2_offset)
> > + *rc_bar2_offset = entry->offset;
> > +
> > + total_mem_size += entry->res->end - entry->res->start + 1;
> > + }
> > +
> > + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> > +
> > + /*
> > + * Validate the results:
> > + *
> > + * The PCIe host controller by design must set the inbound viewport to
> > + * be a contiguous arrangement of all of the system's memory. In
> > + * addition, its size mut be a power of two. To further complicate
> > + * matters, the viewport must start on a pcie-address that is aligned
> > + * on a multiple of its size. If a portion of the viewport does not
> > + * represent system memory -- e.g. 3GB of memory requires a 4GB
> > + * viewport -- we can map the outbound memory in or after 3GB and even
> > + * though the viewport will overlap the outbound memory the controller
> > + * will know to send outbound memory downstream and everything else
> > + * upstream.
> > + *
> > + * For example:
> > + *
> > + * - The best-case scenario, memory up to 3GB, is to place the inbound
> > + * region in the first 4GB of pcie-space, as some legacy devices can
> > + * only address 32bits. We would also like to put the MSI under 4GB
> > + * as well, since some devices require a 32bit MSI target address.
> > + *
> > + * - If the system memory is 4GB or larger we cannot start the inbound
> > + * region at location 0 (since we have to allow some space for
> > + * outbound memory @ 3GB). So instead it will start at the 1x
> > + * multiple of its size
> > + */
> > + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> > + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> > + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off
> > 0x%llx\n",
> > + *rc_bar2_size, *rc_bar2_offset);
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > +{
> > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > + u64 rc_bar2_offset, rc_bar2_size;
> > + void __iomem *base = pcie->base;
> > + struct resource_entry *entry;
> > + unsigned int scb_size_val;
> > + struct resource *res;
> > + int num_out_wins = 0;
> > + u32 tmp;
> > + int i, j, ret, limit;
> > + u16 nlw, cls, lnksta;
> > + bool ssc_good = false;
> > + struct device *dev = pcie->dev;
> > +
> > + /* Reset the bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +
> > + usleep_range(100, 200);
> > +
> > + /* Take the bridge out of reset */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* Wait for SerDes to be stable */
> > + usleep_range(100, 200);
> > +
> > + /* Grab the PCIe hw revision number */
> > + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> > + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
>
> This isn't used anywhere
It's used by MSI further down the line.
> > +
> > + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> > + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> > + BURST_SIZE_128);
> > + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> > +
> > + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> > + &rc_bar2_offset);
> > + if (ret)
> > + return ret;
> > +
> > + tmp = lower_32_bits(rc_bar2_offset);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> > + encode_ibar_size(rc_bar2_size));
> > + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> > + bcm_writel(upper_32_bits(rc_bar2_offset),
> > + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> > +
> > + scb_size_val = rc_bar2_size ?
> > + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> > +
> > + /* disable the PCIe->GISB memory window (RC_BAR1) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> > +
> > + /* disable the PCIe->SCB memory window (RC_BAR3) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> > +
> > + if (!pcie->suspended) {
> > + /* clear any interrupts we find on boot */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> > + }
> > +
> > + /* Mask all interrupts since we are not handling any yet */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > +
> > + if (pcie->gen)
> > + set_gen(base, pcie->gen);
> > +
> > + /* Unassert the fundamental reset */
> > + brcm_pcie_perst_set(pcie, 0);
> > +
> > + /*
> > + * Give the RC/EP time to wake up, before trying to configure RC.
> > + * Intermittently check status for link-up, up to a total of 100ms
> > + * when we don't know if the device is there, and up to 1000ms if
> > + * we do know the device is there.
> > + */
> > + limit = pcie->suspended ? 1000 : 100;
> > + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> > + j += i, i = i * 2)
> > + msleep(i + j > limit ? limit - j : i);
>
> Does it need to be this complex? Also waiting a second during resume seems
> like a long delay.
I'll simplify it. I didn't want to change it as I assumed this is needed on
some odd STB device. We'll deal with it once we enable it.
> > +
> > + if (!brcm_pcie_link_up(pcie)) {
> > + dev_info(dev, "link down\n");
> > + return -ENODEV;
> > + }
> > +
> > + if (!brcm_pcie_rc_mode(pcie)) {
> > + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> > + return -EINVAL;
> > + }
> > +
> > + resource_list_for_each_entry(entry, &bridge->windows) {
> > + res = entry->res;
> > +
> > + if (resource_type(res) != IORESOURCE_MEM)
> > + continue;
> > +
> > + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> > + dev_err(pcie->dev, "too many outbound wins\n");
> > + return -EINVAL;
> > + }
> > +
> > + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> > + res->start - entry->offset,
> > + res->end - res->start + 1);
> > + num_out_wins++;
> > + }
> > +
> > + /*
> > + * For config space accesses on the RC, show the right class for
> > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > + */
> > + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> > +
> > + if (pcie->ssc) {
> > + ret = set_ssc(base);
> > + if (ret == 0)
> > + ssc_good = true;
> > + else
> > + dev_err(dev, "failed attempt to enter ssc mode\n");
> > + }
> > +
> > + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> > + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> > + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> > + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> > +
> > + /* PCIe->SCB endian mode for BAR */
> > + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> > + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> > + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> > +
> > + /*
> > + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> > + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> > + */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> > +
> > + return 0;
> > +}
> > +
> > +/* L23 is a low-power PCIe link state */
> > +static void enter_l23(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + int l23, i;
> > +
> > + /* assert request for L23 */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > +
> > + /* Wait up to 30 msec for L23 */
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + for (i = 0; i < 15 && !l23; i++) {
> > + usleep_range(2000, 2400);
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + }
> > +
> > + if (!l23)
> > + dev_err(pcie->dev, "failed to enter L23\n");
> > +}
> > +
> > +static void turn_off(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > +
> > + if (brcm_pcie_link_up(pcie))
> > + enter_l23(pcie);
> > + /* Assert fundamental reset */
> > + brcm_pcie_perst_set(pcie, 1);
> > + /* Deassert request for L23 in case it was asserted */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > + /* Turn off SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > + /* Shutdown PCIe bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +}
> > +
> > +static int brcm_pcie_suspend(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > +
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + pcie->suspended = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_resume(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > + void __iomem *base;
> > + int ret;
> > +
> > + base = pcie->base;
> > + clk_prepare_enable(pcie->clk);
> > +
> > + /* Take bridge out of reset so we can access the SerDes reg */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + /* Turn on SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* Wait for SerDes to be stable */
> > + usleep_range(100, 200);
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + return ret;
> > +
> > + pcie->suspended = false;
> > +
> > + return 0;
> > +}
> > +
> > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>
> I don't see the value in the first underscore here.
It's value is that the real brcm_pcie_remove() and the probe failure cleanup
routine share code. It saves some code duplication, that said I have no strong
feelings about it.
> > +{
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + clk_put(pcie->clk);
> > +}
> > +
> > +static int brcm_pcie_remove(struct platform_device *pdev)
> > +{
> > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > +
> > + pci_stop_root_bus(pcie->root_bus);
> > + pci_remove_root_bus(pcie->root_bus);
> > + _brcm_pcie_remove(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id brcm_pcie_match[] = {
> > + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > +
> > +static int brcm_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *dn = pdev->dev.of_node;
> > + const struct of_device_id *of_id;
> > + const struct pcie_cfg_data *data;
> > + struct resource *res;
> > + int ret;
> > + struct brcm_pcie *pcie;
> > + void __iomem *base;
> > + struct pci_host_bridge *bridge;
> > + struct pci_bus *child;
> > +
> > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > + if (!bridge)
> > + return -ENOMEM;
> > +
> > + pcie = pci_host_bridge_priv(bridge);
> > +
> > + of_id = of_match_node(brcm_pcie_match, dn);
> > + if (!of_id) {
> > + dev_err(&pdev->dev, "failed to look up compatible string\n");
> > + return -EINVAL;
> > + }
> > +
> > + data = of_id->data;
>
> Can you replace the above (from of_match_node to here) with the following?
>
> data = of_device_get_match_data(pdev->dev)
Yes, way cleaner.
> > + pcie->reg_offsets = data->offsets;
> > + pcie->reg_field_info = data->reg_field_info;
> > + pcie->type = data->type;
> > + pcie->dn = dn;
> > + pcie->dev = &pdev->dev;
> > +
> > + /* We use the domain number as our controller number */
> > + pcie->id = of_get_pci_domain_nr(dn);
> > + if (pcie->id < 0)
> > + return pcie->id;
>
> We don't do anything with this, so you can remove this.
Deleted.
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -EINVAL;
>
> The majority of controller drivers don't bother to check the return value
> here and just pass res into devm_ioremap_resource.
Ok.
> > +
> > + base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > + if (IS_ERR(pcie->clk)) {
> > + dev_err(&pdev->dev, "could not get clock\n");
> > + pcie->clk = NULL;
> > + }
>
> Is this a good use-case for devm_clk_get_optional?
Yes.
> > + pcie->base = base;
> > +
> > + ret = of_pci_get_max_link_speed(dn);
> > + pcie->gen = (ret < 0) ? 0 : ret;
>
> There is no checking that gen isn't too large here, given that we pass
> this into a register later we probably want to check it here.
This is checked by of_pci_get_max_link_speed() internally:
if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
max_link_speed > 4)
return -EINVAL;
return max_link_speed;
> > +
> > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > +
> > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > + if (ret == 0)
> > + /* keep going, as we don't use this intr yet */
> > + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> > + else
> > + pcie->irq = ret;
>
> Given we don't use it yet, please remove it from this patch.
OK
Regards,
Nicolas
Hi Nicolas,
please move this patch behind the driver patches, which is the better order.
Am 06.11.19 um 22:45 schrieb Nicolas Saenz Julienne:
> This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies
> XHCI USB 3.0 controller.
AFAIU this only applies to the Raspberry Pi 4, since the VIA is outside
of the SoC.
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> index a9d84e28f245..c7b2e7b57da6 100644
> --- a/arch/arm/boot/dts/bcm2711.dtsi
> +++ b/arch/arm/boot/dts/bcm2711.dtsi
> @@ -288,6 +288,53 @@
> arm,cpu-registers-not-fw-configured;
> };
>
> + scb {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
> + <0x6 0x00000000 0x6 0x00000000 0x40000000>;
> +
> + pcie_0: pcie@7d500000 {
> + compatible = "brcm,bcm2711-pcie";
> + reg = <0x0 0x7d500000 0x9310>;
> + msi-controller;
> + msi-parent = <&pcie_0>;
> + #address-cells = <3>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + linux,pci-domain = <0>;
> + brcm,enable-ssc;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pcie", "msi";
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
> + IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 2 &gicv2 GIC_SPI 144
> + IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 3 &gicv2 GIC_SPI 145
> + IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 4 &gicv2 GIC_SPI 146
> + IRQ_TYPE_LEVEL_HIGH>;
> +
> + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
> + 0x0 0x04000000>;
> + /*
> + * The wrapper around the PCIe block has a bug
> + * preventing it from accessing beyond the first 3GB of
> + * memory. As the bus DMA mask is rounded up to the
> + * closest power of two of the dma-range size, we're
> + * forced to set the limit at 2GB. This can be
> + * harmlessly changed in the future once the DMA code
> + * handles non power of two DMA limits.
> + */
> + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
> + 0x0 0x80000000>;
In case this bug will ever be fixed, do you see this as a future proof
practical solution?
> + };
> + };
> +
> cpus: cpus {
> #address-cells = <1>;
> #size-cells = <0>;
Hi Nicolas,
Am 06.11.19 um 22:45 schrieb Nicolas Saenz Julienne:
> From: Jim Quinlan <[email protected]>
>
> This commit adds the basic Broadcom STB PCIe controller. Missing is the
> ability to process MSI. This functionality is added in a subsequent
> commit.
>
> The PCIe block contains an MDIO interface. This is a local interface
> only accessible by the PCIe controller. It cannot be used or shared
> by any other HW. As such, the small amount of code for this
> controller is included in this driver as there is little upside to put
> it elsewhere.
>
> This is based on Jim's original submission[1] but adapted and tailored
> specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> the rest of the brcmstb family will soon follow once we get support for
> multiple dma-ranges in dma/direct.
>
> [1] https://patchwork.kernel.org/patch/10605959/
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> drivers/pci/controller/Kconfig | 12 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> 3 files changed, 986 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-brcmstb.c
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index f5de9119e8d3..8b3aae91d8af 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -281,6 +281,18 @@ config VMD
> To compile this driver as a module, choose M here: the
> module will be called vmd.
>
> +config PCIE_BRCMSTB
> + bool "Broadcom Brcmstb PCIe host controller"
looking at the driver suggests me a tristate instead of bool.
> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
please add ARCH_BCM2835 for the Raspberry Pi 4
> + depends on OF
> + depends on SOC_BRCMSTB
Why is this needed?
> + default ARCH_BRCMSTB || BMIPS_GENERIC
also this needs ARCH_BCM2835
> + help
> + Say Y here to enable PCIe host controller support for
> + Broadcom Settop Box SOCs. A Broadcom SOC will may have
> + multiple host controllers as opposed to a single host
> + controller with multiple ports.
> +
> config PCI_HYPERV_INTERFACE
> tristate "Hyper-V PCI Interface"
> depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index a2a22c9d91af..3fc0b0cf5b5b 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> obj-y += dwc/
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> new file mode 100644
> index 000000000000..880ec11d06a1
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -0,0 +1,973 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright (C) 2009 - 2019 Broadcom */
> +
> +#include <linux/clk.h>
> +#include <linux/compiler.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/log2.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/printk.h>
> +#include <linux/sizes.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +
> +#include "../pci.h"
> +
> ...
>
> +
> +/* L23 is a low-power PCIe link state */
> +static void enter_l23(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + int l23, i;
> +
> + /* assert request for L23 */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> +
> + /* Wait up to 30 msec for L23 */
36 msec?
> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> + for (i = 0; i < 15 && !l23; i++) {
> + usleep_range(2000, 2400);
> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> + }
> +
> + if (!l23)
> + dev_err(pcie->dev, "failed to enter L23\n");
I think most user don't know anything about L23.
How about:
failed to enter low-power link state
> +}
> +
> +static void turn_off(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> +
> + if (brcm_pcie_link_up(pcie))
> + enter_l23(pcie);
> + /* Assert fundamental reset */
> + brcm_pcie_perst_set(pcie, 1);
> + /* Deassert request for L23 in case it was asserted */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> + /* Turn off SerDes */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> + /* Shutdown PCIe bridge */
> + brcm_pcie_bridge_sw_init_set(pcie, 1);
> +}
> +
> +static int brcm_pcie_suspend(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> +
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + pcie->suspended = true;
> +
> + return 0;
> +}
> +
> +static int brcm_pcie_resume(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> + void __iomem *base;
> + int ret;
> +
> + base = pcie->base;
> + clk_prepare_enable(pcie->clk);
> +
> + /* Take bridge out of reset so we can access the SerDes reg */
> + brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> + /* Turn on SerDes */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> + /* Wait for SerDes to be stable */
> + usleep_range(100, 200);
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + return ret;
> +
> + pcie->suspended = false;
> +
> + return 0;
> +}
> +
> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> +{
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + clk_put(pcie->clk);
> +}
> +
> +static int brcm_pcie_remove(struct platform_device *pdev)
> +{
> + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> +
> + pci_stop_root_bus(pcie->root_bus);
> + pci_remove_root_bus(pcie->root_bus);
> + _brcm_pcie_remove(pcie);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id brcm_pcie_match[] = {
> + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> +
> +static int brcm_pcie_probe(struct platform_device *pdev)
> +{
> + struct device_node *dn = pdev->dev.of_node;
> + const struct of_device_id *of_id;
> + const struct pcie_cfg_data *data;
> + struct resource *res;
> + int ret;
> + struct brcm_pcie *pcie;
> + void __iomem *base;
> + struct pci_host_bridge *bridge;
> + struct pci_bus *child;
> +
> + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> + if (!bridge)
> + return -ENOMEM;
> +
> + pcie = pci_host_bridge_priv(bridge);
> +
> + of_id = of_match_node(brcm_pcie_match, dn);
> + if (!of_id) {
> + dev_err(&pdev->dev, "failed to look up compatible string\n");
> + return -EINVAL;
> + }
> +
> + data = of_id->data;
> + pcie->reg_offsets = data->offsets;
> + pcie->reg_field_info = data->reg_field_info;
> + pcie->type = data->type;
> + pcie->dn = dn;
> + pcie->dev = &pdev->dev;
> +
> + /* We use the domain number as our controller number */
> + pcie->id = of_get_pci_domain_nr(dn);
> + if (pcie->id < 0)
> + return pcie->id;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -EINVAL;
> +
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> + if (IS_ERR(pcie->clk)) {
we should handle EPROBE_DEFER here
> + dev_err(&pdev->dev, "could not get clock\n");
> + pcie->clk = NULL;
> + }
> + pcie->base = base;
> +
> + ret = of_pci_get_max_link_speed(dn);
> + pcie->gen = (ret < 0) ? 0 : ret;
> +
> + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> +
> + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> + if (ret == 0)
> + /* keep going, as we don't use this intr yet */
> + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> + else
> + pcie->irq = ret;
> +
> + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> + &bridge->dma_ranges, NULL);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(pcie->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "could not enable clock\n");
> + return ret;
> + }
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + goto fail;
> +
> + bridge->dev.parent = &pdev->dev;
> + bridge->busnr = 0;
> + bridge->ops = &brcm_pcie_ops;
> + bridge->sysdata = pcie;
> + bridge->map_irq = of_irq_parse_and_map_pci;
> + bridge->swizzle_irq = pci_common_swizzle;
> +
> + ret = pci_scan_root_bus_bridge(bridge);
> + if (ret < 0) {
> + dev_err(pcie->dev, "Scanning root bridge failed\n");
> + goto fail;
> + }
> +
> + pci_assign_unassigned_bus_resources(bridge->bus);
> + list_for_each_entry(child, &bridge->bus->children, node)
> + pcie_bus_configure_settings(child);
> + pci_bus_add_devices(bridge->bus);
> + platform_set_drvdata(pdev, pcie);
> + pcie->root_bus = bridge->bus;
> +
> + return 0;
> +
> +fail:
> + _brcm_pcie_remove(pcie);
> + return ret;
> +}
> +
> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> + .suspend_noirq = brcm_pcie_suspend,
> + .resume_noirq = brcm_pcie_resume,
> +};
> +
> +static struct platform_driver brcm_pcie_driver = {
> + .probe = brcm_pcie_probe,
> + .remove = brcm_pcie_remove,
> + .driver = {
> + .name = "brcm-pcie",
> + .owner = THIS_MODULE,
This is already done by module_platform_driver
> + .of_match_table = brcm_pcie_match,
> + .pm = &brcm_pcie_pm_ops,
> + },
> +};
> +
> +module_platform_driver(brcm_pcie_driver);
> +
> +MODULE_LICENSE("GPL v2");
This is a mismatch to the SPDX (GPL 2 and higher), because this says GPL
v2 only
Thanks
Stefan
> +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
> +MODULE_AUTHOR("Broadcom");
On Thu, 2019-11-07 at 18:44 +0100, Stefan Wahren wrote:
> Hi Nicolas,
>
> please move this patch behind the driver patches, which is the better order.
>
> Am 06.11.19 um 22:45 schrieb Nicolas Saenz Julienne:
> > This enables bcm2711's PCIe bus, wich is hardwired to a VIA Technologies
> > XHCI USB 3.0 controller.
> AFAIU this only applies to the Raspberry Pi 4, since the VIA is outside
> of the SoC.
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > arch/arm/boot/dts/bcm2711.dtsi | 47 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 47 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> > index a9d84e28f245..c7b2e7b57da6 100644
> > --- a/arch/arm/boot/dts/bcm2711.dtsi
> > +++ b/arch/arm/boot/dts/bcm2711.dtsi
> > @@ -288,6 +288,53 @@
> > arm,cpu-registers-not-fw-configured;
> > };
> >
> > + scb {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > +
> > + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
> > + <0x6 0x00000000 0x6 0x00000000 0x40000000>;
> > +
> > + pcie_0: pcie@7d500000 {
> > + compatible = "brcm,bcm2711-pcie";
> > + reg = <0x0 0x7d500000 0x9310>;
> > + msi-controller;
> > + msi-parent = <&pcie_0>;
> > + #address-cells = <3>;
> > + #interrupt-cells = <1>;
> > + #size-cells = <2>;
> > + linux,pci-domain = <0>;
> > + brcm,enable-ssc;
> > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pcie", "msi";
> > + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
> > + IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 2 &gicv2 GIC_SPI 144
> > + IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 3 &gicv2 GIC_SPI 145
> > + IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 4 &gicv2 GIC_SPI 146
> > + IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
> > + 0x0 0x04000000>;
> > + /*
> > + * The wrapper around the PCIe block has a bug
> > + * preventing it from accessing beyond the first 3GB of
> > + * memory. As the bus DMA mask is rounded up to the
> > + * closest power of two of the dma-range size, we're
> > + * forced to set the limit at 2GB. This can be
> > + * harmlessly changed in the future once the DMA code
> > + * handles non power of two DMA limits.
> > + */
> > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
> > + 0x0 0x80000000>;
> In case this bug will ever be fixed, do you see this as a future proof
> practical solution?
The dts I provide should work on any bcm2711 (fixed or not) and any future
kernel, with the downside that we'll perform some unnecessary buffer bouncing.
If we were able to address the whole 32bit address space on some future bcm2711
we'd be forced to update the dma-ranges in the bootloader based on the SoC
revision.
The driver should work with any sensible dma-range, I even did a test emulating
the 4GB inbound memory setup.
Regards,
Nicolas
On Thu, Nov 07, 2019 at 11:12:58AM -0500, Jim Quinlan wrote:
> On Thu, Nov 7, 2019 at 10:05 AM Andrew Murray <[email protected]> wrote:
> >
> > Thanks for the patch, some initial feedback below, though I will give it a
> > more detailed review on your respin.
> >
> > On Wed, Nov 06, 2019 at 10:45:25PM +0100, Nicolas Saenz Julienne wrote:
> > > From: Jim Quinlan <[email protected]>
> > >
> > > This commit adds the basic Broadcom STB PCIe controller. Missing is the
> > > ability to process MSI. This functionality is added in a subsequent
> > > commit.
> > >
> > > The PCIe block contains an MDIO interface. This is a local interface
> > > only accessible by the PCIe controller. It cannot be used or shared
> > > by any other HW. As such, the small amount of code for this
> > > controller is included in this driver as there is little upside to put
> > > it elsewhere.
> > >
> > > This is based on Jim's original submission[1] but adapted and tailored
> > > specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> > > the rest of the brcmstb family will soon follow once we get support for
> > > multiple dma-ranges in dma/direct.
> >
> > This commit message is very informative and helpful, though I feel a lot
> > of this isn't relevant for a commit message (especially as much of it is
> > time based comments). Instead it would be better to simply describe what
> > the patch does provide, and any additional helpful notes can be provided
> > under the '---' after the signed off (which won't make it into git).
> >
> > >
> > > [1] https://patchwork.kernel.org/patch/10605959/
> > >
> > > Signed-off-by: Jim Quinlan <[email protected]>
> > > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > > ---
> > > drivers/pci/controller/Kconfig | 12 +
> > > drivers/pci/controller/Makefile | 1 +
> > > drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> > > 3 files changed, 986 insertions(+)
> > > create mode 100644 drivers/pci/controller/pcie-brcmstb.c
> > >
> > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > > index f5de9119e8d3..8b3aae91d8af 100644
> > > --- a/drivers/pci/controller/Kconfig
> > > +++ b/drivers/pci/controller/Kconfig
> > > @@ -281,6 +281,18 @@ config VMD
> > > To compile this driver as a module, choose M here: the
> > > module will be called vmd.
> > >
> > > +config PCIE_BRCMSTB
> > > + bool "Broadcom Brcmstb PCIe host controller"
> > > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> >
> > I can't see what ARCH_BRCMSTB adds here. Given this also depends
> > on SOC_BRCMSTB. Are all of these depends really necessary?
> >
> > Also should the bool be "Broadcom STB PCIe host contoller" ?
> >
> > > + depends on OF
> > > + depends on SOC_BRCMSTB
> > > + default ARCH_BRCMSTB || BMIPS_GENERIC
> >
> > Please also include COMPILE_TEST in here (look at the other controllers
> > in the file). This helps improve testing coverage by compiling all drivers
> > even if they can't be run.
> >
> > > + help
> > > + Say Y here to enable PCIe host controller support for
> > > + Broadcom Settop Box SOCs. A Broadcom SOC will may have
> >
> > s/Settop/Set top/ or s/Settop/STB/?
> >
> > > + multiple host controllers as opposed to a single host
> > > + controller with multiple ports.
> >
> > I'm sure many other SOCs may have multiple controllers instead of one
> > with multiple ports. I'm not sure what value this adds here. It's
> > always better to describe enough information so the user can determine
> > if this option will enable something they want on their hardware.
> >
> > > +
> > > config PCI_HYPERV_INTERFACE
> > > tristate "Hyper-V PCI Interface"
> > > depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> > > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> > > index a2a22c9d91af..3fc0b0cf5b5b 100644
> > > --- a/drivers/pci/controller/Makefile
> > > +++ b/drivers/pci/controller/Makefile
> > > @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> > > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > > obj-$(CONFIG_VMD) += vmd.o
> > > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > > obj-y += dwc/
> > >
> > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > > new file mode 100644
> > > index 000000000000..880ec11d06a1
> > > --- /dev/null
> > > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > > @@ -0,0 +1,973 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/* Copyright (C) 2009 - 2019 Broadcom */
> > > +
> > > +#include <linux/clk.h>
> > > +#include <linux/compiler.h>
> > > +#include <linux/delay.h>
> > > +#include <linux/init.h>
> > > +#include <linux/interrupt.h>
> > > +#include <linux/io.h>
> > > +#include <linux/ioport.h>
> > > +#include <linux/irqdomain.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/list.h>
> > > +#include <linux/log2.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/of_irq.h>
> > > +#include <linux/of_pci.h>
> > > +#include <linux/of_platform.h>
> > > +#include <linux/pci.h>
> > > +#include <linux/printk.h>
> > > +#include <linux/sizes.h>
> > > +#include <linux/slab.h>
> > > +#include <linux/string.h>
> > > +#include <linux/types.h>
> > > +
> > > +#include "../pci.h"
> >
> > Is this last include needed? Sometimes controller drivers suffer from copy and
> > paste and this is often included when it isn't needed.
> >
> > > +
> > > +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> > > +#define BRCM_PCIE_CAP_REGS 0x00ac
> > > +
> > > +/*
> > > + * Broadcom Settop Box PCIe Register Offsets. The names are from
> > > + * the chip's RDB and we use them here so that a script can correlate
> > > + * this code and the RDB to prevent discrepancies.
> > > + */
> > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > > +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> > > +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > > +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > > +#define PCIE_MISC_MISC_CTRL 0x4008
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > > +#define PCIE_MISC_PCIE_CTRL 0x4064
> > > +#define PCIE_MISC_PCIE_STATUS 0x4068
> > > +#define PCIE_MISC_REVISION 0x406c
> >
> > PCIE_MISC_REVISION can be removed as it shouldn't be needed
> >
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > > +#define PCIE_INTR2_CPU_BASE 0x4300
> > > +
> > > +/*
> > > + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> > > + * names are from the chip's RDB and we use them here so that a script
> > > + * can correlate this code and the RDB to prevent discrepancies.
> > > + */
> > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
> > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
> > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> > > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> > > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> > > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> > > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> > > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> > > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> > > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> > > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> > > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> > > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> > > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> > > +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> > > +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> > > +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> > > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
> >
> > Most of the above aren't used anywhere, please remove them.
> >
> > > +
> > > +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> > > +#define BRCM_MAX_SCB 0x4
> > > +
> > > +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > > +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> >
> > These two aren't used.
> >
> > > +
> > > +#define BURST_SIZE_128 0
> > > +#define BURST_SIZE_256 1
> > > +#define BURST_SIZE_512 2
> > > +
> > > +/* Offsets from PCIE_INTR2_CPU_BASE */
> > > +#define STATUS 0x0
> > > +#define SET 0x4
> > > +#define CLR 0x8
> > > +#define MASK_STATUS 0xc
> > > +#define MASK_SET 0x10
> > > +#define MASK_CLR 0x14
> >
> > Some of the above are not used anywhere.
> >
> > > +
> > > +#define PCIE_BUSNUM_SHIFT 20
> > > +#define PCIE_SLOT_SHIFT 15
> > > +#define PCIE_FUNC_SHIFT 12
> > > +
> > > +#if defined(__BIG_ENDIAN)
> > > +#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */
> > > +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */
> > > +#else
> > > +#define DATA_ENDIAN 0
> > > +#define MMIO_ENDIAN 0
> > > +#endif
> > > +
> > > +#define MDIO_PORT0 0x0
> > > +#define MDIO_DATA_MASK 0x7fffffff
> > > +#define MDIO_DATA_SHIFT 0x0
> > > +#define MDIO_PORT_MASK 0xf0000
> > > +#define MDIO_PORT_SHIFT 0x16
> > > +#define MDIO_REGAD_MASK 0xffff
> > > +#define MDIO_REGAD_SHIFT 0x0
> > > +#define MDIO_CMD_MASK 0xfff00000
> > > +#define MDIO_CMD_SHIFT 0x14
> > > +#define MDIO_CMD_READ 0x1
> > > +#define MDIO_CMD_WRITE 0x0
> > > +#define MDIO_DATA_DONE_MASK 0x80000000
> > > +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
> > > +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
> > > +#define SSC_REGS_ADDR 0x1100
> > > +#define SET_ADDR_OFFSET 0x1f
> > > +#define SSC_CNTL_OFFSET 0x2
> > > +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> > > +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> > > +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> > > +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> > > +#define SSC_STATUS_OFFSET 0x1
> > > +#define SSC_STATUS_SSC_MASK 0x400
> > > +#define SSC_STATUS_SSC_SHIFT 0xa
> > > +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> > > +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> > > +
> > > +#define IDX_ADDR(pcie) \
> > > + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> > > +#define DATA_ADDR(pcie) \
> > > + ((pcie)->reg_offsets[EXT_CFG_DATA])
> > > +#define PCIE_RGR1_SW_INIT_1(pcie) \
> > > + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> > > +
> > > +enum {
> > > + RGR1_SW_INIT_1,
> > > + EXT_CFG_INDEX,
> > > + EXT_CFG_DATA,
> > > +};
> > > +
> > > +enum {
> > > + RGR1_SW_INIT_1_INIT_MASK,
> > > + RGR1_SW_INIT_1_INIT_SHIFT,
> > > + RGR1_SW_INIT_1_PERST_MASK,
> > > + RGR1_SW_INIT_1_PERST_SHIFT,
> > > +};
> > > +
> > > +enum pcie_type {
> > > + BCM2711,
> > > +};
> > > +
> > > +struct brcm_window {
> > > + dma_addr_t pcie_addr;
> > > + phys_addr_t cpu_addr;
> > > + dma_addr_t size;
> > > +};
> > > +
> > > +/* Internal PCIe Host Controller Information.*/
> > > +struct brcm_pcie {
> > > + struct device *dev;
> > > + void __iomem *base;
> > > + int irq;
> >
> > 'irq' isn't used and can be removed.
> >
> > > + struct clk *clk;
> > > + struct pci_bus *root_bus;
> > > + struct device_node *dn;
> > > + int id;
> >
> > 'id' isn't used and can be removed.
> >
> > > + bool suspended;
> > > + bool ssc;
> > > + int gen;
> > > + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > > + unsigned int rev;
> >
> > 'rev' isn't used and can be removed.
> >
> > > + const int *reg_offsets;
> > > + const int *reg_field_info;
> > > + enum pcie_type type;
> > > +};
> > > +
> > > +struct pcie_cfg_data {
> > > + const int *reg_field_info;
> > > + const int *offsets;
> > > + const enum pcie_type type;
> > > +};
> > > +
> > > +static const int pcie_reg_field_info[] = {
> > > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> > > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> > > +};
> > > +
> > > +static const int pcie_offset_bcm2711[] = {
> > > + [RGR1_SW_INIT_1] = 0x9210,
> > > + [EXT_CFG_INDEX] = 0x9000,
> > > + [EXT_CFG_DATA] = 0x8000,
> > > +};
> > > +
> > > +static const struct pcie_cfg_data bcm2711_cfg = {
> > > + .reg_field_info = pcie_reg_field_info,
> > > + .offsets = pcie_offset_bcm2711,
> > > + .type = BCM2711,
> > > +};
> > > +
> > > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> > > + int where);
> > > +
> > > +static struct pci_ops brcm_pcie_ops = {
> > > + .map_bus = brcm_pcie_map_conf,
> > > + .read = pci_generic_config_read,
> > > + .write = pci_generic_config_write,
> > > +};
> > > +
> > > +#define bcm_readl(a) readl(a)
> > > +#define bcm_writel(d, a) writel(d, a)
> > > +#define bcm_readw(a) readw(a)
> > > +#define bcm_writew(d, a) writew(d, a)
> >
> > Is there much value in these macros?
> >
> > > +
> > > +/* These macros extract/insert fields to host controller's register set. */
> > > +#define RD_FLD(base, reg, field) \
> > > + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> > > +#define WR_FLD(base, reg, field, val) \
> > > + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> > > +#define WR_FLD_RB(base, reg, field, val) \
> > > + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> > > + reg##_##field##_SHIFT, val)
> > > +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> > > + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> > > + reg##_##field##_SHIFT, val)
> > > +#define EXTRACT_FIELD(val, reg, field) \
> > > + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> > > +#define INSERT_FIELD(val, reg, field, field_val) \
> > > + (((val) & ~reg##_##field##_MASK) | \
> > > + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> > > +
> > > +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> > > +{
> > > + return (bcm_readl(p) & mask) >> shift;
> > > +}
> > > +
> > > +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> > > +{
> > > + u32 reg = bcm_readl(p);
> > > +
> > > + reg = (reg & ~mask) | ((val << shift) & mask);
> > > + bcm_writel(reg, p);
> > > +}
> > > +
> > > +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> > > +{
> > > + wr_fld(p, mask, shift, val);
> > > + (void)bcm_readl(p);
> > > +}
> > > +
> > > +static const char *link_speed_to_str(int s)
> > > +{
> > > + switch (s) {
> > > + case 1:
> > > + return "2.5";
> > > + case 2:
> > > + return "5.0";
> > > + case 3:
> > > + return "8.0";
> > > + default:
> > > + break;
> > > + }
> > > + return "???";
> > > +}
> > > +
> > > +/*
> > > + * The roundup_pow_of_two() from log2.h invokes
> > > + * __roundup_pow_of_two(unsigned long), but we really need a
> > > + * such a function to take a native u64 since unsigned long
> > > + * is 32 bits on some configurations. So we provide this helper
> > > + * function below.
> > > + */
> > > +static u64 roundup_pow_of_two_64(u64 n)
> > > +{
> > > + return 1ULL << fls64(n - 1);
> > > +}
> >
> > Given that you use this in one place and that it is a single line, I'd
> > suggest you just drop this function. Alternatively if you wanted to add
> > this function to log2.h then you already have a bunch of users ready to
> > be migrated to it:
> >
> > $ git grep "<< fls64"
> > arch/sparc/mm/init_64.c: m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
> > drivers/net/ethernet/mellanox/mlx4/en_clock.c: u64 max_val_cycles_rounded = 1ULL << fls64(max_val_cycles - 1);
> > drivers/pci/controller/pcie-cadence-ep.c: sz = 1ULL << fls64(sz - 1);
> > drivers/pci/controller/pcie-cadence.c: u64 sz = 1ULL << fls64(size - 1);
> > drivers/pci/controller/pcie-rockchip-ep.c: u64 sz = 1ULL << fls64(size - 1);
> > drivers/pci/controller/pcie-rockchip-ep.c: sz = 1ULL << fls64(sz - 1);
> >
> >
> > > +
> > > +/*
> > > + * This is to convert the size of the inbound "BAR" region to the
> > > + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> > > + */
> > > +int encode_ibar_size(u64 size)
> > > +{
> > > + int log2_in = ilog2(size);
> > > +
> > > + if (log2_in >= 12 && log2_in <= 15)
> > > + /* Covers 4KB to 32KB (inclusive) */
> > > + return (log2_in - 12) + 0x1c;
> > > + else if (log2_in >= 16 && log2_in <= 37)
> > > + /* Covers 64KB to 32GB, (inclusive) */
> >
> > 2^37 != 32GB?
> Comment should be changed
> /* Current chips implement 64KB to 32GB; allow up to 128GB for
> future chips */
> or the value should be changed:
> s/37/35/;
> >
> > > + return log2_in - 15;
> > > + /* Something is awry so disable */
> > > + return 0;
> > > +}
> > > +
> > > +static u32 mdio_form_pkt(int port, int regad, int cmd)
> > > +{
> > > + u32 pkt = 0;
> > > +
> > > + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> > > + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> > > + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> > > +
> > > + return pkt;
> > > +}
> > > +
> > > +/* negative return value indicates error */
> > > +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> > > +{
> > > + int tries;
> > > + u32 data;
> > > +
> > > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> > > + base + PCIE_RC_DL_MDIO_ADDR);
> > > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > > +
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > > + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> > > + udelay(10);
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > > + }
> > > +
> > > + return MDIO_RD_DONE(data)
> > > + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> > > + : -EIO;
> > > +}
> > > +
> > > +/* negative return value indicates error */
> > > +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> > > +{
> > > + int tries;
> > > + u32 data;
> > > +
> > > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> > > + base + PCIE_RC_DL_MDIO_ADDR);
> > > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > > + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> > > + base + PCIE_RC_DL_MDIO_WR_DATA);
> > > +
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > > + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> > > + udelay(10);
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > > + }
> > > +
> > > + return MDIO_WT_DONE(data) ? 0 : -EIO;
> > > +}
> > > +
> > > +/*
> > > + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> > > + * return value indicates error.
> > > + */
> > > +static int set_ssc(void __iomem *base)
> >
> > Please prefix this with brcm_pcie_ (and other similar occurances)
> >
> > > +{
> > > + int tmp;
> > > + u16 wrdata;
> > > + int pll, ssc;
> > > +
> > > + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> > > + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> > > + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + usleep_range(1000, 2000);
> > > + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> > > + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> > > +
> > > + return (ssc && pll) ? 0 : -EIO;
> > > +}
> > > +
> > > +/* Limits operation to a specific generation (1, 2, or 3) */
> > > +static void set_gen(void __iomem *base, int gen)
> > > +{
> > > + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > > + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > > +
> > > + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> > > + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > > +
> > > + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> > > + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > > +}
> > > +
> > > +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> > > + unsigned int win, phys_addr_t cpu_addr,
> > > + dma_addr_t pcie_addr, dma_addr_t size)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + phys_addr_t cpu_addr_mb, limit_addr_mb;
> > > + u32 tmp;
> > > +
> > > + /* Set the base of the pcie_addr window */
> > > + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> > > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> > > + bcm_writel(upper_32_bits(pcie_addr),
> > > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> > > +
> > > + cpu_addr_mb = cpu_addr >> 20;
> > > + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> > > +
> > > + /* Write the addr base low register */
> > > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > > + BASE, cpu_addr_mb);
> > > + /* Write the addr limit low register */
> > > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > > + LIMIT, limit_addr_mb);
> > > +
> > > + /* Write the cpu addr high register */
> > > + tmp = (u32)(cpu_addr_mb >>
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> > > + BASE, tmp);
> > > + /* Write the cpu limit high register */
> > > + tmp = (u32)(limit_addr_mb >>
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> > > + LIMIT, tmp);
> > > +}
> > > +
> > > +/* Configuration space read/write support */
> > > +static int cfg_index(int busnr, int devfn, int reg)
> > > +{
> > > + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> > > + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> > > + | (busnr << PCIE_BUSNUM_SHIFT)
> > > + | (reg & ~3);
> > > +}
> > > +
> > > +/* The controller is capable of serving in both RC and EP roles */
> > > +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > > +
> > > + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> > > +}
> > > +
> > > +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > > + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> > > + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> > > +
> > > + return (dla && plu) ? true : false;
> > > +}
> > > +
> > > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> > > + int where)
> > > +{
> > > + struct brcm_pcie *pcie = bus->sysdata;
> > > + void __iomem *base = pcie->base;
> > > + int idx;
> > > +
> > > + /* Accesses to the RC go right to the RC registers if slot==0 */
> > > + if (pci_is_root_bus(bus))
> > > + return PCI_SLOT(devfn) ? NULL : base + where;
> > > +
> > > + /* For devices, write to the config space index register */
> > > + idx = cfg_index(bus->number, devfn, 0);
> > > + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> > > + return base + DATA_ADDR(pcie) + where;
> > > +}
> > > +
> > > +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > > + unsigned int val)
> > > +{
> > > + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> > > + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > > +
> > > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> > > +}
> > > +
> > > +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> > > + unsigned int val)
> > > +{
> > > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> > > + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> > > + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> > > +}
> > > +
> > > +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> > > + u64 *rc_bar2_size,
> > > + u64 *rc_bar2_offset)
> > > +{
> > > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > > + struct device *dev = pcie->dev;
> > > + struct resource_entry *entry;
> > > + u64 total_mem_size = 0;
> > > +
> > > + *rc_bar2_offset = -1;
> > > +
> > > + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> > > + /*
> > > + * We're promissed the RC will provide a contiguous view of
> >
> > s/promissed/promised/
> >
> > > + * memory to downstream devices. We can then infer the
> > > + * rc_bar2_offset from the lower avaiable dma-range offset.
> > > + */
> > > + if (entry->offset < *rc_bar2_offset)
> > > + *rc_bar2_offset = entry->offset;
> > > +
> > > + total_mem_size += entry->res->end - entry->res->start + 1;
> > > + }
> > > +
> > > + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> > > +
> > > + /*
> > > + * Validate the results:
> > > + *
> > > + * The PCIe host controller by design must set the inbound viewport to
> > > + * be a contiguous arrangement of all of the system's memory. In
> > > + * addition, its size mut be a power of two. To further complicate
> > > + * matters, the viewport must start on a pcie-address that is aligned
> > > + * on a multiple of its size. If a portion of the viewport does not
> > > + * represent system memory -- e.g. 3GB of memory requires a 4GB
> > > + * viewport -- we can map the outbound memory in or after 3GB and even
> > > + * though the viewport will overlap the outbound memory the controller
> > > + * will know to send outbound memory downstream and everything else
> > > + * upstream.
> > > + *
> > > + * For example:
> > > + *
> > > + * - The best-case scenario, memory up to 3GB, is to place the inbound
> > > + * region in the first 4GB of pcie-space, as some legacy devices can
> > > + * only address 32bits. We would also like to put the MSI under 4GB
> > > + * as well, since some devices require a 32bit MSI target address.
> > > + *
> > > + * - If the system memory is 4GB or larger we cannot start the inbound
> > > + * region at location 0 (since we have to allow some space for
> > > + * outbound memory @ 3GB). So instead it will start at the 1x
> > > + * multiple of its size
> > > + */
> > > + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> > > + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> > > + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
> > > + *rc_bar2_size, *rc_bar2_offset);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > > +{
> > > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > > + u64 rc_bar2_offset, rc_bar2_size;
> > > + void __iomem *base = pcie->base;
> > > + struct resource_entry *entry;
> > > + unsigned int scb_size_val;
> > > + struct resource *res;
> > > + int num_out_wins = 0;
> > > + u32 tmp;
> > > + int i, j, ret, limit;
> > > + u16 nlw, cls, lnksta;
> > > + bool ssc_good = false;
> > > + struct device *dev = pcie->dev;
> > > +
> > > + /* Reset the bridge */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > +
> > > + usleep_range(100, 200);
> > > +
> > > + /* Take the bridge out of reset */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > > +
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > > + /* Wait for SerDes to be stable */
> > > + usleep_range(100, 200);
> > > +
> > > + /* Grab the PCIe hw revision number */
> > > + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> > > + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> >
> > This isn't used anywhere
> >
> > > +
> > > + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> > > + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> > > + BURST_SIZE_128);
> > > + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> > > +
> > > + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> > > + &rc_bar2_offset);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + tmp = lower_32_bits(rc_bar2_offset);
> > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> > > + encode_ibar_size(rc_bar2_size));
> > > + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> > > + bcm_writel(upper_32_bits(rc_bar2_offset),
> > > + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> > > +
> > > + scb_size_val = rc_bar2_size ?
> > > + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> > > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> > > +
> > > + /* disable the PCIe->GISB memory window (RC_BAR1) */
> > > + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> > > +
> > > + /* disable the PCIe->SCB memory window (RC_BAR3) */
> > > + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> > > +
> > > + if (!pcie->suspended) {
> > > + /* clear any interrupts we find on boot */
> > > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> > > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> > > + }
> > > +
> > > + /* Mask all interrupts since we are not handling any yet */
> > > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > > +
> > > + if (pcie->gen)
> > > + set_gen(base, pcie->gen);
> > > +
> > > + /* Unassert the fundamental reset */
> > > + brcm_pcie_perst_set(pcie, 0);
> > > +
> > > + /*
> > > + * Give the RC/EP time to wake up, before trying to configure RC.
> > > + * Intermittently check status for link-up, up to a total of 100ms
> > > + * when we don't know if the device is there, and up to 1000ms if
> > > + * we do know the device is there.
> > > + */
> > > + limit = pcie->suspended ? 1000 : 100;
> > > + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> > > + j += i, i = i * 2)
> > > + msleep(i + j > limit ? limit - j : i);
> >
> > Does it need to be this complex? Also waiting a second during resume seems
> > like a long delay.
>
> Agree on the complexity issue. But we've had EP chips that required
> this much time on a resume for reasons unknown. Code could be
> changed to something like
> for (i = 0; i <= limit; i += 100)
> if (brcm_pcie_link_up(pcie)
> break;
> else
> msleep(100);
This is an improvement. If the reasons are unknown how are you confident that
1 second is enough?
>
> >
> > > +
> > > + if (!brcm_pcie_link_up(pcie)) {
> > > + dev_info(dev, "link down\n");
> > > + return -ENODEV;
> > > + }
> > > +
> > > + if (!brcm_pcie_rc_mode(pcie)) {
> > > + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + resource_list_for_each_entry(entry, &bridge->windows) {
> > > + res = entry->res;
> > > +
> > > + if (resource_type(res) != IORESOURCE_MEM)
> > > + continue;
> > > +
> > > + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> > > + dev_err(pcie->dev, "too many outbound wins\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> > > + res->start - entry->offset,
> > > + res->end - res->start + 1);
> > > + num_out_wins++;
> > > + }
> > > +
> > > + /*
> > > + * For config space accesses on the RC, show the right class for
> > > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > > + */
> > > + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> > > +
> > > + if (pcie->ssc) {
> > > + ret = set_ssc(base);
> > > + if (ret == 0)
> > > + ssc_good = true;
> > > + else
> > > + dev_err(dev, "failed attempt to enter ssc mode\n");
> > > + }
> > > +
> > > + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > > + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> > > + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> > > + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> > > + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> > > +
> > > + /* PCIe->SCB endian mode for BAR */
> > > + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> > > + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> > > + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> > > +
> > > + /*
> > > + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> > > + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> > > + */
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +/* L23 is a low-power PCIe link state */
> > > +static void enter_l23(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + int l23, i;
> > > +
> > > + /* assert request for L23 */
> > > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > > +
> > > + /* Wait up to 30 msec for L23 */
> > > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > > + for (i = 0; i < 15 && !l23; i++) {
> > > + usleep_range(2000, 2400);
> > > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > > + }
> > > +
> > > + if (!l23)
> > > + dev_err(pcie->dev, "failed to enter L23\n");
> > > +}
> > > +
> > > +static void turn_off(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > +
> > > + if (brcm_pcie_link_up(pcie))
> > > + enter_l23(pcie);
> > > + /* Assert fundamental reset */
> > > + brcm_pcie_perst_set(pcie, 1);
> > > + /* Deassert request for L23 in case it was asserted */
> > > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > > + /* Turn off SerDes */
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > > + /* Shutdown PCIe bridge */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > +}
> > > +
> > > +static int brcm_pcie_suspend(struct device *dev)
> > > +{
> > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > +
> > > + turn_off(pcie);
> > > + clk_disable_unprepare(pcie->clk);
> > > + pcie->suspended = true;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int brcm_pcie_resume(struct device *dev)
> > > +{
> > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > + void __iomem *base;
> > > + int ret;
> > > +
> > > + base = pcie->base;
> > > + clk_prepare_enable(pcie->clk);
> > > +
> > > + /* Take bridge out of reset so we can access the SerDes reg */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > > +
> > > + /* Turn on SerDes */
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > > + /* Wait for SerDes to be stable */
> > > + usleep_range(100, 200);
> > > +
> > > + ret = brcm_pcie_setup(pcie);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + pcie->suspended = false;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> >
> > I don't see the value in the first underscore here.
> We have a function _brcm_pcie_remove() and a function
> brcm_pciie_remove(). The former is invoked by the latter, but the
> former is also invoked later in the code as well.
That's OK, missed this.
Thanks,
Andrew Murray
>
> Jim Quinlan
> Broadcom
>
> >
> > > +{
> > > + turn_off(pcie);
> > > + clk_disable_unprepare(pcie->clk);
> > > + clk_put(pcie->clk);
> > > +}
> > > +
> > > +static int brcm_pcie_remove(struct platform_device *pdev)
> > > +{
> > > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > > +
> > > + pci_stop_root_bus(pcie->root_bus);
> > > + pci_remove_root_bus(pcie->root_bus);
> > > + _brcm_pcie_remove(pcie);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static const struct of_device_id brcm_pcie_match[] = {
> > > + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> > > + {},
> > > +};
> > > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > > +
> > > +static int brcm_pcie_probe(struct platform_device *pdev)
> > > +{
> > > + struct device_node *dn = pdev->dev.of_node;
> > > + const struct of_device_id *of_id;
> > > + const struct pcie_cfg_data *data;
> > > + struct resource *res;
> > > + int ret;
> > > + struct brcm_pcie *pcie;
> > > + void __iomem *base;
> > > + struct pci_host_bridge *bridge;
> > > + struct pci_bus *child;
> > > +
> > > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > > + if (!bridge)
> > > + return -ENOMEM;
> > > +
> > > + pcie = pci_host_bridge_priv(bridge);
> > > +
> > > + of_id = of_match_node(brcm_pcie_match, dn);
> > > + if (!of_id) {
> > > + dev_err(&pdev->dev, "failed to look up compatible string\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + data = of_id->data;
> >
> > Can you replace the above (from of_match_node to here) with the following?
> >
> > data = of_device_get_match_data(pdev->dev)
> >
> > > + pcie->reg_offsets = data->offsets;
> > > + pcie->reg_field_info = data->reg_field_info;
> > > + pcie->type = data->type;
> > > + pcie->dn = dn;
> > > + pcie->dev = &pdev->dev;
> > > +
> > > + /* We use the domain number as our controller number */
> > > + pcie->id = of_get_pci_domain_nr(dn);
> > > + if (pcie->id < 0)
> > > + return pcie->id;
> >
> > We don't do anything with this, so you can remove this.
> >
> > > +
> > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > + if (!res)
> > > + return -EINVAL;
> >
> > The majority of controller drivers don't bother to check the return value
> > here and just pass res into devm_ioremap_resource.
> >
> > > +
> > > + base = devm_ioremap_resource(&pdev->dev, res);
> > > + if (IS_ERR(base))
> > > + return PTR_ERR(base);
> > > +
> > > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > > + if (IS_ERR(pcie->clk)) {
> > > + dev_err(&pdev->dev, "could not get clock\n");
> > > + pcie->clk = NULL;
> > > + }
> >
> > Is this a good use-case for devm_clk_get_optional?
> >
> > > + pcie->base = base;
> > > +
> > > + ret = of_pci_get_max_link_speed(dn);
> > > + pcie->gen = (ret < 0) ? 0 : ret;
> >
> > There is no checking that gen isn't too large here, given that we pass
> > this into a register later we probably want to check it here.
> >
> > > +
> > > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > > +
> > > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > > + if (ret == 0)
> > > + /* keep going, as we don't use this intr yet */
> > > + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> > > + else
> > > + pcie->irq = ret;
> >
> > Given we don't use it yet, please remove it from this patch.
> >
> > > +
> > > + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> > > + &bridge->dma_ranges, NULL);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + ret = clk_prepare_enable(pcie->clk);
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "could not enable clock\n");
> > > + return ret;
> > > + }
> > > +
> > > + ret = brcm_pcie_setup(pcie);
> > > + if (ret)
> > > + goto fail;
> > > +
> > > + bridge->dev.parent = &pdev->dev;
> > > + bridge->busnr = 0;
> > > + bridge->ops = &brcm_pcie_ops;
> > > + bridge->sysdata = pcie;
> > > + bridge->map_irq = of_irq_parse_and_map_pci;
> > > + bridge->swizzle_irq = pci_common_swizzle;
> > > +
> > > + ret = pci_scan_root_bus_bridge(bridge);
> > > + if (ret < 0) {
> > > + dev_err(pcie->dev, "Scanning root bridge failed\n");
> > > + goto fail;
> > > + }
> > > +
> > > + pci_assign_unassigned_bus_resources(bridge->bus);
> > > + list_for_each_entry(child, &bridge->bus->children, node)
> > > + pcie_bus_configure_settings(child);
> > > + pci_bus_add_devices(bridge->bus);
> > > + platform_set_drvdata(pdev, pcie);
> > > + pcie->root_bus = bridge->bus;
> > > +
> > > + return 0;
> > > +
> > > +fail:
> > > + _brcm_pcie_remove(pcie);
> > > + return ret;
> > > +}
> > > +
> > > +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> > > + .suspend_noirq = brcm_pcie_suspend,
> > > + .resume_noirq = brcm_pcie_resume,
> > > +};
> > > +
> > > +static struct platform_driver brcm_pcie_driver = {
> > > + .probe = brcm_pcie_probe,
> > > + .remove = brcm_pcie_remove,
> > > + .driver = {
> > > + .name = "brcm-pcie",
> > > + .owner = THIS_MODULE,
> > > + .of_match_table = brcm_pcie_match,
> > > + .pm = &brcm_pcie_pm_ops,
> > > + },
> > > +};
> > > +
> > > +module_platform_driver(brcm_pcie_driver);
> > > +
> > > +MODULE_LICENSE("GPL v2");
> > > +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
> > > +MODULE_AUTHOR("Broadcom");
> > > --
> > > 2.23.0
> > >
On Thu, Nov 07, 2019 at 06:30:25PM +0100, Nicolas Saenz Julienne wrote:
> Hi Andrew,
> thanks for taking the time to review this.
>
> On Thu, 2019-11-07 at 15:00 +0000, Andrew Murray wrote:
> > Thanks for the patch, some initial feedback below, though I will give it a
> > more detailed review on your respin.
> >
> > On Wed, Nov 06, 2019 at 10:45:25PM +0100, Nicolas Saenz Julienne wrote:
> > > From: Jim Quinlan <[email protected]>
> > >
> > > This commit adds the basic Broadcom STB PCIe controller. Missing is the
> > > ability to process MSI. This functionality is added in a subsequent
> > > commit.
> > >
> > > The PCIe block contains an MDIO interface. This is a local interface
> > > only accessible by the PCIe controller. It cannot be used or shared
> > > by any other HW. As such, the small amount of code for this
> > > controller is included in this driver as there is little upside to put
> > > it elsewhere.
> > >
> > > This is based on Jim's original submission[1] but adapted and tailored
> > > specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> > > the rest of the brcmstb family will soon follow once we get support for
> > > multiple dma-ranges in dma/direct.
> >
> > This commit message is very informative and helpful, though I feel a lot
> > of this isn't relevant for a commit message (especially as much of it is
> > time based comments). Instead it would be better to simply describe what
> > the patch does provide, and any additional helpful notes can be provided
> > under the '---' after the signed off (which won't make it into git).
>
> Ok noted
>
> > > [1] https://patchwork.kernel.org/patch/10605959/
> > >
> > > Signed-off-by: Jim Quinlan <[email protected]>
> > > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > > ---
> > > drivers/pci/controller/Kconfig | 12 +
> > > drivers/pci/controller/Makefile | 1 +
> > > drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> > > 3 files changed, 986 insertions(+)
> > > create mode 100644 drivers/pci/controller/pcie-brcmstb.c
> > >
> > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > > index f5de9119e8d3..8b3aae91d8af 100644
> > > --- a/drivers/pci/controller/Kconfig
> > > +++ b/drivers/pci/controller/Kconfig
> > > @@ -281,6 +281,18 @@ config VMD
> > > To compile this driver as a module, choose M here: the
> > > module will be called vmd.
> > >
> > > +config PCIE_BRCMSTB
> > > + bool "Broadcom Brcmstb PCIe host controller"
> > > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> >
> > I can't see what ARCH_BRCMSTB adds here. Given this also depends
> > on SOC_BRCMSTB. Are all of these depends really necessary?
>
> You're right, too many unnecessary depends. I missed this. For now only
> ARCH_BCM2835 will do. I'll clean it up.
>
> > Also should the bool be "Broadcom STB PCIe host contoller" ?
>
> I'd rather keep the STB mention as it's the overall platform this is aimed for
> (and it's on the driver name), but for the sake of clarity I'll update it to
> something the likes of: "Bradcom STB & Raspberry Pi 4 PCIe host
> controller"
>
> > > + depends on OF
> > > + depends on SOC_BRCMSTB
> > > + default ARCH_BRCMSTB || BMIPS_GENERIC
> >
> > Please also include COMPILE_TEST in here (look at the other controllers
> > in the file). This helps improve testing coverage by compiling all drivers
> > even if they can't be run.
>
> OK
>
> > > + help
> > > + Say Y here to enable PCIe host controller support for
> > > + Broadcom Settop Box SOCs. A Broadcom SOC will may have
> >
> > s/Settop/Set top/ or s/Settop/STB/?
>
> Let's default to STB. I'll look around for more offenders.
Happy with anything, just keen for it to be consistent.
>
> > > + multiple host controllers as opposed to a single host
> > > + controller with multiple ports.
> >
> > I'm sure many other SOCs may have multiple controllers instead of one
> > with multiple ports. I'm not sure what value this adds here. It's
> > always better to describe enough information so the user can determine
> > if this option will enable something they want on their hardware.
>
> Agree, I'll remove that sentence.
>
> > > +
> > > config PCI_HYPERV_INTERFACE
> > > tristate "Hyper-V PCI Interface"
> > > depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> > > diff --git a/drivers/pci/controller/Makefile
> > > b/drivers/pci/controller/Makefile
> > > index a2a22c9d91af..3fc0b0cf5b5b 100644
> > > --- a/drivers/pci/controller/Makefile
> > > +++ b/drivers/pci/controller/Makefile
> > > @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> > > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > > obj-$(CONFIG_VMD) += vmd.o
> > > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > > obj-y += dwc/
> > >
> > > diff --git a/drivers/pci/controller/pcie-brcmstb.c
> > > b/drivers/pci/controller/pcie-brcmstb.c
> > > new file mode 100644
> > > index 000000000000..880ec11d06a1
> > > --- /dev/null
> > > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > > @@ -0,0 +1,973 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/* Copyright (C) 2009 - 2019 Broadcom */
> > > +
> > > +#include <linux/clk.h>
> > > +#include <linux/compiler.h>
> > > +#include <linux/delay.h>
> > > +#include <linux/init.h>
> > > +#include <linux/interrupt.h>
> > > +#include <linux/io.h>
> > > +#include <linux/ioport.h>
> > > +#include <linux/irqdomain.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/list.h>
> > > +#include <linux/log2.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_address.h>
> > > +#include <linux/of_irq.h>
> > > +#include <linux/of_pci.h>
> > > +#include <linux/of_platform.h>
> > > +#include <linux/pci.h>
> > > +#include <linux/printk.h>
> > > +#include <linux/sizes.h>
> > > +#include <linux/slab.h>
> > > +#include <linux/string.h>
> > > +#include <linux/types.h>
> > > +
> > > +#include "../pci.h"
> >
> > Is this last include needed? Sometimes controller drivers suffer from copy and
> > paste and this is often included when it isn't needed.
>
> It's needed in order to call of_pci_get_max_link_speed().
Thanks.
>
> > > +
> > > +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> > > +#define BRCM_PCIE_CAP_REGS 0x00ac
> > > +
> > > +/*
> > > + * Broadcom Settop Box PCIe Register Offsets. The names are from
> > > + * the chip's RDB and we use them here so that a script can correlate
> > > + * this code and the RDB to prevent discrepancies.
> > > + */
> > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > > +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> > > +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > > +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > > +#define PCIE_MISC_MISC_CTRL 0x4008
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > > +#define PCIE_MISC_PCIE_CTRL 0x4064
> > > +#define PCIE_MISC_PCIE_STATUS 0x4068
> > > +#define PCIE_MISC_REVISION 0x406c
> >
> > PCIE_MISC_REVISION can be removed as it shouldn't be needed
>
> See my comment below regarding revision.
>
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > > +#define PCIE_INTR2_CPU_BASE 0x4300
> > > +
> > > +/*
> > > + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> > > + * names are from the chip's RDB and we use them here so that a script
> > > + * can correlate this code and the RDB to prevent discrepancies.
> > > + */
> > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK
> > > 0xc
> > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT
> > > 0x2
> > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> > > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> > > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> > > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> > > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> > > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> > > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> > > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> > > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> > > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> > > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> > > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> > > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> > > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> > > +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> > > +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff000
> > > 00
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x080000
> > > 00
> > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> > > +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> > > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
> >
> > Most of the above aren't used anywhere, please remove them.
>
> OK
>
> > > +
> > > +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> > > +#define BRCM_MAX_SCB 0x4
> > > +
> > > +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > > +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> >
> > These two aren't used.
>
> As with the revision, this is only used once MSI is introduced, on the next
> patch. I'll move it there if you prefer it.
Yes please move them to the first point of use.
>
> > > +
> > > +#define BURST_SIZE_128 0
> > > +#define BURST_SIZE_256 1
> > > +#define BURST_SIZE_512 2
> > > +
> > > +/* Offsets from PCIE_INTR2_CPU_BASE */
> > > +#define STATUS 0x0
> > > +#define SET 0x4
> > > +#define CLR 0x8
> > > +#define MASK_STATUS 0xc
> > > +#define MASK_SET 0x10
> > > +#define MASK_CLR 0x14
> >
> > Some of the above are not used anywhere.
>
> OK
>
> > > +
> > > +#define PCIE_BUSNUM_SHIFT 20
> > > +#define PCIE_SLOT_SHIFT 15
> > > +#define PCIE_FUNC_SHIFT 12
> > > +
> > > +#if defined(__BIG_ENDIAN)
> > > +#define DATA_ENDIAN 2 /* PCIe->DDR inbound
> traffic
> > > */
> > > +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound
> > > traffic */
> > > +#else
> > > +#define DATA_ENDIAN 0
> > > +#define MMIO_ENDIAN 0
> > > +#endif
> > > +
> > > +#define MDIO_PORT0 0x0
> > > +#define MDIO_DATA_MASK 0x7fffffff
> > > +#define MDIO_DATA_SHIFT 0x0
> > > +#define MDIO_PORT_MASK 0xf0000
> > > +#define MDIO_PORT_SHIFT 0x16
> > > +#define MDIO_REGAD_MASK 0xffff
> > > +#define MDIO_REGAD_SHIFT 0x0
> > > +#define MDIO_CMD_MASK 0xfff00000
> > > +#define MDIO_CMD_SHIFT 0x14
> > > +#define MDIO_CMD_READ 0x1
> > > +#define MDIO_CMD_WRITE 0x0
> > > +#define MDIO_DATA_DONE_MASK 0x80000000
> > > +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1
> > > : 0)
> > > +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0
> > > : 1)
> > > +#define SSC_REGS_ADDR 0x1100
> > > +#define SET_ADDR_OFFSET 0x1f
> > > +#define SSC_CNTL_OFFSET 0x2
> > > +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> > > +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> > > +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> > > +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> > > +#define SSC_STATUS_OFFSET 0x1
> > > +#define SSC_STATUS_SSC_MASK 0x400
> > > +#define SSC_STATUS_SSC_SHIFT 0xa
> > > +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> > > +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> > > +
> > > +#define IDX_ADDR(pcie) \
> > > + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> > > +#define DATA_ADDR(pcie) \
> > > + ((pcie)->reg_offsets[EXT_CFG_DATA])
> > > +#define PCIE_RGR1_SW_INIT_1(pcie) \
> > > + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> > > +
> > > +enum {
> > > + RGR1_SW_INIT_1,
> > > + EXT_CFG_INDEX,
> > > + EXT_CFG_DATA,
> > > +};
> > > +
> > > +enum {
> > > + RGR1_SW_INIT_1_INIT_MASK,
> > > + RGR1_SW_INIT_1_INIT_SHIFT,
> > > + RGR1_SW_INIT_1_PERST_MASK,
> > > + RGR1_SW_INIT_1_PERST_SHIFT,
> > > +};
> > > +
> > > +enum pcie_type {
> > > + BCM2711,
> > > +};
> > > +
> > > +struct brcm_window {
> > > + dma_addr_t pcie_addr;
> > > + phys_addr_t cpu_addr;
> > > + dma_addr_t size;
> > > +};
> > > +
> > > +/* Internal PCIe Host Controller Information.*/
> > > +struct brcm_pcie {
> > > + struct device *dev;
> > > + void __iomem *base;
> > > + int irq;
> >
> > 'irq' isn't used and can be removed.
>
> Yes
>
> > > + struct clk *clk;
> > > + struct pci_bus *root_bus;
> > > + struct device_node *dn;
> > > + int id;
> >
> > 'id' isn't used and can be removed.
>
> Yes
>
> > > + bool suspended;
> > > + bool ssc;
> > > + int gen;
> > > + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > > + unsigned int rev;
> >
> > 'rev' isn't used and can be removed.
>
> It's used by the MSI code further down the line. If you want I'll move it to
> that patch.
Yes please.
>
> > > + const int *reg_offsets;
> > > + const int *reg_field_info;
> > > + enum pcie_type type;
> > > +};
> > > +
> > > +struct pcie_cfg_data {
> > > + const int *reg_field_info;
> > > + const int *offsets;
> > > + const enum pcie_type type;
> > > +};
> > > +
> > > +static const int pcie_reg_field_info[] = {
> > > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> > > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> > > +};
> > > +
> > > +static const int pcie_offset_bcm2711[] = {
> > > + [RGR1_SW_INIT_1] = 0x9210,
> > > + [EXT_CFG_INDEX] = 0x9000,
> > > + [EXT_CFG_DATA] = 0x8000,
> > > +};
> > > +
> > > +static const struct pcie_cfg_data bcm2711_cfg = {
> > > + .reg_field_info = pcie_reg_field_info,
> > > + .offsets = pcie_offset_bcm2711,
> > > + .type = BCM2711,
> > > +};
> > > +
> > > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
> > > devfn,
> > > + int where);
> > > +
> > > +static struct pci_ops brcm_pcie_ops = {
> > > + .map_bus = brcm_pcie_map_conf,
> > > + .read = pci_generic_config_read,
> > > + .write = pci_generic_config_write,
> > > +};
> > > +
> > > +#define bcm_readl(a) readl(a)
> > > +#define bcm_writel(d, a) writel(d, a)
> > > +#define bcm_readw(a) readw(a)
> > > +#define bcm_writew(d, a) writew(d, a)
> >
> > Is there much value in these macros?
>
> Yes, once we introduce MIPS users, they'll need to use __raw_write*(). It'll
> make the patch simpler.
>
> > > +
> > > +/* These macros extract/insert fields to host controller's register set. */
> > > +#define RD_FLD(base, reg, field) \
> > > + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> > > +#define WR_FLD(base, reg, field, val) \
> > > + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> > > +#define WR_FLD_RB(base, reg, field, val) \
> > > + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> > > + reg##_##field##_SHIFT, val)
> > > +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> > > + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> > > + reg##_##field##_SHIFT, val)
> > > +#define EXTRACT_FIELD(val, reg, field) \
> > > + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> > > +#define INSERT_FIELD(val, reg, field, field_val) \
> > > + (((val) & ~reg##_##field##_MASK) | \
> > > + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> > > +
> > > +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> > > +{
> > > + return (bcm_readl(p) & mask) >> shift;
> > > +}
> > > +
> > > +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> > > +{
> > > + u32 reg = bcm_readl(p);
> > > +
> > > + reg = (reg & ~mask) | ((val << shift) & mask);
> > > + bcm_writel(reg, p);
> > > +}
> > > +
> > > +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> > > +{
> > > + wr_fld(p, mask, shift, val);
> > > + (void)bcm_readl(p);
> > > +}
> > > +
> > > +static const char *link_speed_to_str(int s)
> > > +{
> > > + switch (s) {
> > > + case 1:
> > > + return "2.5";
> > > + case 2:
> > > + return "5.0";
> > > + case 3:
> > > + return "8.0";
> > > + default:
> > > + break;
> > > + }
> > > + return "???";
> > > +}
> > > +
> > > +/*
> > > + * The roundup_pow_of_two() from log2.h invokes
> > > + * __roundup_pow_of_two(unsigned long), but we really need a
> > > + * such a function to take a native u64 since unsigned long
> > > + * is 32 bits on some configurations. So we provide this helper
> > > + * function below.
> > > + */
> > > +static u64 roundup_pow_of_two_64(u64 n)
> > > +{
> > > + return 1ULL << fls64(n - 1);
> > > +}
> >
> > Given that you use this in one place and that it is a single line, I'd
> > suggest you just drop this function. Alternatively if you wanted to add
> > this function to log2.h then you already have a bunch of users ready to
> > be migrated to it:
> >
> > $ git grep "<<
> > fls64"
> > arch/sparc/mm/init_64.c: m_end += pa_start & ~((1ul << fls64(m_mask)) -
> > 1);
> > drivers/net/ethernet/mellanox/mlx4/en_clock.c: u64 max_val_cycles_rounded =
> > 1ULL << fls64(max_val_cycles - 1);
> > drivers/pci/controller/pcie-cadence-ep.c: sz = 1ULL << fls64(sz - 1);
> > drivers/pci/controller/pcie-cadence.c: u64 sz = 1ULL << fls64(size - 1);
> > drivers/pci/controller/pcie-rockchip-ep.c: u64 sz = 1ULL << fls64(size -
> > 1);
> > drivers/pci/controller/pcie-rockchip-ep.c: sz = 1ULL << fls64(sz - 1);
>
> I'll add it to log2.h
Excellent.
>
> > > +
> > > +/*
> > > + * This is to convert the size of the inbound "BAR" region to the
> > > + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> > > + */
> > > +int encode_ibar_size(u64 size)
> > > +{
> > > + int log2_in = ilog2(size);
> > > +
> > > + if (log2_in >= 12 && log2_in <= 15)
> > > + /* Covers 4KB to 32KB (inclusive) */
> > > + return (log2_in - 12) + 0x1c;
> > > + else if (log2_in >= 16 && log2_in <= 37)
> > > + /* Covers 64KB to 32GB, (inclusive) */
> >
> > 2^37 != 32GB?
>
> I picked up Jim's comment.
>
> > > + return log2_in - 15;
> > > + /* Something is awry so disable */
> > > + return 0;
> > > +}
> > > +
> > > +static u32 mdio_form_pkt(int port, int regad, int cmd)
> > > +{
> > > + u32 pkt = 0;
> > > +
> > > + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> > > + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> > > + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> > > +
> > > + return pkt;
> > > +}
> > > +
> > > +/* negative return value indicates error */
> > > +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> > > +{
> > > + int tries;
> > > + u32 data;
> > > +
> > > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> > > + base + PCIE_RC_DL_MDIO_ADDR);
> > > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > > +
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > > + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> > > + udelay(10);
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > > + }
> > > +
> > > + return MDIO_RD_DONE(data)
> > > + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> > > + : -EIO;
> > > +}
> > > +
> > > +/* negative return value indicates error */
> > > +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> > > +{
> > > + int tries;
> > > + u32 data;
> > > +
> > > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> > > + base + PCIE_RC_DL_MDIO_ADDR);
> > > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > > + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> > > + base + PCIE_RC_DL_MDIO_WR_DATA);
> > > +
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > > + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> > > + udelay(10);
> > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > > + }
> > > +
> > > + return MDIO_WT_DONE(data) ? 0 : -EIO;
> > > +}
> > > +
> > > +/*
> > > + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> > > + * return value indicates error.
> > > + */
> > > +static int set_ssc(void __iomem *base)
> >
> > Please prefix this with brcm_pcie_ (and other similar occurances)
> >
>
> OK
>
> > > +{
> > > + int tmp;
> > > + u16 wrdata;
> > > + int pll, ssc;
> > > +
> > > + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> > > + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> > > + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + usleep_range(1000, 2000);
> > > + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> > > + if (tmp < 0)
> > > + return tmp;
> > > +
> > > + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> > > + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> > > +
> > > + return (ssc && pll) ? 0 : -EIO;
> > > +}
> > > +
> > > +/* Limits operation to a specific generation (1, 2, or 3) */
> > > +static void set_gen(void __iomem *base, int gen)
> > > +{
> > > + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > > + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > > +
> > > + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> > > + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > > +
> > > + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> > > + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > > +}
> > > +
> > > +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> > > + unsigned int win, phys_addr_t cpu_addr,
> > > + dma_addr_t pcie_addr, dma_addr_t size)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + phys_addr_t cpu_addr_mb, limit_addr_mb;
> > > + u32 tmp;
> > > +
> > > + /* Set the base of the pcie_addr window */
> > > + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> > > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> > > + bcm_writel(upper_32_bits(pcie_addr),
> > > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> > > +
> > > + cpu_addr_mb = cpu_addr >> 20;
> > > + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> > > +
> > > + /* Write the addr base low register */
> > > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > > + BASE, cpu_addr_mb);
> > > + /* Write the addr limit low register */
> > > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > > + LIMIT, limit_addr_mb);
> > > +
> > > + /* Write the cpu addr high register */
> > > + tmp = (u32)(cpu_addr_mb >>
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> > > + BASE, tmp);
> > > + /* Write the cpu limit high register */
> > > + tmp = (u32)(limit_addr_mb >>
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> > > + LIMIT, tmp);
> > > +}
> > > +
> > > +/* Configuration space read/write support */
> > > +static int cfg_index(int busnr, int devfn, int reg)
> > > +{
> > > + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> > > + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> > > + | (busnr << PCIE_BUSNUM_SHIFT)
> > > + | (reg & ~3);
> > > +}
> > > +
> > > +/* The controller is capable of serving in both RC and EP roles */
> > > +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > > +
> > > + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> > > +}
> > > +
> > > +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > > + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> > > + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> > > +
> > > + return (dla && plu) ? true : false;
> > > +}
> > > +
> > > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
> > > devfn,
> > > + int where)
> > > +{
> > > + struct brcm_pcie *pcie = bus->sysdata;
> > > + void __iomem *base = pcie->base;
> > > + int idx;
> > > +
> > > + /* Accesses to the RC go right to the RC registers if slot==0 */
> > > + if (pci_is_root_bus(bus))
> > > + return PCI_SLOT(devfn) ? NULL : base + where;
> > > +
> > > + /* For devices, write to the config space index register */
> > > + idx = cfg_index(bus->number, devfn, 0);
> > > + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> > > + return base + DATA_ADDR(pcie) + where;
> > > +}
> > > +
> > > +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > > + unsigned int val)
> > > +{
> > > + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> > > + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > > +
> > > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> > > +}
> > > +
> > > +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> > > + unsigned int val)
> > > +{
> > > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> > > + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> > > + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> > > +}
> > > +
> > > +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie
> > > *pcie,
> > > + u64 *rc_bar2_size,
> > > + u64 *rc_bar2_offset)
> > > +{
> > > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > > + struct device *dev = pcie->dev;
> > > + struct resource_entry *entry;
> > > + u64 total_mem_size = 0;
> > > +
> > > + *rc_bar2_offset = -1;
> > > +
> > > + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> > > + /*
> > > + * We're promissed the RC will provide a contiguous view of
> >
> > s/promissed/promised/
>
> Corrected
>
> > > + * memory to downstream devices. We can then infer the
> > > + * rc_bar2_offset from the lower avaiable dma-range offset.
> > > + */
> > > + if (entry->offset < *rc_bar2_offset)
> > > + *rc_bar2_offset = entry->offset;
> > > +
> > > + total_mem_size += entry->res->end - entry->res->start + 1;
> > > + }
> > > +
> > > + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> > > +
> > > + /*
> > > + * Validate the results:
> > > + *
> > > + * The PCIe host controller by design must set the inbound viewport to
> > > + * be a contiguous arrangement of all of the system's memory. In
> > > + * addition, its size mut be a power of two. To further complicate
> > > + * matters, the viewport must start on a pcie-address that is aligned
> > > + * on a multiple of its size. If a portion of the viewport does not
> > > + * represent system memory -- e.g. 3GB of memory requires a 4GB
> > > + * viewport -- we can map the outbound memory in or after 3GB and even
> > > + * though the viewport will overlap the outbound memory the controller
> > > + * will know to send outbound memory downstream and everything else
> > > + * upstream.
> > > + *
> > > + * For example:
> > > + *
> > > + * - The best-case scenario, memory up to 3GB, is to place the inbound
> > > + * region in the first 4GB of pcie-space, as some legacy devices can
> > > + * only address 32bits. We would also like to put the MSI under 4GB
> > > + * as well, since some devices require a 32bit MSI target address.
> > > + *
> > > + * - If the system memory is 4GB or larger we cannot start the inbound
> > > + * region at location 0 (since we have to allow some space for
> > > + * outbound memory @ 3GB). So instead it will start at the 1x
> > > + * multiple of its size
> > > + */
> > > + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> > > + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> > > + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off
> > > 0x%llx\n",
> > > + *rc_bar2_size, *rc_bar2_offset);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > > +{
> > > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > > + u64 rc_bar2_offset, rc_bar2_size;
> > > + void __iomem *base = pcie->base;
> > > + struct resource_entry *entry;
> > > + unsigned int scb_size_val;
> > > + struct resource *res;
> > > + int num_out_wins = 0;
> > > + u32 tmp;
> > > + int i, j, ret, limit;
> > > + u16 nlw, cls, lnksta;
> > > + bool ssc_good = false;
> > > + struct device *dev = pcie->dev;
> > > +
> > > + /* Reset the bridge */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > +
> > > + usleep_range(100, 200);
> > > +
> > > + /* Take the bridge out of reset */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > > +
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > > + /* Wait for SerDes to be stable */
> > > + usleep_range(100, 200);
> > > +
> > > + /* Grab the PCIe hw revision number */
> > > + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> > > + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> >
> > This isn't used anywhere
>
> It's used by MSI further down the line.
>
> > > +
> > > + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> > > + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> > > + BURST_SIZE_128);
> > > + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> > > +
> > > + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> > > + &rc_bar2_offset);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + tmp = lower_32_bits(rc_bar2_offset);
> > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> > > + encode_ibar_size(rc_bar2_size));
> > > + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> > > + bcm_writel(upper_32_bits(rc_bar2_offset),
> > > + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> > > +
> > > + scb_size_val = rc_bar2_size ?
> > > + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> > > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> > > +
> > > + /* disable the PCIe->GISB memory window (RC_BAR1) */
> > > + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> > > +
> > > + /* disable the PCIe->SCB memory window (RC_BAR3) */
> > > + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> > > +
> > > + if (!pcie->suspended) {
> > > + /* clear any interrupts we find on boot */
> > > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> > > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> > > + }
> > > +
> > > + /* Mask all interrupts since we are not handling any yet */
> > > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > > +
> > > + if (pcie->gen)
> > > + set_gen(base, pcie->gen);
> > > +
> > > + /* Unassert the fundamental reset */
> > > + brcm_pcie_perst_set(pcie, 0);
> > > +
> > > + /*
> > > + * Give the RC/EP time to wake up, before trying to configure RC.
> > > + * Intermittently check status for link-up, up to a total of 100ms
> > > + * when we don't know if the device is there, and up to 1000ms if
> > > + * we do know the device is there.
> > > + */
> > > + limit = pcie->suspended ? 1000 : 100;
> > > + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> > > + j += i, i = i * 2)
> > > + msleep(i + j > limit ? limit - j : i);
> >
> > Does it need to be this complex? Also waiting a second during resume seems
> > like a long delay.
>
> I'll simplify it. I didn't want to change it as I assumed this is needed on
> some odd STB device. We'll deal with it once we enable it.
Thanks.
>
> > > +
> > > + if (!brcm_pcie_link_up(pcie)) {
> > > + dev_info(dev, "link down\n");
> > > + return -ENODEV;
> > > + }
> > > +
> > > + if (!brcm_pcie_rc_mode(pcie)) {
> > > + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + resource_list_for_each_entry(entry, &bridge->windows) {
> > > + res = entry->res;
> > > +
> > > + if (resource_type(res) != IORESOURCE_MEM)
> > > + continue;
> > > +
> > > + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> > > + dev_err(pcie->dev, "too many outbound wins\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> > > + res->start - entry->offset,
> > > + res->end - res->start + 1);
> > > + num_out_wins++;
> > > + }
> > > +
> > > + /*
> > > + * For config space accesses on the RC, show the right class for
> > > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > > + */
> > > + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> > > +
> > > + if (pcie->ssc) {
> > > + ret = set_ssc(base);
> > > + if (ret == 0)
> > > + ssc_good = true;
> > > + else
> > > + dev_err(dev, "failed attempt to enter ssc mode\n");
> > > + }
> > > +
> > > + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > > + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> > > + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> > > + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> > > + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> > > +
> > > + /* PCIe->SCB endian mode for BAR */
> > > + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> > > + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> > > + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> > > +
> > > + /*
> > > + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> > > + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> > > + */
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +/* L23 is a low-power PCIe link state */
> > > +static void enter_l23(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > + int l23, i;
> > > +
> > > + /* assert request for L23 */
> > > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > > +
> > > + /* Wait up to 30 msec for L23 */
> > > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > > + for (i = 0; i < 15 && !l23; i++) {
> > > + usleep_range(2000, 2400);
> > > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > > + }
> > > +
> > > + if (!l23)
> > > + dev_err(pcie->dev, "failed to enter L23\n");
> > > +}
> > > +
> > > +static void turn_off(struct brcm_pcie *pcie)
> > > +{
> > > + void __iomem *base = pcie->base;
> > > +
> > > + if (brcm_pcie_link_up(pcie))
> > > + enter_l23(pcie);
> > > + /* Assert fundamental reset */
> > > + brcm_pcie_perst_set(pcie, 1);
> > > + /* Deassert request for L23 in case it was asserted */
> > > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > > + /* Turn off SerDes */
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > > + /* Shutdown PCIe bridge */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > +}
> > > +
> > > +static int brcm_pcie_suspend(struct device *dev)
> > > +{
> > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > +
> > > + turn_off(pcie);
> > > + clk_disable_unprepare(pcie->clk);
> > > + pcie->suspended = true;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int brcm_pcie_resume(struct device *dev)
> > > +{
> > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > + void __iomem *base;
> > > + int ret;
> > > +
> > > + base = pcie->base;
> > > + clk_prepare_enable(pcie->clk);
> > > +
> > > + /* Take bridge out of reset so we can access the SerDes reg */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > > +
> > > + /* Turn on SerDes */
> > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > > + /* Wait for SerDes to be stable */
> > > + usleep_range(100, 200);
> > > +
> > > + ret = brcm_pcie_setup(pcie);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + pcie->suspended = false;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> >
> > I don't see the value in the first underscore here.
>
> It's value is that the real brcm_pcie_remove() and the probe failure cleanup
> routine share code. It saves some code duplication, that said I have no strong
> feelings about it.
That's OK then. However I think it's more common to use a double
underscore for functions like this.
>
> > > +{
> > > + turn_off(pcie);
> > > + clk_disable_unprepare(pcie->clk);
> > > + clk_put(pcie->clk);
> > > +}
> > > +
> > > +static int brcm_pcie_remove(struct platform_device *pdev)
> > > +{
> > > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > > +
> > > + pci_stop_root_bus(pcie->root_bus);
> > > + pci_remove_root_bus(pcie->root_bus);
> > > + _brcm_pcie_remove(pcie);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static const struct of_device_id brcm_pcie_match[] = {
> > > + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> > > + {},
> > > +};
> > > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > > +
> > > +static int brcm_pcie_probe(struct platform_device *pdev)
> > > +{
> > > + struct device_node *dn = pdev->dev.of_node;
> > > + const struct of_device_id *of_id;
> > > + const struct pcie_cfg_data *data;
> > > + struct resource *res;
> > > + int ret;
> > > + struct brcm_pcie *pcie;
> > > + void __iomem *base;
> > > + struct pci_host_bridge *bridge;
> > > + struct pci_bus *child;
> > > +
> > > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > > + if (!bridge)
> > > + return -ENOMEM;
> > > +
> > > + pcie = pci_host_bridge_priv(bridge);
> > > +
> > > + of_id = of_match_node(brcm_pcie_match, dn);
> > > + if (!of_id) {
> > > + dev_err(&pdev->dev, "failed to look up compatible string\n");
> > > + return -EINVAL;
> > > + }
> > > +
> > > + data = of_id->data;
> >
> > Can you replace the above (from of_match_node to here) with the following?
> >
> > data = of_device_get_match_data(pdev->dev)
>
> Yes, way cleaner.
>
> > > + pcie->reg_offsets = data->offsets;
> > > + pcie->reg_field_info = data->reg_field_info;
> > > + pcie->type = data->type;
> > > + pcie->dn = dn;
> > > + pcie->dev = &pdev->dev;
> > > +
> > > + /* We use the domain number as our controller number */
> > > + pcie->id = of_get_pci_domain_nr(dn);
> > > + if (pcie->id < 0)
> > > + return pcie->id;
> >
> > We don't do anything with this, so you can remove this.
>
> Deleted.
>
> > > +
> > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > + if (!res)
> > > + return -EINVAL;
> >
> > The majority of controller drivers don't bother to check the return value
> > here and just pass res into devm_ioremap_resource.
>
> Ok.
>
> > > +
> > > + base = devm_ioremap_resource(&pdev->dev, res);
> > > + if (IS_ERR(base))
> > > + return PTR_ERR(base);
> > > +
> > > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > > + if (IS_ERR(pcie->clk)) {
> > > + dev_err(&pdev->dev, "could not get clock\n");
> > > + pcie->clk = NULL;
> > > + }
> >
> > Is this a good use-case for devm_clk_get_optional?
>
> Yes.
>
> > > + pcie->base = base;
> > > +
> > > + ret = of_pci_get_max_link_speed(dn);
> > > + pcie->gen = (ret < 0) ? 0 : ret;
> >
> > There is no checking that gen isn't too large here, given that we pass
> > this into a register later we probably want to check it here.
>
> This is checked by of_pci_get_max_link_speed() internally:
>
> if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
> max_link_speed > 4)
> return -EINVAL;
>
> return max_link_speed;
Ah of course!
Thanks,
Andrew Murray
>
> > > +
> > > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > > +
> > > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > > + if (ret == 0)
> > > + /* keep going, as we don't use this intr yet */
> > > + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> > > + else
> > > + pcie->irq = ret;
> >
> > Given we don't use it yet, please remove it from this patch.
>
> OK
>
> Regards,
> Nicolas
>
Hi Stefan,
thanks for the review!
On Thu, 2019-11-07 at 18:50 +0100, Stefan Wahren wrote:
> Hi Nicolas,
>
> Am 06.11.19 um 22:45 schrieb Nicolas Saenz Julienne:
> > From: Jim Quinlan <[email protected]>
> >
> > This commit adds the basic Broadcom STB PCIe controller. Missing is the
> > ability to process MSI. This functionality is added in a subsequent
> > commit.
> >
> > The PCIe block contains an MDIO interface. This is a local interface
> > only accessible by the PCIe controller. It cannot be used or shared
> > by any other HW. As such, the small amount of code for this
> > controller is included in this driver as there is little upside to put
> > it elsewhere.
> >
> > This is based on Jim's original submission[1] but adapted and tailored
> > specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> > the rest of the brcmstb family will soon follow once we get support for
> > multiple dma-ranges in dma/direct.
> >
> > [1] https://patchwork.kernel.org/patch/10605959/
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > drivers/pci/controller/Kconfig | 12 +
> > drivers/pci/controller/Makefile | 1 +
> > drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> > 3 files changed, 986 insertions(+)
> > create mode 100644 drivers/pci/controller/pcie-brcmstb.c
> >
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index f5de9119e8d3..8b3aae91d8af 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -281,6 +281,18 @@ config VMD
> > To compile this driver as a module, choose M here: the
> > module will be called vmd.
> >
> > +config PCIE_BRCMSTB
> > + bool "Broadcom Brcmstb PCIe host controller"
> looking at the driver suggests me a tristate instead of bool.
> > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> please add ARCH_BCM2835 for the Raspberry Pi 4
> > + depends on OF
> > + depends on SOC_BRCMSTB
> Why is this needed?
It's not, I missed it. For now, I edited it so it only depends on ARCH_BCM2835.
> > + default ARCH_BRCMSTB || BMIPS_GENERIC
> also this needs ARCH_BCM2835
> > + help
> > + Say Y here to enable PCIe host controller support for
> > + Broadcom Settop Box SOCs. A Broadcom SOC will may have
> > + multiple host controllers as opposed to a single host
> > + controller with multiple ports.
> > +
> > config PCI_HYPERV_INTERFACE
> > tristate "Hyper-V PCI Interface"
> > depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> > diff --git a/drivers/pci/controller/Makefile
> > b/drivers/pci/controller/Makefile
> > index a2a22c9d91af..3fc0b0cf5b5b 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > obj-$(CONFIG_VMD) += vmd.o
> > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > obj-y += dwc/
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c
> > b/drivers/pci/controller/pcie-brcmstb.c
> > new file mode 100644
> > index 000000000000..880ec11d06a1
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -0,0 +1,973 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* Copyright (C) 2009 - 2019 Broadcom */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/compiler.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/ioport.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/kernel.h>
> > +#include <linux/list.h>
> > +#include <linux/log2.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pci.h>
> > +#include <linux/printk.h>
> > +#include <linux/sizes.h>
> > +#include <linux/slab.h>
> > +#include <linux/string.h>
> > +#include <linux/types.h>
> > +
> > +#include "../pci.h"
> > +
> > ...
> >
> > +
> > +/* L23 is a low-power PCIe link state */
> > +static void enter_l23(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + int l23, i;
> > +
> > + /* assert request for L23 */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > +
> > + /* Wait up to 30 msec for L23 */
> 36 msec?
Yes :)
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + for (i = 0; i < 15 && !l23; i++) {
> > + usleep_range(2000, 2400);
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + }
> > +
> > + if (!l23)
> > + dev_err(pcie->dev, "failed to enter L23\n");
>
> I think most user don't know anything about L23.
>
> How about:
>
> failed to enter low-power link state
Noted
> > +}
> > +
> > +static void turn_off(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > +
> > + if (brcm_pcie_link_up(pcie))
> > + enter_l23(pcie);
> > + /* Assert fundamental reset */
> > + brcm_pcie_perst_set(pcie, 1);
> > + /* Deassert request for L23 in case it was asserted */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > + /* Turn off SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > + /* Shutdown PCIe bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +}
> > +
> > +static int brcm_pcie_suspend(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > +
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + pcie->suspended = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_resume(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > + void __iomem *base;
> > + int ret;
> > +
> > + base = pcie->base;
> > + clk_prepare_enable(pcie->clk);
> > +
> > + /* Take bridge out of reset so we can access the SerDes reg */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + /* Turn on SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* Wait for SerDes to be stable */
> > + usleep_range(100, 200);
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + return ret;
> > +
> > + pcie->suspended = false;
> > +
> > + return 0;
> > +}
> > +
> > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> > +{
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + clk_put(pcie->clk);
> > +}
> > +
> > +static int brcm_pcie_remove(struct platform_device *pdev)
> > +{
> > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > +
> > + pci_stop_root_bus(pcie->root_bus);
> > + pci_remove_root_bus(pcie->root_bus);
> > + _brcm_pcie_remove(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id brcm_pcie_match[] = {
> > + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > +
> > +static int brcm_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *dn = pdev->dev.of_node;
> > + const struct of_device_id *of_id;
> > + const struct pcie_cfg_data *data;
> > + struct resource *res;
> > + int ret;
> > + struct brcm_pcie *pcie;
> > + void __iomem *base;
> > + struct pci_host_bridge *bridge;
> > + struct pci_bus *child;
> > +
> > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > + if (!bridge)
> > + return -ENOMEM;
> > +
> > + pcie = pci_host_bridge_priv(bridge);
> > +
> > + of_id = of_match_node(brcm_pcie_match, dn);
> > + if (!of_id) {
> > + dev_err(&pdev->dev, "failed to look up compatible string\n");
> > + return -EINVAL;
> > + }
> > +
> > + data = of_id->data;
> > + pcie->reg_offsets = data->offsets;
> > + pcie->reg_field_info = data->reg_field_info;
> > + pcie->type = data->type;
> > + pcie->dn = dn;
> > + pcie->dev = &pdev->dev;
> > +
> > + /* We use the domain number as our controller number */
> > + pcie->id = of_get_pci_domain_nr(dn);
> > + if (pcie->id < 0)
> > + return pcie->id;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -EINVAL;
> > +
> > + base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > + if (IS_ERR(pcie->clk)) {
> we should handle EPROBE_DEFER here
Yes, I'll keep it in mind.
> > + dev_err(&pdev->dev, "could not get clock\n");
> > + pcie->clk = NULL;
> > + }
> > + pcie->base = base;
> > +
> > + ret = of_pci_get_max_link_speed(dn);
> > + pcie->gen = (ret < 0) ? 0 : ret;
> > +
> > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > +
> > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > + if (ret == 0)
> > + /* keep going, as we don't use this intr yet */
> > + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> > + else
> > + pcie->irq = ret;
> > +
> > + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> > + &bridge->dma_ranges, NULL);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_prepare_enable(pcie->clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "could not enable clock\n");
> > + return ret;
> > + }
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + goto fail;
> > +
> > + bridge->dev.parent = &pdev->dev;
> > + bridge->busnr = 0;
> > + bridge->ops = &brcm_pcie_ops;
> > + bridge->sysdata = pcie;
> > + bridge->map_irq = of_irq_parse_and_map_pci;
> > + bridge->swizzle_irq = pci_common_swizzle;
> > +
> > + ret = pci_scan_root_bus_bridge(bridge);
> > + if (ret < 0) {
> > + dev_err(pcie->dev, "Scanning root bridge failed\n");
> > + goto fail;
> > + }
> > +
> > + pci_assign_unassigned_bus_resources(bridge->bus);
> > + list_for_each_entry(child, &bridge->bus->children, node)
> > + pcie_bus_configure_settings(child);
> > + pci_bus_add_devices(bridge->bus);
> > + platform_set_drvdata(pdev, pcie);
> > + pcie->root_bus = bridge->bus;
> > +
> > + return 0;
> > +
> > +fail:
> > + _brcm_pcie_remove(pcie);
> > + return ret;
> > +}
> > +
> > +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> > + .suspend_noirq = brcm_pcie_suspend,
> > + .resume_noirq = brcm_pcie_resume,
> > +};
> > +
> > +static struct platform_driver brcm_pcie_driver = {
> > + .probe = brcm_pcie_probe,
> > + .remove = brcm_pcie_remove,
> > + .driver = {
> > + .name = "brcm-pcie",
> > + .owner = THIS_MODULE,
> This is already done by module_platform_driver
Noted
> > + .of_match_table = brcm_pcie_match,
> > + .pm = &brcm_pcie_pm_ops,
> > + },
> > +};
> > +
> > +module_platform_driver(brcm_pcie_driver);
> > +
> > +MODULE_LICENSE("GPL v2");
>
> This is a mismatch to the SPDX (GPL 2 and higher), because this says GPL
> v2 only
Noted
Regards,
Nicolas
On Fri, Nov 8, 2019 at 5:52 AM Andrew Murray <[email protected]> wrote:
>
> On Thu, Nov 07, 2019 at 11:12:58AM -0500, Jim Quinlan wrote:
> > On Thu, Nov 7, 2019 at 10:05 AM Andrew Murray <[email protected]> wrote:
> > >
> > > Thanks for the patch, some initial feedback below, though I will give it a
> > > more detailed review on your respin.
> > >
> > > On Wed, Nov 06, 2019 at 10:45:25PM +0100, Nicolas Saenz Julienne wrote:
> > > > From: Jim Quinlan <[email protected]>
> > > >
> > > > This commit adds the basic Broadcom STB PCIe controller. Missing is the
> > > > ability to process MSI. This functionality is added in a subsequent
> > > > commit.
> > > >
> > > > The PCIe block contains an MDIO interface. This is a local interface
> > > > only accessible by the PCIe controller. It cannot be used or shared
> > > > by any other HW. As such, the small amount of code for this
> > > > controller is included in this driver as there is little upside to put
> > > > it elsewhere.
> > > >
> > > > This is based on Jim's original submission[1] but adapted and tailored
> > > > specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> > > > the rest of the brcmstb family will soon follow once we get support for
> > > > multiple dma-ranges in dma/direct.
> > >
> > > This commit message is very informative and helpful, though I feel a lot
> > > of this isn't relevant for a commit message (especially as much of it is
> > > time based comments). Instead it would be better to simply describe what
> > > the patch does provide, and any additional helpful notes can be provided
> > > under the '---' after the signed off (which won't make it into git).
> > >
> > > >
> > > > [1] https://patchwork.kernel.org/patch/10605959/
> > > >
> > > > Signed-off-by: Jim Quinlan <[email protected]>
> > > > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > > > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > > > ---
> > > > drivers/pci/controller/Kconfig | 12 +
> > > > drivers/pci/controller/Makefile | 1 +
> > > > drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> > > > 3 files changed, 986 insertions(+)
> > > > create mode 100644 drivers/pci/controller/pcie-brcmstb.c
> > > >
> > > > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > > > index f5de9119e8d3..8b3aae91d8af 100644
> > > > --- a/drivers/pci/controller/Kconfig
> > > > +++ b/drivers/pci/controller/Kconfig
> > > > @@ -281,6 +281,18 @@ config VMD
> > > > To compile this driver as a module, choose M here: the
> > > > module will be called vmd.
> > > >
> > > > +config PCIE_BRCMSTB
> > > > + bool "Broadcom Brcmstb PCIe host controller"
> > > > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> > >
> > > I can't see what ARCH_BRCMSTB adds here. Given this also depends
> > > on SOC_BRCMSTB. Are all of these depends really necessary?
> > >
> > > Also should the bool be "Broadcom STB PCIe host contoller" ?
> > >
> > > > + depends on OF
> > > > + depends on SOC_BRCMSTB
> > > > + default ARCH_BRCMSTB || BMIPS_GENERIC
> > >
> > > Please also include COMPILE_TEST in here (look at the other controllers
> > > in the file). This helps improve testing coverage by compiling all drivers
> > > even if they can't be run.
> > >
> > > > + help
> > > > + Say Y here to enable PCIe host controller support for
> > > > + Broadcom Settop Box SOCs. A Broadcom SOC will may have
> > >
> > > s/Settop/Set top/ or s/Settop/STB/?
> > >
> > > > + multiple host controllers as opposed to a single host
> > > > + controller with multiple ports.
> > >
> > > I'm sure many other SOCs may have multiple controllers instead of one
> > > with multiple ports. I'm not sure what value this adds here. It's
> > > always better to describe enough information so the user can determine
> > > if this option will enable something they want on their hardware.
> > >
> > > > +
> > > > config PCI_HYPERV_INTERFACE
> > > > tristate "Hyper-V PCI Interface"
> > > > depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> > > > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> > > > index a2a22c9d91af..3fc0b0cf5b5b 100644
> > > > --- a/drivers/pci/controller/Makefile
> > > > +++ b/drivers/pci/controller/Makefile
> > > > @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > > > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> > > > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > > > obj-$(CONFIG_VMD) += vmd.o
> > > > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > > > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > > > obj-y += dwc/
> > > >
> > > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > > > new file mode 100644
> > > > index 000000000000..880ec11d06a1
> > > > --- /dev/null
> > > > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > > > @@ -0,0 +1,973 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/* Copyright (C) 2009 - 2019 Broadcom */
> > > > +
> > > > +#include <linux/clk.h>
> > > > +#include <linux/compiler.h>
> > > > +#include <linux/delay.h>
> > > > +#include <linux/init.h>
> > > > +#include <linux/interrupt.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/ioport.h>
> > > > +#include <linux/irqdomain.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/list.h>
> > > > +#include <linux/log2.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/of_address.h>
> > > > +#include <linux/of_irq.h>
> > > > +#include <linux/of_pci.h>
> > > > +#include <linux/of_platform.h>
> > > > +#include <linux/pci.h>
> > > > +#include <linux/printk.h>
> > > > +#include <linux/sizes.h>
> > > > +#include <linux/slab.h>
> > > > +#include <linux/string.h>
> > > > +#include <linux/types.h>
> > > > +
> > > > +#include "../pci.h"
> > >
> > > Is this last include needed? Sometimes controller drivers suffer from copy and
> > > paste and this is often included when it isn't needed.
> > >
> > > > +
> > > > +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> > > > +#define BRCM_PCIE_CAP_REGS 0x00ac
> > > > +
> > > > +/*
> > > > + * Broadcom Settop Box PCIe Register Offsets. The names are from
> > > > + * the chip's RDB and we use them here so that a script can correlate
> > > > + * this code and the RDB to prevent discrepancies.
> > > > + */
> > > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> > > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > > > +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> > > > +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > > > +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > > > +#define PCIE_MISC_MISC_CTRL 0x4008
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> > > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> > > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > > > +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > > > +#define PCIE_MISC_PCIE_CTRL 0x4064
> > > > +#define PCIE_MISC_PCIE_STATUS 0x4068
> > > > +#define PCIE_MISC_REVISION 0x406c
> > >
> > > PCIE_MISC_REVISION can be removed as it shouldn't be needed
> > >
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > > > +#define PCIE_INTR2_CPU_BASE 0x4300
> > > > +
> > > > +/*
> > > > + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> > > > + * names are from the chip's RDB and we use them here so that a script
> > > > + * can correlate this code and the RDB to prevent discrepancies.
> > > > + */
> > > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
> > > > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
> > > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> > > > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> > > > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> > > > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> > > > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> > > > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> > > > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> > > > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> > > > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> > > > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> > > > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> > > > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> > > > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> > > > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> > > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> > > > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> > > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> > > > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> > > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> > > > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> > > > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> > > > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> > > > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> > > > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> > > > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> > > > +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> > > > +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> > > > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> > > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> > > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> > > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> > > > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> > > > +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> > > > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
> > >
> > > Most of the above aren't used anywhere, please remove them.
> > >
> > > > +
> > > > +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> > > > +#define BRCM_MAX_SCB 0x4
> > > > +
> > > > +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > > > +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> > >
> > > These two aren't used.
> > >
> > > > +
> > > > +#define BURST_SIZE_128 0
> > > > +#define BURST_SIZE_256 1
> > > > +#define BURST_SIZE_512 2
> > > > +
> > > > +/* Offsets from PCIE_INTR2_CPU_BASE */
> > > > +#define STATUS 0x0
> > > > +#define SET 0x4
> > > > +#define CLR 0x8
> > > > +#define MASK_STATUS 0xc
> > > > +#define MASK_SET 0x10
> > > > +#define MASK_CLR 0x14
> > >
> > > Some of the above are not used anywhere.
> > >
> > > > +
> > > > +#define PCIE_BUSNUM_SHIFT 20
> > > > +#define PCIE_SLOT_SHIFT 15
> > > > +#define PCIE_FUNC_SHIFT 12
> > > > +
> > > > +#if defined(__BIG_ENDIAN)
> > > > +#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */
> > > > +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */
> > > > +#else
> > > > +#define DATA_ENDIAN 0
> > > > +#define MMIO_ENDIAN 0
> > > > +#endif
> > > > +
> > > > +#define MDIO_PORT0 0x0
> > > > +#define MDIO_DATA_MASK 0x7fffffff
> > > > +#define MDIO_DATA_SHIFT 0x0
> > > > +#define MDIO_PORT_MASK 0xf0000
> > > > +#define MDIO_PORT_SHIFT 0x16
> > > > +#define MDIO_REGAD_MASK 0xffff
> > > > +#define MDIO_REGAD_SHIFT 0x0
> > > > +#define MDIO_CMD_MASK 0xfff00000
> > > > +#define MDIO_CMD_SHIFT 0x14
> > > > +#define MDIO_CMD_READ 0x1
> > > > +#define MDIO_CMD_WRITE 0x0
> > > > +#define MDIO_DATA_DONE_MASK 0x80000000
> > > > +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
> > > > +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
> > > > +#define SSC_REGS_ADDR 0x1100
> > > > +#define SET_ADDR_OFFSET 0x1f
> > > > +#define SSC_CNTL_OFFSET 0x2
> > > > +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> > > > +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> > > > +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> > > > +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> > > > +#define SSC_STATUS_OFFSET 0x1
> > > > +#define SSC_STATUS_SSC_MASK 0x400
> > > > +#define SSC_STATUS_SSC_SHIFT 0xa
> > > > +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> > > > +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> > > > +
> > > > +#define IDX_ADDR(pcie) \
> > > > + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> > > > +#define DATA_ADDR(pcie) \
> > > > + ((pcie)->reg_offsets[EXT_CFG_DATA])
> > > > +#define PCIE_RGR1_SW_INIT_1(pcie) \
> > > > + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> > > > +
> > > > +enum {
> > > > + RGR1_SW_INIT_1,
> > > > + EXT_CFG_INDEX,
> > > > + EXT_CFG_DATA,
> > > > +};
> > > > +
> > > > +enum {
> > > > + RGR1_SW_INIT_1_INIT_MASK,
> > > > + RGR1_SW_INIT_1_INIT_SHIFT,
> > > > + RGR1_SW_INIT_1_PERST_MASK,
> > > > + RGR1_SW_INIT_1_PERST_SHIFT,
> > > > +};
> > > > +
> > > > +enum pcie_type {
> > > > + BCM2711,
> > > > +};
> > > > +
> > > > +struct brcm_window {
> > > > + dma_addr_t pcie_addr;
> > > > + phys_addr_t cpu_addr;
> > > > + dma_addr_t size;
> > > > +};
> > > > +
> > > > +/* Internal PCIe Host Controller Information.*/
> > > > +struct brcm_pcie {
> > > > + struct device *dev;
> > > > + void __iomem *base;
> > > > + int irq;
> > >
> > > 'irq' isn't used and can be removed.
> > >
> > > > + struct clk *clk;
> > > > + struct pci_bus *root_bus;
> > > > + struct device_node *dn;
> > > > + int id;
> > >
> > > 'id' isn't used and can be removed.
> > >
> > > > + bool suspended;
> > > > + bool ssc;
> > > > + int gen;
> > > > + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > > > + unsigned int rev;
> > >
> > > 'rev' isn't used and can be removed.
> > >
> > > > + const int *reg_offsets;
> > > > + const int *reg_field_info;
> > > > + enum pcie_type type;
> > > > +};
> > > > +
> > > > +struct pcie_cfg_data {
> > > > + const int *reg_field_info;
> > > > + const int *offsets;
> > > > + const enum pcie_type type;
> > > > +};
> > > > +
> > > > +static const int pcie_reg_field_info[] = {
> > > > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> > > > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> > > > +};
> > > > +
> > > > +static const int pcie_offset_bcm2711[] = {
> > > > + [RGR1_SW_INIT_1] = 0x9210,
> > > > + [EXT_CFG_INDEX] = 0x9000,
> > > > + [EXT_CFG_DATA] = 0x8000,
> > > > +};
> > > > +
> > > > +static const struct pcie_cfg_data bcm2711_cfg = {
> > > > + .reg_field_info = pcie_reg_field_info,
> > > > + .offsets = pcie_offset_bcm2711,
> > > > + .type = BCM2711,
> > > > +};
> > > > +
> > > > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> > > > + int where);
> > > > +
> > > > +static struct pci_ops brcm_pcie_ops = {
> > > > + .map_bus = brcm_pcie_map_conf,
> > > > + .read = pci_generic_config_read,
> > > > + .write = pci_generic_config_write,
> > > > +};
> > > > +
> > > > +#define bcm_readl(a) readl(a)
> > > > +#define bcm_writel(d, a) writel(d, a)
> > > > +#define bcm_readw(a) readw(a)
> > > > +#define bcm_writew(d, a) writew(d, a)
> > >
> > > Is there much value in these macros?
> > >
> > > > +
> > > > +/* These macros extract/insert fields to host controller's register set. */
> > > > +#define RD_FLD(base, reg, field) \
> > > > + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> > > > +#define WR_FLD(base, reg, field, val) \
> > > > + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> > > > +#define WR_FLD_RB(base, reg, field, val) \
> > > > + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> > > > + reg##_##field##_SHIFT, val)
> > > > +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> > > > + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> > > > + reg##_##field##_SHIFT, val)
> > > > +#define EXTRACT_FIELD(val, reg, field) \
> > > > + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> > > > +#define INSERT_FIELD(val, reg, field, field_val) \
> > > > + (((val) & ~reg##_##field##_MASK) | \
> > > > + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> > > > +
> > > > +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> > > > +{
> > > > + return (bcm_readl(p) & mask) >> shift;
> > > > +}
> > > > +
> > > > +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> > > > +{
> > > > + u32 reg = bcm_readl(p);
> > > > +
> > > > + reg = (reg & ~mask) | ((val << shift) & mask);
> > > > + bcm_writel(reg, p);
> > > > +}
> > > > +
> > > > +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> > > > +{
> > > > + wr_fld(p, mask, shift, val);
> > > > + (void)bcm_readl(p);
> > > > +}
> > > > +
> > > > +static const char *link_speed_to_str(int s)
> > > > +{
> > > > + switch (s) {
> > > > + case 1:
> > > > + return "2.5";
> > > > + case 2:
> > > > + return "5.0";
> > > > + case 3:
> > > > + return "8.0";
> > > > + default:
> > > > + break;
> > > > + }
> > > > + return "???";
> > > > +}
> > > > +
> > > > +/*
> > > > + * The roundup_pow_of_two() from log2.h invokes
> > > > + * __roundup_pow_of_two(unsigned long), but we really need a
> > > > + * such a function to take a native u64 since unsigned long
> > > > + * is 32 bits on some configurations. So we provide this helper
> > > > + * function below.
> > > > + */
> > > > +static u64 roundup_pow_of_two_64(u64 n)
> > > > +{
> > > > + return 1ULL << fls64(n - 1);
> > > > +}
> > >
> > > Given that you use this in one place and that it is a single line, I'd
> > > suggest you just drop this function. Alternatively if you wanted to add
> > > this function to log2.h then you already have a bunch of users ready to
> > > be migrated to it:
> > >
> > > $ git grep "<< fls64"
> > > arch/sparc/mm/init_64.c: m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
> > > drivers/net/ethernet/mellanox/mlx4/en_clock.c: u64 max_val_cycles_rounded = 1ULL << fls64(max_val_cycles - 1);
> > > drivers/pci/controller/pcie-cadence-ep.c: sz = 1ULL << fls64(sz - 1);
> > > drivers/pci/controller/pcie-cadence.c: u64 sz = 1ULL << fls64(size - 1);
> > > drivers/pci/controller/pcie-rockchip-ep.c: u64 sz = 1ULL << fls64(size - 1);
> > > drivers/pci/controller/pcie-rockchip-ep.c: sz = 1ULL << fls64(sz - 1);
> > >
> > >
> > > > +
> > > > +/*
> > > > + * This is to convert the size of the inbound "BAR" region to the
> > > > + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> > > > + */
> > > > +int encode_ibar_size(u64 size)
> > > > +{
> > > > + int log2_in = ilog2(size);
> > > > +
> > > > + if (log2_in >= 12 && log2_in <= 15)
> > > > + /* Covers 4KB to 32KB (inclusive) */
> > > > + return (log2_in - 12) + 0x1c;
> > > > + else if (log2_in >= 16 && log2_in <= 37)
> > > > + /* Covers 64KB to 32GB, (inclusive) */
> > >
> > > 2^37 != 32GB?
> > Comment should be changed
> > /* Current chips implement 64KB to 32GB; allow up to 128GB for
> > future chips */
> > or the value should be changed:
> > s/37/35/;
> > >
> > > > + return log2_in - 15;
> > > > + /* Something is awry so disable */
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static u32 mdio_form_pkt(int port, int regad, int cmd)
> > > > +{
> > > > + u32 pkt = 0;
> > > > +
> > > > + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> > > > + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> > > > + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> > > > +
> > > > + return pkt;
> > > > +}
> > > > +
> > > > +/* negative return value indicates error */
> > > > +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> > > > +{
> > > > + int tries;
> > > > + u32 data;
> > > > +
> > > > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> > > > + base + PCIE_RC_DL_MDIO_ADDR);
> > > > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > > > +
> > > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > > > + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> > > > + udelay(10);
> > > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > > > + }
> > > > +
> > > > + return MDIO_RD_DONE(data)
> > > > + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> > > > + : -EIO;
> > > > +}
> > > > +
> > > > +/* negative return value indicates error */
> > > > +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> > > > +{
> > > > + int tries;
> > > > + u32 data;
> > > > +
> > > > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> > > > + base + PCIE_RC_DL_MDIO_ADDR);
> > > > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > > > + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> > > > + base + PCIE_RC_DL_MDIO_WR_DATA);
> > > > +
> > > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > > > + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> > > > + udelay(10);
> > > > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > > > + }
> > > > +
> > > > + return MDIO_WT_DONE(data) ? 0 : -EIO;
> > > > +}
> > > > +
> > > > +/*
> > > > + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> > > > + * return value indicates error.
> > > > + */
> > > > +static int set_ssc(void __iomem *base)
> > >
> > > Please prefix this with brcm_pcie_ (and other similar occurances)
> > >
> > > > +{
> > > > + int tmp;
> > > > + u16 wrdata;
> > > > + int pll, ssc;
> > > > +
> > > > + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> > > > + if (tmp < 0)
> > > > + return tmp;
> > > > +
> > > > + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> > > > + if (tmp < 0)
> > > > + return tmp;
> > > > +
> > > > + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> > > > + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> > > > + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> > > > + if (tmp < 0)
> > > > + return tmp;
> > > > +
> > > > + usleep_range(1000, 2000);
> > > > + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> > > > + if (tmp < 0)
> > > > + return tmp;
> > > > +
> > > > + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> > > > + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
> > > > +
> > > > + return (ssc && pll) ? 0 : -EIO;
> > > > +}
> > > > +
> > > > +/* Limits operation to a specific generation (1, 2, or 3) */
> > > > +static void set_gen(void __iomem *base, int gen)
> > > > +{
> > > > + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > > > + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > > > +
> > > > + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> > > > + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > > > +
> > > > + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> > > > + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > > > +}
> > > > +
> > > > +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> > > > + unsigned int win, phys_addr_t cpu_addr,
> > > > + dma_addr_t pcie_addr, dma_addr_t size)
> > > > +{
> > > > + void __iomem *base = pcie->base;
> > > > + phys_addr_t cpu_addr_mb, limit_addr_mb;
> > > > + u32 tmp;
> > > > +
> > > > + /* Set the base of the pcie_addr window */
> > > > + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> > > > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> > > > + bcm_writel(upper_32_bits(pcie_addr),
> > > > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> > > > +
> > > > + cpu_addr_mb = cpu_addr >> 20;
> > > > + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> > > > +
> > > > + /* Write the addr base low register */
> > > > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > > > + BASE, cpu_addr_mb);
> > > > + /* Write the addr limit low register */
> > > > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > > > + LIMIT, limit_addr_mb);
> > > > +
> > > > + /* Write the cpu addr high register */
> > > > + tmp = (u32)(cpu_addr_mb >>
> > > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > > > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> > > > + BASE, tmp);
> > > > + /* Write the cpu limit high register */
> > > > + tmp = (u32)(limit_addr_mb >>
> > > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > > > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > > > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> > > > + LIMIT, tmp);
> > > > +}
> > > > +
> > > > +/* Configuration space read/write support */
> > > > +static int cfg_index(int busnr, int devfn, int reg)
> > > > +{
> > > > + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> > > > + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> > > > + | (busnr << PCIE_BUSNUM_SHIFT)
> > > > + | (reg & ~3);
> > > > +}
> > > > +
> > > > +/* The controller is capable of serving in both RC and EP roles */
> > > > +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> > > > +{
> > > > + void __iomem *base = pcie->base;
> > > > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > > > +
> > > > + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> > > > +}
> > > > +
> > > > +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> > > > +{
> > > > + void __iomem *base = pcie->base;
> > > > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > > > + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> > > > + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> > > > +
> > > > + return (dla && plu) ? true : false;
> > > > +}
> > > > +
> > > > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> > > > + int where)
> > > > +{
> > > > + struct brcm_pcie *pcie = bus->sysdata;
> > > > + void __iomem *base = pcie->base;
> > > > + int idx;
> > > > +
> > > > + /* Accesses to the RC go right to the RC registers if slot==0 */
> > > > + if (pci_is_root_bus(bus))
> > > > + return PCI_SLOT(devfn) ? NULL : base + where;
> > > > +
> > > > + /* For devices, write to the config space index register */
> > > > + idx = cfg_index(bus->number, devfn, 0);
> > > > + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> > > > + return base + DATA_ADDR(pcie) + where;
> > > > +}
> > > > +
> > > > +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > > > + unsigned int val)
> > > > +{
> > > > + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> > > > + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > > > +
> > > > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> > > > +}
> > > > +
> > > > +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> > > > + unsigned int val)
> > > > +{
> > > > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> > > > + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> > > > + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> > > > +}
> > > > +
> > > > +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> > > > + u64 *rc_bar2_size,
> > > > + u64 *rc_bar2_offset)
> > > > +{
> > > > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > > > + struct device *dev = pcie->dev;
> > > > + struct resource_entry *entry;
> > > > + u64 total_mem_size = 0;
> > > > +
> > > > + *rc_bar2_offset = -1;
> > > > +
> > > > + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> > > > + /*
> > > > + * We're promissed the RC will provide a contiguous view of
> > >
> > > s/promissed/promised/
> > >
> > > > + * memory to downstream devices. We can then infer the
> > > > + * rc_bar2_offset from the lower avaiable dma-range offset.
> > > > + */
> > > > + if (entry->offset < *rc_bar2_offset)
> > > > + *rc_bar2_offset = entry->offset;
> > > > +
> > > > + total_mem_size += entry->res->end - entry->res->start + 1;
> > > > + }
> > > > +
> > > > + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> > > > +
> > > > + /*
> > > > + * Validate the results:
> > > > + *
> > > > + * The PCIe host controller by design must set the inbound viewport to
> > > > + * be a contiguous arrangement of all of the system's memory. In
> > > > + * addition, its size mut be a power of two. To further complicate
> > > > + * matters, the viewport must start on a pcie-address that is aligned
> > > > + * on a multiple of its size. If a portion of the viewport does not
> > > > + * represent system memory -- e.g. 3GB of memory requires a 4GB
> > > > + * viewport -- we can map the outbound memory in or after 3GB and even
> > > > + * though the viewport will overlap the outbound memory the controller
> > > > + * will know to send outbound memory downstream and everything else
> > > > + * upstream.
> > > > + *
> > > > + * For example:
> > > > + *
> > > > + * - The best-case scenario, memory up to 3GB, is to place the inbound
> > > > + * region in the first 4GB of pcie-space, as some legacy devices can
> > > > + * only address 32bits. We would also like to put the MSI under 4GB
> > > > + * as well, since some devices require a 32bit MSI target address.
> > > > + *
> > > > + * - If the system memory is 4GB or larger we cannot start the inbound
> > > > + * region at location 0 (since we have to allow some space for
> > > > + * outbound memory @ 3GB). So instead it will start at the 1x
> > > > + * multiple of its size
> > > > + */
> > > > + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> > > > + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> > > > + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
> > > > + *rc_bar2_size, *rc_bar2_offset);
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > > > +{
> > > > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > > > + u64 rc_bar2_offset, rc_bar2_size;
> > > > + void __iomem *base = pcie->base;
> > > > + struct resource_entry *entry;
> > > > + unsigned int scb_size_val;
> > > > + struct resource *res;
> > > > + int num_out_wins = 0;
> > > > + u32 tmp;
> > > > + int i, j, ret, limit;
> > > > + u16 nlw, cls, lnksta;
> > > > + bool ssc_good = false;
> > > > + struct device *dev = pcie->dev;
> > > > +
> > > > + /* Reset the bridge */
> > > > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > > +
> > > > + usleep_range(100, 200);
> > > > +
> > > > + /* Take the bridge out of reset */
> > > > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > > > +
> > > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > > > + /* Wait for SerDes to be stable */
> > > > + usleep_range(100, 200);
> > > > +
> > > > + /* Grab the PCIe hw revision number */
> > > > + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> > > > + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> > >
> > > This isn't used anywhere
> > >
> > > > +
> > > > + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> > > > + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> > > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> > > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> > > > + BURST_SIZE_128);
> > > > + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
> > > > +
> > > > + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> > > > + &rc_bar2_offset);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + tmp = lower_32_bits(rc_bar2_offset);
> > > > + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> > > > + encode_ibar_size(rc_bar2_size));
> > > > + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> > > > + bcm_writel(upper_32_bits(rc_bar2_offset),
> > > > + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> > > > +
> > > > + scb_size_val = rc_bar2_size ?
> > > > + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> > > > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> > > > +
> > > > + /* disable the PCIe->GISB memory window (RC_BAR1) */
> > > > + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> > > > +
> > > > + /* disable the PCIe->SCB memory window (RC_BAR3) */
> > > > + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> > > > +
> > > > + if (!pcie->suspended) {
> > > > + /* clear any interrupts we find on boot */
> > > > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> > > > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> > > > + }
> > > > +
> > > > + /* Mask all interrupts since we are not handling any yet */
> > > > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > > > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > > > +
> > > > + if (pcie->gen)
> > > > + set_gen(base, pcie->gen);
> > > > +
> > > > + /* Unassert the fundamental reset */
> > > > + brcm_pcie_perst_set(pcie, 0);
> > > > +
> > > > + /*
> > > > + * Give the RC/EP time to wake up, before trying to configure RC.
> > > > + * Intermittently check status for link-up, up to a total of 100ms
> > > > + * when we don't know if the device is there, and up to 1000ms if
> > > > + * we do know the device is there.
> > > > + */
> > > > + limit = pcie->suspended ? 1000 : 100;
> > > > + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> > > > + j += i, i = i * 2)
> > > > + msleep(i + j > limit ? limit - j : i);
> > >
> > > Does it need to be this complex? Also waiting a second during resume seems
> > > like a long delay.
> >
> > Agree on the complexity issue. But we've had EP chips that required
> > this much time on a resume for reasons unknown. Code could be
> > changed to something like
> > for (i = 0; i <= limit; i += 100)
> > if (brcm_pcie_link_up(pcie)
> > break;
> > else
> > msleep(100);
>
> This is an improvement. If the reasons are unknown how are you confident that
> 1 second is enough?
IIRC, the biggest delay I ever observed on resume was ~600ms, so 1sec
seemed a reasonable compromise.. Sometimes customers select the
cheapest/oldest EP to do the job and their choice occasionally comes
with atypical behavior.
Thanks, Jim
>
> >
> > >
> > > > +
> > > > + if (!brcm_pcie_link_up(pcie)) {
> > > > + dev_info(dev, "link down\n");
> > > > + return -ENODEV;
> > > > + }
> > > > +
> > > > + if (!brcm_pcie_rc_mode(pcie)) {
> > > > + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + resource_list_for_each_entry(entry, &bridge->windows) {
> > > > + res = entry->res;
> > > > +
> > > > + if (resource_type(res) != IORESOURCE_MEM)
> > > > + continue;
> > > > +
> > > > + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> > > > + dev_err(pcie->dev, "too many outbound wins\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> > > > + res->start - entry->offset,
> > > > + res->end - res->start + 1);
> > > > + num_out_wins++;
> > > > + }
> > > > +
> > > > + /*
> > > > + * For config space accesses on the RC, show the right class for
> > > > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > > > + */
> > > > + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> > > > +
> > > > + if (pcie->ssc) {
> > > > + ret = set_ssc(base);
> > > > + if (ret == 0)
> > > > + ssc_good = true;
> > > > + else
> > > > + dev_err(dev, "failed attempt to enter ssc mode\n");
> > > > + }
> > > > +
> > > > + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > > > + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> > > > + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> > > > + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> > > > + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> > > > +
> > > > + /* PCIe->SCB endian mode for BAR */
> > > > + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> > > > + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> > > > + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> > > > +
> > > > + /*
> > > > + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> > > > + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> > > > + */
> > > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +/* L23 is a low-power PCIe link state */
> > > > +static void enter_l23(struct brcm_pcie *pcie)
> > > > +{
> > > > + void __iomem *base = pcie->base;
> > > > + int l23, i;
> > > > +
> > > > + /* assert request for L23 */
> > > > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > > > +
> > > > + /* Wait up to 30 msec for L23 */
> > > > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > > > + for (i = 0; i < 15 && !l23; i++) {
> > > > + usleep_range(2000, 2400);
> > > > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > > > + }
> > > > +
> > > > + if (!l23)
> > > > + dev_err(pcie->dev, "failed to enter L23\n");
> > > > +}
> > > > +
> > > > +static void turn_off(struct brcm_pcie *pcie)
> > > > +{
> > > > + void __iomem *base = pcie->base;
> > > > +
> > > > + if (brcm_pcie_link_up(pcie))
> > > > + enter_l23(pcie);
> > > > + /* Assert fundamental reset */
> > > > + brcm_pcie_perst_set(pcie, 1);
> > > > + /* Deassert request for L23 in case it was asserted */
> > > > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > > > + /* Turn off SerDes */
> > > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > > > + /* Shutdown PCIe bridge */
> > > > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > > +}
> > > > +
> > > > +static int brcm_pcie_suspend(struct device *dev)
> > > > +{
> > > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > > +
> > > > + turn_off(pcie);
> > > > + clk_disable_unprepare(pcie->clk);
> > > > + pcie->suspended = true;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int brcm_pcie_resume(struct device *dev)
> > > > +{
> > > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > > + void __iomem *base;
> > > > + int ret;
> > > > +
> > > > + base = pcie->base;
> > > > + clk_prepare_enable(pcie->clk);
> > > > +
> > > > + /* Take bridge out of reset so we can access the SerDes reg */
> > > > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > > > +
> > > > + /* Turn on SerDes */
> > > > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > > > + /* Wait for SerDes to be stable */
> > > > + usleep_range(100, 200);
> > > > +
> > > > + ret = brcm_pcie_setup(pcie);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + pcie->suspended = false;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> > >
> > > I don't see the value in the first underscore here.
> > We have a function _brcm_pcie_remove() and a function
> > brcm_pciie_remove(). The former is invoked by the latter, but the
> > former is also invoked later in the code as well.
>
> That's OK, missed this.
>
> Thanks,
>
> Andrew Murray
>
> >
> > Jim Quinlan
> > Broadcom
> >
> > >
> > > > +{
> > > > + turn_off(pcie);
> > > > + clk_disable_unprepare(pcie->clk);
> > > > + clk_put(pcie->clk);
> > > > +}
> > > > +
> > > > +static int brcm_pcie_remove(struct platform_device *pdev)
> > > > +{
> > > > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > > > +
> > > > + pci_stop_root_bus(pcie->root_bus);
> > > > + pci_remove_root_bus(pcie->root_bus);
> > > > + _brcm_pcie_remove(pcie);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static const struct of_device_id brcm_pcie_match[] = {
> > > > + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> > > > + {},
> > > > +};
> > > > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > > > +
> > > > +static int brcm_pcie_probe(struct platform_device *pdev)
> > > > +{
> > > > + struct device_node *dn = pdev->dev.of_node;
> > > > + const struct of_device_id *of_id;
> > > > + const struct pcie_cfg_data *data;
> > > > + struct resource *res;
> > > > + int ret;
> > > > + struct brcm_pcie *pcie;
> > > > + void __iomem *base;
> > > > + struct pci_host_bridge *bridge;
> > > > + struct pci_bus *child;
> > > > +
> > > > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > > > + if (!bridge)
> > > > + return -ENOMEM;
> > > > +
> > > > + pcie = pci_host_bridge_priv(bridge);
> > > > +
> > > > + of_id = of_match_node(brcm_pcie_match, dn);
> > > > + if (!of_id) {
> > > > + dev_err(&pdev->dev, "failed to look up compatible string\n");
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + data = of_id->data;
> > >
> > > Can you replace the above (from of_match_node to here) with the following?
> > >
> > > data = of_device_get_match_data(pdev->dev)
> > >
> > > > + pcie->reg_offsets = data->offsets;
> > > > + pcie->reg_field_info = data->reg_field_info;
> > > > + pcie->type = data->type;
> > > > + pcie->dn = dn;
> > > > + pcie->dev = &pdev->dev;
> > > > +
> > > > + /* We use the domain number as our controller number */
> > > > + pcie->id = of_get_pci_domain_nr(dn);
> > > > + if (pcie->id < 0)
> > > > + return pcie->id;
> > >
> > > We don't do anything with this, so you can remove this.
> > >
> > > > +
> > > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > > > + if (!res)
> > > > + return -EINVAL;
> > >
> > > The majority of controller drivers don't bother to check the return value
> > > here and just pass res into devm_ioremap_resource.
> > >
> > > > +
> > > > + base = devm_ioremap_resource(&pdev->dev, res);
> > > > + if (IS_ERR(base))
> > > > + return PTR_ERR(base);
> > > > +
> > > > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > > > + if (IS_ERR(pcie->clk)) {
> > > > + dev_err(&pdev->dev, "could not get clock\n");
> > > > + pcie->clk = NULL;
> > > > + }
> > >
> > > Is this a good use-case for devm_clk_get_optional?
> > >
> > > > + pcie->base = base;
> > > > +
> > > > + ret = of_pci_get_max_link_speed(dn);
> > > > + pcie->gen = (ret < 0) ? 0 : ret;
> > >
> > > There is no checking that gen isn't too large here, given that we pass
> > > this into a register later we probably want to check it here.
> > >
> > > > +
> > > > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > > > +
> > > > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > > > + if (ret == 0)
> > > > + /* keep going, as we don't use this intr yet */
> > > > + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> > > > + else
> > > > + pcie->irq = ret;
> > >
> > > Given we don't use it yet, please remove it from this patch.
> > >
> > > > +
> > > > + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> > > > + &bridge->dma_ranges, NULL);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + ret = clk_prepare_enable(pcie->clk);
> > > > + if (ret) {
> > > > + dev_err(&pdev->dev, "could not enable clock\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = brcm_pcie_setup(pcie);
> > > > + if (ret)
> > > > + goto fail;
> > > > +
> > > > + bridge->dev.parent = &pdev->dev;
> > > > + bridge->busnr = 0;
> > > > + bridge->ops = &brcm_pcie_ops;
> > > > + bridge->sysdata = pcie;
> > > > + bridge->map_irq = of_irq_parse_and_map_pci;
> > > > + bridge->swizzle_irq = pci_common_swizzle;
> > > > +
> > > > + ret = pci_scan_root_bus_bridge(bridge);
> > > > + if (ret < 0) {
> > > > + dev_err(pcie->dev, "Scanning root bridge failed\n");
> > > > + goto fail;
> > > > + }
> > > > +
> > > > + pci_assign_unassigned_bus_resources(bridge->bus);
> > > > + list_for_each_entry(child, &bridge->bus->children, node)
> > > > + pcie_bus_configure_settings(child);
> > > > + pci_bus_add_devices(bridge->bus);
> > > > + platform_set_drvdata(pdev, pcie);
> > > > + pcie->root_bus = bridge->bus;
> > > > +
> > > > + return 0;
> > > > +
> > > > +fail:
> > > > + _brcm_pcie_remove(pcie);
> > > > + return ret;
> > > > +}
> > > > +
> > > > +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> > > > + .suspend_noirq = brcm_pcie_suspend,
> > > > + .resume_noirq = brcm_pcie_resume,
> > > > +};
> > > > +
> > > > +static struct platform_driver brcm_pcie_driver = {
> > > > + .probe = brcm_pcie_probe,
> > > > + .remove = brcm_pcie_remove,
> > > > + .driver = {
> > > > + .name = "brcm-pcie",
> > > > + .owner = THIS_MODULE,
> > > > + .of_match_table = brcm_pcie_match,
> > > > + .pm = &brcm_pcie_pm_ops,
> > > > + },
> > > > +};
> > > > +
> > > > +module_platform_driver(brcm_pcie_driver);
> > > > +
> > > > +MODULE_LICENSE("GPL v2");
> > > > +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
> > > > +MODULE_AUTHOR("Broadcom");
> > > > --
> > > > 2.23.0
> > > >
Hi,
On 11/6/19 3:45 PM, Nicolas Saenz Julienne wrote:
> From: Jim Quinlan <[email protected]>
>
> This commit adds the basic Broadcom STB PCIe controller. Missing is the
> ability to process MSI. This functionality is added in a subsequent
> commit.
>
> The PCIe block contains an MDIO interface. This is a local interface
> only accessible by the PCIe controller. It cannot be used or shared
> by any other HW. As such, the small amount of code for this
> controller is included in this driver as there is little upside to put
> it elsewhere.
>
> This is based on Jim's original submission[1] but adapted and tailored
> specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> the rest of the brcmstb family will soon follow once we get support for
> multiple dma-ranges in dma/direct.
>
> [1] https://patchwork.kernel.org/patch/10605959/
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> drivers/pci/controller/Kconfig | 12 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> 3 files changed, 986 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-brcmstb.c
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index f5de9119e8d3..8b3aae91d8af 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -281,6 +281,18 @@ config VMD
> To compile this driver as a module, choose M here: the
> module will be called vmd.
>
> +config PCIE_BRCMSTB
> + bool "Broadcom Brcmstb PCIe host controller"
> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> + depends on OF
> + depends on SOC_BRCMSTB
> + default ARCH_BRCMSTB || BMIPS_GENERIC
> + help
> + Say Y here to enable PCIe host controller support for
> + Broadcom Settop Box SOCs. A Broadcom SOC will may have
> + multiple host controllers as opposed to a single host
> + controller with multiple ports.
> +
> config PCI_HYPERV_INTERFACE
> tristate "Hyper-V PCI Interface"
> depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index a2a22c9d91af..3fc0b0cf5b5b 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> obj-y += dwc/
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> new file mode 100644
> index 000000000000..880ec11d06a1
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -0,0 +1,973 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright (C) 2009 - 2019 Broadcom */
> +
> +#include <linux/clk.h>
> +#include <linux/compiler.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/log2.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/pci.h>
> +#include <linux/printk.h>
> +#include <linux/sizes.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +
> +#include "../pci.h"
> +
> +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> +#define BRCM_PCIE_CAP_REGS 0x00ac
> +
> +/*
> + * Broadcom Settop Box PCIe Register Offsets. The names are from
> + * the chip's RDB and we use them here so that a script can correlate
> + * this code and the RDB to prevent discrepancies.
> + */
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> +#define PCIE_MISC_MISC_CTRL 0x4008
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> +#define PCIE_MISC_PCIE_CTRL 0x4064
> +#define PCIE_MISC_PCIE_STATUS 0x4068
> +#define PCIE_MISC_REVISION 0x406c
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> +#define PCIE_INTR2_CPU_BASE 0x4300
> +
> +/*
> + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> + * names are from the chip's RDB and we use them here so that a script
> + * can correlate this code and the RDB to prevent discrepancies.
> + */
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
> +
> +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> +#define BRCM_MAX_SCB 0x4
> +
> +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> +
> +#define BURST_SIZE_128 0
> +#define BURST_SIZE_256 1
> +#define BURST_SIZE_512 2
> +
> +/* Offsets from PCIE_INTR2_CPU_BASE */
> +#define STATUS 0x0
> +#define SET 0x4
> +#define CLR 0x8
> +#define MASK_STATUS 0xc
> +#define MASK_SET 0x10
> +#define MASK_CLR 0x14
> +
> +#define PCIE_BUSNUM_SHIFT 20
> +#define PCIE_SLOT_SHIFT 15
> +#define PCIE_FUNC_SHIFT 12
> +
> +#if defined(__BIG_ENDIAN)
> +#define DATA_ENDIAN 2 /* PCIe->DDR inbound traffic */
> +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound traffic */
> +#else
> +#define DATA_ENDIAN 0
> +#define MMIO_ENDIAN 0
> +#endif
> +
> +#define MDIO_PORT0 0x0
> +#define MDIO_DATA_MASK 0x7fffffff
> +#define MDIO_DATA_SHIFT 0x0
> +#define MDIO_PORT_MASK 0xf0000
> +#define MDIO_PORT_SHIFT 0x16
> +#define MDIO_REGAD_MASK 0xffff
> +#define MDIO_REGAD_SHIFT 0x0
> +#define MDIO_CMD_MASK 0xfff00000
> +#define MDIO_CMD_SHIFT 0x14
> +#define MDIO_CMD_READ 0x1
> +#define MDIO_CMD_WRITE 0x0
> +#define MDIO_DATA_DONE_MASK 0x80000000
> +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
> +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
> +#define SSC_REGS_ADDR 0x1100
> +#define SET_ADDR_OFFSET 0x1f
> +#define SSC_CNTL_OFFSET 0x2
> +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> +#define SSC_STATUS_OFFSET 0x1
> +#define SSC_STATUS_SSC_MASK 0x400
> +#define SSC_STATUS_SSC_SHIFT 0xa
> +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> +
> +#define IDX_ADDR(pcie) \
> + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> +#define DATA_ADDR(pcie) \
> + ((pcie)->reg_offsets[EXT_CFG_DATA])
> +#define PCIE_RGR1_SW_INIT_1(pcie) \
> + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> +
> +enum {
> + RGR1_SW_INIT_1,
> + EXT_CFG_INDEX,
> + EXT_CFG_DATA,
> +};
> +
> +enum {
> + RGR1_SW_INIT_1_INIT_MASK,
> + RGR1_SW_INIT_1_INIT_SHIFT,
> + RGR1_SW_INIT_1_PERST_MASK,
> + RGR1_SW_INIT_1_PERST_SHIFT,
> +};
> +
> +enum pcie_type {
> + BCM2711,
> +};
> +
> +struct brcm_window {
> + dma_addr_t pcie_addr;
> + phys_addr_t cpu_addr;
> + dma_addr_t size;
> +};
> +
> +/* Internal PCIe Host Controller Information.*/
> +struct brcm_pcie {
> + struct device *dev;
> + void __iomem *base;
> + int irq;
> + struct clk *clk;
> + struct pci_bus *root_bus;
> + struct device_node *dn;
> + int id;
> + bool suspended;
> + bool ssc;
> + int gen;
> + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> + unsigned int rev;
> + const int *reg_offsets;
> + const int *reg_field_info;
> + enum pcie_type type;
> +};
> +
> +struct pcie_cfg_data {
> + const int *reg_field_info;
> + const int *offsets;
> + const enum pcie_type type;
> +};
> +
> +static const int pcie_reg_field_info[] = {
> + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> +};
> +
> +static const int pcie_offset_bcm2711[] = {
> + [RGR1_SW_INIT_1] = 0x9210,
> + [EXT_CFG_INDEX] = 0x9000,
> + [EXT_CFG_DATA] = 0x8000,
> +};
Given that there is currently only a single set of register offsets,
this seems like it could be simpler.
> +
> +static const struct pcie_cfg_data bcm2711_cfg = {
> + .reg_field_info = pcie_reg_field_info,
> + .offsets = pcie_offset_bcm2711,
> + .type = BCM2711,
> +};
> +
> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> + int where);
> +
> +static struct pci_ops brcm_pcie_ops = {
> + .map_bus = brcm_pcie_map_conf,
> + .read = pci_generic_config_read,
> + .write = pci_generic_config_write,
> +};
> +
> +#define bcm_readl(a) readl(a)
> +#define bcm_writel(d, a) writel(d, a)
> +#define bcm_readw(a) readw(a)
> +#define bcm_writew(d, a) writew(d, a)
> +
> +/* These macros extract/insert fields to host controller's register set. */
> +#define RD_FLD(base, reg, field) \
> + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> +#define WR_FLD(base, reg, field, val) \
> + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> +#define WR_FLD_RB(base, reg, field, val) \
> + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> + reg##_##field##_SHIFT, val)
> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> + reg##_##field##_SHIFT, val)
> +#define EXTRACT_FIELD(val, reg, field) \
> + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> +#define INSERT_FIELD(val, reg, field, field_val) \
> + (((val) & ~reg##_##field##_MASK) | \
> + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> +
> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> +{
> + return (bcm_readl(p) & mask) >> shift;
> +}
> +
> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> + u32 reg = bcm_readl(p);
> +
> + reg = (reg & ~mask) | ((val << shift) & mask);
> + bcm_writel(reg, p);
> +}
> +
> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> +{
> + wr_fld(p, mask, shift, val);
> + (void)bcm_readl(p);
> +}
> +
> +static const char *link_speed_to_str(int s)
> +{
> + switch (s) {
> + case 1:
> + return "2.5";
> + case 2:
> + return "5.0";
> + case 3:
> + return "8.0";
> + default:
> + break;
> + }
> + return "???";
> +}
> +
> +/*
> + * The roundup_pow_of_two() from log2.h invokes
> + * __roundup_pow_of_two(unsigned long), but we really need a
> + * such a function to take a native u64 since unsigned long
> + * is 32 bits on some configurations. So we provide this helper
> + * function below.
> + */
> +static u64 roundup_pow_of_two_64(u64 n)
> +{
> + return 1ULL << fls64(n - 1);
> +}
> +
> +/*
> + * This is to convert the size of the inbound "BAR" region to the
> + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> + */
> +int encode_ibar_size(u64 size)
> +{
> + int log2_in = ilog2(size);
> +
> + if (log2_in >= 12 && log2_in <= 15)
> + /* Covers 4KB to 32KB (inclusive) */
> + return (log2_in - 12) + 0x1c;
> + else if (log2_in >= 16 && log2_in <= 37)
> + /* Covers 64KB to 32GB, (inclusive) */
> + return log2_in - 15;
> + /* Something is awry so disable */
> + return 0;
> +}
> +
> +static u32 mdio_form_pkt(int port, int regad, int cmd)
> +{
> + u32 pkt = 0;
> +
> + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> +
> + return pkt;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> +{
> + int tries;
> + u32 data;
> +
> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> + base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> +
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> + udelay(10);
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> + }
> +
> + return MDIO_RD_DONE(data)
> + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> + : -EIO;
> +}
> +
> +/* negative return value indicates error */
> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> +{
> + int tries;
> + u32 data;
> +
> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> + base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> + base + PCIE_RC_DL_MDIO_WR_DATA);
> +
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> + udelay(10);
> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> + }
> +
> + return MDIO_WT_DONE(data) ? 0 : -EIO;
> +}
> +
> +/*
> + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> + * return value indicates error.
> + */
> +static int set_ssc(void __iomem *base)
> +{
> + int tmp;
> + u16 wrdata;
> + int pll, ssc;
> +
> + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> + if (tmp < 0)
> + return tmp;
> +
> + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> + if (tmp < 0)
> + return tmp;
> +
> + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> + if (tmp < 0)
> + return tmp;
> +
> + usleep_range(1000, 2000);
> + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> + if (tmp < 0)
> + return tmp;
> +
> + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
This is actually the PCIe phy?
> +
> + return (ssc && pll) ? 0 : -EIO;
> +}
> +
> +/* Limits operation to a specific generation (1, 2, or 3) */
> +static void set_gen(void __iomem *base, int gen)
> +{
> + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> +
> + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> +
> + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> +}
> +
> +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> + unsigned int win, phys_addr_t cpu_addr,
> + dma_addr_t pcie_addr, dma_addr_t size)
> +{
> + void __iomem *base = pcie->base;
> + phys_addr_t cpu_addr_mb, limit_addr_mb;
> + u32 tmp;
> +
> + /* Set the base of the pcie_addr window */
> + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> + bcm_writel(upper_32_bits(pcie_addr),
> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> +
> + cpu_addr_mb = cpu_addr >> 20;
> + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> +
> + /* Write the addr base low register */
> + WR_FLD_WITH_OFFSET(base, (win * 4),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> + BASE, cpu_addr_mb);
> + /* Write the addr limit low register */
> + WR_FLD_WITH_OFFSET(base, (win * 4),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> + LIMIT, limit_addr_mb);
> +
> + /* Write the cpu addr high register */
> + tmp = (u32)(cpu_addr_mb >>
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> + WR_FLD_WITH_OFFSET(base, (win * 8),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> + BASE, tmp);
> + /* Write the cpu limit high register */
> + tmp = (u32)(limit_addr_mb >>
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> + WR_FLD_WITH_OFFSET(base, (win * 8),
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> + LIMIT, tmp);
> +}
So this is translating a high CPU address to a <32-bit PCI MMIO window?
I thought there was some kind of 32-bit limitation in front of this root
port? This makes it sound like the root port can recieve 64-bit MMIO
writes just fine. IIRC XHCI can run with just two 64-bit BARS, so it
sounds like the translation here isn't strictly nessisary until someone
wants a 32-bit non-prefechable bar. No?
> +
> +/* Configuration space read/write support */
> +static int cfg_index(int busnr, int devfn, int reg)
> +{
> + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> + | (busnr << PCIE_BUSNUM_SHIFT)
> + | (reg & ~3);
> +}
> +
> +/* The controller is capable of serving in both RC and EP roles */
> +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> +
> + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> +}
> +
> +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> +
> + return (dla && plu) ? true : false;
> +}
> +
> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
> + int where)
> +{
> + struct brcm_pcie *pcie = bus->sysdata;
> + void __iomem *base = pcie->base;
> + int idx;
> +
> + /* Accesses to the RC go right to the RC registers if slot==0 */
> + if (pci_is_root_bus(bus))
> + return PCI_SLOT(devfn) ? NULL : base + where;
> +
> + /* For devices, write to the config space index register */
> + idx = cfg_index(bus->number, devfn, 0);
> + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> + return base + DATA_ADDR(pcie) + where;
> +}
So, each pci cfg space access requires a cfg register write, so that the
data space for the bdf can be accessed?
Using map_bus() to setup the cfg region rather than overriding the
generic read/write callbacks means that in the future we can't enable
PCI_LOCKLESS_CONFIG in a generic arm64 kernel.
> +
> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> + unsigned int val)
> +{
> + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> +
> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> +}
> +
> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> + unsigned int val)
> +{
> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> +}
> +
> +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
> + u64 *rc_bar2_size,
> + u64 *rc_bar2_offset)
> +{
> + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> + struct device *dev = pcie->dev;
> + struct resource_entry *entry;
> + u64 total_mem_size = 0;
> +
> + *rc_bar2_offset = -1;
> +
> + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> + /*
> + * We're promissed the RC will provide a contiguous view of
> + * memory to downstream devices. We can then infer the
> + * rc_bar2_offset from the lower avaiable dma-range offset.
> + */
> + if (entry->offset < *rc_bar2_offset)
> + *rc_bar2_offset = entry->offset;
> +
> + total_mem_size += entry->res->end - entry->res->start + 1;
> + }
> +
> + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> +
> + /*
> + * Validate the results:
> + *
> + * The PCIe host controller by design must set the inbound viewport to
> + * be a contiguous arrangement of all of the system's memory. In
> + * addition, its size mut be a power of two. To further complicate
> + * matters, the viewport must start on a pcie-address that is aligned
> + * on a multiple of its size. If a portion of the viewport does not
> + * represent system memory -- e.g. 3GB of memory requires a 4GB
> + * viewport -- we can map the outbound memory in or after 3GB and even
> + * though the viewport will overlap the outbound memory the controller
> + * will know to send outbound memory downstream and everything else
> + * upstream.
> + *
> + * For example:
> + *
> + * - The best-case scenario, memory up to 3GB, is to place the inbound
> + * region in the first 4GB of pcie-space, as some legacy devices can
> + * only address 32bits. We would also like to put the MSI under 4GB
> + * as well, since some devices require a 32bit MSI target address.
> + *
> + * - If the system memory is 4GB or larger we cannot start the inbound
> + * region at location 0 (since we have to allow some space for
> + * outbound memory @ 3GB). So instead it will start at the 1x
> + * multiple of its size
> + */
> + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
> + *rc_bar2_size, *rc_bar2_offset);
> + return -EINVAL;
> + }
If the MMIO window isn't translated and is left high, does it work to
just use a single 0->$TOP_OF_RAM mapping, even with the 32-bit
limitation? Or is the 32-bit limitation comming from this programming?
> +
> + return 0;
> +}
> +
> +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> +{
> + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> + u64 rc_bar2_offset, rc_bar2_size;
> + void __iomem *base = pcie->base;
> + struct resource_entry *entry;
> + unsigned int scb_size_val;
> + struct resource *res;
> + int num_out_wins = 0;
> + u32 tmp;
> + int i, j, ret, limit;
> + u16 nlw, cls, lnksta;
> + bool ssc_good = false;
> + struct device *dev = pcie->dev;
> +
> + /* Reset the bridge */
> + brcm_pcie_bridge_sw_init_set(pcie, 1);
> +
> + usleep_range(100, 200);
> +
> + /* Take the bridge out of reset */
> + brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> + /* Wait for SerDes to be stable */
> + usleep_range(100, 200);
> +
> + /* Grab the PCIe hw revision number */
> + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> +
> + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> + BURST_SIZE_128);
> + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
Presumablly users will want to use PCIe at some point in the future for
booting/etc. That means the firmware will perform sufficient setup that
you shouldn't need much of the code in this function if the address
windows, serdes, etc are functional when linux boots. Similarly for
suspend/resume.
> +
> + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> + &rc_bar2_offset);
> + if (ret)
> + return ret;
> +
> + tmp = lower_32_bits(rc_bar2_offset);
> + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> + encode_ibar_size(rc_bar2_size));
> + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> + bcm_writel(upper_32_bits(rc_bar2_offset),
> + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> +
> + scb_size_val = rc_bar2_size ?
> + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> +
> + /* disable the PCIe->GISB memory window (RC_BAR1) */
> + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> +
> + /* disable the PCIe->SCB memory window (RC_BAR3) */
> + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> +
> + if (!pcie->suspended) {
> + /* clear any interrupts we find on boot */
> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> + }
> +
> + /* Mask all interrupts since we are not handling any yet */
> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> +
> + if (pcie->gen)
> + set_gen(base, pcie->gen);
> +
> + /* Unassert the fundamental reset */
> + brcm_pcie_perst_set(pcie, 0);
> +
> + /*
> + * Give the RC/EP time to wake up, before trying to configure RC.
> + * Intermittently check status for link-up, up to a total of 100ms
> + * when we don't know if the device is there, and up to 1000ms if
> + * we do know the device is there.
> + */
> + limit = pcie->suspended ? 1000 : 100;
> + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> + j += i, i = i * 2)
> + msleep(i + j > limit ? limit - j : i);
> +
> + if (!brcm_pcie_link_up(pcie)) {
> + dev_info(dev, "link down\n");
> + return -ENODEV;
> + }
> +
> + if (!brcm_pcie_rc_mode(pcie)) {
> + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> + return -EINVAL;
> + }
> +
> + resource_list_for_each_entry(entry, &bridge->windows) {
> + res = entry->res;
> +
> + if (resource_type(res) != IORESOURCE_MEM)
> + continue;
> +
> + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> + dev_err(pcie->dev, "too many outbound wins\n");
> + return -EINVAL;
> + }
> +
> + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> + res->start - entry->offset,
> + res->end - res->start + 1);
> + num_out_wins++;
> + }
> +
> + /*
> + * For config space accesses on the RC, show the right class for
> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> + */
> + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> +
> + if (pcie->ssc) {
> + ret = set_ssc(base);
> + if (ret == 0)
> + ssc_good = true;
> + else
> + dev_err(dev, "failed attempt to enter ssc mode\n");
> + }
> +
> + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> +
> + /* PCIe->SCB endian mode for BAR */
> + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> +
> + /*
> + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> + */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> +
> + return 0;
> +}
> +
> +/* L23 is a low-power PCIe link state */
> +static void enter_l23(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> + int l23, i;
> +
> + /* assert request for L23 */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> +
> + /* Wait up to 30 msec for L23 */
> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> + for (i = 0; i < 15 && !l23; i++) {
> + usleep_range(2000, 2400);
> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> + }
> +
> + if (!l23)
> + dev_err(pcie->dev, "failed to enter L23\n");
> +}
> +
> +static void turn_off(struct brcm_pcie *pcie)
> +{
> + void __iomem *base = pcie->base;
> +
> + if (brcm_pcie_link_up(pcie))
> + enter_l23(pcie);
> + /* Assert fundamental reset */
> + brcm_pcie_perst_set(pcie, 1);
> + /* Deassert request for L23 in case it was asserted */
> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> + /* Turn off SerDes */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> + /* Shutdown PCIe bridge */
> + brcm_pcie_bridge_sw_init_set(pcie, 1);
> +}
> +
> +static int brcm_pcie_suspend(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> +
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + pcie->suspended = true;
> +
> + return 0;
> +}
> +
> +static int brcm_pcie_resume(struct device *dev)
> +{
> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> + void __iomem *base;
> + int ret;
> +
> + base = pcie->base;
> + clk_prepare_enable(pcie->clk);
> +
> + /* Take bridge out of reset so we can access the SerDes reg */
> + brcm_pcie_bridge_sw_init_set(pcie, 0);
> +
> + /* Turn on SerDes */
> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> + /* Wait for SerDes to be stable */
> + usleep_range(100, 200);
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + return ret;
> +
> + pcie->suspended = false;
> +
> + return 0;
> +}
> +
> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> +{
> + turn_off(pcie);
> + clk_disable_unprepare(pcie->clk);
> + clk_put(pcie->clk);
> +}
> +
> +static int brcm_pcie_remove(struct platform_device *pdev)
> +{
> + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> +
> + pci_stop_root_bus(pcie->root_bus);
> + pci_remove_root_bus(pcie->root_bus);
> + _brcm_pcie_remove(pcie);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id brcm_pcie_match[] = {
> + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> +
> +static int brcm_pcie_probe(struct platform_device *pdev)
> +{
> + struct device_node *dn = pdev->dev.of_node;
> + const struct of_device_id *of_id;
> + const struct pcie_cfg_data *data;
> + struct resource *res;
> + int ret;
> + struct brcm_pcie *pcie;
> + void __iomem *base;
> + struct pci_host_bridge *bridge;
> + struct pci_bus *child;
> +
> + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> + if (!bridge)
> + return -ENOMEM;
> +
> + pcie = pci_host_bridge_priv(bridge);
> +
> + of_id = of_match_node(brcm_pcie_match, dn);
> + if (!of_id) {
> + dev_err(&pdev->dev, "failed to look up compatible string\n");
> + return -EINVAL;
> + }
> +
> + data = of_id->data;
> + pcie->reg_offsets = data->offsets;
> + pcie->reg_field_info = data->reg_field_info;
> + pcie->type = data->type;
> + pcie->dn = dn;
> + pcie->dev = &pdev->dev;
> +
> + /* We use the domain number as our controller number */
> + pcie->id = of_get_pci_domain_nr(dn);
> + if (pcie->id < 0)
> + return pcie->id;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -EINVAL;
> +
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> + if (IS_ERR(pcie->clk)) {
> + dev_err(&pdev->dev, "could not get clock\n");
> + pcie->clk = NULL;
> + }
Is there a sw_pcie clock in the system?
> + pcie->base = base;
> +
> + ret = of_pci_get_max_link_speed(dn);
> + pcie->gen = (ret < 0) ? 0 : ret;
> +
> + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> +
> + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> + if (ret == 0)
> + /* keep going, as we don't use this intr yet */
> + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> + else
> + pcie->irq = ret;
> +
> + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> + &bridge->dma_ranges, NULL);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(pcie->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "could not enable clock\n");
> + return ret;
> + }
> +
> + ret = brcm_pcie_setup(pcie);
> + if (ret)
> + goto fail;
> +
> + bridge->dev.parent = &pdev->dev;
> + bridge->busnr = 0;
> + bridge->ops = &brcm_pcie_ops;
> + bridge->sysdata = pcie;
> + bridge->map_irq = of_irq_parse_and_map_pci;
> + bridge->swizzle_irq = pci_common_swizzle;
> +
> + ret = pci_scan_root_bus_bridge(bridge);
> + if (ret < 0) {
> + dev_err(pcie->dev, "Scanning root bridge failed\n");
> + goto fail;
> + }
> +
> + pci_assign_unassigned_bus_resources(bridge->bus);
> + list_for_each_entry(child, &bridge->bus->children, node)
> + pcie_bus_configure_settings(child);
> + pci_bus_add_devices(bridge->bus);
> + platform_set_drvdata(pdev, pcie);
> + pcie->root_bus = bridge->bus;
> +
> + return 0;
> +
> +fail:
> + _brcm_pcie_remove(pcie);
> + return ret;
> +}
> +
> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> + .suspend_noirq = brcm_pcie_suspend,
> + .resume_noirq = brcm_pcie_resume,
> +};
> +
> +static struct platform_driver brcm_pcie_driver = {
> + .probe = brcm_pcie_probe,
> + .remove = brcm_pcie_remove,
> + .driver = {
> + .name = "brcm-pcie",
> + .owner = THIS_MODULE,
> + .of_match_table = brcm_pcie_match,
> + .pm = &brcm_pcie_pm_ops,
> + },
> +};
> +
> +module_platform_driver(brcm_pcie_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
> +MODULE_AUTHOR("Broadcom");
>
Hi Marc,
thanks for the review!
On Thu, 2019-11-07 at 16:49 +0109, Marc Zyngier wrote:
> On 2019-11-06 22:54, Nicolas Saenz Julienne wrote:
> > From: Jim Quinlan <[email protected]>
> >
> > This commit adds MSI to the Broadcom STB PCIe host controller. It
> > does
> > not add MSIX since that functionality is not in the HW. The MSI
> > controller is physically located within the PCIe block, however,
> > there
> > is no reason why the MSI controller could not be moved elsewhere in
> > the future.
> >
> > Since the internal Brcmstb MSI controller is intertwined with the
> > PCIe
> > controller, it is not its own platform device but rather part of the
> > PCIe platform device.
> >
> > This is based on Jim's original submission[1] with some slight
> > changes
> > regarding how pcie->msi_target_addr is decided.
> >
> > [1] https://patchwork.kernel.org/patch/10605955/
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > drivers/pci/controller/Kconfig | 2 +-
> > drivers/pci/controller/pcie-brcmstb.c | 333
> > +++++++++++++++++++++++++-
> > 2 files changed, 332 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/Kconfig
> > b/drivers/pci/controller/Kconfig
> > index 8b3aae91d8af..99b972ad3f2f 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -284,7 +284,7 @@ config VMD
> > config PCIE_BRCMSTB
> > bool "Broadcom Brcmstb PCIe host controller"
> > depends on ARCH_BRCMSTB || BMIPS_GENERIC
> > - depends on OF
> > + depends on OF && PCI_MSI
> > depends on SOC_BRCMSTB
> > default ARCH_BRCMSTB || BMIPS_GENERIC
> > help
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c
> > b/drivers/pci/controller/pcie-brcmstb.c
> > index 880ec11d06a1..26053e69b95f 100644
> > --- a/drivers/pci/controller/pcie-brcmstb.c
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -1,6 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0
> > /* Copyright (C) 2009 - 2019 Broadcom */
> >
> > +#include <linux/bitops.h>
> > #include <linux/clk.h>
> > #include <linux/compiler.h>
> > #include <linux/delay.h>
> > @@ -8,11 +9,13 @@
> > #include <linux/interrupt.h>
> > #include <linux/io.h>
> > #include <linux/ioport.h>
> > +#include <linux/irqchip/chained_irq.h>
> > #include <linux/irqdomain.h>
> > #include <linux/kernel.h>
> > #include <linux/list.h>
> > #include <linux/log2.h>
> > #include <linux/module.h>
> > +#include <linux/msi.h>
> > #include <linux/of_address.h>
> > #include <linux/of_irq.h>
> > #include <linux/of_pci.h>
> > @@ -46,6 +49,9 @@
> > #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > +#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
> > +#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
> > +#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
> > #define PCIE_MISC_PCIE_CTRL 0x4064
> > #define PCIE_MISC_PCIE_STATUS 0x4068
> > #define PCIE_MISC_REVISION 0x406c
> > @@ -54,6 +60,7 @@
> > #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > #define PCIE_INTR2_CPU_BASE 0x4300
> > +#define PCIE_MSI_INTR2_BASE 0x4500
> >
> > /*
> > * Broadcom Settop Box PCIe Register Field shift and mask info. The
> > @@ -114,6 +121,8 @@
> >
> > #define BRCM_NUM_PCIE_OUT_WINS 0x4
> > #define BRCM_MAX_SCB 0x4
> > +#define BRCM_INT_PCI_MSI_NR 32
> > +#define BRCM_PCIE_HW_REV_33 0x0303
> >
> > #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> > @@ -199,6 +208,33 @@ struct brcm_window {
> > dma_addr_t size;
> > };
> >
> > +struct brcm_msi {
> > + struct device *dev;
> > + void __iomem *base;
> > + struct device_node *dn;
> > + struct irq_domain *msi_domain;
> > + struct irq_domain *inner_domain;
> > + struct mutex lock; /* guards the alloc/free operations */
> > + u64 target_addr;
> > + int irq;
> > +
> > + /* intr_base is the base pointer for interrupt status/set/clr regs
> > */
> > + void __iomem *intr_base;
> > +
> > + /* intr_legacy_mask indicates how many bits are MSI interrupts */
> > + u32 intr_legacy_mask;
> > +
> > + /*
> > + * intr_legacy_offset indicates bit position of MSI_01. It is
> > + * to map the register bit position to a hwirq that starts at 0.
> > + */
> > + u32 intr_legacy_offset;
> > +
> > + /* used indicates which MSI interrupts have been alloc'd */
> > + unsigned long used;
> > + unsigned int rev;
> > +};
> > +
> > /* Internal PCIe Host Controller Information.*/
> > struct brcm_pcie {
> > struct device *dev;
> > @@ -211,7 +247,10 @@ struct brcm_pcie {
> > bool suspended;
> > bool ssc;
> > int gen;
> > + u64 msi_target_addr;
> > struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > + struct brcm_msi *msi;
> > + bool msi_internal;
>
> Do you need both of these fields? Is there any case where msi is valid
> and msi_internal is false?
You're right, got rid of msi_internal.
>
> > unsigned int rev;
> > const int *reg_offsets;
> > const int *reg_field_info;
> > @@ -477,6 +516,267 @@ static void brcm_pcie_set_outbound_win(struct
> > brcm_pcie *pcie,
> > LIMIT, tmp);
> > }
> >
> > +static struct irq_chip brcm_msi_irq_chip = {
> > + .name = "Brcm_MSI",
> > + .irq_mask = pci_msi_mask_irq,
> > + .irq_unmask = pci_msi_unmask_irq,
> > +};
> > +
> > +static struct msi_domain_info brcm_msi_domain_info = {
> > + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> > + MSI_FLAG_PCI_MSIX),
>
> Is there a particular reason for not supporting MultiMSI? I won't miss
> it, but it might be worth documenting the restriction if the HW cannot
> support it (though I can't immediately see why).
There is no actual restriction. As Jim tells me, there never was the need for
it. If it's fine with you, we'll leave that as an enhancement for the future,
specially since the RPi's XHCI device only uses one MSI interrupt.
> > + .chip = &brcm_msi_irq_chip,
> > +};
> > +
> > +static void brcm_pcie_msi_isr(struct irq_desc *desc)
> > +{
> > + struct irq_chip *chip = irq_desc_get_chip(desc);
> > + struct brcm_msi *msi;
> > + unsigned long status, virq;
> > + u32 mask, bit, hwirq;
> > + struct device *dev;
> > +
> > + chained_irq_enter(chip, desc);
> > + msi = irq_desc_get_handler_data(desc);
> > + mask = msi->intr_legacy_mask;
> > + dev = msi->dev;
> > +
> > + while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
>
> Is this loop really worth it? If, as I imagine, this register is at the
> end of a wet piece of string, this additional read (likely to return
> zero)
> will have a measurable latency impact...
I think this one was cargo-culted, TBH this pattern is all over the place.
Though, now that you point it out, I can't really provide a justification for
it. Maybe Jim can contradict me here, but It's working fine without it.
> > + for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
> > + /* clear the interrupt */
> > + bcm_writel(1 << bit, msi->intr_base + CLR);
> > +
> > + /* Account for legacy interrupt offset */
> > + hwirq = bit - msi->intr_legacy_offset;
> > +
> > + virq = irq_find_mapping(msi->inner_domain, hwirq);
> > + if (virq) {
> > + if (msi->used & (1 << hwirq))
> > + generic_handle_irq(virq);
> > + else
> > + dev_info(dev, "unhandled MSI %d\n",
> > + hwirq);
>
> Can this ever happen? If you've found the mapping in the irqdomain,
> the MSI obviously has been allocated. Or am I missing something?
Agree, I'll get rid of it.
> > + } else {
> > + /* Unknown MSI, just clear it */
> > + dev_dbg(dev, "unexpected MSI\n");
> > + }
> > + }
> > + }
> > + chained_irq_exit(chip, desc);
> > +}
> > +
> > +static void brcm_compose_msi_msg(struct irq_data *data, struct
> > msi_msg *msg)
> > +{
> > + struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
> > + u32 temp;
> > +
> > + msg->address_lo = lower_32_bits(msi->target_addr);
> > + msg->address_hi = upper_32_bits(msi->target_addr);
> > + temp = bcm_readl(msi->base + PCIE_MISC_MSI_DATA_CONFIG);
Well as far as the RPi is concerned I can do without it. I don't know if there
is an odd case on STB devices where we need it, maybe Jim can shine some light
into it. Regardless I think I'll remove it for now, we can then fix it once we
enable other users for the controller.
> > + msg->data = ((temp >> 16) & (temp & 0xffff)) | data->hwirq;
> > +}
> > +
> > +static int brcm_msi_set_affinity(struct irq_data *irq_data,
> > + const struct cpumask *mask, bool force)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static struct irq_chip brcm_msi_bottom_irq_chip = {
> > + .name = "Brcm_MSI",
> > + .irq_compose_msi_msg = brcm_compose_msi_msg,
> > + .irq_set_affinity = brcm_msi_set_affinity,
> > +};
> > +
> > +static int brcm_msi_alloc(struct brcm_msi *msi)
> > +{
> > + int bit, hwirq;
> > +
> > + mutex_lock(&msi->lock);
> > + bit = ~msi->used ? ffz(msi->used) : -1;
> > +
> > + if (bit >= 0 && bit < BRCM_INT_PCI_MSI_NR) {
> > + msi->used |= (1 << bit);
> > + hwirq = bit - msi->intr_legacy_offset;
> > + } else {
> > + hwirq = -ENOSPC;
> > + }
>
> Please consider using bitmap_find_free_region() and co, instead of
> open coding your allocator.
Noted.
> > +
> > + mutex_unlock(&msi->lock);
> > + return hwirq;
> > +}
> > +
> > +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
> > +{
> > + mutex_lock(&msi->lock);
> > + msi->used &= ~(1 << (hwirq + msi->intr_legacy_offset));
> > + mutex_unlock(&msi->lock);
> > +}
> > +
> > +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned
> > int virq,
> > + unsigned int nr_irqs, void *args)
> > +{
> > + struct brcm_msi *msi = domain->host_data;
> > + int hwirq;
> > +
> > + hwirq = brcm_msi_alloc(msi);
> > +
> > + if (hwirq < 0)
> > + return hwirq;
> > +
> > + irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
> > + &brcm_msi_bottom_irq_chip, domain->host_data,
> > + handle_simple_irq, NULL, NULL);
>
> simple_irq doesn't quite match what this does. This really should
> use an edge flow.
Ok, I'll look into it.
> > + return 0;
> > +}
> > +
> > +static void brcm_irq_domain_free(struct irq_domain *domain,
> > + unsigned int virq, unsigned int nr_irqs)
> > +{
> > + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
> > + struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
> > +
> > + brcm_msi_free(msi, d->hwirq);
> > +}
> > +
> > +static void brcm_msi_set_regs(struct brcm_msi *msi)
> > +{
> > + u32 data_val, msi_lo, msi_hi;
> > +
> > + if (msi->rev >= BRCM_PCIE_HW_REV_33) {
> > + /*
> > + * ffe0 -- least sig 5 bits are 0 indicating 32 msgs
> > + * 6540 -- this is our arbitrary unique data value
> > + */
> > + data_val = 0xffe06540;
> > + } else {
> > + /*
> > + * fff8 -- least sig 3 bits are 0 indicating 8 msgs
> > + * 6540 -- this is our arbitrary unique data value
> > + */
> > + data_val = 0xfff86540;
> > + }
> > +
> > + /*
> > + * Make sure we are not masking MSIs. Note that MSIs can be
> > masked,
> > + * but that occurs on the PCIe EP device
>
> That's not a guarantee, specially with plain MultiMSI. I'm actually
> minded to move the masking to be purely local on the MSI controllers
> I maintain.
Sorry, I'm a little lost here. The way I understand it after reset, even with
multiMSI, on the EP side all vectors are umasked. So it would make sense to do
the same on the controller.
The way I see it, we want to avoid using this register anyway, as with multiMSI
we'd only get function wide masking, which I guess is not all that useful.
> > + */
> > + bcm_writel(0xffffffff & msi->intr_legacy_mask,
> > + msi->intr_base + MASK_CLR);
> > +
> > + msi_lo = lower_32_bits(msi->target_addr);
> > + msi_hi = upper_32_bits(msi->target_addr);
> > + /*
> > + * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
> > + * enable, which we set to 1.
> > + */
> > + bcm_writel(msi_lo | 1, msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
> > + bcm_writel(msi_hi, msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
> > + bcm_writel(data_val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
> > +}
> > +
> > +static const struct irq_domain_ops msi_domain_ops = {
> > + .alloc = brcm_irq_domain_alloc,
> > + .free = brcm_irq_domain_free,
> > +};
> > +
> > +static int brcm_allocate_domains(struct brcm_msi *msi)
> > +{
> > + struct fwnode_handle *fwnode = of_node_to_fwnode(msi->dn);
> > + struct device *dev = msi->dev;
> > +
> > + msi->inner_domain = irq_domain_add_linear(NULL,
> > BRCM_INT_PCI_MSI_NR,
> > + &msi_domain_ops, msi);
> > + if (!msi->inner_domain) {
> > + dev_err(dev, "failed to create IRQ domain\n");
> > + return -ENOMEM;
> > + }
> > +
> > + msi->msi_domain = pci_msi_create_irq_domain(fwnode,
> > + &brcm_msi_domain_info,
> > + msi->inner_domain);
> > + if (!msi->msi_domain) {
> > + dev_err(dev, "failed to create MSI domain\n");
> > + irq_domain_remove(msi->inner_domain);
> > + return -ENOMEM;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void brcm_free_domains(struct brcm_msi *msi)
> > +{
> > + irq_domain_remove(msi->msi_domain);
> > + irq_domain_remove(msi->inner_domain);
> > +}
> > +
> > +static void brcm_msi_remove(struct brcm_pcie *pcie)
> > +{
> > + struct brcm_msi *msi = pcie->msi;
> > +
> > + if (!msi)
> > + return;
> > + irq_set_chained_handler(msi->irq, NULL);
> > + irq_set_handler_data(msi->irq, NULL);
> > + brcm_free_domains(msi);
> > +}
> > +
> > +static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
> > +{
> > + struct brcm_msi *msi;
> > + int irq, ret;
> > + struct device *dev = pcie->dev;
> > +
> > + irq = irq_of_parse_and_map(dev->of_node, 1);
> > + if (irq <= 0) {
> > + dev_err(dev, "cannot map msi intr\n");
> > + return -ENODEV;
> > + }
> > +
> > + msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
> > + if (!msi)
> > + return -ENOMEM;
> > +
> > + msi->dev = dev;
> > + msi->base = pcie->base;
> > + msi->rev = pcie->rev;
> > + msi->dn = pcie->dn;
> > + msi->target_addr = pcie->msi_target_addr;
> > + msi->irq = irq;
> > +
> > + ret = brcm_allocate_domains(msi);
> > + if (ret)
> > + return ret;
>
> You seem to rely on the devm_* allocators to cleanup on failure. But as
> far
> as I can see, failing to initialize the MSI subsystem doesn't translate
> in
> a PCIe init failure, hence keeping the memory around.
Indeed, I see what you mean. I say let's fail.
Regards,
Nicolas
Hi Nicolas,
On 2019-11-11 12:31, Nicolas Saenz Julienne wrote:
> Hi Marc,
> thanks for the review!
>
> On Thu, 2019-11-07 at 16:49 +0109, Marc Zyngier wrote:
>> On 2019-11-06 22:54, Nicolas Saenz Julienne wrote:
>> > From: Jim Quinlan <[email protected]>
>> >
>> > This commit adds MSI to the Broadcom STB PCIe host controller. It
>> > does
>> > not add MSIX since that functionality is not in the HW. The MSI
>> > controller is physically located within the PCIe block, however,
>> > there
>> > is no reason why the MSI controller could not be moved elsewhere
>> in
>> > the future.
>> >
>> > Since the internal Brcmstb MSI controller is intertwined with the
>> > PCIe
>> > controller, it is not its own platform device but rather part of
>> the
>> > PCIe platform device.
>> >
>> > This is based on Jim's original submission[1] with some slight
>> > changes
>> > regarding how pcie->msi_target_addr is decided.
>> >
>> > [1] https://patchwork.kernel.org/patch/10605955/
>> >
>> > Signed-off-by: Jim Quinlan <[email protected]>
>> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
>> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
>> > ---
>> > drivers/pci/controller/Kconfig | 2 +-
>> > drivers/pci/controller/pcie-brcmstb.c | 333
>> > +++++++++++++++++++++++++-
>> > 2 files changed, 332 insertions(+), 3 deletions(-)
[...]
>> > +static struct msi_domain_info brcm_msi_domain_info = {
>> > + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
>> > + MSI_FLAG_PCI_MSIX),
>>
>> Is there a particular reason for not supporting MultiMSI? I won't
>> miss
>> it, but it might be worth documenting the restriction if the HW
>> cannot
>> support it (though I can't immediately see why).
>
> There is no actual restriction. As Jim tells me, there never was the
> need for
> it. If it's fine with you, we'll leave that as an enhancement for the
> future,
> specially since the RPi's XHCI device only uses one MSI interrupt.
Sure, that's fine. But as soon as someone takes this SoC and sticks it
on
a different board (RPi CM4 anyone?), this will become a requirement (I
thought
MultiMSI dead 4 years ago, and have been proved wrong many times
since).
>
>> > + .chip = &brcm_msi_irq_chip,
>> > +};
>> > +
>> > +static void brcm_pcie_msi_isr(struct irq_desc *desc)
>> > +{
>> > + struct irq_chip *chip = irq_desc_get_chip(desc);
>> > + struct brcm_msi *msi;
>> > + unsigned long status, virq;
>> > + u32 mask, bit, hwirq;
>> > + struct device *dev;
>> > +
>> > + chained_irq_enter(chip, desc);
>> > + msi = irq_desc_get_handler_data(desc);
>> > + mask = msi->intr_legacy_mask;
>> > + dev = msi->dev;
>> > +
>> > + while ((status = bcm_readl(msi->intr_base + STATUS) & mask)) {
>>
>> Is this loop really worth it? If, as I imagine, this register is at
>> the
>> end of a wet piece of string, this additional read (likely to return
>> zero)
>> will have a measurable latency impact...
>
> I think this one was cargo-culted, TBH this pattern is all over the
> place.
> Though, now that you point it out, I can't really provide a
> justification for
> it. Maybe Jim can contradict me here, but It's working fine without
> it.
I know this pattern is ultra common (hey, the GIC uses it), but I'm
somehow doubtful of its benefit. On GICv3, not reading the status
register again has given us a performance boost for most workloads.
[...]
>> > + /*
>> > + * Make sure we are not masking MSIs. Note that MSIs can be
>> > masked,
>> > + * but that occurs on the PCIe EP device
>>
>> That's not a guarantee, specially with plain MultiMSI. I'm actually
>> minded to move the masking to be purely local on the MSI controllers
>> I maintain.
>
> Sorry, I'm a little lost here. The way I understand it after reset,
> even with
> multiMSI, on the EP side all vectors are umasked. So it would make
> sense to do
> the same on the controller.
>
> The way I see it, we want to avoid using this register anyway, as
> with multiMSI
> we'd only get function wide masking, which I guess is not all that
> useful.
Yeah, I wasn't 100% clear. Unless you have MSI-X, there is no guarantee
to have a mask bit per MSI. Multi-MSI definitely has only this problem.
My advice would be to let the PCI layer deal with enabling/disabling
interrupts at the endpoint level, and let this driver manage the
masking at its own level, using the MASK registers.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
Hi Jeremy,
thanks for the review.
On Mon, 2019-11-11 at 01:10 -0600, Jeremy Linton wrote:
> Hi,
>
>
> On 11/6/19 3:45 PM, Nicolas Saenz Julienne wrote:
> > From: Jim Quinlan <[email protected]>
> >
> > This commit adds the basic Broadcom STB PCIe controller. Missing is the
> > ability to process MSI. This functionality is added in a subsequent
> > commit.
> >
> > The PCIe block contains an MDIO interface. This is a local interface
> > only accessible by the PCIe controller. It cannot be used or shared
> > by any other HW. As such, the small amount of code for this
> > controller is included in this driver as there is little upside to put
> > it elsewhere.
> >
> > This is based on Jim's original submission[1] but adapted and tailored
> > specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
> > the rest of the brcmstb family will soon follow once we get support for
> > multiple dma-ranges in dma/direct.
> >
> > [1] https://patchwork.kernel.org/patch/10605959/
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > drivers/pci/controller/Kconfig | 12 +
> > drivers/pci/controller/Makefile | 1 +
> > drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
> > 3 files changed, 986 insertions(+)
> > create mode 100644 drivers/pci/controller/pcie-brcmstb.c
> >
> > diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> > index f5de9119e8d3..8b3aae91d8af 100644
> > --- a/drivers/pci/controller/Kconfig
> > +++ b/drivers/pci/controller/Kconfig
> > @@ -281,6 +281,18 @@ config VMD
> > To compile this driver as a module, choose M here: the
> > module will be called vmd.
> >
> > +config PCIE_BRCMSTB
> > + bool "Broadcom Brcmstb PCIe host controller"
> > + depends on ARCH_BRCMSTB || BMIPS_GENERIC
> > + depends on OF
> > + depends on SOC_BRCMSTB
> > + default ARCH_BRCMSTB || BMIPS_GENERIC
> > + help
> > + Say Y here to enable PCIe host controller support for
> > + Broadcom Settop Box SOCs. A Broadcom SOC will may have
> > + multiple host controllers as opposed to a single host
> > + controller with multiple ports.
> > +
> > config PCI_HYPERV_INTERFACE
> > tristate "Hyper-V PCI Interface"
> > depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
> > diff --git a/drivers/pci/controller/Makefile
> > b/drivers/pci/controller/Makefile
> > index a2a22c9d91af..3fc0b0cf5b5b 100644
> > --- a/drivers/pci/controller/Makefile
> > +++ b/drivers/pci/controller/Makefile
> > @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> > obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
> > obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> > obj-$(CONFIG_VMD) += vmd.o
> > +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> > # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> > obj-y += dwc/
> >
> > diff --git a/drivers/pci/controller/pcie-brcmstb.c
> > b/drivers/pci/controller/pcie-brcmstb.c
> > new file mode 100644
> > index 000000000000..880ec11d06a1
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > @@ -0,0 +1,973 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* Copyright (C) 2009 - 2019 Broadcom */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/compiler.h>
> > +#include <linux/delay.h>
> > +#include <linux/init.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/ioport.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/kernel.h>
> > +#include <linux/list.h>
> > +#include <linux/log2.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/pci.h>
> > +#include <linux/printk.h>
> > +#include <linux/sizes.h>
> > +#include <linux/slab.h>
> > +#include <linux/string.h>
> > +#include <linux/types.h>
> > +
> > +#include "../pci.h"
> > +
> > +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
> > +#define BRCM_PCIE_CAP_REGS 0x00ac
> > +
> > +/*
> > + * Broadcom Settop Box PCIe Register Offsets. The names are from
> > + * the chip's RDB and we use them here so that a script can correlate
> > + * this code and the RDB to prevent discrepancies.
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> > +#define PCIE_RC_DL_MDIO_ADDR 0x1100
> > +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> > +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> > +#define PCIE_MISC_MISC_CTRL 0x4008
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
> > +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
> > +#define PCIE_MISC_PCIE_CTRL 0x4064
> > +#define PCIE_MISC_PCIE_STATUS 0x4068
> > +#define PCIE_MISC_REVISION 0x406c
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > +#define PCIE_INTR2_CPU_BASE 0x4300
> > +
> > +/*
> > + * Broadcom Settop Box PCIe Register Field shift and mask info. The
> > + * names are from the chip's RDB and we use them here so that a script
> > + * can correlate this code and the RDB to prevent discrepancies.
> > + */
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK
> > 0xc
> > +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT
> > 0x2
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
> > +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
> > +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
> > +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
> > +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
> > +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
> > +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
> > +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
> > +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
> > +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
> > +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
> > +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
> > +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff000
> > 00
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
> > +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x080000
> > 00
> > +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
> > +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
> > +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
> > +
> > +#define BRCM_NUM_PCIE_OUT_WINS 0x4
> > +#define BRCM_MAX_SCB 0x4
> > +
> > +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
> > +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
> > +
> > +#define BURST_SIZE_128 0
> > +#define BURST_SIZE_256 1
> > +#define BURST_SIZE_512 2
> > +
> > +/* Offsets from PCIE_INTR2_CPU_BASE */
> > +#define STATUS 0x0
> > +#define SET 0x4
> > +#define CLR 0x8
> > +#define MASK_STATUS 0xc
> > +#define MASK_SET 0x10
> > +#define MASK_CLR 0x14
> > +
> > +#define PCIE_BUSNUM_SHIFT 20
> > +#define PCIE_SLOT_SHIFT 15
> > +#define PCIE_FUNC_SHIFT 12
> > +
> > +#if defined(__BIG_ENDIAN)
> > +#define DATA_ENDIAN 2 /* PCIe->DDR inbound
traffic
> > */
> > +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound
> > traffic */
> > +#else
> > +#define DATA_ENDIAN 0
> > +#define MMIO_ENDIAN 0
> > +#endif
> > +
> > +#define MDIO_PORT0 0x0
> > +#define MDIO_DATA_MASK 0x7fffffff
> > +#define MDIO_DATA_SHIFT 0x0
> > +#define MDIO_PORT_MASK 0xf0000
> > +#define MDIO_PORT_SHIFT 0x16
> > +#define MDIO_REGAD_MASK 0xffff
> > +#define MDIO_REGAD_SHIFT 0x0
> > +#define MDIO_CMD_MASK 0xfff00000
> > +#define MDIO_CMD_SHIFT 0x14
> > +#define MDIO_CMD_READ 0x1
> > +#define MDIO_CMD_WRITE 0x0
> > +#define MDIO_DATA_DONE_MASK 0x80000000
> > +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1
> > : 0)
> > +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0
> > : 1)
> > +#define SSC_REGS_ADDR 0x1100
> > +#define SET_ADDR_OFFSET 0x1f
> > +#define SSC_CNTL_OFFSET 0x2
> > +#define SSC_CNTL_OVRD_EN_MASK 0x8000
> > +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
> > +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
> > +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
> > +#define SSC_STATUS_OFFSET 0x1
> > +#define SSC_STATUS_SSC_MASK 0x400
> > +#define SSC_STATUS_SSC_SHIFT 0xa
> > +#define SSC_STATUS_PLL_LOCK_MASK 0x800
> > +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
> > +
> > +#define IDX_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_INDEX])
> > +#define DATA_ADDR(pcie) \
> > + ((pcie)->reg_offsets[EXT_CFG_DATA])
> > +#define PCIE_RGR1_SW_INIT_1(pcie) \
> > + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
> > +
> > +enum {
> > + RGR1_SW_INIT_1,
> > + EXT_CFG_INDEX,
> > + EXT_CFG_DATA,
> > +};
> > +
> > +enum {
> > + RGR1_SW_INIT_1_INIT_MASK,
> > + RGR1_SW_INIT_1_INIT_SHIFT,
> > + RGR1_SW_INIT_1_PERST_MASK,
> > + RGR1_SW_INIT_1_PERST_SHIFT,
> > +};
> > +
> > +enum pcie_type {
> > + BCM2711,
> > +};
> > +
> > +struct brcm_window {
> > + dma_addr_t pcie_addr;
> > + phys_addr_t cpu_addr;
> > + dma_addr_t size;
> > +};
> > +
> > +/* Internal PCIe Host Controller Information.*/
> > +struct brcm_pcie {
> > + struct device *dev;
> > + void __iomem *base;
> > + int irq;
> > + struct clk *clk;
> > + struct pci_bus *root_bus;
> > + struct device_node *dn;
> > + int id;
> > + bool suspended;
> > + bool ssc;
> > + int gen;
> > + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
> > + unsigned int rev;
> > + const int *reg_offsets;
> > + const int *reg_field_info;
> > + enum pcie_type type;
> > +};
> > +
> > +struct pcie_cfg_data {
> > + const int *reg_field_info;
> > + const int *offsets;
> > + const enum pcie_type type;
> > +};
> > +
> > +static const int pcie_reg_field_info[] = {
> > + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
> > + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
> > +};
> > +
> > +static const int pcie_offset_bcm2711[] = {
> > + [RGR1_SW_INIT_1] = 0x9210,
> > + [EXT_CFG_INDEX] = 0x9000,
> > + [EXT_CFG_DATA] = 0x8000,
> > +};
>
> Given that there is currently only a single set of register offsets,
> this seems like it could be simpler.
You're right, there is no need for it as of this series. But since we know
we'll be supporting other SoCs in the near future I figured it was harmless to
leave this as a dt dependent config.
> > +
> > +static const struct pcie_cfg_data bcm2711_cfg = {
> > + .reg_field_info = pcie_reg_field_info,
> > + .offsets = pcie_offset_bcm2711,
> > + .type = BCM2711,
> > +};
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
> > devfn,
> > + int where);
> > +
> > +static struct pci_ops brcm_pcie_ops = {
> > + .map_bus = brcm_pcie_map_conf,
> > + .read = pci_generic_config_read,
> > + .write = pci_generic_config_write,
> > +};
> > +
> > +#define bcm_readl(a) readl(a)
> > +#define bcm_writel(d, a) writel(d, a)
> > +#define bcm_readw(a) readw(a)
> > +#define bcm_writew(d, a) writew(d, a)
> > +
> > +/* These macros extract/insert fields to host controller's register set. */
> > +#define RD_FLD(base, reg, field) \
> > + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
> > +#define WR_FLD(base, reg, field, val) \
> > + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
> > +#define WR_FLD_RB(base, reg, field, val) \
> > + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
> > + reg##_##field##_SHIFT, val)
> > +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
> > + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
> > + reg##_##field##_SHIFT, val)
> > +#define EXTRACT_FIELD(val, reg, field) \
> > + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
> > +#define INSERT_FIELD(val, reg, field, field_val) \
> > + (((val) & ~reg##_##field##_MASK) | \
> > + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
> > +
> > +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
> > +{
> > + return (bcm_readl(p) & mask) >> shift;
> > +}
> > +
> > +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + u32 reg = bcm_readl(p);
> > +
> > + reg = (reg & ~mask) | ((val << shift) & mask);
> > + bcm_writel(reg, p);
> > +}
> > +
> > +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
> > +{
> > + wr_fld(p, mask, shift, val);
> > + (void)bcm_readl(p);
> > +}
> > +
> > +static const char *link_speed_to_str(int s)
> > +{
> > + switch (s) {
> > + case 1:
> > + return "2.5";
> > + case 2:
> > + return "5.0";
> > + case 3:
> > + return "8.0";
> > + default:
> > + break;
> > + }
> > + return "???";
> > +}
> > +
> > +/*
> > + * The roundup_pow_of_two() from log2.h invokes
> > + * __roundup_pow_of_two(unsigned long), but we really need a
> > + * such a function to take a native u64 since unsigned long
> > + * is 32 bits on some configurations. So we provide this helper
> > + * function below.
> > + */
> > +static u64 roundup_pow_of_two_64(u64 n)
> > +{
> > + return 1ULL << fls64(n - 1);
> > +}
> > +
> > +/*
> > + * This is to convert the size of the inbound "BAR" region to the
> > + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
> > + */
> > +int encode_ibar_size(u64 size)
> > +{
> > + int log2_in = ilog2(size);
> > +
> > + if (log2_in >= 12 && log2_in <= 15)
> > + /* Covers 4KB to 32KB (inclusive) */
> > + return (log2_in - 12) + 0x1c;
> > + else if (log2_in >= 16 && log2_in <= 37)
> > + /* Covers 64KB to 32GB, (inclusive) */
> > + return log2_in - 15;
> > + /* Something is awry so disable */
> > + return 0;
> > +}
> > +
> > +static u32 mdio_form_pkt(int port, int regad, int cmd)
> > +{
> > + u32 pkt = 0;
> > +
> > + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
> > + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
> > + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
> > +
> > + return pkt;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_read(void __iomem *base, u8 port, u8 regad)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
> > + }
> > +
> > + return MDIO_RD_DONE(data)
> > + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
> > + : -EIO;
> > +}
> > +
> > +/* negative return value indicates error */
> > +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
> > +{
> > + int tries;
> > + u32 data;
> > +
> > + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
> > + base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
> > + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
> > + base + PCIE_RC_DL_MDIO_WR_DATA);
> > +
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
> > + udelay(10);
> > + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
> > + }
> > +
> > + return MDIO_WT_DONE(data) ? 0 : -EIO;
> > +}
> > +
> > +/*
> > + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
> > + * return value indicates error.
> > + */
> > +static int set_ssc(void __iomem *base)
> > +{
> > + int tmp;
> > + u16 wrdata;
> > + int pll, ssc;
> > +
> > + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
> > + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
> > + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + usleep_range(1000, 2000);
> > + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
> > + if (tmp < 0)
> > + return tmp;
> > +
> > + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
> > + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
>
> This is actually the PCIe phy?
I'll let Jim reply this one.
> > +
> > + return (ssc && pll) ? 0 : -EIO;
> > +}
> > +
> > +/* Limits operation to a specific generation (1, 2, or 3) */
> > +static void set_gen(void __iomem *base, int gen)
> > +{
> > + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > +
> > + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
> > + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
> > +
> > + lnkctl2 = (lnkctl2 & ~0xf) | gen;
> > + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
> > +}
> > +
> > +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
> > + unsigned int win, phys_addr_t cpu_addr,
> > + dma_addr_t pcie_addr, dma_addr_t size)
> > +{
> > + void __iomem *base = pcie->base;
> > + phys_addr_t cpu_addr_mb, limit_addr_mb;
> > + u32 tmp;
> > +
> > + /* Set the base of the pcie_addr window */
> > + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
> > + bcm_writel(upper_32_bits(pcie_addr),
> > + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
> > +
> > + cpu_addr_mb = cpu_addr >> 20;
> > + limit_addr_mb = (cpu_addr + size - 1) >> 20;
> > +
> > + /* Write the addr base low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + BASE, cpu_addr_mb);
> > + /* Write the addr limit low register */
> > + WR_FLD_WITH_OFFSET(base, (win * 4),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
> > + LIMIT, limit_addr_mb);
> > +
> > + /* Write the cpu addr high register */
> > + tmp = (u32)(cpu_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
> > + BASE, tmp);
> > + /* Write the cpu limit high register */
> > + tmp = (u32)(limit_addr_mb >>
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
> > + WR_FLD_WITH_OFFSET(base, (win * 8),
> > + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
> > + LIMIT, tmp);
> > +}
>
> So this is translating a high CPU address to a <32-bit PCI MMIO window?
Yes, for the record, this is what the RPi4 uses:
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
> I thought there was some kind of 32-bit limitation in front of this root
> port?
We have a limitation for DMA accesses (can't access the 0xc0000000-0xffffffff
area) due to a bug on the PCIe core integration, not a limitation on the
interconnect. But this doesn't apply for BAR accesses. Though....
> This makes it sound like the root port can recieve 64-bit MMIO
> writes just fine.
...I've been told we have to imperatively place the outbound memory area in the
lower 4GB. This is a shortcoming on the PCIe controller side.
> IIRC XHCI can run with just two 64-bit BARS, so it
> sounds like the translation here isn't strictly nessisary until someone
> wants a 32-bit non-prefechable bar. No?
> > +
> > +/* Configuration space read/write support */
> > +static int cfg_index(int busnr, int devfn, int reg)
> > +{
> > + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
> > + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
> > + | (busnr << PCIE_BUSNUM_SHIFT)
> > + | (reg & ~3);
> > +}
> > +
> > +/* The controller is capable of serving in both RC and EP roles */
> > +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > +
> > + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
> > +}
> > +
> > +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
> > + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
> > + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
> > +
> > + return (dla && plu) ? true : false;
> > +}
> > +
> > +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
> > devfn,
> > + int where)
> > +{
> > + struct brcm_pcie *pcie = bus->sysdata;
> > + void __iomem *base = pcie->base;
> > + int idx;
> > +
> > + /* Accesses to the RC go right to the RC registers if slot==0 */
> > + if (pci_is_root_bus(bus))
> > + return PCI_SLOT(devfn) ? NULL : base + where;
> > +
> > + /* For devices, write to the config space index register */
> > + idx = cfg_index(bus->number, devfn, 0);
> > + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
> > + return base + DATA_ADDR(pcie) + where;
> > +}
>
> So, each pci cfg space access requires a cfg register write, so that the
> data space for the bdf can be accessed?
Yes, that's it.
> Using map_bus() to setup the cfg region rather than overriding the
> generic read/write callbacks means that in the future we can't enable
> PCI_LOCKLESS_CONFIG in a generic arm64 kernel.
That'd be hard anyways, it seems to me that a lot of arm64 devices depend on
this, right?
> > +
> > +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
> > + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
> > +
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
> > +}
> > +
> > +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
> > + unsigned int val)
> > +{
> > + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
> > + PCIE_RGR1_SW_INIT_1_PERST_MASK,
> > + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
> > +}
> > +
> > +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie
> > *pcie,
> > + u64 *rc_bar2_size,
> > + u64 *rc_bar2_offset)
> > +{
> > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > + struct device *dev = pcie->dev;
> > + struct resource_entry *entry;
> > + u64 total_mem_size = 0;
> > +
> > + *rc_bar2_offset = -1;
> > +
> > + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> > + /*
> > + * We're promissed the RC will provide a contiguous view of
> > + * memory to downstream devices. We can then infer the
> > + * rc_bar2_offset from the lower avaiable dma-range offset.
> > + */
> > + if (entry->offset < *rc_bar2_offset)
> > + *rc_bar2_offset = entry->offset;
> > +
> > + total_mem_size += entry->res->end - entry->res->start + 1;
> > + }
> > +
> > + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
> > +
> > + /*
> > + * Validate the results:
> > + *
> > + * The PCIe host controller by design must set the inbound viewport to
> > + * be a contiguous arrangement of all of the system's memory. In
> > + * addition, its size mut be a power of two. To further complicate
> > + * matters, the viewport must start on a pcie-address that is aligned
> > + * on a multiple of its size. If a portion of the viewport does not
> > + * represent system memory -- e.g. 3GB of memory requires a 4GB
> > + * viewport -- we can map the outbound memory in or after 3GB and even
> > + * though the viewport will overlap the outbound memory the controller
> > + * will know to send outbound memory downstream and everything else
> > + * upstream.
> > + *
> > + * For example:
> > + *
> > + * - The best-case scenario, memory up to 3GB, is to place the inbound
> > + * region in the first 4GB of pcie-space, as some legacy devices can
> > + * only address 32bits. We would also like to put the MSI under 4GB
> > + * as well, since some devices require a 32bit MSI target address.
> > + *
> > + * - If the system memory is 4GB or larger we cannot start the inbound
> > + * region at location 0 (since we have to allow some space for
> > + * outbound memory @ 3GB). So instead it will start at the 1x
> > + * multiple of its size
> > + */
> > + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
> > + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
> > + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off
> > 0x%llx\n",
> > + *rc_bar2_size, *rc_bar2_offset);
> > + return -EINVAL;
> > + }
>
> If the MMIO window isn't translated and is left high
Sadly, as I commented in the outbound memory config code, this is not possible.
> does it work to just use a single 0->$TOP_OF_RAM mapping, even with the
> 32-bit limitation? Or is the 32-bit limitation comming from this programming?
We can use that 1:1 mapping as long as we leave some space for the outbound
memory and follow the alignment rules stated above. It's a HW limitation.
Just let me stress that in the end I'm just validating whatever the firmware
provided, I'm not really modifying anything here. I could do away with the
check as it'd be plain silly if the FW provided wrong dma-ranges. But since
people are likely to play around with RPi's dtb, I figured it's worthwhile.
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > +{
> > + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> > + u64 rc_bar2_offset, rc_bar2_size;
> > + void __iomem *base = pcie->base;
> > + struct resource_entry *entry;
> > + unsigned int scb_size_val;
> > + struct resource *res;
> > + int num_out_wins = 0;
> > + u32 tmp;
> > + int i, j, ret, limit;
> > + u16 nlw, cls, lnksta;
> > + bool ssc_good = false;
> > + struct device *dev = pcie->dev;
> > +
> > + /* Reset the bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +
> > + usleep_range(100, 200);
> > +
> > + /* Take the bridge out of reset */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* Wait for SerDes to be stable */
> > + usleep_range(100, 200);
> > +
> > + /* Grab the PCIe hw revision number */
> > + tmp = bcm_readl(base + PCIE_MISC_REVISION);
> > + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
> > +
> > + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
> > + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
> > + BURST_SIZE_128);
> > + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
>
> Presumablly users will want to use PCIe at some point in the future for
> booting/etc. That means the firmware will perform sufficient setup that
> you shouldn't need much of the code in this function if the address
> windows, serdes, etc are functional when linux boots. Similarly for
> suspend/resume.
I see what you mean, although it's not the case for now as RPi's firmware
doesn't initialize anything. Though I can imagine some people might want this
if the RPi4 compute module ever comes out.
If it's OK with you I think we can let it be for now.
> > +
> > + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
> > + &rc_bar2_offset);
> > + if (ret)
> > + return ret;
> > +
> > + tmp = lower_32_bits(rc_bar2_offset);
> > + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
> > + encode_ibar_size(rc_bar2_size));
> > + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
> > + bcm_writel(upper_32_bits(rc_bar2_offset),
> > + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
> > +
> > + scb_size_val = rc_bar2_size ?
> > + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
> > + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
> > +
> > + /* disable the PCIe->GISB memory window (RC_BAR1) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
> > +
> > + /* disable the PCIe->SCB memory window (RC_BAR3) */
> > + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
> > +
> > + if (!pcie->suspended) {
> > + /* clear any interrupts we find on boot */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
> > + }
> > +
> > + /* Mask all interrupts since we are not handling any yet */
> > + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
> > +
> > + if (pcie->gen)
> > + set_gen(base, pcie->gen);
> > +
> > + /* Unassert the fundamental reset */
> > + brcm_pcie_perst_set(pcie, 0);
> > +
> > + /*
> > + * Give the RC/EP time to wake up, before trying to configure RC.
> > + * Intermittently check status for link-up, up to a total of 100ms
> > + * when we don't know if the device is there, and up to 1000ms if
> > + * we do know the device is there.
> > + */
> > + limit = pcie->suspended ? 1000 : 100;
> > + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
> > + j += i, i = i * 2)
> > + msleep(i + j > limit ? limit - j : i);
> > +
> > + if (!brcm_pcie_link_up(pcie)) {
> > + dev_info(dev, "link down\n");
> > + return -ENODEV;
> > + }
> > +
> > + if (!brcm_pcie_rc_mode(pcie)) {
> > + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
> > + return -EINVAL;
> > + }
> > +
> > + resource_list_for_each_entry(entry, &bridge->windows) {
> > + res = entry->res;
> > +
> > + if (resource_type(res) != IORESOURCE_MEM)
> > + continue;
> > +
> > + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
> > + dev_err(pcie->dev, "too many outbound wins\n");
> > + return -EINVAL;
> > + }
> > +
> > + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
> > + res->start - entry->offset,
> > + res->end - res->start + 1);
> > + num_out_wins++;
> > + }
> > +
> > + /*
> > + * For config space accesses on the RC, show the right class for
> > + * a PCIe-PCIe bridge (the default setting is to be EP mode).
> > + */
> > + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
> > +
> > + if (pcie->ssc) {
> > + ret = set_ssc(base);
> > + if (ret == 0)
> > + ssc_good = true;
> > + else
> > + dev_err(dev, "failed attempt to enter ssc mode\n");
> > + }
> > +
> > + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> > + cls = lnksta & PCI_EXP_LNKSTA_CLS;
> > + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> > + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
> > + nlw, ssc_good ? "(SSC)" : "(!SSC)");
> > +
> > + /* PCIe->SCB endian mode for BAR */
> > + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
> > + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
> > + ENDIAN_MODE_BAR2, DATA_ENDIAN);
> > +
> > + /*
> > + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
> > + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
> > + */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
> > +
> > + return 0;
> > +}
> > +
> > +/* L23 is a low-power PCIe link state */
> > +static void enter_l23(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > + int l23, i;
> > +
> > + /* assert request for L23 */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
> > +
> > + /* Wait up to 30 msec for L23 */
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + for (i = 0; i < 15 && !l23; i++) {
> > + usleep_range(2000, 2400);
> > + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
> > + }
> > +
> > + if (!l23)
> > + dev_err(pcie->dev, "failed to enter L23\n");
> > +}
> > +
> > +static void turn_off(struct brcm_pcie *pcie)
> > +{
> > + void __iomem *base = pcie->base;
> > +
> > + if (brcm_pcie_link_up(pcie))
> > + enter_l23(pcie);
> > + /* Assert fundamental reset */
> > + brcm_pcie_perst_set(pcie, 1);
> > + /* Deassert request for L23 in case it was asserted */
> > + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
> > + /* Turn off SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
> > + /* Shutdown PCIe bridge */
> > + brcm_pcie_bridge_sw_init_set(pcie, 1);
> > +}
> > +
> > +static int brcm_pcie_suspend(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > +
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + pcie->suspended = true;
> > +
> > + return 0;
> > +}
> > +
> > +static int brcm_pcie_resume(struct device *dev)
> > +{
> > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > + void __iomem *base;
> > + int ret;
> > +
> > + base = pcie->base;
> > + clk_prepare_enable(pcie->clk);
> > +
> > + /* Take bridge out of reset so we can access the SerDes reg */
> > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > +
> > + /* Turn on SerDes */
> > + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
> > + /* Wait for SerDes to be stable */
> > + usleep_range(100, 200);
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + return ret;
> > +
> > + pcie->suspended = false;
> > +
> > + return 0;
> > +}
> > +
> > +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
> > +{
> > + turn_off(pcie);
> > + clk_disable_unprepare(pcie->clk);
> > + clk_put(pcie->clk);
> > +}
> > +
> > +static int brcm_pcie_remove(struct platform_device *pdev)
> > +{
> > + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
> > +
> > + pci_stop_root_bus(pcie->root_bus);
> > + pci_remove_root_bus(pcie->root_bus);
> > + _brcm_pcie_remove(pcie);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id brcm_pcie_match[] = {
> > + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > +
> > +static int brcm_pcie_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *dn = pdev->dev.of_node;
> > + const struct of_device_id *of_id;
> > + const struct pcie_cfg_data *data;
> > + struct resource *res;
> > + int ret;
> > + struct brcm_pcie *pcie;
> > + void __iomem *base;
> > + struct pci_host_bridge *bridge;
> > + struct pci_bus *child;
> > +
> > + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
> > + if (!bridge)
> > + return -ENOMEM;
> > +
> > + pcie = pci_host_bridge_priv(bridge);
> > +
> > + of_id = of_match_node(brcm_pcie_match, dn);
> > + if (!of_id) {
> > + dev_err(&pdev->dev, "failed to look up compatible string\n");
> > + return -EINVAL;
> > + }
> > +
> > + data = of_id->data;
> > + pcie->reg_offsets = data->offsets;
> > + pcie->reg_field_info = data->reg_field_info;
> > + pcie->type = data->type;
> > + pcie->dn = dn;
> > + pcie->dev = &pdev->dev;
> > +
> > + /* We use the domain number as our controller number */
> > + pcie->id = of_get_pci_domain_nr(dn);
> > + if (pcie->id < 0)
> > + return pcie->id;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -EINVAL;
> > +
> > + base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
> > + if (IS_ERR(pcie->clk)) {
> > + dev_err(&pdev->dev, "could not get clock\n");
> > + pcie->clk = NULL;
> > + }
>
> Is there a sw_pcie clock in the system?
AFAIK it's there and there's a firmware interface available. That said, if
possible (i.e. not clashing with some firmware routine) it would be nice to
integrate it into the memory mapped clock driver. It's always the preferred
solution. Though to do so we need more documentation.
Overall it's not really needed for now.
> > + pcie->base = base;
> > +
> > + ret = of_pci_get_max_link_speed(dn);
> > + pcie->gen = (ret < 0) ? 0 : ret;
> > +
> > + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
> > +
> > + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
> > + if (ret == 0)
> > + /* keep going, as we don't use this intr yet */
> > + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
> > + else
> > + pcie->irq = ret;
> > +
> > + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
> > + &bridge->dma_ranges, NULL);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_prepare_enable(pcie->clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "could not enable clock\n");
> > + return ret;
> > + }
> > +
> > + ret = brcm_pcie_setup(pcie);
> > + if (ret)
> > + goto fail;
> > +
> > + bridge->dev.parent = &pdev->dev;
> > + bridge->busnr = 0;
> > + bridge->ops = &brcm_pcie_ops;
> > + bridge->sysdata = pcie;
> > + bridge->map_irq = of_irq_parse_and_map_pci;
> > + bridge->swizzle_irq = pci_common_swizzle;
> > +
> > + ret = pci_scan_root_bus_bridge(bridge);
> > + if (ret < 0) {
> > + dev_err(pcie->dev, "Scanning root bridge failed\n");
> > + goto fail;
> > + }
> > +
> > + pci_assign_unassigned_bus_resources(bridge->bus);
> > + list_for_each_entry(child, &bridge->bus->children, node)
> > + pcie_bus_configure_settings(child);
> > + pci_bus_add_devices(bridge->bus);
> > + platform_set_drvdata(pdev, pcie);
> > + pcie->root_bus = bridge->bus;
> > +
> > + return 0;
> > +
> > +fail:
> > + _brcm_pcie_remove(pcie);
> > + return ret;
> > +}
> > +
> > +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> > + .suspend_noirq = brcm_pcie_suspend,
> > + .resume_noirq = brcm_pcie_resume,
> > +};
> > +
> > +static struct platform_driver brcm_pcie_driver = {
> > + .probe = brcm_pcie_probe,
> > + .remove = brcm_pcie_remove,
> > + .driver = {
> > + .name = "brcm-pcie",
> > + .owner = THIS_MODULE,
> > + .of_match_table = brcm_pcie_match,
> > + .pm = &brcm_pcie_pm_ops,
> > + },
> > +};
> > +
> > +module_platform_driver(brcm_pcie_driver);
> > +
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
> > +MODULE_AUTHOR("Broadcom");
> >
On 11/11/19 7:29 AM, Nicolas Saenz Julienne wrote:
> Hi Jeremy,
> thanks for the review.
>
> On Mon, 2019-11-11 at 01:10 -0600, Jeremy Linton wrote:
[snip]
>>> +static const int pcie_offset_bcm2711[] = {
>>> + [RGR1_SW_INIT_1] = 0x9210,
>>> + [EXT_CFG_INDEX] = 0x9000,
>>> + [EXT_CFG_DATA] = 0x8000,
>>> +};
>>
>> Given that there is currently only a single set of register offsets,
>> this seems like it could be simpler.
>
> You're right, there is no need for it as of this series. But since we know
> we'll be supporting other SoCs in the near future I figured it was harmless to
> leave this as a dt dependent config.
I would rather leave it as is right now because while possibly
inefficient, adding a later series whose purpose is to add register
indirection would just clutter the review process IMHO, the way it is
right now does not hurt.
(please trim your replies to remove what you are not responding to).
--
Florian
Hi,
On 11/11/19 9:29 AM, Nicolas Saenz Julienne wrote:
> Hi Jeremy,
> thanks for the review.
>
> On Mon, 2019-11-11 at 01:10 -0600, Jeremy Linton wrote:
>> Hi,
>>
>>
>> On 11/6/19 3:45 PM, Nicolas Saenz Julienne wrote:
>>> From: Jim Quinlan <[email protected]>
>>>
>>> This commit adds the basic Broadcom STB PCIe controller. Missing is the
>>> ability to process MSI. This functionality is added in a subsequent
>>> commit.
>>>
>>> The PCIe block contains an MDIO interface. This is a local interface
>>> only accessible by the PCIe controller. It cannot be used or shared
>>> by any other HW. As such, the small amount of code for this
>>> controller is included in this driver as there is little upside to put
>>> it elsewhere.
>>>
>>> This is based on Jim's original submission[1] but adapted and tailored
>>> specifically to bcm2711's needs (that's the Raspberry Pi 4). Support for
>>> the rest of the brcmstb family will soon follow once we get support for
>>> multiple dma-ranges in dma/direct.
>>>
>>> [1] https://patchwork.kernel.org/patch/10605959/
>>>
>>> Signed-off-by: Jim Quinlan <[email protected]>
>>> Co-developed-by: Nicolas Saenz Julienne <[email protected]>
>>> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
>>> ---
>>> drivers/pci/controller/Kconfig | 12 +
>>> drivers/pci/controller/Makefile | 1 +
>>> drivers/pci/controller/pcie-brcmstb.c | 973 ++++++++++++++++++++++++++
>>> 3 files changed, 986 insertions(+)
>>> create mode 100644 drivers/pci/controller/pcie-brcmstb.c
>>>
>>> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
>>> index f5de9119e8d3..8b3aae91d8af 100644
>>> --- a/drivers/pci/controller/Kconfig
>>> +++ b/drivers/pci/controller/Kconfig
>>> @@ -281,6 +281,18 @@ config VMD
>>> To compile this driver as a module, choose M here: the
>>> module will be called vmd.
>>>
>>> +config PCIE_BRCMSTB
>>> + bool "Broadcom Brcmstb PCIe host controller"
>>> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
>>> + depends on OF
>>> + depends on SOC_BRCMSTB
>>> + default ARCH_BRCMSTB || BMIPS_GENERIC
>>> + help
>>> + Say Y here to enable PCIe host controller support for
>>> + Broadcom Settop Box SOCs. A Broadcom SOC will may have
>>> + multiple host controllers as opposed to a single host
>>> + controller with multiple ports.
>>> +
>>> config PCI_HYPERV_INTERFACE
>>> tristate "Hyper-V PCI Interface"
>>> depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
>>> diff --git a/drivers/pci/controller/Makefile
>>> b/drivers/pci/controller/Makefile
>>> index a2a22c9d91af..3fc0b0cf5b5b 100644
>>> --- a/drivers/pci/controller/Makefile
>>> +++ b/drivers/pci/controller/Makefile
>>> @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>>> obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
>>> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>>> obj-$(CONFIG_VMD) += vmd.o
>>> +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
>>> # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
>>> obj-y += dwc/
>>>
>>> diff --git a/drivers/pci/controller/pcie-brcmstb.c
>>> b/drivers/pci/controller/pcie-brcmstb.c
>>> new file mode 100644
>>> index 000000000000..880ec11d06a1
>>> --- /dev/null
>>> +++ b/drivers/pci/controller/pcie-brcmstb.c
>>> @@ -0,0 +1,973 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/* Copyright (C) 2009 - 2019 Broadcom */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/compiler.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/init.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/io.h>
>>> +#include <linux/ioport.h>
>>> +#include <linux/irqdomain.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/list.h>
>>> +#include <linux/log2.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/of_irq.h>
>>> +#include <linux/of_pci.h>
>>> +#include <linux/of_platform.h>
>>> +#include <linux/pci.h>
>>> +#include <linux/printk.h>
>>> +#include <linux/sizes.h>
>>> +#include <linux/slab.h>
>>> +#include <linux/string.h>
>>> +#include <linux/types.h>
>>> +
>>> +#include "../pci.h"
>>> +
>>> +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
>>> +#define BRCM_PCIE_CAP_REGS 0x00ac
>>> +
>>> +/*
>>> + * Broadcom Settop Box PCIe Register Offsets. The names are from
>>> + * the chip's RDB and we use them here so that a script can correlate
>>> + * this code and the RDB to prevent discrepancies.
>>> + */
>>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
>>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
>>> +#define PCIE_RC_DL_MDIO_ADDR 0x1100
>>> +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
>>> +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
>>> +#define PCIE_MISC_MISC_CTRL 0x4008
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
>>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
>>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
>>> +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
>>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
>>> +#define PCIE_MISC_PCIE_CTRL 0x4064
>>> +#define PCIE_MISC_PCIE_STATUS 0x4068
>>> +#define PCIE_MISC_REVISION 0x406c
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
>>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
>>> +#define PCIE_INTR2_CPU_BASE 0x4300
>>> +
>>> +/*
>>> + * Broadcom Settop Box PCIe Register Field shift and mask info. The
>>> + * names are from the chip's RDB and we use them here so that a script
>>> + * can correlate this code and the RDB to prevent discrepancies.
>>> + */
>>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK
>>> 0xc
>>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT
>>> 0x2
>>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
>>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
>>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
>>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
>>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
>>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
>>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
>>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
>>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
>>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
>>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
>>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
>>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
>>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
>>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
>>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
>>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
>>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
>>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
>>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
>>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
>>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
>>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
>>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
>>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
>>> +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
>>> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff000
>>> 00
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
>>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
>>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
>>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
>>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x080000
>>> 00
>>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
>>> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
>>> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
>>> +
>>> +#define BRCM_NUM_PCIE_OUT_WINS 0x4
>>> +#define BRCM_MAX_SCB 0x4
>>> +
>>> +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
>>> +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
>>> +
>>> +#define BURST_SIZE_128 0
>>> +#define BURST_SIZE_256 1
>>> +#define BURST_SIZE_512 2
>>> +
>>> +/* Offsets from PCIE_INTR2_CPU_BASE */
>>> +#define STATUS 0x0
>>> +#define SET 0x4
>>> +#define CLR 0x8
>>> +#define MASK_STATUS 0xc
>>> +#define MASK_SET 0x10
>>> +#define MASK_CLR 0x14
>>> +
>>> +#define PCIE_BUSNUM_SHIFT 20
>>> +#define PCIE_SLOT_SHIFT 15
>>> +#define PCIE_FUNC_SHIFT 12
>>> +
>>> +#if defined(__BIG_ENDIAN)
>>> +#define DATA_ENDIAN 2 /* PCIe->DDR inbound
> traffic
>>> */
>>> +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound
>>> traffic */
>>> +#else
>>> +#define DATA_ENDIAN 0
>>> +#define MMIO_ENDIAN 0
>>> +#endif
>>> +
>>> +#define MDIO_PORT0 0x0
>>> +#define MDIO_DATA_MASK 0x7fffffff
>>> +#define MDIO_DATA_SHIFT 0x0
>>> +#define MDIO_PORT_MASK 0xf0000
>>> +#define MDIO_PORT_SHIFT 0x16
>>> +#define MDIO_REGAD_MASK 0xffff
>>> +#define MDIO_REGAD_SHIFT 0x0
>>> +#define MDIO_CMD_MASK 0xfff00000
>>> +#define MDIO_CMD_SHIFT 0x14
>>> +#define MDIO_CMD_READ 0x1
>>> +#define MDIO_CMD_WRITE 0x0
>>> +#define MDIO_DATA_DONE_MASK 0x80000000
>>> +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1
>>> : 0)
>>> +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0
>>> : 1)
>>> +#define SSC_REGS_ADDR 0x1100
>>> +#define SET_ADDR_OFFSET 0x1f
>>> +#define SSC_CNTL_OFFSET 0x2
>>> +#define SSC_CNTL_OVRD_EN_MASK 0x8000
>>> +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
>>> +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
>>> +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
>>> +#define SSC_STATUS_OFFSET 0x1
>>> +#define SSC_STATUS_SSC_MASK 0x400
>>> +#define SSC_STATUS_SSC_SHIFT 0xa
>>> +#define SSC_STATUS_PLL_LOCK_MASK 0x800
>>> +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
>>> +
>>> +#define IDX_ADDR(pcie) \
>>> + ((pcie)->reg_offsets[EXT_CFG_INDEX])
>>> +#define DATA_ADDR(pcie) \
>>> + ((pcie)->reg_offsets[EXT_CFG_DATA])
>>> +#define PCIE_RGR1_SW_INIT_1(pcie) \
>>> + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
>>> +
>>> +enum {
>>> + RGR1_SW_INIT_1,
>>> + EXT_CFG_INDEX,
>>> + EXT_CFG_DATA,
>>> +};
>>> +
>>> +enum {
>>> + RGR1_SW_INIT_1_INIT_MASK,
>>> + RGR1_SW_INIT_1_INIT_SHIFT,
>>> + RGR1_SW_INIT_1_PERST_MASK,
>>> + RGR1_SW_INIT_1_PERST_SHIFT,
>>> +};
>>> +
>>> +enum pcie_type {
>>> + BCM2711,
>>> +};
>>> +
>>> +struct brcm_window {
>>> + dma_addr_t pcie_addr;
>>> + phys_addr_t cpu_addr;
>>> + dma_addr_t size;
>>> +};
>>> +
>>> +/* Internal PCIe Host Controller Information.*/
>>> +struct brcm_pcie {
>>> + struct device *dev;
>>> + void __iomem *base;
>>> + int irq;
>>> + struct clk *clk;
>>> + struct pci_bus *root_bus;
>>> + struct device_node *dn;
>>> + int id;
>>> + bool suspended;
>>> + bool ssc;
>>> + int gen;
>>> + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
>>> + unsigned int rev;
>>> + const int *reg_offsets;
>>> + const int *reg_field_info;
>>> + enum pcie_type type;
>>> +};
>>> +
>>> +struct pcie_cfg_data {
>>> + const int *reg_field_info;
>>> + const int *offsets;
>>> + const enum pcie_type type;
>>> +};
>>> +
>>> +static const int pcie_reg_field_info[] = {
>>> + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
>>> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
>>> +};
>>> +
>>> +static const int pcie_offset_bcm2711[] = {
>>> + [RGR1_SW_INIT_1] = 0x9210,
>>> + [EXT_CFG_INDEX] = 0x9000,
>>> + [EXT_CFG_DATA] = 0x8000,
>>> +};
>>
>> Given that there is currently only a single set of register offsets,
>> this seems like it could be simpler.
>
> You're right, there is no need for it as of this series. But since we know
> we'll be supporting other SoCs in the near future I figured it was harmless to
> leave this as a dt dependent config.
>
>>> +
>>> +static const struct pcie_cfg_data bcm2711_cfg = {
>>> + .reg_field_info = pcie_reg_field_info,
>>> + .offsets = pcie_offset_bcm2711,
>>> + .type = BCM2711,
>>> +};
>>> +
>>> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
>>> devfn,
>>> + int where);
>>> +
>>> +static struct pci_ops brcm_pcie_ops = {
>>> + .map_bus = brcm_pcie_map_conf,
>>> + .read = pci_generic_config_read,
>>> + .write = pci_generic_config_write,
>>> +};
>>> +
>>> +#define bcm_readl(a) readl(a)
>>> +#define bcm_writel(d, a) writel(d, a)
>>> +#define bcm_readw(a) readw(a)
>>> +#define bcm_writew(d, a) writew(d, a)
>>> +
>>> +/* These macros extract/insert fields to host controller's register set. */
>>> +#define RD_FLD(base, reg, field) \
>>> + rd_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
>>> +#define WR_FLD(base, reg, field, val) \
>>> + wr_fld((base) + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
>>> +#define WR_FLD_RB(base, reg, field, val) \
>>> + wr_fld_rb((base) + reg, reg##_##field##_MASK, \
>>> + reg##_##field##_SHIFT, val)
>>> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
>>> + wr_fld((base) + reg + (off), reg##_##field##_MASK, \
>>> + reg##_##field##_SHIFT, val)
>>> +#define EXTRACT_FIELD(val, reg, field) \
>>> + (((val) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
>>> +#define INSERT_FIELD(val, reg, field, field_val) \
>>> + (((val) & ~reg##_##field##_MASK) | \
>>> + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
>>> +
>>> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
>>> +{
>>> + return (bcm_readl(p) & mask) >> shift;
>>> +}
>>> +
>>> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
>>> +{
>>> + u32 reg = bcm_readl(p);
>>> +
>>> + reg = (reg & ~mask) | ((val << shift) & mask);
>>> + bcm_writel(reg, p);
>>> +}
>>> +
>>> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
>>> +{
>>> + wr_fld(p, mask, shift, val);
>>> + (void)bcm_readl(p);
>>> +}
>>> +
>>> +static const char *link_speed_to_str(int s)
>>> +{
>>> + switch (s) {
>>> + case 1:
>>> + return "2.5";
>>> + case 2:
>>> + return "5.0";
>>> + case 3:
>>> + return "8.0";
>>> + default:
>>> + break;
>>> + }
>>> + return "???";
>>> +}
>>> +
>>> +/*
>>> + * The roundup_pow_of_two() from log2.h invokes
>>> + * __roundup_pow_of_two(unsigned long), but we really need a
>>> + * such a function to take a native u64 since unsigned long
>>> + * is 32 bits on some configurations. So we provide this helper
>>> + * function below.
>>> + */
>>> +static u64 roundup_pow_of_two_64(u64 n)
>>> +{
>>> + return 1ULL << fls64(n - 1);
>>> +}
>>> +
>>> +/*
>>> + * This is to convert the size of the inbound "BAR" region to the
>>> + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
>>> + */
>>> +int encode_ibar_size(u64 size)
>>> +{
>>> + int log2_in = ilog2(size);
>>> +
>>> + if (log2_in >= 12 && log2_in <= 15)
>>> + /* Covers 4KB to 32KB (inclusive) */
>>> + return (log2_in - 12) + 0x1c;
>>> + else if (log2_in >= 16 && log2_in <= 37)
>>> + /* Covers 64KB to 32GB, (inclusive) */
>>> + return log2_in - 15;
>>> + /* Something is awry so disable */
>>> + return 0;
>>> +}
>>> +
>>> +static u32 mdio_form_pkt(int port, int regad, int cmd)
>>> +{
>>> + u32 pkt = 0;
>>> +
>>> + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
>>> + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
>>> + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
>>> +
>>> + return pkt;
>>> +}
>>> +
>>> +/* negative return value indicates error */
>>> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
>>> +{
>>> + int tries;
>>> + u32 data;
>>> +
>>> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
>>> + base + PCIE_RC_DL_MDIO_ADDR);
>>> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>>> +
>>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>>> + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
>>> + udelay(10);
>>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>>> + }
>>> +
>>> + return MDIO_RD_DONE(data)
>>> + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
>>> + : -EIO;
>>> +}
>>> +
>>> +/* negative return value indicates error */
>>> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
>>> +{
>>> + int tries;
>>> + u32 data;
>>> +
>>> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
>>> + base + PCIE_RC_DL_MDIO_ADDR);
>>> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>>> + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
>>> + base + PCIE_RC_DL_MDIO_WR_DATA);
>>> +
>>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>>> + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
>>> + udelay(10);
>>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>>> + }
>>> +
>>> + return MDIO_WT_DONE(data) ? 0 : -EIO;
>>> +}
>>> +
>>> +/*
>>> + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
>>> + * return value indicates error.
>>> + */
>>> +static int set_ssc(void __iomem *base)
>>> +{
>>> + int tmp;
>>> + u16 wrdata;
>>> + int pll, ssc;
>>> +
>>> + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
>>> + if (tmp < 0)
>>> + return tmp;
>>> +
>>> + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
>>> + if (tmp < 0)
>>> + return tmp;
>>> +
>>> + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
>>> + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
>>> + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
>>> + if (tmp < 0)
>>> + return tmp;
>>> +
>>> + usleep_range(1000, 2000);
>>> + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
>>> + if (tmp < 0)
>>> + return tmp;
>>> +
>>> + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
>>> + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
>>
>> This is actually the PCIe phy?
>
> I'll let Jim reply this one.
>
>>> +
>>> + return (ssc && pll) ? 0 : -EIO;
>>> +}
>>> +
>>> +/* Limits operation to a specific generation (1, 2, or 3) */
>>> +static void set_gen(void __iomem *base, int gen)
>>> +{
>>> + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
>>> + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
>>> +
>>> + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
>>> + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
>>> +
>>> + lnkctl2 = (lnkctl2 & ~0xf) | gen;
>>> + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
>>> +}
>>> +
>>> +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
>>> + unsigned int win, phys_addr_t cpu_addr,
>>> + dma_addr_t pcie_addr, dma_addr_t size)
>>> +{
>>> + void __iomem *base = pcie->base;
>>> + phys_addr_t cpu_addr_mb, limit_addr_mb;
>>> + u32 tmp;
>>> +
>>> + /* Set the base of the pcie_addr window */
>>> + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
>>> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
>>> + bcm_writel(upper_32_bits(pcie_addr),
>>> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
>>> +
>>> + cpu_addr_mb = cpu_addr >> 20;
>>> + limit_addr_mb = (cpu_addr + size - 1) >> 20;
>>> +
>>> + /* Write the addr base low register */
>>> + WR_FLD_WITH_OFFSET(base, (win * 4),
>>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>>> + BASE, cpu_addr_mb);
>>> + /* Write the addr limit low register */
>>> + WR_FLD_WITH_OFFSET(base, (win * 4),
>>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>>> + LIMIT, limit_addr_mb);
>>> +
>>> + /* Write the cpu addr high register */
>>> + tmp = (u32)(cpu_addr_mb >>
>>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>>> + WR_FLD_WITH_OFFSET(base, (win * 8),
>>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
>>> + BASE, tmp);
>>> + /* Write the cpu limit high register */
>>> + tmp = (u32)(limit_addr_mb >>
>>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>>> + WR_FLD_WITH_OFFSET(base, (win * 8),
>>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
>>> + LIMIT, tmp);
>>> +}
>>
>> So this is translating a high CPU address to a <32-bit PCI MMIO window?
>
> Yes, for the record, this is what the RPi4 uses:
>
> ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
>
>> I thought there was some kind of 32-bit limitation in front of this root
>> port?
>
> We have a limitation for DMA accesses (can't access the 0xc0000000-0xffffffff
> area) due to a bug on the PCIe core integration, not a limitation on the
> interconnect. But this doesn't apply for BAR accesses. Though....
>
>> This makes it sound like the root port can recieve 64-bit MMIO
>> writes just fine.
>
> ...I've been told we have to imperatively place the outbound memory area in the
> lower 4GB. This is a shortcoming on the PCIe controller side.
So its CPU 0x600000000->0x600400000 being translated to PCIe
0xf800000->0xF8400000. Which looks to be reserved in the lower 4G
address space on the CPU as well (can't really tell without docs). So,
Ideally it would just be a 1:1 translation @ 0xf8000000 on both the CPU
and PCI side, but presumably it can't decode that? And the PCIe side can
recieve 64-bit transactions @0x600000000, but can't form large MMIO TLPs
at that address?
>
>> IIRC XHCI can run with just two 64-bit BARS, so it
>> sounds like the translation here isn't strictly nessisary until someone
>> wants a 32-bit non-prefechable bar. No?
>>> +
>>> +/* Configuration space read/write support */
>>> +static int cfg_index(int busnr, int devfn, int reg)
>>> +{
>>> + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
>>> + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
>>> + | (busnr << PCIE_BUSNUM_SHIFT)
>>> + | (reg & ~3);
>>> +}
>>> +
>>> +/* The controller is capable of serving in both RC and EP roles */
>>> +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
>>> +{
>>> + void __iomem *base = pcie->base;
>>> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
>>> +
>>> + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
>>> +}
>>> +
>>> +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
>>> +{
>>> + void __iomem *base = pcie->base;
>>> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
>>> + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
>>> + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
>>> +
>>> + return (dla && plu) ? true : false;
>>> +}
>>> +
>>> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int
>>> devfn,
>>> + int where)
>>> +{
>>> + struct brcm_pcie *pcie = bus->sysdata;
>>> + void __iomem *base = pcie->base;
>>> + int idx;
>>> +
>>> + /* Accesses to the RC go right to the RC registers if slot==0 */
>>> + if (pci_is_root_bus(bus))
>>> + return PCI_SLOT(devfn) ? NULL : base + where;
>>> +
>>> + /* For devices, write to the config space index register */
>>> + idx = cfg_index(bus->number, devfn, 0);
>>> + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
>>> + return base + DATA_ADDR(pcie) + where;
>>> +}
>>
>> So, each pci cfg space access requires a cfg register write, so that the
>> data space for the bdf can be accessed?
>
> Yes, that's it.
>
>> Using map_bus() to setup the cfg region rather than overriding the
>> generic read/write callbacks means that in the future we can't enable
>> PCI_LOCKLESS_CONFIG in a generic arm64 kernel.
>
> That'd be hard anyways, it seems to me that a lot of arm64 devices depend on
> this, right?
I'm not really sure, the lock removal appeared fairly recently as a perf
optimization. Which makes sense for ECAM (which should be the goal of
all the ARM SOCs these days to avoid the need for PCIe host drivers)
platforms.
Quite a number of ARM platforms shouldn't need the lock as their CFG
accessors are only quirked for alignment or address mapping. Which means
that we are penalizing platforms that dont need the lock for the ones
that do.
>
>>> +
>>> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
>>> + unsigned int val)
>>> +{
>>> + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
>>> + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
>>> +
>>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift, val);
>>> +}
>>> +
>>> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
>>> + unsigned int val)
>>> +{
>>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
>>> + PCIE_RGR1_SW_INIT_1_PERST_MASK,
>>> + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
>>> +}
>>> +
>>> +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie
>>> *pcie,
>>> + u64 *rc_bar2_size,
>>> + u64 *rc_bar2_offset)
>>> +{
>>> + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
>>> + struct device *dev = pcie->dev;
>>> + struct resource_entry *entry;
>>> + u64 total_mem_size = 0;
>>> +
>>> + *rc_bar2_offset = -1;
>>> +
>>> + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
>>> + /*
>>> + * We're promissed the RC will provide a contiguous view of
>>> + * memory to downstream devices. We can then infer the
>>> + * rc_bar2_offset from the lower avaiable dma-range offset.
>>> + */
>>> + if (entry->offset < *rc_bar2_offset)
>>> + *rc_bar2_offset = entry->offset;
>>> +
>>> + total_mem_size += entry->res->end - entry->res->start + 1;
>>> + }
>>> +
>>> + *rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
>>> +
>>> + /*
>>> + * Validate the results:
>>> + *
>>> + * The PCIe host controller by design must set the inbound viewport to
>>> + * be a contiguous arrangement of all of the system's memory. In
>>> + * addition, its size mut be a power of two. To further complicate
>>> + * matters, the viewport must start on a pcie-address that is aligned
>>> + * on a multiple of its size. If a portion of the viewport does not
>>> + * represent system memory -- e.g. 3GB of memory requires a 4GB
>>> + * viewport -- we can map the outbound memory in or after 3GB and even
>>> + * though the viewport will overlap the outbound memory the controller
>>> + * will know to send outbound memory downstream and everything else
>>> + * upstream.
>>> + *
>>> + * For example:
>>> + *
>>> + * - The best-case scenario, memory up to 3GB, is to place the inbound
>>> + * region in the first 4GB of pcie-space, as some legacy devices can
>>> + * only address 32bits. We would also like to put the MSI under 4GB
>>> + * as well, since some devices require a 32bit MSI target address.
>>> + *
>>> + * - If the system memory is 4GB or larger we cannot start the inbound
>>> + * region at location 0 (since we have to allow some space for
>>> + * outbound memory @ 3GB). So instead it will start at the 1x
>>> + * multiple of its size
>>> + */
>>> + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
>>> + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
>>> + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off
>>> 0x%llx\n",
>>> + *rc_bar2_size, *rc_bar2_offset);
>>> + return -EINVAL;
>>> + }
>>
>> If the MMIO window isn't translated and is left high
>
> Sadly, as I commented in the outbound memory config code, this is not possible.
>
>> does it work to just use a single 0->$TOP_OF_RAM mapping, even with the
>> 32-bit limitation? Or is the 32-bit limitation comming from this programming?
>
> We can use that 1:1 mapping as long as we leave some space for the outbound
> memory and follow the alignment rules stated above. It's a HW limitation.
>
> Just let me stress that in the end I'm just validating whatever the firmware
> provided, I'm not really modifying anything here. I could do away with the
> check as it'd be plain silly if the FW provided wrong dma-ranges. But since
> people are likely to play around with RPi's dtb, I figured it's worthwhile.
>
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int brcm_pcie_setup(struct brcm_pcie *pcie)
>>> +{
>>> + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
>>> + u64 rc_bar2_offset, rc_bar2_size;
>>> + void __iomem *base = pcie->base;
>>> + struct resource_entry *entry;
>>> + unsigned int scb_size_val;
>>> + struct resource *res;
>>> + int num_out_wins = 0;
>>> + u32 tmp;
>>> + int i, j, ret, limit;
>>> + u16 nlw, cls, lnksta;
>>> + bool ssc_good = false;
>>> + struct device *dev = pcie->dev;
>>> +
>>> + /* Reset the bridge */
>>> + brcm_pcie_bridge_sw_init_set(pcie, 1);
>>> +
>>> + usleep_range(100, 200);
>>> +
>>> + /* Take the bridge out of reset */
>>> + brcm_pcie_bridge_sw_init_set(pcie, 0);
>>> +
>>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>>> + /* Wait for SerDes to be stable */
>>> + usleep_range(100, 200);
>>> +
>>> + /* Grab the PCIe hw revision number */
>>> + tmp = bcm_readl(base + PCIE_MISC_REVISION);
>>> + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
>>> +
>>> + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
>>> + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
>>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
>>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE,
>>> + BURST_SIZE_128);
>>> + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
>>
>> Presumablly users will want to use PCIe at some point in the future for
>> booting/etc. That means the firmware will perform sufficient setup that
>> you shouldn't need much of the code in this function if the address
>> windows, serdes, etc are functional when linux boots. Similarly for
>> suspend/resume.
>
> I see what you mean, although it's not the case for now as RPi's firmware
> doesn't initialize anything. Though I can imagine some people might want this
> if the RPi4 compute module ever comes out.
>
> If it's OK with you I think we can let it be for now.
Well this is actually why I commented on the whole set. A large part of
this driver appears to be working around the shortcommings in the
current firmware when it comes to programming the bridge. Once the
firmware integrates that functionality (there appear to be rpi ports
underway in uboot/edk2/atf) large parts of this driver will become
unessisary. Not to mention the other OS's that have historically wanted
to support the rpi will have an easier time of it as well.
>
>>> +
>>> + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
>>> + &rc_bar2_offset);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + tmp = lower_32_bits(rc_bar2_offset);
>>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
>>> + encode_ibar_size(rc_bar2_size));
>>> + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
>>> + bcm_writel(upper_32_bits(rc_bar2_offset),
>>> + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
>>> +
>>> + scb_size_val = rc_bar2_size ?
>>> + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
>>> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
>>> +
>>> + /* disable the PCIe->GISB memory window (RC_BAR1) */
>>> + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
>>> +
>>> + /* disable the PCIe->SCB memory window (RC_BAR3) */
>>> + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
>>> +
>>> + if (!pcie->suspended) {
>>> + /* clear any interrupts we find on boot */
>>> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
>>> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
>>> + }
>>> +
>>> + /* Mask all interrupts since we are not handling any yet */
>>> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
>>> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
>>> +
>>> + if (pcie->gen)
>>> + set_gen(base, pcie->gen);
>>> +
>>> + /* Unassert the fundamental reset */
>>> + brcm_pcie_perst_set(pcie, 0);
>>> +
>>> + /*
>>> + * Give the RC/EP time to wake up, before trying to configure RC.
>>> + * Intermittently check status for link-up, up to a total of 100ms
>>> + * when we don't know if the device is there, and up to 1000ms if
>>> + * we do know the device is there.
>>> + */
>>> + limit = pcie->suspended ? 1000 : 100;
>>> + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
>>> + j += i, i = i * 2)
>>> + msleep(i + j > limit ? limit - j : i);
>>> +
>>> + if (!brcm_pcie_link_up(pcie)) {
>>> + dev_info(dev, "link down\n");
>>> + return -ENODEV;
>>> + }
>>> +
>>> + if (!brcm_pcie_rc_mode(pcie)) {
>>> + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + resource_list_for_each_entry(entry, &bridge->windows) {
>>> + res = entry->res;
>>> +
>>> + if (resource_type(res) != IORESOURCE_MEM)
>>> + continue;
>>> +
>>> + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
>>> + dev_err(pcie->dev, "too many outbound wins\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
>>> + res->start - entry->offset,
>>> + res->end - res->start + 1);
>>> + num_out_wins++;
>>> + }
>>> +
>>> + /*
>>> + * For config space accesses on the RC, show the right class for
>>> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
>>> + */
>>> + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
>>> +
>>> + if (pcie->ssc) {
>>> + ret = set_ssc(base);
>>> + if (ret == 0)
>>> + ssc_good = true;
>>> + else
>>> + dev_err(dev, "failed attempt to enter ssc mode\n");
>>> + }
>>> +
>>> + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
>>> + cls = lnksta & PCI_EXP_LNKSTA_CLS;
>>> + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
>>> + dev_info(dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
>>> + nlw, ssc_good ? "(SSC)" : "(!SSC)");
>>> +
>>> + /* PCIe->SCB endian mode for BAR */
>>> + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
>>> + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
>>> + ENDIAN_MODE_BAR2, DATA_ENDIAN);
>>> +
>>> + /*
>>> + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
>>> + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
>>> + */
>>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +/* L23 is a low-power PCIe link state */
>>> +static void enter_l23(struct brcm_pcie *pcie)
>>> +{
>>> + void __iomem *base = pcie->base;
>>> + int l23, i;
>>> +
>>> + /* assert request for L23 */
>>> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
>>> +
>>> + /* Wait up to 30 msec for L23 */
>>> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
>>> + for (i = 0; i < 15 && !l23; i++) {
>>> + usleep_range(2000, 2400);
>>> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
>>> + }
>>> +
>>> + if (!l23)
>>> + dev_err(pcie->dev, "failed to enter L23\n");
>>> +}
>>> +
>>> +static void turn_off(struct brcm_pcie *pcie)
>>> +{
>>> + void __iomem *base = pcie->base;
>>> +
>>> + if (brcm_pcie_link_up(pcie))
>>> + enter_l23(pcie);
>>> + /* Assert fundamental reset */
>>> + brcm_pcie_perst_set(pcie, 1);
>>> + /* Deassert request for L23 in case it was asserted */
>>> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
>>> + /* Turn off SerDes */
>>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
>>> + /* Shutdown PCIe bridge */
>>> + brcm_pcie_bridge_sw_init_set(pcie, 1);
>>> +}
>>> +
>>> +static int brcm_pcie_suspend(struct device *dev)
>>> +{
>>> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
>>> +
>>> + turn_off(pcie);
>>> + clk_disable_unprepare(pcie->clk);
>>> + pcie->suspended = true;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int brcm_pcie_resume(struct device *dev)
>>> +{
>>> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
>>> + void __iomem *base;
>>> + int ret;
>>> +
>>> + base = pcie->base;
>>> + clk_prepare_enable(pcie->clk);
>>> +
>>> + /* Take bridge out of reset so we can access the SerDes reg */
>>> + brcm_pcie_bridge_sw_init_set(pcie, 0);
>>> +
>>> + /* Turn on SerDes */
>>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>>> + /* Wait for SerDes to be stable */
>>> + usleep_range(100, 200);
>>> +
>>> + ret = brcm_pcie_setup(pcie);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + pcie->suspended = false;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>>> +{
>>> + turn_off(pcie);
>>> + clk_disable_unprepare(pcie->clk);
>>> + clk_put(pcie->clk);
>>> +}
>>> +
>>> +static int brcm_pcie_remove(struct platform_device *pdev)
>>> +{
>>> + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
>>> +
>>> + pci_stop_root_bus(pcie->root_bus);
>>> + pci_remove_root_bus(pcie->root_bus);
>>> + _brcm_pcie_remove(pcie);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct of_device_id brcm_pcie_match[] = {
>>> + { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
>>> +
>>> +static int brcm_pcie_probe(struct platform_device *pdev)
>>> +{
>>> + struct device_node *dn = pdev->dev.of_node;
>>> + const struct of_device_id *of_id;
>>> + const struct pcie_cfg_data *data;
>>> + struct resource *res;
>>> + int ret;
>>> + struct brcm_pcie *pcie;
>>> + void __iomem *base;
>>> + struct pci_host_bridge *bridge;
>>> + struct pci_bus *child;
>>> +
>>> + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
>>> + if (!bridge)
>>> + return -ENOMEM;
>>> +
>>> + pcie = pci_host_bridge_priv(bridge);
>>> +
>>> + of_id = of_match_node(brcm_pcie_match, dn);
>>> + if (!of_id) {
>>> + dev_err(&pdev->dev, "failed to look up compatible string\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + data = of_id->data;
>>> + pcie->reg_offsets = data->offsets;
>>> + pcie->reg_field_info = data->reg_field_info;
>>> + pcie->type = data->type;
>>> + pcie->dn = dn;
>>> + pcie->dev = &pdev->dev;
>>> +
>>> + /* We use the domain number as our controller number */
>>> + pcie->id = of_get_pci_domain_nr(dn);
>>> + if (pcie->id < 0)
>>> + return pcie->id;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + if (!res)
>>> + return -EINVAL;
>>> +
>>> + base = devm_ioremap_resource(&pdev->dev, res);
>>> + if (IS_ERR(base))
>>> + return PTR_ERR(base);
>>> +
>>> + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
>>> + if (IS_ERR(pcie->clk)) {
>>> + dev_err(&pdev->dev, "could not get clock\n");
>>> + pcie->clk = NULL;
>>> + }
>>
>> Is there a sw_pcie clock in the system?
>
> AFAIK it's there and there's a firmware interface available. That said, if
> possible (i.e. not clashing with some firmware routine) it would be nice to
> integrate it into the memory mapped clock driver. It's always the preferred
> solution. Though to do so we need more documentation.
>
> Overall it's not really needed for now.
>
>>> + pcie->base = base;
>>> +
>>> + ret = of_pci_get_max_link_speed(dn);
>>> + pcie->gen = (ret < 0) ? 0 : ret;
>>> +
>>> + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
>>> +
>>> + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
>>> + if (ret == 0)
>>> + /* keep going, as we don't use this intr yet */
>>> + dev_warn(pcie->dev, "cannot get PCIe interrupt\n");
>>> + else
>>> + pcie->irq = ret;
>>> +
>>> + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
>>> + &bridge->dma_ranges, NULL);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + ret = clk_prepare_enable(pcie->clk);
>>> + if (ret) {
>>> + dev_err(&pdev->dev, "could not enable clock\n");
>>> + return ret;
>>> + }
>>> +
>>> + ret = brcm_pcie_setup(pcie);
>>> + if (ret)
>>> + goto fail;
>>> +
>>> + bridge->dev.parent = &pdev->dev;
>>> + bridge->busnr = 0;
>>> + bridge->ops = &brcm_pcie_ops;
>>> + bridge->sysdata = pcie;
>>> + bridge->map_irq = of_irq_parse_and_map_pci;
>>> + bridge->swizzle_irq = pci_common_swizzle;
>>> +
>>> + ret = pci_scan_root_bus_bridge(bridge);
>>> + if (ret < 0) {
>>> + dev_err(pcie->dev, "Scanning root bridge failed\n");
>>> + goto fail;
>>> + }
>>> +
>>> + pci_assign_unassigned_bus_resources(bridge->bus);
>>> + list_for_each_entry(child, &bridge->bus->children, node)
>>> + pcie_bus_configure_settings(child);
>>> + pci_bus_add_devices(bridge->bus);
>>> + platform_set_drvdata(pdev, pcie);
>>> + pcie->root_bus = bridge->bus;
>>> +
>>> + return 0;
>>> +
>>> +fail:
>>> + _brcm_pcie_remove(pcie);
>>> + return ret;
>>> +}
>>> +
>>> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
>>> + .suspend_noirq = brcm_pcie_suspend,
>>> + .resume_noirq = brcm_pcie_resume,
>>> +};
>>> +
>>> +static struct platform_driver brcm_pcie_driver = {
>>> + .probe = brcm_pcie_probe,
>>> + .remove = brcm_pcie_remove,
>>> + .driver = {
>>> + .name = "brcm-pcie",
>>> + .owner = THIS_MODULE,
>>> + .of_match_table = brcm_pcie_match,
>>> + .pm = &brcm_pcie_pm_ops,
>>> + },
>>> +};
>>> +
>>> +module_platform_driver(brcm_pcie_driver);
>>> +
>>> +MODULE_LICENSE("GPL v2");
>>> +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
>>> +MODULE_AUTHOR("Broadcom");
>>>
>
On 11/11/2019 12:00 PM, Jeremy Linton wrote:
[snip]
>>> Presumablly users will want to use PCIe at some point in the future for
>>> booting/etc. That means the firmware will perform sufficient setup that
>>> you shouldn't need much of the code in this function if the address
>>> windows, serdes, etc are functional when linux boots. Similarly for
>>> suspend/resume.
>>
>> I see what you mean, although it's not the case for now as RPi's firmware
>> doesn't initialize anything. Though I can imagine some people might
>> want this
>> if the RPi4 compute module ever comes out.
>>
>> If it's OK with you I think we can let it be for now.
>
> Well this is actually why I commented on the whole set. A large part of
> this driver appears to be working around the shortcommings in the
> current firmware when it comes to programming the bridge. Once the
> firmware integrates that functionality (there appear to be rpi ports
> underway in uboot/edk2/atf) large parts of this driver will become
> unessisary. Not to mention the other OS's that have historically wanted
> to support the rpi will have an easier time of it as well.
You are making this assumption based on the current submission which
specifically targets 2711 for now, the latter which could, in premise
gain support for an uboot/edk2/atf doing a fair amount of configuration
on behalf of Linux. This same driver is used on MIPS platforms (no
firmware), on ARMv7a 32-bit platforms with no ATF, and on ARM 64-bit
platforms with an ATF that we purposely have made unaware of PCIe. Those
platforms also support suspend to DRAM and S2. In Suspend to DRAM, all
register contents are lost since PCIe is not on the always-on island,
which is why a fair amount of (re)configuration also occurs there.
There is not to my knowledge any firmware, or software prior to Linux
configuring the PCIe bridge (2711 or otherwise) because it historically
has not been required/deemed necessary/desirable and for the vast
majority of platforms where this driver is used, I expect that situation
to remain for the years to come. For Broadcom STB platforms where this
has been used for the most part, none of our customers have used PCIe to
connect a southbridge to gain SATA/USB/Ethernet peripherals, since we
have all of those on-chip already, therefore even the boot loader(s)
used on these platforms do not support boot from PCIe. The vast majority
(98%) of use cases are WLAN, and occasionally NVMe.
Since there are a few @arm.com participants in this thread, if
standardization of the PCIe host bridge is so important, maybe
entertaining the idea of delivering a PCIe MAC (and leaving the PHY as
something to be done by the integrator) as another IP in your portfolio
would given some give some incentive to avoiding doing that piece of HW
(and FW, and SW) and save the pain of compliance, memory semantics,
bridging and all of those things easy to get wrong.
--
Florian
Hi Andrew,
On Thu, 2019-11-07 at 10:37 +0000, Andrew Murray wrote:
> > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
> > + 0x0 0x04000000>;
>
> Is legacy I/O supported by this controller?
>
No, it isn't.
Regards,
Nicolas
On Wed, Nov 06, 2019 at 10:45:23PM +0100, Nicolas Saenz Julienne wrote:
> From: Jim Quinlan <[email protected]>
>
> The DT bindings description of the brcmstb PCIe device is described.
> This node can only be used for now on the Raspberry Pi 4.
>
> This was based on Jim's original submission[1], converted to yaml and
> adapted to the RPi4 case.
>
> [1] https://patchwork.kernel.org/patch/10605937/
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> ---
> .../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++
> 1 file changed, 116 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
I'm working on a common PCI host schema that should cut down some of the
standard props.
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> new file mode 100644
> index 000000000000..0b81c26f8568
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -0,0 +1,116 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license new bindings please:
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Brcmstb PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> + - Nicolas Saenz Julienne <[email protected]>
> +
> +properties:
> + compatible:
> + const: brcm,bcm2711-pcie # The Raspberry Pi 4
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: PCIe host controller
> + - description: builtin MSI controller
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 2
> + items:
> + - const: pcie
> + - const: msi
> +
> + "#address-cells":
> + const: 3
> +
> + "#size-cells":
> + const: 2
> +
> + "#interrupt-cells":
> + const: 1
> +
> + interrupt-map-mask: true
> +
> + interrupt-map: true
4 entries?
You'll need to bracket <> each entry in the example and dts.
> +
> + ranges: true
How many entries?
> +
> + dma-ranges: true
How many entries?
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: sw_pcie
> +
> + msi-controller:
> + description: Identifies the node as an MSI controller.
> + type: boolean
> +
> + msi-parent:
> + description: MSI controller the device is capable of using.
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> + linux,pci-domain:
> + description: PCI domain ID. Should be unique for each host controller.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + brcm,enable-ssc:
> + description: Indicates usage of spread-spectrum clocking.
> + type: boolean
> +
> +required:
> + - compatible
> + - reg
> + - "#address-cells"
> + - "#size-cells"
> + - "#interrupt-cells"
> + - interrupt-map-mask
> + - interrupt-map
> + - ranges
> + - dma-ranges
> + - linux,pci-domain
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + scb {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + pcie0: pcie@7d500000 {
> + compatible = "brcm,bcm2711-pcie";
> + reg = <0x0 0x7d500000 0x9310>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pcie", "msi";
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH
> + 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + msi-parent = <&pcie0>;
> + msi-controller;
> + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
> + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
> + linux,pci-domain = <0>;
> + brcm,enable-ssc;
> + };
> + };
> --
> 2.23.0
>
On Tue, 2019-11-12 at 22:15 -0600, Rob Herring wrote:
> On Wed, Nov 06, 2019 at 10:45:23PM +0100, Nicolas Saenz Julienne wrote:
> > From: Jim Quinlan <[email protected]>
> >
> > The DT bindings description of the brcmstb PCIe device is described.
> > This node can only be used for now on the Raspberry Pi 4.
> >
> > This was based on Jim's original submission[1], converted to yaml and
> > adapted to the RPi4 case.
> >
> > [1] https://patchwork.kernel.org/patch/10605937/
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
> > Co-developed-by: Nicolas Saenz Julienne <[email protected]>
> > Signed-off-by: Nicolas Saenz Julienne <[email protected]>
> > ---
> > .../bindings/pci/brcm,stb-pcie.yaml | 116 ++++++++++++++++++
> > 1 file changed, 116 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
>
> I'm working on a common PCI host schema that should cut down some of the
> standard props.
Is there a way for me to have a look at it so I can rebase the binding on top
of it?
> > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > new file mode 100644
> > index 000000000000..0b81c26f8568
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > @@ -0,0 +1,116 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license new bindings please:
>
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Noted
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Brcmstb PCIe Host Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Nicolas Saenz Julienne <[email protected]>
> > +
> > +properties:
> > + compatible:
> > + const: brcm,bcm2711-pcie # The Raspberry Pi 4
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 2
> > + items:
> > + - description: PCIe host controller
> > + - description: builtin MSI controller
> > +
> > + interrupt-names:
> > + minItems: 1
> > + maxItems: 2
> > + items:
> > + - const: pcie
> > + - const: msi
> > +
> > + "#address-cells":
> > + const: 3
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > + "#interrupt-cells":
> > + const: 1
> > +
> > + interrupt-map-mask: true
> > +
> > + interrupt-map: true
>
> 4 entries?
You're right, for this specific case, as XHCI is hardwired and only uses one
irq, we'd only need the first entry. Although who knows, maybe they are wired
nonetheless. I guess it's safer to assume they aren't for now.
> You'll need to bracket <> each entry in the example and dts.
Ok
> > +
> > + ranges: true
>
> How many entries?
One, I'll update it.
> > +
> > + dma-ranges: true
>
> How many entries?
One, I'll update it.
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + items:
> > + - const: sw_pcie
> > +
> > + msi-controller:
> > + description: Identifies the node as an MSI controller.
> > + type: boolean
> > +
> > + msi-parent:
> > + description: MSI controller the device is capable of using.
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > +
> > + linux,pci-domain:
> > + description: PCI domain ID. Should be unique for each host controller.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + brcm,enable-ssc:
> > + description: Indicates usage of spread-spectrum clocking.
> > + type: boolean
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - "#address-cells"
> > + - "#size-cells"
> > + - "#interrupt-cells"
> > + - interrupt-map-mask
> > + - interrupt-map
> > + - ranges
> > + - dma-ranges
> > + - linux,pci-domain
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + scb {
> > + #address-cells = <2>;
> > + #size-cells = <1>;
> > + pcie0: pcie@7d500000 {
> > + compatible = "brcm,bcm2711-pcie";
> > + reg = <0x0 0x7d500000 0x9310>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pcie", "msi";
> > + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> > + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
> > IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 2 &gicv2 GIC_SPI 144
> > IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 3 &gicv2 GIC_SPI 145
> > IRQ_TYPE_LEVEL_HIGH
> > + 0 0 0 4 &gicv2 GIC_SPI 146
> > IRQ_TYPE_LEVEL_HIGH>;
> > + msi-parent = <&pcie0>;
> > + msi-controller;
> > + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0
> > 0x04000000>;
> > + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
> > 0x0 0x80000000>;
> > + linux,pci-domain = <0>;
> > + brcm,enable-ssc;
> > + };
> > + };
> > --
> > 2.23.0
> >
>
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