Qualcomm crypto engine supports hardware accelerated algorithms for
encryption and authentication. Enable support for aes,des,3des encryption
algorithms and sha1,sha256, hmac(sha1),hmac(sha256) authentication
algorithms on sdm845.The patch series has been tested using the kernel
crypto testing module tcrypto.ko.
v1->v2:
- Rebased to linux-next v5.10-rc4.
- Fixed subject line format in all patches as per Bjorn's feedback.
Thara Gopinath (6):
dt-binding:clock: Add entry for crypto engine RPMH clock resource
clk:qcom:rpmh: Add CE clock on sdm845.
drivers:crypto:qce: Enable support for crypto engine on sdm845.
drivers:crypto:qce: Fix SHA result buffer corruption issues.
dts:qcom:sdm845: Add dt entries to support crypto engine.
devicetree:bindings:crypto: Extend qcom-qce binding to add support for
crypto engine version 5.4
.../devicetree/bindings/crypto/qcom-qce.txt | 4 ++-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 +++++++++++++++++++
drivers/clk/qcom/clk-rpmh.c | 2 ++
drivers/crypto/qce/core.c | 17 ++++++++++-
drivers/crypto/qce/sha.c | 2 +-
include/dt-bindings/clock/qcom,rpmh.h | 1 +
6 files changed, 53 insertions(+), 3 deletions(-)
--
2.25.1
Add support Qualcomm Crypto Engine accelerated encryption and
authentication algorithms on sdm845.
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/crypto/qce/core.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/core.c b/drivers/crypto/qce/core.c
index ea616b7259ae..67c3ca13e55b 100644
--- a/drivers/crypto/qce/core.c
+++ b/drivers/crypto/qce/core.c
@@ -160,7 +160,21 @@ static int qce_check_version(struct qce_device *qce)
return -ENODEV;
qce->burst_size = QCE_BAM_BURST_SIZE;
- qce->pipe_pair_id = 1;
+
+ /*
+ * Rx and tx pipes are treated as a pair inside CE.
+ * Pipe pair number depends on the actual BAM dma pipe
+ * that is used for transfers. The BAM dma pipes are passed
+ * from the device tree and used to derive the pipe pair
+ * id in the CE driver as follows.
+ * BAM dma pipes(rx, tx) CE pipe pair id
+ * 0,1 0
+ * 2,3 1
+ * 4,5 2
+ * 6,7 3
+ * ...
+ */
+ qce->pipe_pair_id = qce->dma.rxchan->chan_id >> 1;
dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
major, minor, step);
@@ -261,6 +275,7 @@ static int qce_crypto_remove(struct platform_device *pdev)
static const struct of_device_id qce_crypto_of_match[] = {
{ .compatible = "qcom,crypto-v5.1", },
+ { .compatible = "qcom,crypto-v5.4", },
{}
};
MODULE_DEVICE_TABLE(of, qce_crypto_of_match);
--
2.25.1
Add crypto engine (CE) and CE BAM related nodes and definitions to
"sdm845.dtsi".
Signed-off-by: Thara Gopinath <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 ++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 40e8c11f23ab..b5b2ea97681f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2138,6 +2138,36 @@ ufs_mem_phy_lanes: lanes@1d87400 {
};
};
+ cryptobam: dma@1dc4000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x24000>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rpmhcc RPMH_CE_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ qcom,controlled-remotely = <1>;
+ iommus = <&apps_smmu 0x704 0x1>,
+ <&apps_smmu 0x706 0x1>,
+ <&apps_smmu 0x714 0x1>,
+ <&apps_smmu 0x716 0x1>;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,crypto-v5.4";
+ reg = <0 0x01dfa000 0 0x6000>;
+ clocks = <&gcc GCC_CE1_AHB_CLK>,
+ <&gcc GCC_CE1_AHB_CLK>,
+ <&rpmhcc RPMH_CE_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 6>, <&cryptobam 7>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x704 0x1>,
+ <&apps_smmu 0x706 0x1>,
+ <&apps_smmu 0x714 0x1>,
+ <&apps_smmu 0x716 0x1>;
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sdm845-ipa";
--
2.25.1
Add compatible string to support v5.4 crypto engine.
Signed-off-by: Thara Gopinath <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
---
Documentation/devicetree/bindings/crypto/qcom-qce.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
index fdd53b184ba8..ed1ede9c0acc 100644
--- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
@@ -2,7 +2,9 @@ Qualcomm crypto engine driver
Required properties:
-- compatible : should be "qcom,crypto-v5.1"
+- compatible : should be
+ "qcom,crypto-v5.1" for ipq6018
+ "qcom,crypto-v5.4" for sdm845
- reg : specifies base physical address and size of the registers map
- clocks : phandle to clock-controller plus clock-specifier pair
- clock-names : "iface" clocks register interface
--
2.25.1
Add clock id forc CE clock resource which is required to bring up the
crypto engine on sdm845.
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
---
include/dt-bindings/clock/qcom,rpmh.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h
index 2e6c54e65455..30111c8f7fe9 100644
--- a/include/dt-bindings/clock/qcom,rpmh.h
+++ b/include/dt-bindings/clock/qcom,rpmh.h
@@ -21,5 +21,6 @@
#define RPMH_IPA_CLK 12
#define RPMH_LN_BB_CLK1 13
#define RPMH_LN_BB_CLK1_A 14
+#define RPMH_CE_CLK 15
#endif
--
2.25.1
Partial hash was being copied into the final result buffer without the
entire message block processed. Depending on how the end user processes
this result buffer, errors vary from result buffer corruption to result
buffer poisoing. Fix this issue by ensuring that only the final hash value
is copied into the result buffer.
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
---
drivers/crypto/qce/sha.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index 87be96a0b0bb..61c418c12345 100644
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -48,7 +48,7 @@ static void qce_ahash_done(void *data)
dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
memcpy(rctx->digest, result->auth_iv, digestsize);
- if (req->result)
+ if (req->result && rctx->last_blk)
memcpy(req->result, result->auth_iv, digestsize);
rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
--
2.25.1
Quoting Thara Gopinath (2020-11-19 07:52:31)
> Partial hash was being copied into the final result buffer without the
> entire message block processed. Depending on how the end user processes
> this result buffer, errors vary from result buffer corruption to result
> buffer poisoing. Fix this issue by ensuring that only the final hash value
> is copied into the result buffer.
>
> Reviewed-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
Any Fixes tag?
Quoting Thara Gopinath (2020-11-19 07:52:28)
> Add clock id forc CE clock resource which is required to bring up the
> crypto engine on sdm845.
>
> Reviewed-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Thara Gopinath <[email protected]>
> ---
Applied to clk-next
On Thu, Nov 19, 2020 at 10:52:27AM -0500, Thara Gopinath wrote:
> Qualcomm crypto engine supports hardware accelerated algorithms for
> encryption and authentication. Enable support for aes,des,3des encryption
> algorithms and sha1,sha256, hmac(sha1),hmac(sha256) authentication
> algorithms on sdm845.The patch series has been tested using the kernel
> crypto testing module tcrypto.ko.
>
> v1->v2:
> - Rebased to linux-next v5.10-rc4.
> - Fixed subject line format in all patches as per Bjorn's feedback.
>
> Thara Gopinath (6):
> dt-binding:clock: Add entry for crypto engine RPMH clock resource
> clk:qcom:rpmh: Add CE clock on sdm845.
> drivers:crypto:qce: Enable support for crypto engine on sdm845.
> drivers:crypto:qce: Fix SHA result buffer corruption issues.
> dts:qcom:sdm845: Add dt entries to support crypto engine.
> devicetree:bindings:crypto: Extend qcom-qce binding to add support for
> crypto engine version 5.4
>
> .../devicetree/bindings/crypto/qcom-qce.txt | 4 ++-
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 +++++++++++++++++++
> drivers/clk/qcom/clk-rpmh.c | 2 ++
> drivers/crypto/qce/core.c | 17 ++++++++++-
> drivers/crypto/qce/sha.c | 2 +-
> include/dt-bindings/clock/qcom,rpmh.h | 1 +
> 6 files changed, 53 insertions(+), 3 deletions(-)
Patches 3-4 applied. Thanks.
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Thu, Nov 19, 2020 at 10:52:33AM -0500, Thara Gopinath wrote:
> Add compatible string to support v5.4 crypto engine.
>
> Signed-off-by: Thara Gopinath <[email protected]>
> Reviewed-by: Bjorn Andersson <[email protected]>
> ---
> Documentation/devicetree/bindings/crypto/qcom-qce.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> index fdd53b184ba8..ed1ede9c0acc 100644
> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
> @@ -2,7 +2,9 @@ Qualcomm crypto engine driver
>
> Required properties:
>
> -- compatible : should be "qcom,crypto-v5.1"
> +- compatible : should be
> + "qcom,crypto-v5.1" for ipq6018
> + "qcom,crypto-v5.4" for sdm845
An outstanding example of why to use SoC specific compatibles rather
than versions. Keep v5.1, but use SoC compatibles going forward.
> - reg : specifies base physical address and size of the registers map
> - clocks : phandle to clock-controller plus clock-specifier pair
> - clock-names : "iface" clocks register interface
> --
> 2.25.1
>
On 12/7/20 5:09 PM, Rob Herring wrote:
> On Thu, Nov 19, 2020 at 10:52:33AM -0500, Thara Gopinath wrote:
>> Add compatible string to support v5.4 crypto engine.
>>
>> Signed-off-by: Thara Gopinath <[email protected]>
>> Reviewed-by: Bjorn Andersson <[email protected]>
>> ---
>> Documentation/devicetree/bindings/crypto/qcom-qce.txt | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
>> index fdd53b184ba8..ed1ede9c0acc 100644
>> --- a/Documentation/devicetree/bindings/crypto/qcom-qce.txt
>> +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
>> @@ -2,7 +2,9 @@ Qualcomm crypto engine driver
>>
>> Required properties:
>>
>> -- compatible : should be "qcom,crypto-v5.1"
>> +- compatible : should be
>> + "qcom,crypto-v5.1" for ipq6018
>> + "qcom,crypto-v5.4" for sdm845
>
> An outstanding example of why to use SoC specific compatibles rather
> than versions. Keep v5.1, but use SoC compatibles going forward.
Hi Rob,
Thanks for the review. We have different Soc's using the same version of
the ip. Is it okay to have "qcom,sdm845-crypto", "qcom,crypto-v5.4" amd
have only "qcom,crypto-<version>" in the driver ?
>
>> - reg : specifies base physical address and size of the registers map
>> - clocks : phandle to clock-controller plus clock-specifier pair
>> - clock-names : "iface" clocks register interface
>> --
>> 2.25.1
>>
--
Warm Regards
Thara