A great deal of these patches have now been applied through various trees.
We now need to grab the attention of the outstanding DMA clients (MUSB and
Crypto) to progress.
Also, Linus could probably do with a hand from Vinod for the remaining
dmaengine patches.
Thanks in advance.
Documentation/devicetree/bindings/dma/ste-dma40.txt | 4 ++
Documentation/devicetree/bindings/usb/ux500-usb.txt | 50 ++++++++++++++++++
arch/arm/mach-ux500/board-mop500-audio.c | 12 ++---
arch/arm/mach-ux500/board-mop500-sdi.c | 16 +++---
arch/arm/mach-ux500/board-mop500.c | 36 +++++--------
arch/arm/mach-ux500/cpu-db8500.c | 34 ++++--------
arch/arm/mach-ux500/devices-db8500.c | 80 ----------------------------
arch/arm/mach-ux500/usb.c | 37 +++----------
drivers/crypto/ux500/cryp/cryp.h | 7 ++-
drivers/crypto/ux500/cryp/cryp_core.c | 31 ++++++++++-
drivers/crypto/ux500/hash/hash_alg.h | 5 +-
drivers/crypto/ux500/hash/hash_core.c | 24 ++++++++-
drivers/dma/ste_dma40.c | 292 +++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------
drivers/dma/ste_dma40_ll.c | 189 +++++++++++++++++++++++++++++++++--------------------------------
drivers/dma/ste_dma40_ll.h | 3 +-
drivers/usb/musb/ux500.c | 61 ++++++++++++++++++++-
drivers/usb/musb/ux500_dma.c | 59 ++++++++++++---------
include/linux/platform_data/dma-ste-dma40.h | 25 ++-------
include/linux/platform_data/usb-musb-ux500.h | 5 +-
sound/soc/ux500/ux500_pcm.c | 10 ++--
20 files changed, 506 insertions(+), 474 deletions(-)
Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
should be possible to remove them from the auxdata structure. However,
after doing so the drivers fail. Common clk is still reliant on the
dev_name() call to do device name matching, which will fail due to the
fact that Device Tree naming differs somewhat do the more traditional
conventions.
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/cpu-db8500.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 96ddbae..b1c9241 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -230,15 +230,15 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
/* Requires call-back bindings. */
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
/* Requires DMA bindings. */
+ OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
+ /* Requires clock name bindings. */
OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
- OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", NULL),
OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", NULL),
OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", NULL),
OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", NULL),
- /* Requires clock name bindings. */
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
--
1.7.10.4
DMA channel configuration information should be setup in the driver.
The Ux500 Hash driver now does this, so there's no need to send it
though here too.
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/board-mop500.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 52ffe1c..ec916ca 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -446,11 +446,7 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
.dir = STEDMA40_MEM_TO_PERIPH,
.dev_type = DB8500_DMA_DEV50_HAC1_TX,
- .src_info.data_width = STEDMA40_WORD_WIDTH,
- .dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
- .src_info.psize = STEDMA40_PSIZE_LOG_16,
- .dst_info.psize = STEDMA40_PSIZE_LOG_16,
};
static struct hash_platform_data u8500_hash1_platform_data = {
--
1.7.10.4
If we fail to prepare the ux500-cryp clock before enabling it the
platform will fail to boot. Here we insure this happens.
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Andreas Westin <[email protected]>
Cc: [email protected]
Acked-by: Ulf Hansson <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/crypto/ux500/cryp/cryp_core.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 32f4806..ccdf173 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1458,11 +1458,17 @@ static int ux500_cryp_probe(struct platform_device *pdev)
goto out_regulator;
}
+ ret = clk_prepare(device_data->clk);
+ if (ret) {
+ dev_err(dev, "[%s]: clk_prepare() failed!", __func__);
+ goto out_clk;
+ }
+
/* Enable device power (and clock) */
ret = cryp_enable_power(device_data->dev, device_data, false);
if (ret) {
dev_err(dev, "[%s]: cryp_enable_power() failed!", __func__);
- goto out_clk;
+ goto out_clk_unprepare;
}
cryp_error = cryp_check(device_data);
@@ -1523,6 +1529,9 @@ static int ux500_cryp_probe(struct platform_device *pdev)
out_power:
cryp_disable_power(device_data->dev, device_data, false);
+out_clk_unprepare:
+ clk_unprepare(device_data->clk);
+
out_clk:
clk_put(device_data->clk);
@@ -1593,6 +1602,7 @@ static int ux500_cryp_remove(struct platform_device *pdev)
dev_err(&pdev->dev, "[%s]: cryp_disable_power() failed",
__func__);
+ clk_unprepare(device_data->clk);
clk_put(device_data->clk);
regulator_put(device_data->pwr_regulator);
--
1.7.10.4
If we can ever get to a state where we can solely search for DMA channels
by name, this will almost completely alleviate the requirement to pass
copious amounts of information though platform data. Here we take the
first step towards this. The next step will be to enable Device Tree
complete with name<->event_line mapping.
Cc: Felipe Balbi <[email protected]>
Cc: [email protected]
Acked-by: Linus Walleij <[email protected]>
Acked-by: Fabio Baltieri <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/usb/musb/ux500_dma.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 4bd5400..7d80699 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -34,6 +34,11 @@
#include <linux/platform_data/usb-musb-ux500.h>
#include "musb_core.h"
+static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12",
+ "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" };
+static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12",
+ "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" };
+
struct ux500_dma_channel {
struct dma_channel channel;
struct ux500_dma_controller *controller;
@@ -291,6 +296,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
struct musb_hdrc_platform_data *plat = dev->platform_data;
struct ux500_musb_board_data *data;
struct dma_channel *dma_channel = NULL;
+ char **chan_names;
u32 ch_num;
u8 dir;
u8 is_tx = 0;
@@ -312,6 +318,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
/* Prepare the loop for RX channels */
channel_array = controller->rx_channel;
param_array = data ? data->dma_rx_param_array : NULL;
+ chan_names = (char **)iep_chan_names;
for (dir = 0; dir < 2; dir++) {
for (ch_num = 0;
@@ -327,9 +334,15 @@ static int ux500_dma_controller_start(struct dma_controller *c)
dma_channel->status = MUSB_DMA_STATUS_FREE;
dma_channel->max_len = SZ_16M;
- ux500_channel->dma_chan = dma_request_channel(mask,
- data->dma_filter,
- param_array[ch_num]);
+ ux500_channel->dma_chan =
+ dma_request_slave_channel(dev, chan_names[ch_num]);
+
+ if (!ux500_channel->dma_chan)
+ ux500_channel->dma_chan =
+ dma_request_channel(mask,
+ data->dma_filter,
+ param_array[ch_num]);
+
if (!ux500_channel->dma_chan) {
ERR("Dma pipe allocation error dir=%d ch=%d\n",
dir, ch_num);
@@ -345,6 +358,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
/* Prepare the loop for TX channels */
channel_array = controller->tx_channel;
param_array = data ? data->dma_tx_param_array : NULL;
+ chan_names = (char **)oep_chan_names;
is_tx = 1;
}
--
1.7.10.4
DMA addresses are now passed as part of the dmaengine API by invoking
dmaengine_slave_config(). So there's no requirement for the DMA40
driver to look them up in a table provided by platform data. This
method does not fit in well using Device Tree either.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/devices-db8500.c | 80 ---------------------------
include/linux/platform_data/dma-ste-dma40.h | 2 -
2 files changed, 82 deletions(-)
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index bed25a3..e21ffd8 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,87 +42,7 @@ static struct resource dma40_resources[] = {
}
};
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
- /* MUSB - these will be runtime-reconfigured */
- [DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
- [DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
- [DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
- [DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
- [DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
- [DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
- [DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
- [DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
- /* PrimeCells - run-time configured */
- [DB8500_DMA_DEV0_SPI0] = -1,
- [DB8500_DMA_DEV1_SD_MMC0] = -1,
- [DB8500_DMA_DEV2_SD_MMC1] = -1,
- [DB8500_DMA_DEV3_SD_MMC2] = -1,
- [DB8500_DMA_DEV8_SSP0] = -1,
- [DB8500_DMA_DEV9_SSP1] = -1,
- [DB8500_DMA_DEV11_UART2] = -1,
- [DB8500_DMA_DEV12_UART1] = -1,
- [DB8500_DMA_DEV13_UART0] = -1,
- [DB8500_DMA_DEV28_SD_MM2] = -1,
- [DB8500_DMA_DEV29_SD_MM0] = -1,
- [DB8500_DMA_DEV32_SD_MM1] = -1,
- [DB8500_DMA_DEV33_SPI2] = -1,
- [DB8500_DMA_DEV35_SPI1] = -1,
- [DB8500_DMA_DEV40_SPI3] = -1,
- [DB8500_DMA_DEV41_SD_MM3] = -1,
- [DB8500_DMA_DEV42_SD_MM4] = -1,
- [DB8500_DMA_DEV43_SD_MM5] = -1,
- [DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
- [DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
- [DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
- [DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
- [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
- /* MUSB - these will be runtime-reconfigured */
- [DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1,
- [DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1,
- [DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1,
- [DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1,
- [DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1,
- [DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1,
- [DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1,
- [DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1,
- /* PrimeCells */
- [DB8500_DMA_DEV0_SPI0] = -1,
- [DB8500_DMA_DEV1_SD_MMC0] = -1,
- [DB8500_DMA_DEV2_SD_MMC1] = -1,
- [DB8500_DMA_DEV3_SD_MMC2] = -1,
- [DB8500_DMA_DEV8_SSP0] = -1,
- [DB8500_DMA_DEV9_SSP1] = -1,
- [DB8500_DMA_DEV11_UART2] = -1,
- [DB8500_DMA_DEV12_UART1] = -1,
- [DB8500_DMA_DEV13_UART0] = -1,
- [DB8500_DMA_DEV28_SD_MM2] = -1,
- [DB8500_DMA_DEV29_SD_MM0] = -1,
- [DB8500_DMA_DEV32_SD_MM1] = -1,
- [DB8500_DMA_DEV33_SPI2] = -1,
- [DB8500_DMA_DEV35_SPI1] = -1,
- [DB8500_DMA_DEV40_SPI3] = -1,
- [DB8500_DMA_DEV41_SD_MM3] = -1,
- [DB8500_DMA_DEV42_SD_MM4] = -1,
- [DB8500_DMA_DEV43_SD_MM5] = -1,
- [DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
- [DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
- [DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
- [DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-
struct stedma40_platform_data dma40_plat_data = {
- .dev_rx = dma40_rx_map,
- .dev_tx = dma40_tx_map,
.disabled_channels = {-1},
};
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index c54af61..af0064e 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -152,8 +152,6 @@ struct stedma40_chan_cfg {
* for 'multiple of 4' channels, like 8.
*/
struct stedma40_platform_data {
- const dma_addr_t *dev_tx;
- const dma_addr_t *dev_rx;
int disabled_channels[STEDMA40_MAX_PHYS];
int *soft_lli_chans;
int num_of_soft_lli_chans;
--
1.7.10.4
The aim is to make the code that little more readable.
Acked-by: Vinod Koul <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 6ed7757..08bc58a 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -54,8 +54,8 @@
#define MAX_LCLA_ALLOC_ATTEMPTS 256
/* Bit markings for allocation map */
-#define D40_ALLOC_FREE (1 << 31)
-#define D40_ALLOC_PHY (1 << 30)
+#define D40_ALLOC_FREE BIT(31)
+#define D40_ALLOC_PHY BIT(30)
#define D40_ALLOC_LOG_FREE 0
/* Reserved event lines for memcpy only. */
@@ -1738,7 +1738,7 @@ static irqreturn_t d40_handle_interrupt(int irq, void *data)
}
/* ACK interrupt */
- writel(1 << idx, base->virtbase + il[row].clr);
+ writel(BIT(idx), base->virtbase + il[row].clr);
spin_lock(&d40c->lock);
@@ -1828,8 +1828,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy,
if (phy->allocated_src == D40_ALLOC_FREE)
phy->allocated_src = D40_ALLOC_LOG_FREE;
- if (!(phy->allocated_src & (1 << log_event_line))) {
- phy->allocated_src |= 1 << log_event_line;
+ if (!(phy->allocated_src & BIT(log_event_line))) {
+ phy->allocated_src |= BIT(log_event_line);
goto found;
} else
goto not_found;
@@ -1840,8 +1840,8 @@ static bool d40_alloc_mask_set(struct d40_phy_res *phy,
if (phy->allocated_dst == D40_ALLOC_FREE)
phy->allocated_dst = D40_ALLOC_LOG_FREE;
- if (!(phy->allocated_dst & (1 << log_event_line))) {
- phy->allocated_dst |= 1 << log_event_line;
+ if (!(phy->allocated_dst & BIT(log_event_line))) {
+ phy->allocated_dst |= BIT(log_event_line);
goto found;
} else
goto not_found;
@@ -1871,11 +1871,11 @@ static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
/* Logical channel */
if (is_src) {
- phy->allocated_src &= ~(1 << log_event_line);
+ phy->allocated_src &= ~BIT(log_event_line);
if (phy->allocated_src == D40_ALLOC_LOG_FREE)
phy->allocated_src = D40_ALLOC_FREE;
} else {
- phy->allocated_dst &= ~(1 << log_event_line);
+ phy->allocated_dst &= ~BIT(log_event_line);
if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
phy->allocated_dst = D40_ALLOC_FREE;
}
@@ -2356,7 +2356,7 @@ static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
u32 rtreg;
u32 event = D40_TYPE_TO_EVENT(dev_type);
u32 group = D40_TYPE_TO_GROUP(dev_type);
- u32 bit = 1 << event;
+ u32 bit = BIT(event);
u32 prioreg;
struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
--
1.7.10.4
The dma_mask will always be the same as the coherent_dma_mask, so let's
cut down on the platform_data burden and set it as such in the driver.
This also saves us from supporting it separately when we come to enable
this driver for Device Tree.
Cc: Felipe Balbi <[email protected]>
Cc: [email protected]
Acked-by: Linus Walleij <[email protected]>
Acked-by: Fabio Baltieri <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/usb.c | 3 ---
drivers/usb/musb/ux500.c | 2 +-
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 49d6e57..2f9abe9 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -74,8 +74,6 @@ static struct ux500_musb_board_data musb_board_data = {
.dma_filter = stedma40_filter,
};
-static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
-
static struct musb_hdrc_platform_data musb_platform_data = {
.mode = MUSB_OTG,
.board_data = &musb_board_data,
@@ -98,7 +96,6 @@ struct platform_device ux500_musb_device = {
.id = 0,
.dev = {
.platform_data = &musb_platform_data,
- .dma_mask = &ux500_musb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(usb_resources),
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 371776f..3cf10bc 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -228,7 +228,7 @@ static int ux500_probe(struct platform_device *pdev)
}
musb->dev.parent = &pdev->dev;
- musb->dev.dma_mask = pdev->dev.dma_mask;
+ musb->dev.dma_mask = &pdev->dev.coherent_dma_mask;
musb->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;
glue->dev = &pdev->dev;
--
1.7.10.4
We're now using the transfer direction definitions provided by the DMA
sub-system, so the home-brew ones have become obsolete.
Signed-off-by: Lee Jones <[email protected]>
---
include/linux/platform_data/dma-ste-dma40.h | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 288dc24..54ddca6 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -77,14 +77,6 @@ enum stedma40_periph_data_width {
STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
};
-enum stedma40_xfer_dir {
- STEDMA40_MEM_TO_MEM = 1,
- STEDMA40_MEM_TO_PERIPH,
- STEDMA40_PERIPH_TO_MEM,
- STEDMA40_PERIPH_TO_PERIPH
-};
-
-
/**
* struct stedma40_half_channel_info - dst/src channel configuration
*
@@ -120,7 +112,7 @@ struct stedma40_half_channel_info {
*
*/
struct stedma40_chan_cfg {
- enum stedma40_xfer_dir dir;
+ enum dma_transfer_direction dir;
bool high_priority;
bool realtime;
enum stedma40_mode mode;
--
1.7.10.4
Some platforms have channels which are not available for normal use.
This information is currently passed though platform data in internal
BSP kernels. Once those platforms land, they'll need to configure them
appropriately, so we may as well add the infrastructure.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
Documentation/devicetree/bindings/dma/ste-dma40.txt | 2 ++
drivers/dma/ste_dma40.c | 17 ++++++++++++++++-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index aa272d8..bea5b73 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -11,6 +11,7 @@ Required properties:
Optional properties:
- dma-channels: Number of channels supported by hardware - if not present
the driver will attempt to obtain the information from H/W
+- disabled-channels: Channels which can not be used
Example:
@@ -23,6 +24,7 @@ Example:
#dma-cells = <2>;
memcpy-channels = <56 57 58 59 60>;
+ disabled-channels = <12>;
dma-channels = <8>;
};
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 4e528dd..ffac822 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -3482,7 +3482,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
struct device_node *np)
{
struct stedma40_platform_data *pdata;
- int num_phy = 0, num_memcpy = 0;
+ int num_phy = 0, num_memcpy = 0, num_disabled = 0;
const const __be32 *list;
pdata = devm_kzalloc(&pdev->dev,
@@ -3511,6 +3511,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
dma40_memcpy_channels,
num_memcpy);
+ list = of_get_property(np, "disabled-channels", &num_disabled);
+ num_disabled /= sizeof(*list);
+
+ if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
+ d40_err(&pdev->dev,
+ "Invalid number of disabled channels specified (%d)\n",
+ num_disabled);
+ return -EINVAL;
+ }
+
+ of_property_read_u32_array(np, "disabled-channels",
+ pdata->disabled_channels,
+ num_disabled);
+ pdata->disabled_channels[num_disabled] = -1;
+
pdev->dev.platform_data = pdata;
return 0;
--
1.7.10.4
The aim is to make the code that little more readable.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40_ll.c | 44 ++++++++++++++++++++++----------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 121c0ce..5ddd724 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -20,28 +20,28 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
/* src is mem? -> increase address pos */
if (cfg->dir == DMA_MEM_TO_DEV ||
cfg->dir == DMA_MEM_TO_MEM)
- l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
+ l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
/* dst is mem? -> increase address pos */
if (cfg->dir == DMA_DEV_TO_MEM ||
cfg->dir == DMA_MEM_TO_MEM)
- l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
+ l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
/* src is hw? -> master port 1 */
if (cfg->dir == DMA_DEV_TO_MEM ||
cfg->dir == DMA_DEV_TO_DEV)
- l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
+ l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
/* dst is hw? -> master port 1 */
if (cfg->dir == DMA_MEM_TO_DEV ||
cfg->dir == DMA_DEV_TO_DEV)
- l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
+ l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
- l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
+ l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
- l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
+ l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
@@ -58,39 +58,39 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
if ((cfg->dir == DMA_DEV_TO_MEM) ||
(cfg->dir == DMA_DEV_TO_DEV)) {
/* Set master port to 1 */
- src |= 1 << D40_SREG_CFG_MST_POS;
+ src |= BIT(D40_SREG_CFG_MST_POS);
src |= D40_TYPE_TO_EVENT(cfg->dev_type);
if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
- src |= 1 << D40_SREG_CFG_PHY_TM_POS;
+ src |= BIT(D40_SREG_CFG_PHY_TM_POS);
else
src |= 3 << D40_SREG_CFG_PHY_TM_POS;
}
if ((cfg->dir == DMA_MEM_TO_DEV) ||
(cfg->dir == DMA_DEV_TO_DEV)) {
/* Set master port to 1 */
- dst |= 1 << D40_SREG_CFG_MST_POS;
+ dst |= BIT(D40_SREG_CFG_MST_POS);
dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
- dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
+ dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
else
dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
}
/* Interrupt on end of transfer for destination */
- dst |= 1 << D40_SREG_CFG_TIM_POS;
+ dst |= BIT(D40_SREG_CFG_TIM_POS);
/* Generate interrupt on error */
- src |= 1 << D40_SREG_CFG_EIM_POS;
- dst |= 1 << D40_SREG_CFG_EIM_POS;
+ src |= BIT(D40_SREG_CFG_EIM_POS);
+ dst |= BIT(D40_SREG_CFG_EIM_POS);
/* PSIZE */
if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
- src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+ src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
}
if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
- dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
+ dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
}
@@ -100,14 +100,14 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
/* Set the priority bit to high for the physical channel */
if (cfg->high_priority) {
- src |= 1 << D40_SREG_CFG_PRI_POS;
- dst |= 1 << D40_SREG_CFG_PRI_POS;
+ src |= BIT(D40_SREG_CFG_PRI_POS);
+ dst |= BIT(D40_SREG_CFG_PRI_POS);
}
if (cfg->src_info.big_endian)
- src |= 1 << D40_SREG_CFG_LBE_POS;
+ src |= BIT(D40_SREG_CFG_LBE_POS);
if (cfg->dst_info.big_endian)
- dst |= 1 << D40_SREG_CFG_LBE_POS;
+ dst |= BIT(D40_SREG_CFG_LBE_POS);
*src_cfg = src;
*dst_cfg = dst;
@@ -157,15 +157,15 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
/* If this scatter list entry is the last one, no next link */
if (next_lli == 0)
- lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
+ lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
else
lli->reg_lnk = next_lli;
/* Set/clear interrupt generation on this link item.*/
if (term_int)
- lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
+ lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
else
- lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
+ lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
/* Post link */
lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
--
1.7.10.4
At this moment in time the memcpy channels which can be used by the D40
are fixed, as each supported platform in Mainline uses the same ones.
However, platforms do exist which don't follow this convention, so
these will need to be tailored. Fortunately, these platforms will be DT
only, so this change has very little impact on platform data.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
.../devicetree/bindings/dma/ste-dma40.txt | 2 +
drivers/dma/ste_dma40.c | 40 ++++++++++++++++----
include/linux/platform_data/dma-ste-dma40.h | 2 +
3 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index 2679a87..aa272d8 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -6,6 +6,7 @@ Required properties:
- reg-names: Names of the above areas to use during resource look-up
- interrupt: Should contain the DMAC interrupt number
- #dma-cells: must be <3>
+- memcpy-channels: Channels to be used for memcpy
Optional properties:
- dma-channels: Number of channels supported by hardware - if not present
@@ -21,6 +22,7 @@ Example:
interrupts = <0 25 0x4>;
#dma-cells = <2>;
+ memcpy-channels = <56 57 58 59 60>;
dma-channels = <8>;
};
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 76c255f..ae462d3 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -58,6 +58,8 @@
#define D40_ALLOC_PHY BIT(30)
#define D40_ALLOC_LOG_FREE 0
+#define D40_MEMCPY_MAX_CHANS 8
+
/* Reserved event lines for memcpy only. */
#define DB8500_DMA_MEMCPY_EV_0 51
#define DB8500_DMA_MEMCPY_EV_1 56
@@ -522,6 +524,8 @@ struct d40_gen_dmac {
* @phy_start: Physical memory start of the DMA registers.
* @phy_size: Size of the DMA register map.
* @irq: The IRQ number.
+ * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
+ * transfers).
* @num_phy_chans: The number of physical channels. Read from HW. This
* is the number of available channels for this driver, not counting "Secure
* mode" allocated physical channels.
@@ -565,6 +569,7 @@ struct d40_base {
phys_addr_t phy_start;
resource_size_t phy_size;
int irq;
+ int num_memcpy_chans;
int num_phy_chans;
int num_log_chans;
struct device_dma_parameters dma_parms;
@@ -2938,7 +2943,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
}
d40_chan_init(base, &base->dma_memcpy, base->log_chans,
- base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
+ base->num_log_chans, base->num_memcpy_chans);
dma_cap_zero(base->dma_memcpy.cap_mask);
dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
@@ -3139,6 +3144,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
struct d40_base *base = NULL;
int num_log_chans = 0;
int num_phy_chans;
+ int num_memcpy_chans;
int clk_ret = -EINVAL;
int i;
u32 pid;
@@ -3209,6 +3215,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
else
num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
+ /* The number of channels used for memcpy */
+ if (plat_data->num_of_memcpy_chans)
+ num_memcpy_chans = plat_data->num_of_memcpy_chans;
+ else
+ num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
+
num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
dev_info(&pdev->dev,
@@ -3216,7 +3228,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
rev, res->start, num_phy_chans, num_log_chans);
base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
- (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
+ (num_phy_chans + num_log_chans + num_memcpy_chans) *
sizeof(struct d40_chan), GFP_KERNEL);
if (base == NULL) {
@@ -3226,6 +3238,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
base->rev = rev;
base->clk = clk;
+ base->num_memcpy_chans = num_memcpy_chans;
base->num_phy_chans = num_phy_chans;
base->num_log_chans = num_log_chans;
base->phy_start = res->start;
@@ -3469,12 +3482,8 @@ static int __init d40_of_probe(struct platform_device *pdev,
struct device_node *np)
{
struct stedma40_platform_data *pdata;
-
- /*
- * FIXME: Fill in this routine as more support is added.
- * First platform enabled (u8500) doens't need any extra
- * properties to run, so this is fairly sparce currently.
- */
+ int num_memcpy = 0;
+ const const __be32 *list;
pdata = devm_kzalloc(&pdev->dev,
sizeof(struct stedma40_platform_data),
@@ -3482,6 +3491,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
if (!pdata)
return -ENOMEM;
+ list = of_get_property(np, "memcpy-channels", &num_memcpy);
+ num_memcpy /= sizeof(*list);
+
+ if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
+ d40_err(&pdev->dev,
+ "Invalid number of memcpy channels specified (%d)\n",
+ num_memcpy);
+ return -EINVAL;
+ }
+ pdata->num_of_memcpy_chans = num_memcpy;
+
+ of_property_read_u32_array(np, "memcpy-channels",
+ dma40_memcpy_channels,
+ num_memcpy);
+
pdev->dev.platform_data = pdata;
return 0;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index ceba6dc..1bb9b18 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -132,6 +132,7 @@ struct stedma40_chan_cfg {
* @num_of_soft_lli_chans: The number of channels that needs to be configured
* to use SoftLLI.
* @use_esram_lcla: flag for mapping the lcla into esram region
+ * @num_of_memcpy_chans: The number of channels reserved for memcpy.
* @num_of_phy_chans: The number of physical channels implemented in HW.
* 0 means reading the number of channels from DMA HW but this is only valid
* for 'multiple of 4' channels, like 8.
@@ -141,6 +142,7 @@ struct stedma40_platform_data {
int *soft_lli_chans;
int num_of_soft_lli_chans;
bool use_esram_lcla;
+ int num_of_memcpy_chans;
int num_of_phy_chans;
};
--
1.7.10.4
The DMA platform data is now empty due to some recent refactoring,
so there is no longer a requirement to pass it though.
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/cpu-db8500.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index b407601..3b77e36 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -259,8 +259,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
"ux500-msp-i2s.3", &msp3_platform_data),
/* Requires clock name bindings and channel address lookup table. */
- OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
- "dma40.0", &dma40_plat_data),
+ OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
{},
};
--
1.7.10.4
During the initial setup of a logical channel, it is necessary to unmask
the GIM in order to receive generated terminal count and error interrupts.
We're separating out this required code so it will be possible to move
the remaining code in d40_phy_cfg(), which is mostly runtime configuration
into the runtime_config() routine.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40.c | 4 ++++
drivers/dma/ste_dma40_ll.c | 5 -----
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 5e9f6d6..759293e 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2513,6 +2513,10 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
d40c->lcpa = d40c->base->lcpa_base +
d40c->dma_cfg.dev_type *
D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
+
+ /* Unmask the Global Interrupt Mask. */
+ d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
+ d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
}
dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 5eb6c10..435a223 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -107,11 +107,6 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
src |= 1 << D40_SREG_CFG_PRI_POS;
dst |= 1 << D40_SREG_CFG_PRI_POS;
}
-
- } else {
- /* Logical channel */
- dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
- src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
}
if (cfg->src_info.big_endian)
--
1.7.10.4
Unsure of the author's intentions, rather than just removing the nop,
we're replacing it with a comment containing the possible intention
of the statement OR:ing with 0.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40_ll.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index a035dfe..27b818d 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -182,8 +182,10 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
else
lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
- /* Post link */
- lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
+ /*
+ * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
+ * Relink happens after transfer completion.
+ */
return 0;
}
--
1.7.10.4
When a DMA client requests and configures a DMA channel, it requests
data_width in Bytes. The DMA40 driver then swiftly converts it over to
the necessary register bit value. Unfortunately, for any subsequent
calculations we have to shift '1' by the bit pattern (1 << data_width)
times to make any sense of it.
This patch flips the semantics on its head and only converts the value
to its respective register bit pattern when writing to registers. This
way we can use the true data_width (in Bytes) value.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40.c | 63 +++++++++++----------------
drivers/dma/ste_dma40_ll.c | 43 ++++++++++++------
include/linux/platform_data/dma-ste-dma40.h | 9 +---
sound/soc/ux500/ux500_pcm.c | 10 ++---
4 files changed, 60 insertions(+), 65 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 483da16..76c255f 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -80,11 +80,11 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
.mode = STEDMA40_MODE_PHYSICAL,
.dir = DMA_MEM_TO_MEM,
- .src_info.data_width = STEDMA40_BYTE_WIDTH,
+ .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.src_info.psize = STEDMA40_PSIZE_PHY_1,
.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
- .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+ .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.dst_info.psize = STEDMA40_PSIZE_PHY_1,
.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
};
@@ -94,11 +94,11 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
.mode = STEDMA40_MODE_LOGICAL,
.dir = DMA_MEM_TO_MEM,
- .src_info.data_width = STEDMA40_BYTE_WIDTH,
+ .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.src_info.psize = STEDMA40_PSIZE_LOG_1,
.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
- .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+ .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
.dst_info.psize = STEDMA40_PSIZE_LOG_1,
.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
};
@@ -1005,20 +1005,21 @@ static int d40_psize_2_burst_size(bool is_log, int psize)
/*
* The dma only supports transmitting packages up to
- * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
- * dma elements required to send the entire sg list
+ * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
+ *
+ * Calculate the total number of dma elements required to send the entire sg list.
*/
static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
{
int dmalen;
u32 max_w = max(data_width1, data_width2);
u32 min_w = min(data_width1, data_width2);
- u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
+ u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
if (seg_max > STEDMA40_MAX_SEG_SIZE)
- seg_max -= (1 << max_w);
+ seg_max -= max_w;
- if (!IS_ALIGNED(size, 1 << max_w))
+ if (!IS_ALIGNED(size, max_w))
return -EINVAL;
if (size <= seg_max)
@@ -1464,7 +1465,7 @@ static u32 d40_residue(struct d40_chan *d40c)
>> D40_SREG_ELEM_PHY_ECNT_POS;
}
- return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
+ return num_elt * d40c->dma_cfg.dst_info.data_width;
}
static bool d40_tx_is_linked(struct d40_chan *d40c)
@@ -1784,9 +1785,9 @@ static int d40_validate_conf(struct d40_chan *d40c,
}
if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
- (1 << conf->src_info.data_width) !=
+ conf->src_info.data_width !=
d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
- (1 << conf->dst_info.data_width)) {
+ conf->dst_info.data_width) {
/*
* The DMAC hardware only supports
* src (burst x width) == dst (burst x width)
@@ -2673,33 +2674,10 @@ static void d40_terminate_all(struct dma_chan *chan)
static int
dma40_config_to_halfchannel(struct d40_chan *d40c,
struct stedma40_half_channel_info *info,
- enum dma_slave_buswidth width,
u32 maxburst)
{
- enum stedma40_periph_data_width addr_width;
int psize;
- switch (width) {
- case DMA_SLAVE_BUSWIDTH_1_BYTE:
- addr_width = STEDMA40_BYTE_WIDTH;
- break;
- case DMA_SLAVE_BUSWIDTH_2_BYTES:
- addr_width = STEDMA40_HALFWORD_WIDTH;
- break;
- case DMA_SLAVE_BUSWIDTH_4_BYTES:
- addr_width = STEDMA40_WORD_WIDTH;
- break;
- case DMA_SLAVE_BUSWIDTH_8_BYTES:
- addr_width = STEDMA40_DOUBLEWORD_WIDTH;
- break;
- default:
- dev_err(d40c->base->dev,
- "illegal peripheral address width "
- "requested (%d)\n",
- width);
- return -EINVAL;
- }
-
if (chan_is_logical(d40c)) {
if (maxburst >= 16)
psize = STEDMA40_PSIZE_LOG_16;
@@ -2720,7 +2698,6 @@ dma40_config_to_halfchannel(struct d40_chan *d40c,
psize = STEDMA40_PSIZE_PHY_1;
}
- info->data_width = addr_width;
info->psize = psize;
info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
@@ -2804,14 +2781,24 @@ static int d40_set_runtime_config(struct dma_chan *chan,
src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
}
+ /* Only valid widths are; 1, 2, 4 and 8. */
+ if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
+ src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
+ dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
+ dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
+ ((src_addr_width > 1) && (src_addr_width & 1)) ||
+ ((dst_addr_width > 1) && (dst_addr_width & 1)))
+ return -EINVAL;
+
+ cfg->src_info.data_width = src_addr_width;
+ cfg->dst_info.data_width = dst_addr_width;
+
ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
- src_addr_width,
src_maxburst);
if (ret)
return ret;
ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
- dst_addr_width,
dst_maxburst);
if (ret)
return ret;
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index 5ddd724..a035dfe 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -10,6 +10,18 @@
#include "ste_dma40_ll.h"
+u8 d40_width_to_bits(enum dma_slave_buswidth width)
+{
+ if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
+ return STEDMA40_ESIZE_8_BIT;
+ else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
+ return STEDMA40_ESIZE_16_BIT;
+ else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
+ return STEDMA40_ESIZE_64_BIT;
+ else
+ return STEDMA40_ESIZE_32_BIT;
+}
+
/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
u32 *lcsp1, u32 *lcsp3)
@@ -39,11 +51,13 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
- l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
+ l3 |= d40_width_to_bits(cfg->dst_info.data_width)
+ << D40_MEM_LCSP3_DCFG_ESIZE_POS;
l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
- l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
+ l1 |= d40_width_to_bits(cfg->src_info.data_width)
+ << D40_MEM_LCSP1_SCFG_ESIZE_POS;
*lcsp1 = l1;
*lcsp3 = l3;
@@ -95,8 +109,10 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
}
/* Element size */
- src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
- dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
+ src |= d40_width_to_bits(cfg->src_info.data_width)
+ << D40_SREG_CFG_ESIZE_POS;
+ dst |= d40_width_to_bits(cfg->dst_info.data_width)
+ << D40_SREG_CFG_ESIZE_POS;
/* Set the priority bit to high for the physical channel */
if (cfg->high_priority) {
@@ -133,23 +149,22 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
num_elems = 2 << psize;
/* Must be aligned */
- if (!IS_ALIGNED(data, 0x1 << data_width))
+ if (!IS_ALIGNED(data, data_width))
return -EINVAL;
/* Transfer size can't be smaller than (num_elms * elem_size) */
- if (data_size < num_elems * (0x1 << data_width))
+ if (data_size < num_elems * data_width)
return -EINVAL;
/* The number of elements. IE now many chunks */
- lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
+ lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
/*
* Distance to next element sized entry.
* Usually the size of the element unless you want gaps.
*/
if (addr_inc)
- lli->reg_elt |= (0x1 << data_width) <<
- D40_SREG_ELEM_PHY_EIDX_POS;
+ lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;
/* Where the data is */
lli->reg_ptr = data;
@@ -177,16 +192,16 @@ static int d40_seg_size(int size, int data_width1, int data_width2)
{
u32 max_w = max(data_width1, data_width2);
u32 min_w = min(data_width1, data_width2);
- u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
+ u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
if (seg_max > STEDMA40_MAX_SEG_SIZE)
- seg_max -= (1 << max_w);
+ seg_max -= max_w;
if (size <= seg_max)
return size;
if (size <= 2 * seg_max)
- return ALIGN(size / 2, 1 << max_w);
+ return ALIGN(size / 2, max_w);
return seg_max;
}
@@ -352,10 +367,10 @@ static void d40_log_fill_lli(struct d40_log_lli *lli,
lli->lcsp13 = reg_cfg;
/* The number of elements to transfer */
- lli->lcsp02 = ((data_size >> data_width) <<
+ lli->lcsp02 = ((data_size / data_width) <<
D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
- BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
+ BUG_ON((data_size / data_width) > STEDMA40_MAX_SEG_SIZE);
/* 16 LSBs address of the current element */
lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index 54ddca6..ceba6dc 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -70,13 +70,6 @@ enum stedma40_flow_ctrl {
STEDMA40_FLOW_CTRL,
};
-enum stedma40_periph_data_width {
- STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
- STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
- STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
- STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
-};
-
/**
* struct stedma40_half_channel_info - dst/src channel configuration
*
@@ -87,7 +80,7 @@ enum stedma40_periph_data_width {
*/
struct stedma40_half_channel_info {
bool big_endian;
- enum stedma40_periph_data_width data_width;
+ enum dma_slave_buswidth data_width;
int psize;
enum stedma40_flow_ctrl flow_ctrl;
};
diff --git a/sound/soc/ux500/ux500_pcm.c b/sound/soc/ux500/ux500_pcm.c
index b6e5ae2..31f9bbc 100644
--- a/sound/soc/ux500/ux500_pcm.c
+++ b/sound/soc/ux500/ux500_pcm.c
@@ -76,20 +76,20 @@ static struct dma_chan *ux500_pcm_request_chan(struct snd_soc_pcm_runtime *rtd,
dma_params = snd_soc_dai_get_dma_data(dai, substream);
dma_cfg = dma_params->dma_cfg;
- mem_data_width = STEDMA40_HALFWORD_WIDTH;
+ mem_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
switch (dma_params->data_size) {
case 32:
- per_data_width = STEDMA40_WORD_WIDTH;
+ per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
break;
case 16:
- per_data_width = STEDMA40_HALFWORD_WIDTH;
+ per_data_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
break;
case 8:
- per_data_width = STEDMA40_BYTE_WIDTH;
+ per_data_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
break;
default:
- per_data_width = STEDMA40_WORD_WIDTH;
+ per_data_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
}
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
--
1.7.10.4
STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
duplicating such things.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40.c | 56 ++++++++++++++++++++++----------------------
drivers/dma/ste_dma40_ll.c | 24 +++++++++----------
2 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 08bc58a..483da16 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -78,7 +78,7 @@ static int dma40_memcpy_channels[] = {
/* Default configuration for physcial memcpy */
struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
.mode = STEDMA40_MODE_PHYSICAL,
- .dir = STEDMA40_MEM_TO_MEM,
+ .dir = DMA_MEM_TO_MEM,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.src_info.psize = STEDMA40_PSIZE_PHY_1,
@@ -92,7 +92,7 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
/* Default configuration for logical memcpy */
struct stedma40_chan_cfg dma40_memcpy_conf_log = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_MEM,
+ .dir = DMA_MEM_TO_MEM,
.src_info.data_width = STEDMA40_BYTE_WIDTH,
.src_info.psize = STEDMA40_PSIZE_LOG_1,
@@ -843,7 +843,7 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
* that uses linked lists.
*/
if (!(chan->phy_chan->use_soft_lli &&
- chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM))
+ chan->dma_cfg.dir == DMA_DEV_TO_MEM))
curr_lcla = d40_lcla_alloc_one(chan, desc);
first_lcla = curr_lcla;
@@ -1311,12 +1311,12 @@ static void d40_config_set_event(struct d40_chan *d40c,
u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
/* Enable event line connected to device (or memcpy) */
- if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
- (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+ if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
+ (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
__d40_config_set_event(d40c, event_type, event,
D40_CHAN_REG_SSLNK);
- if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM)
+ if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
__d40_config_set_event(d40c, event_type, event,
D40_CHAN_REG_SDLNK);
}
@@ -1774,7 +1774,7 @@ static int d40_validate_conf(struct d40_chan *d40c,
res = -EINVAL;
}
- if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
+ if (conf->dir == DMA_DEV_TO_DEV) {
/*
* DMAC HW supports it. Will be added to this driver,
* in case any dma client requires it.
@@ -1905,11 +1905,11 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
phys = d40c->base->phy_res;
num_phy_chans = d40c->base->num_phy_chans;
- if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
+ if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
log_num = 2 * dev_type;
is_src = true;
- } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
- d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+ } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+ d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
/* dst event lines are used for logical memcpy */
log_num = 2 * dev_type + 1;
is_src = false;
@@ -1920,7 +1920,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
event_line = D40_TYPE_TO_EVENT(dev_type);
if (!is_log) {
- if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+ if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
/* Find physical half channel */
if (d40c->dma_cfg.use_fixed_channel) {
i = d40c->dma_cfg.phy_channel;
@@ -2068,10 +2068,10 @@ static int d40_free_dma(struct d40_chan *d40c)
return -EINVAL;
}
- if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
- d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
+ if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+ d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
is_src = false;
- else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
+ else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
is_src = true;
else {
chan_err(d40c, "Unknown direction\n");
@@ -2133,10 +2133,10 @@ static bool d40_is_paused(struct d40_chan *d40c)
goto _exit;
}
- if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
- d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
+ if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
+ d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
status = readl(chanbase + D40_CHAN_REG_SDLNK);
- } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
+ } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
status = readl(chanbase + D40_CHAN_REG_SSLNK);
} else {
chan_err(d40c, "Unknown direction\n");
@@ -2387,12 +2387,12 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
if (d40c->base->rev < 3)
return;
- if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
- (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+ if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
+ (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
- if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
- (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
+ if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
+ (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
}
@@ -2423,11 +2423,11 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
switch (D40_DT_FLAGS_DIR(flags)) {
case 0:
- cfg.dir = STEDMA40_MEM_TO_PERIPH;
+ cfg.dir = DMA_MEM_TO_DEV;
cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
break;
case 1:
- cfg.dir = STEDMA40_PERIPH_TO_MEM;
+ cfg.dir = DMA_DEV_TO_MEM;
cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
break;
}
@@ -2473,7 +2473,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
d40_set_prio_realtime(d40c);
if (chan_is_logical(d40c)) {
- if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
+ if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
d40c->lcpa = d40c->base->lcpa_base +
d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
else
@@ -2746,12 +2746,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
if (config->direction == DMA_DEV_TO_MEM) {
config_addr = config->src_addr;
- if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
+ if (cfg->dir != DMA_DEV_TO_MEM)
dev_dbg(d40c->base->dev,
"channel was not configured for peripheral "
"to memory transfer (%d) overriding\n",
cfg->dir);
- cfg->dir = STEDMA40_PERIPH_TO_MEM;
+ cfg->dir = DMA_DEV_TO_MEM;
/* Configure the memory side */
if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
@@ -2762,12 +2762,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
} else if (config->direction == DMA_MEM_TO_DEV) {
config_addr = config->dst_addr;
- if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
+ if (cfg->dir != DMA_MEM_TO_DEV)
dev_dbg(d40c->base->dev,
"channel was not configured for memory "
"to peripheral transfer (%d) overriding\n",
cfg->dir);
- cfg->dir = STEDMA40_MEM_TO_PERIPH;
+ cfg->dir = DMA_MEM_TO_DEV;
/* Configure the memory side */
if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
index ab5a2a7..121c0ce 100644
--- a/drivers/dma/ste_dma40_ll.c
+++ b/drivers/dma/ste_dma40_ll.c
@@ -18,23 +18,23 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
u32 l1 = 0; /* src */
/* src is mem? -> increase address pos */
- if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
- cfg->dir == STEDMA40_MEM_TO_MEM)
+ if (cfg->dir == DMA_MEM_TO_DEV ||
+ cfg->dir == DMA_MEM_TO_MEM)
l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
/* dst is mem? -> increase address pos */
- if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
- cfg->dir == STEDMA40_MEM_TO_MEM)
+ if (cfg->dir == DMA_DEV_TO_MEM ||
+ cfg->dir == DMA_MEM_TO_MEM)
l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
/* src is hw? -> master port 1 */
- if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
- cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
+ if (cfg->dir == DMA_DEV_TO_MEM ||
+ cfg->dir == DMA_DEV_TO_DEV)
l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
/* dst is hw? -> master port 1 */
- if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
- cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
+ if (cfg->dir == DMA_MEM_TO_DEV ||
+ cfg->dir == DMA_DEV_TO_DEV)
l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
@@ -55,8 +55,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
u32 src = 0;
u32 dst = 0;
- if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
- (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+ if ((cfg->dir == DMA_DEV_TO_MEM) ||
+ (cfg->dir == DMA_DEV_TO_DEV)) {
/* Set master port to 1 */
src |= 1 << D40_SREG_CFG_MST_POS;
src |= D40_TYPE_TO_EVENT(cfg->dev_type);
@@ -66,8 +66,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
else
src |= 3 << D40_SREG_CFG_PHY_TM_POS;
}
- if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
- (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
+ if ((cfg->dir == DMA_MEM_TO_DEV) ||
+ (cfg->dir == DMA_DEV_TO_DEV)) {
/* Set master port to 1 */
dst |= 1 << D40_SREG_CFG_MST_POS;
dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
--
1.7.10.4
STEDMA40_*_TO_* direction definitions are identical in all but name to
the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
duplicating such things.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/board-mop500-audio.c | 12 ++++++------
arch/arm/mach-ux500/board-mop500-sdi.c | 16 ++++++++--------
arch/arm/mach-ux500/board-mop500.c | 22 +++++++++++-----------
arch/arm/mach-ux500/usb.c | 4 ++--
4 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index ec87262..bfe443d 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -21,13 +21,13 @@
static struct stedma40_chan_cfg msp0_dma_rx = {
.high_priority = true,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
};
static struct stedma40_chan_cfg msp0_dma_tx = {
.high_priority = true,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
};
@@ -39,13 +39,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
static struct stedma40_chan_cfg msp1_dma_rx = {
.high_priority = true,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV30_MSP3,
};
static struct stedma40_chan_cfg msp1_dma_tx = {
.high_priority = true,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV30_MSP1,
};
@@ -57,13 +57,13 @@ struct msp_i2s_platform_data msp1_platform_data = {
static struct stedma40_chan_cfg msp2_dma_rx = {
.high_priority = true,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV14_MSP2,
};
static struct stedma40_chan_cfg msp2_dma_tx = {
.high_priority = true,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV14_MSP2,
.use_fixed_channel = true,
.phy_channel = 1,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 29be714..e6891d1 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -34,13 +34,13 @@
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV29_SD_MM0,
};
static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV29_SD_MM0,
};
#endif
@@ -81,13 +81,13 @@ void mop500_sdi_tc35892_init(struct device *parent)
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV32_SD_MM1,
};
static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV32_SD_MM1,
};
#endif
@@ -112,13 +112,13 @@ struct mmci_platform_data mop500_sdi1_data = {
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV28_SD_MM2,
};
static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV28_SD_MM2,
};
#endif
@@ -144,13 +144,13 @@ struct mmci_platform_data mop500_sdi2_data = {
#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV42_SD_MM4,
};
static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV42_SD_MM4,
};
#endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ba26ae3..0b018c4 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -424,19 +424,19 @@ void mop500_snowball_ethernet_clock_enable(void)
static struct cryp_platform_data u8500_cryp1_platform_data = {
.mem_to_engine = {
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV48_CAC1,
.mode = STEDMA40_MODE_LOGICAL,
},
.engine_to_mem = {
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV48_CAC1,
.mode = STEDMA40_MODE_LOGICAL,
}
};
static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV50_HAC1_TX,
.mode = STEDMA40_MODE_LOGICAL,
};
@@ -455,13 +455,13 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV8_SSP0,
};
static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV8_SSP0,
};
#endif
@@ -490,37 +490,37 @@ static void __init mop500_spi_init(struct device *parent)
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV13_UART0,
};
static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV13_UART0,
};
static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV12_UART1,
};
static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV12_UART1,
};
static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_PERIPH_TO_MEM,
+ .dir = DMA_DEV_TO_MEM,
.dev_type = DB8500_DMA_DEV11_UART2,
};
static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
.mode = STEDMA40_MODE_LOGICAL,
- .dir = STEDMA40_MEM_TO_PERIPH,
+ .dir = DMA_MEM_TO_DEV,
.dev_type = DB8500_DMA_DEV11_UART2,
};
#endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 2f9abe9..b7bd8d3 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -14,12 +14,12 @@
#define MUSB_DMA40_RX_CH { \
.mode = STEDMA40_MODE_LOGICAL, \
- .dir = STEDMA40_PERIPH_TO_MEM, \
+ .dir = DMA_DEV_TO_MEM, \
}
#define MUSB_DMA40_TX_CH { \
.mode = STEDMA40_MODE_LOGICAL, \
- .dir = STEDMA40_MEM_TO_PERIPH, \
+ .dir = DMA_MEM_TO_DEV, \
}
static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
--
1.7.10.4
The recently DT:ed MUSB driver will require clock-name by device-name
look-up capability, until common clk has is properly supported by the
ux500 platform.
Acked-by: Linus Walleij <[email protected]>
Acked-by: Fabio Baltieri <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/cpu-db8500.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index b1c9241..e20bc10 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -253,6 +253,7 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+ OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
&db8500_prcmu_pdata),
OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
--
1.7.10.4
In its current state, the ux500-musb driver uses platform data pointers
blindly with no prior checking. If no platform data pointer is passed
this will Oops the kernel. In this patch we ensure platform data and
board data are present prior to using them.
Cc: Felipe Balbi <[email protected]>
Cc: [email protected]
Acked-by: Fabio Baltieri <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/usb/musb/ux500_dma.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 382291b..4bd5400 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -289,7 +289,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
struct musb *musb = controller->private_data;
struct device *dev = musb->controller;
struct musb_hdrc_platform_data *plat = dev->platform_data;
- struct ux500_musb_board_data *data = plat->board_data;
+ struct ux500_musb_board_data *data;
struct dma_channel *dma_channel = NULL;
u32 ch_num;
u8 dir;
@@ -299,14 +299,19 @@ static int ux500_dma_controller_start(struct dma_controller *c)
struct ux500_dma_channel *channel_array;
dma_cap_mask_t mask;
+ if (!plat) {
+ dev_err(musb->controller, "No platform data\n");
+ return -EINVAL;
+ }
+ data = plat->board_data;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
/* Prepare the loop for RX channels */
channel_array = controller->rx_channel;
- param_array = data->dma_rx_param_array;
+ param_array = data ? data->dma_rx_param_array : NULL;
for (dir = 0; dir < 2; dir++) {
for (ch_num = 0;
@@ -339,7 +344,7 @@ static int ux500_dma_controller_start(struct dma_controller *c)
/* Prepare the loop for TX channels */
channel_array = controller->tx_channel;
- param_array = data->dma_tx_param_array;
+ param_array = data ? data->dma_tx_param_array : NULL;
is_tx = 1;
}
--
1.7.10.4
Using the dmaengine API, allocating and configuring a channel are two
separate actions. Here we're removing logical channel configuration from
the channel allocating routines.
Cc: Vinod Koul <[email protected]>
Cc: Dan Williams <[email protected]>
Cc: Per Forlin <[email protected]>
Cc: Rabin Vincent <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b7fe46b..ba84df8 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2040,6 +2040,9 @@ static int d40_config_memcpy(struct d40_chan *d40c)
d40c->dma_cfg = dma40_memcpy_conf_log;
d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
+ d40_log_cfg(&d40c->dma_cfg,
+ &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
+
} else if (dma_has_cap(DMA_MEMCPY, cap) &&
dma_has_cap(DMA_SLAVE, cap)) {
d40c->dma_cfg = dma40_memcpy_conf_phy;
@@ -2508,9 +2511,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
d40_set_prio_realtime(d40c);
if (chan_is_logical(d40c)) {
- d40_log_cfg(&d40c->dma_cfg,
- &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
-
if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
d40c->lcpa = d40c->base->lcpa_base +
d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
--
1.7.10.4
The MUSB HDRC configuration never changes between each of the ux500
supported platforms, so there's little point passing it though platform
data. If we set it in the driver instead, we can make good use of it
when booting with either ATAGs or Device Tree.
Cc: Felipe Balbi <[email protected]>
Cc: [email protected]
Acked-by: Linus Walleij <[email protected]>
Acked-by: Fabio Baltieri <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/usb.c | 8 --------
drivers/usb/musb/ux500.c | 8 ++++++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index a21c2e1..49d6e57 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -76,16 +76,8 @@ static struct ux500_musb_board_data musb_board_data = {
static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
-static struct musb_hdrc_config musb_hdrc_config = {
- .multipoint = true,
- .dyn_fifo = true,
- .num_eps = 16,
- .ram_bits = 16,
-};
-
static struct musb_hdrc_platform_data musb_platform_data = {
.mode = MUSB_OTG,
- .config = &musb_hdrc_config,
.board_data = &musb_board_data,
};
diff --git a/drivers/usb/musb/ux500.c b/drivers/usb/musb/ux500.c
index 2c80004..371776f 100644
--- a/drivers/usb/musb/ux500.c
+++ b/drivers/usb/musb/ux500.c
@@ -30,6 +30,13 @@
#include "musb_core.h"
+static struct musb_hdrc_config ux500_musb_hdrc_config = {
+ .multipoint = true,
+ .dyn_fifo = true,
+ .num_eps = 16,
+ .ram_bits = 16,
+};
+
struct ux500_glue {
struct device *dev;
struct platform_device *musb;
@@ -229,6 +236,7 @@ static int ux500_probe(struct platform_device *pdev)
glue->clk = clk;
pdata->platform_ops = &ux500_ops;
+ pdata->config = &ux500_musb_hdrc_config;
platform_set_drvdata(pdev, glue);
--
1.7.10.4
For all ux500 based platforms the maximum number of end-points are used.
Move this knowledge into the driver so we can relinquish the burden from
platform data. This also removes quite a bit of complexity from the driver
and will aid us when we come to enable the driver for Device Tree.
Cc: Felipe Balbi <[email protected]>
Cc: [email protected]
Acked-by: Linus Walleij <[email protected]>
Acked-by: Fabio Baltieri <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/usb.c | 14 ++++++------
drivers/usb/musb/ux500_dma.c | 30 ++++++++------------------
include/linux/platform_data/usb-musb-ux500.h | 5 +----
3 files changed, 16 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 72754e3..a21c2e1 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -22,7 +22,7 @@
.dir = STEDMA40_MEM_TO_PERIPH, \
}
-static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
= {
MUSB_DMA40_RX_CH,
MUSB_DMA40_RX_CH,
@@ -34,7 +34,7 @@ static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
MUSB_DMA40_RX_CH
};
-static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
= {
MUSB_DMA40_TX_CH,
MUSB_DMA40_TX_CH,
@@ -46,7 +46,7 @@ static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
MUSB_DMA40_TX_CH,
};
-static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
+static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
&musb_dma_rx_ch[0],
&musb_dma_rx_ch[1],
&musb_dma_rx_ch[2],
@@ -57,7 +57,7 @@ static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
&musb_dma_rx_ch[7]
};
-static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
+static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
&musb_dma_tx_ch[0],
&musb_dma_tx_ch[1],
&musb_dma_tx_ch[2],
@@ -71,8 +71,6 @@ static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
static struct ux500_musb_board_data musb_board_data = {
.dma_rx_param_array = ux500_dma_rx_param_array,
.dma_tx_param_array = ux500_dma_tx_param_array,
- .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
- .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
.dma_filter = stedma40_filter,
};
@@ -119,7 +117,7 @@ static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
{
u32 idx;
- for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
+ for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
musb_dma_rx_ch[idx].dev_type = dev_type[idx];
}
@@ -127,7 +125,7 @@ static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
{
u32 idx;
- for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
+ for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
musb_dma_tx_ch[idx].dev_type = dev_type[idx];
}
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
index 3381206..382291b 100644
--- a/drivers/usb/musb/ux500_dma.c
+++ b/drivers/usb/musb/ux500_dma.c
@@ -48,10 +48,8 @@ struct ux500_dma_channel {
struct ux500_dma_controller {
struct dma_controller controller;
- struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
- struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
- u32 num_rx_channels;
- u32 num_tx_channels;
+ struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
+ struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS];
void *private_data;
dma_addr_t phy_base;
};
@@ -144,19 +142,15 @@ static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
struct ux500_dma_channel *ux500_channel = NULL;
struct musb *musb = controller->private_data;
u8 ch_num = hw_ep->epnum - 1;
- u32 max_ch;
- /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
+ /* 8 DMA channels (0 - 7). Each DMA channel can only be allocated
* to specified hw_ep. For example DMA channel 0 can only be allocated
* to hw_ep 1 and 9.
*/
if (ch_num > 7)
ch_num -= 8;
- max_ch = is_tx ? controller->num_tx_channels :
- controller->num_rx_channels;
-
- if (ch_num >= max_ch)
+ if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS)
return NULL;
ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
@@ -264,7 +258,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c)
struct dma_channel *channel;
u8 ch_num;
- for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
+ for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
channel = &controller->rx_channel[ch_num].channel;
ux500_channel = channel->private_data;
@@ -274,7 +268,7 @@ static int ux500_dma_controller_stop(struct dma_controller *c)
dma_release_channel(ux500_channel->dma_chan);
}
- for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
+ for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) {
channel = &controller->tx_channel[ch_num].channel;
ux500_channel = channel->private_data;
@@ -303,26 +297,21 @@ static int ux500_dma_controller_start(struct dma_controller *c)
void **param_array;
struct ux500_dma_channel *channel_array;
- u32 ch_count;
dma_cap_mask_t mask;
- if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
- (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
- return -EINVAL;
- controller->num_rx_channels = data->num_rx_channels;
- controller->num_tx_channels = data->num_tx_channels;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
/* Prepare the loop for RX channels */
channel_array = controller->rx_channel;
- ch_count = data->num_rx_channels;
param_array = data->dma_rx_param_array;
for (dir = 0; dir < 2; dir++) {
- for (ch_num = 0; ch_num < ch_count; ch_num++) {
+ for (ch_num = 0;
+ ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS;
+ ch_num++) {
ux500_channel = &channel_array[ch_num];
ux500_channel->controller = controller;
ux500_channel->ch_num = ch_num;
@@ -350,7 +339,6 @@ static int ux500_dma_controller_start(struct dma_controller *c)
/* Prepare the loop for TX channels */
channel_array = controller->tx_channel;
- ch_count = data->num_tx_channels;
param_array = data->dma_tx_param_array;
is_tx = 1;
}
diff --git a/include/linux/platform_data/usb-musb-ux500.h b/include/linux/platform_data/usb-musb-ux500.h
index 4c1cc50..dd9c83a 100644
--- a/include/linux/platform_data/usb-musb-ux500.h
+++ b/include/linux/platform_data/usb-musb-ux500.h
@@ -9,14 +9,11 @@
#include <linux/dmaengine.h>
-#define UX500_MUSB_DMA_NUM_RX_CHANNELS 8
-#define UX500_MUSB_DMA_NUM_TX_CHANNELS 8
+#define UX500_MUSB_DMA_NUM_RX_TX_CHANNELS 8
struct ux500_musb_board_data {
void **dma_rx_param_array;
void **dma_tx_param_array;
- u32 num_rx_channels;
- u32 num_tx_channels;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
};
--
1.7.10.4
It was required to pass DMA channel configuration information to the
MMC driver before the new DMA API was in place. Now that it is, and
is fully compatible with Device Tree we can stop doing that.
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/cpu-db8500.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 9b26fe2..96ddbae 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -234,10 +234,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
- OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data),
- OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data),
- OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data),
- OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data),
+ OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", NULL),
+ OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", NULL),
+ OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", NULL),
+ OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", NULL),
/* Requires clock name bindings. */
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
--
1.7.10.4
These drivers are now operational and even use the latest common clk
and DMA APIs. There's no reason why we shouldn't start them up now.
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/board-mop500.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 38e321c..ba26ae3 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -637,6 +637,8 @@ static void __init snowball_init_machine(void)
mop500_snowball_ethernet_clock_enable();
+ u8500_cryp1_hash1_init(parent);
+
/* This board has full regulator constraints */
regulator_has_full_constraints();
}
--
1.7.10.4
The Cryp driver is currently silent and the Hash driver prints the
name of its probe function unnecessarily. Let's just put a nice
descriptive one-liner there instead.
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Andreas Westin <[email protected]>
Cc: [email protected]
Acked-by: Arnd Bergmann <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/crypto/ux500/cryp/cryp_core.c | 2 ++
drivers/crypto/ux500/hash/hash_core.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index d9c863d..4f8b11a 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1541,6 +1541,8 @@ static int ux500_cryp_probe(struct platform_device *pdev)
goto out_power;
}
+ dev_info(dev, "successfully registered\n");
+
return 0;
out_power:
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 6269576..9ca6fbb 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1772,7 +1772,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
goto out_power;
}
- dev_info(dev, "[%s] successfully probed\n", __func__);
+ dev_info(dev, "successfully registered\n");
return 0;
out_power:
--
1.7.10.4
DMA channel configuration information should be setup in the driver.
The Ux500 Cryp driver now does this, so there's no need to send it
though here too.
Reviewed-by: Linus Walleij <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/board-mop500.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index ec916ca..38e321c 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -426,20 +426,12 @@ static struct cryp_platform_data u8500_cryp1_platform_data = {
.mem_to_engine = {
.dir = STEDMA40_MEM_TO_PERIPH,
.dev_type = DB8500_DMA_DEV48_CAC1,
- .src_info.data_width = STEDMA40_WORD_WIDTH,
- .dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
- .src_info.psize = STEDMA40_PSIZE_LOG_4,
- .dst_info.psize = STEDMA40_PSIZE_LOG_4,
},
.engine_to_mem = {
.dir = STEDMA40_PERIPH_TO_MEM,
.dev_type = DB8500_DMA_DEV48_CAC1,
- .src_info.data_width = STEDMA40_WORD_WIDTH,
- .dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
- .src_info.psize = STEDMA40_PSIZE_LOG_4,
- .dst_info.psize = STEDMA40_PSIZE_LOG_4,
}
};
--
1.7.10.4
The DMA controller currently takes configuration information from
information passed though dma_channel_request(), but it shouldn't.
Using the API, the DMA channel should only be configured during
a dma_slave_config() call.
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Andreas Westin <[email protected]>
Cc: [email protected]
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/crypto/ux500/cryp/cryp.h | 7 ++++++-
drivers/crypto/ux500/cryp/cryp_core.c | 17 +++++++++++++++++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ux500/cryp/cryp.h b/drivers/crypto/ux500/cryp/cryp.h
index 14cfd05..d1d6606 100644
--- a/drivers/crypto/ux500/cryp/cryp.h
+++ b/drivers/crypto/ux500/cryp/cryp.h
@@ -114,6 +114,9 @@ enum cryp_status_id {
};
/* Cryp DMA interface */
+#define CRYP_DMA_TX_FIFO 0x08
+#define CRYP_DMA_RX_FIFO 0x10
+
enum cryp_dma_req_type {
CRYP_DMA_DISABLE_BOTH,
CRYP_DMA_ENABLE_IN_DATA,
@@ -217,7 +220,8 @@ struct cryp_dma {
/**
* struct cryp_device_data - structure for a cryp device.
- * @base: Pointer to the hardware base address.
+ * @base: Pointer to virtual base address of the cryp device.
+ * @phybase: Pointer to physical memory location of the cryp device.
* @dev: Pointer to the devices dev structure.
* @clk: Pointer to the device's clock control.
* @pwr_regulator: Pointer to the device's power control.
@@ -232,6 +236,7 @@ struct cryp_dma {
*/
struct cryp_device_data {
struct cryp_register __iomem *base;
+ phys_addr_t phybase;
struct device *dev;
struct clk *clk;
struct regulator *pwr_regulator;
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index ccdf173..d9c863d 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -475,6 +475,19 @@ static int cryp_get_device_data(struct cryp_ctx *ctx,
static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
struct device *dev)
{
+ struct dma_slave_config mem2cryp = {
+ .direction = DMA_MEM_TO_DEV,
+ .dst_addr = device_data->phybase + CRYP_DMA_TX_FIFO,
+ .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+ .dst_maxburst = 4,
+ };
+ struct dma_slave_config cryp2mem = {
+ .direction = DMA_DEV_TO_MEM,
+ .src_addr = device_data->phybase + CRYP_DMA_RX_FIFO,
+ .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
+ .src_maxburst = 4,
+ };
+
dma_cap_zero(device_data->dma.mask);
dma_cap_set(DMA_SLAVE, device_data->dma.mask);
@@ -490,6 +503,9 @@ static void cryp_dma_setup_channel(struct cryp_device_data *device_data,
stedma40_filter,
device_data->dma.cfg_cryp2mem);
+ dmaengine_slave_config(device_data->dma.chan_mem2cryp, &mem2cryp);
+ dmaengine_slave_config(device_data->dma.chan_cryp2mem, &cryp2mem);
+
init_completion(&device_data->dma.cryp_dma_complete);
}
@@ -1431,6 +1447,7 @@ static int ux500_cryp_probe(struct platform_device *pdev)
goto out_kfree;
}
+ device_data->phybase = res->start;
device_data->base = ioremap(res->start, resource_size(res));
if (!device_data->base) {
dev_err(dev, "[%s]: ioremap failed!", __func__);
--
1.7.10.4
If we fail to prepare the ux500-hash clock before enabling it the
platform will fail to boot. Here we insure this happens.
Cc: Herbert Xu <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Andreas Westin <[email protected]>
Cc: [email protected]
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Ulf Hansson <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
---
drivers/crypto/ux500/hash/hash_core.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index cf55089..4b02428 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1726,11 +1726,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
goto out_regulator;
}
+ ret = clk_prepare(device_data->clk);
+ if (ret) {
+ dev_err(dev, "[%s] clk_prepare() failed!", __func__);
+ goto out_clk;
+ }
+
/* Enable device power (and clock) */
ret = hash_enable_power(device_data, false);
if (ret) {
dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
- goto out_clk;
+ goto out_clk_unprepare;
}
ret = hash_check_hw(device_data);
@@ -1762,6 +1768,9 @@ static int ux500_hash_probe(struct platform_device *pdev)
out_power:
hash_disable_power(device_data, false);
+out_clk_unprepare:
+ clk_unprepare(device_data->clk);
+
out_clk:
clk_put(device_data->clk);
@@ -1826,6 +1835,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
dev_err(dev, "[%s]: hash_disable_power() failed",
__func__);
+ clk_unprepare(device_data->clk);
clk_put(device_data->clk);
regulator_put(device_data->regulator);
--
1.7.10.4
'struct stedma40_half_channel_info's header comment says that it's
called 'struct stedma40_chan_cfg'. Let's straighten that out.
Signed-off-by: Lee Jones <[email protected]>
---
include/linux/platform_data/dma-ste-dma40.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
index af0064e..288dc24 100644
--- a/include/linux/platform_data/dma-ste-dma40.h
+++ b/include/linux/platform_data/dma-ste-dma40.h
@@ -86,7 +86,7 @@ enum stedma40_xfer_dir {
/**
- * struct stedma40_chan_cfg - dst/src channel configuration
+ * struct stedma40_half_channel_info - dst/src channel configuration
*
* @big_endian: true if the src/dst should be read as big endian
* @data_width: Data width of the src/dst hardware
--
1.7.10.4
DMA data width and packet size information is only required at channel
configuration time. Any information passed from platform data is passed
directly to the DMA40 driver to use during channel allocation, but these
pieces of information are subsequently ignored by the driver, so we may
as well remove them.
Signed-off-by: Lee Jones <[email protected]>
---
arch/arm/mach-ux500/usb.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 45af303..72754e3 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -15,19 +15,11 @@
#define MUSB_DMA40_RX_CH { \
.mode = STEDMA40_MODE_LOGICAL, \
.dir = STEDMA40_PERIPH_TO_MEM, \
- .src_info.data_width = STEDMA40_WORD_WIDTH, \
- .dst_info.data_width = STEDMA40_WORD_WIDTH, \
- .src_info.psize = STEDMA40_PSIZE_LOG_16, \
- .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
}
#define MUSB_DMA40_TX_CH { \
.mode = STEDMA40_MODE_LOGICAL, \
.dir = STEDMA40_MEM_TO_PERIPH, \
- .src_info.data_width = STEDMA40_WORD_WIDTH, \
- .dst_info.data_width = STEDMA40_WORD_WIDTH, \
- .src_info.psize = STEDMA40_PSIZE_LOG_16, \
- .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
}
static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
--
1.7.10.4
Addresses are now stored in local data structures and are easy to
obtain, thus a specialist function used to fetch them is now surplus
to requirement.
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40.c | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 57a127e..6ed7757 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2267,24 +2267,6 @@ err:
return NULL;
}
-static dma_addr_t
-d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
-{
- struct stedma40_platform_data *plat = chan->base->plat_data;
- struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
- dma_addr_t addr = 0;
-
- if (chan->runtime_addr)
- return chan->runtime_addr;
-
- if (direction == DMA_DEV_TO_MEM)
- addr = plat->dev_rx[cfg->dev_type];
- else if (direction == DMA_MEM_TO_DEV)
- addr = plat->dev_tx[cfg->dev_type];
-
- return addr;
-}
-
static struct dma_async_tx_descriptor *
d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
struct scatterlist *sg_dst, unsigned int sg_len,
--
1.7.10.4
Addresses are passed in from the client's driver via the invocation of
dmaengine_slave_config(), so there's no need to fetch them from platform
data too, hardwired or otherwise. This is a great step forward, as it
elevates a large burden from platform data in the way of a look-up
table.
Signed-off-by: Lee Jones <[email protected]>
---
drivers/dma/ste_dma40.c | 51 ++++++++++-------------------------------------
1 file changed, 11 insertions(+), 40 deletions(-)
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index ba84df8..57a127e 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1774,22 +1774,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
res = -EINVAL;
}
- if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
- d40c->base->plat_data->dev_tx[conf->dev_type] == 0 &&
- d40c->runtime_addr == 0) {
- chan_err(d40c, "Invalid TX channel address (%d)\n",
- conf->dev_type);
- res = -EINVAL;
- }
-
- if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
- d40c->base->plat_data->dev_rx[conf->dev_type] == 0 &&
- d40c->runtime_addr == 0) {
- chan_err(d40c, "Invalid RX channel address (%d)\n",
- conf->dev_type);
- res = -EINVAL;
- }
-
if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
/*
* DMAC HW supports it. Will be added to this driver,
@@ -2327,14 +2311,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
if (sg_next(&sg_src[sg_len - 1]) == sg_src)
desc->cyclic = true;
- if (direction != DMA_TRANS_NONE) {
- dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
-
- if (direction == DMA_DEV_TO_MEM)
- src_dev_addr = dev_addr;
- else if (direction == DMA_MEM_TO_DEV)
- dst_dev_addr = dev_addr;
- }
+ if (direction == DMA_DEV_TO_MEM)
+ src_dev_addr = chan->runtime_addr;
+ else if (direction == DMA_MEM_TO_DEV)
+ dst_dev_addr = chan->runtime_addr;
if (chan_is_logical(chan))
ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
@@ -2782,15 +2762,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
dst_maxburst = config->dst_maxburst;
if (config->direction == DMA_DEV_TO_MEM) {
- dma_addr_t dev_addr_rx =
- d40c->base->plat_data->dev_rx[cfg->dev_type];
-
config_addr = config->src_addr;
- if (dev_addr_rx)
- dev_dbg(d40c->base->dev,
- "channel has a pre-wired RX address %08x "
- "overriding with %08x\n",
- dev_addr_rx, config_addr);
+
if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
dev_dbg(d40c->base->dev,
"channel was not configured for peripheral "
@@ -2805,15 +2778,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
dst_maxburst = src_maxburst;
} else if (config->direction == DMA_MEM_TO_DEV) {
- dma_addr_t dev_addr_tx =
- d40c->base->plat_data->dev_tx[cfg->dev_type];
-
config_addr = config->dst_addr;
- if (dev_addr_tx)
- dev_dbg(d40c->base->dev,
- "channel has a pre-wired TX address %08x "
- "overriding with %08x\n",
- dev_addr_tx, config_addr);
+
if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
dev_dbg(d40c->base->dev,
"channel was not configured for memory "
@@ -2833,6 +2799,11 @@ static int d40_set_runtime_config(struct dma_chan *chan,
return -EINVAL;
}
+ if (config_addr <= 0) {
+ dev_err(d40c->base->dev, "no address supplied\n");
+ return -EINVAL;
+ }
+
if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
dev_err(d40c->base->dev,
"src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
--
1.7.10.4
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> During the initial setup of a logical channel, it is necessary to unmask
> the GIM in order to receive generated terminal count and error interrupts.
> We're separating out this required code so it will be possible to move
> the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> into the runtime_config() routine.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Tentatively applied to my ux500-dma40 branch.
This lacks an ACK from Vinod...
I cannot get any of this stack of patches up to ARM SoC
before I have Vinod's ACK on all hitting drivers/dma/*
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> Using the dmaengine API, allocating and configuring a channel are two
> separate actions. Here we're removing logical channel configuration from
> the channel allocating routines.
This commit message is also incorrect, but I amended it.
Besides, when I amend commit messages I make sure I really
understand what is going on so no big deal...
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
I still need Vinod's ACK on this before I send it anywhere.
Patch applied!
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> It was required to pass DMA channel configuration information to the
> MMC driver before the new DMA API was in place. Now that it is, and
> is fully compatible with Device Tree we can stop doing that.
>
> Reviewed-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
So since the use of dma_request_slave_channel() is not upstream,
I guess this will break DMA use (i.e slow down transfers!) on all
device tree boots?
I'd be happy to apply it once the MMCI patch is in linux-next
indicating there may just be a window in the merge period
where it falls back to IRQ mode, but I don't want to disable
DMA on DT boots for an entire kernel cycle just like that.
Not applied as of yet.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> Addresses are passed in from the client's driver via the invocation of
> dmaengine_slave_config(), so there's no need to fetch them from platform
> data too, hardwired or otherwise. This is a great step forward, as it
> elevates a large burden from platform data in the way of a look-up
> table.
>
> Signed-off-by: Lee Jones <[email protected]>
This should be the case even without patch 5 & 6 so patch tentatively
applied.
Waiting for Vinod's ACK on this though.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> Addresses are now stored in local data structures and are easy to
> obtain, thus a specialist function used to fetch them is now surplus
> to requirement.
>
> Signed-off-by: Lee Jones <[email protected]>
Patch tentatively applied, waiting for Vinod's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
> should be possible to remove them from the auxdata structure. However,
> after doing so the drivers fail. Common clk is still reliant on the
> dev_name() call to do device name matching, which will fail due to the
> fact that Device Tree naming differs somewhat do the more traditional
> conventions.
>
> Reviewed-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Cannot be applied due to dependency on 5/39.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> DMA addresses are now passed as part of the dmaengine API by invoking
> dmaengine_slave_config(). So there's no requirement for the DMA40
> driver to look them up in a table provided by platform data. This
> method does not fit in well using Device Tree either.
>
> Signed-off-by: Lee Jones <[email protected]>
Good riddance. Patch tentatively applied.
Awaiting Vinod's ACK for include/platform_data/*.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> 'struct stedma40_half_channel_info's header comment says that it's
> called 'struct stedma40_chan_cfg'. Let's straighten that out.
>
> Signed-off-by: Lee Jones <[email protected]>
Patch tentatively applied waiting for Vinod's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> If we fail to prepare the ux500-hash clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Arnd Bergmann <[email protected]>
> Acked-by: Ulf Hansson <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
This patch seems to be totally independent of the other stuff
in the patch series, and it even seems like an -rc fix to me
(I don't think the crypto device works without this).
This should go into the crypto tree?
Else please convince Herbert to give his ACK on this
before I apply it.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> DMA data width and packet size information is only required at channel
> configuration time. Any information passed from platform data is passed
> directly to the DMA40 driver to use during channel allocation, but these
> pieces of information are subsequently ignored by the driver, so we may
> as well remove them.
>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Ulf Hansson <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
This patch also looks like -rc series stuff for the crypto tree.
BTW: these two clk_prepare_enable() patches are
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
I guess this stuff is dependent on the stuff Fabio has recently sent to
Felipe for the ux500 musb DMA so these musb patches should
primarily go through his tree.
It seems like the later changes to the platform code
(arch/arm/mach-ux500) may be sufficiently orthogonal
so it can be done out-of-order?
I can't merge any of this without Felipes ACKs in any
case.
Yours,
Linus Walleij
Hello Linus,
On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>
> > For all ux500 based platforms the maximum number of end-points are used.
> > Move this knowledge into the driver so we can relinquish the burden from
> > platform data. This also removes quite a bit of complexity from the driver
> > and will aid us when we come to enable the driver for Device Tree.
> >
> > Cc: Felipe Balbi <[email protected]>
> > Cc: [email protected]
> > Acked-by: Linus Walleij <[email protected]>
> > Acked-by: Fabio Baltieri <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
>
> I guess this stuff is dependent on the stuff Fabio has recently sent to
> Felipe for the ux500 musb DMA so these musb patches should
> primarily go through his tree.
Not really, I only sent some coding style fix for the dma driver, as
almost all of my work was in the usb phy files. I also checked my
latest series against Lee's tree and the two seems to merge without any
conflict, so as far as I'm concerned it's really up to you and Felipe.
Fabio
> It seems like the later changes to the platform code
> (arch/arm/mach-ux500) may be sufficiently orthogonal
> so it can be done out-of-order?
>
> I can't merge any of this without Felipes ACKs in any
> case.
>
> Yours,
> Linus Walleij
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
--
Fabio Baltieri
On Wed, May 15, 2013 at 10:51:59AM +0100, Lee Jones wrote:
> At this moment in time the memcpy channels which can be used by the D40
> are fixed, as each supported platform in Mainline uses the same ones.
> However, platforms do exist which don't follow this convention, so
> these will need to be tailored. Fortunately, these platforms will be DT
> only, so this change has very little impact on platform data.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Acked-by: Vinod Koul <[email protected]>
> ---
> .../devicetree/bindings/dma/ste-dma40.txt | 2 +
> drivers/dma/ste_dma40.c | 40 ++++++++++++++++----
> include/linux/platform_data/dma-ste-dma40.h | 2 +
> 3 files changed, 36 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> index 2679a87..aa272d8 100644
> --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
> +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> @@ -6,6 +6,7 @@ Required properties:
> - reg-names: Names of the above areas to use during resource look-up
> - interrupt: Should contain the DMAC interrupt number
> - #dma-cells: must be <3>
> +- memcpy-channels: Channels to be used for memcpy
>
> Optional properties:
> - dma-channels: Number of channels supported by hardware - if not present
> @@ -21,6 +22,7 @@ Example:
> interrupts = <0 25 0x4>;
>
> #dma-cells = <2>;
> + memcpy-channels = <56 57 58 59 60>;
> dma-channels = <8>;
> };
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 76c255f..ae462d3 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -58,6 +58,8 @@
> #define D40_ALLOC_PHY BIT(30)
> #define D40_ALLOC_LOG_FREE 0
>
> +#define D40_MEMCPY_MAX_CHANS 8
> +
> /* Reserved event lines for memcpy only. */
> #define DB8500_DMA_MEMCPY_EV_0 51
> #define DB8500_DMA_MEMCPY_EV_1 56
> @@ -522,6 +524,8 @@ struct d40_gen_dmac {
> * @phy_start: Physical memory start of the DMA registers.
> * @phy_size: Size of the DMA register map.
> * @irq: The IRQ number.
> + * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
> + * transfers).
> * @num_phy_chans: The number of physical channels. Read from HW. This
> * is the number of available channels for this driver, not counting "Secure
> * mode" allocated physical channels.
> @@ -565,6 +569,7 @@ struct d40_base {
> phys_addr_t phy_start;
> resource_size_t phy_size;
> int irq;
> + int num_memcpy_chans;
> int num_phy_chans;
> int num_log_chans;
> struct device_dma_parameters dma_parms;
> @@ -2938,7 +2943,7 @@ static int __init d40_dmaengine_init(struct d40_base *base,
> }
>
> d40_chan_init(base, &base->dma_memcpy, base->log_chans,
> - base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
> + base->num_log_chans, base->num_memcpy_chans);
>
> dma_cap_zero(base->dma_memcpy.cap_mask);
> dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
> @@ -3139,6 +3144,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
> struct d40_base *base = NULL;
> int num_log_chans = 0;
> int num_phy_chans;
> + int num_memcpy_chans;
> int clk_ret = -EINVAL;
> int i;
> u32 pid;
> @@ -3209,6 +3215,12 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
> else
> num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
>
> + /* The number of channels used for memcpy */
> + if (plat_data->num_of_memcpy_chans)
> + num_memcpy_chans = plat_data->num_of_memcpy_chans;
> + else
> + num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
> +
> num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
>
> dev_info(&pdev->dev,
> @@ -3216,7 +3228,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
> rev, res->start, num_phy_chans, num_log_chans);
>
> base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
> - (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
> + (num_phy_chans + num_log_chans + num_memcpy_chans) *
> sizeof(struct d40_chan), GFP_KERNEL);
>
> if (base == NULL) {
> @@ -3226,6 +3238,7 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
>
> base->rev = rev;
> base->clk = clk;
> + base->num_memcpy_chans = num_memcpy_chans;
> base->num_phy_chans = num_phy_chans;
> base->num_log_chans = num_log_chans;
> base->phy_start = res->start;
> @@ -3469,12 +3482,8 @@ static int __init d40_of_probe(struct platform_device *pdev,
> struct device_node *np)
> {
> struct stedma40_platform_data *pdata;
> -
> - /*
> - * FIXME: Fill in this routine as more support is added.
> - * First platform enabled (u8500) doens't need any extra
> - * properties to run, so this is fairly sparce currently.
> - */
> + int num_memcpy = 0;
> + const const __be32 *list;
>
> pdata = devm_kzalloc(&pdev->dev,
> sizeof(struct stedma40_platform_data),
> @@ -3482,6 +3491,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
> if (!pdata)
> return -ENOMEM;
>
> + list = of_get_property(np, "memcpy-channels", &num_memcpy);
> + num_memcpy /= sizeof(*list);
> +
> + if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
> + d40_err(&pdev->dev,
> + "Invalid number of memcpy channels specified (%d)\n",
> + num_memcpy);
> + return -EINVAL;
> + }
> + pdata->num_of_memcpy_chans = num_memcpy;
> +
> + of_property_read_u32_array(np, "memcpy-channels",
> + dma40_memcpy_channels,
> + num_memcpy);
> +
> pdev->dev.platform_data = pdata;
>
> return 0;
> diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
> index ceba6dc..1bb9b18 100644
> --- a/include/linux/platform_data/dma-ste-dma40.h
> +++ b/include/linux/platform_data/dma-ste-dma40.h
> @@ -132,6 +132,7 @@ struct stedma40_chan_cfg {
> * @num_of_soft_lli_chans: The number of channels that needs to be configured
> * to use SoftLLI.
> * @use_esram_lcla: flag for mapping the lcla into esram region
> + * @num_of_memcpy_chans: The number of channels reserved for memcpy.
> * @num_of_phy_chans: The number of physical channels implemented in HW.
> * 0 means reading the number of channels from DMA HW but this is only valid
> * for 'multiple of 4' channels, like 8.
> @@ -141,6 +142,7 @@ struct stedma40_platform_data {
> int *soft_lli_chans;
> int num_of_soft_lli_chans;
> bool use_esram_lcla;
> + int num_of_memcpy_chans;
> int num_of_phy_chans;
> };
>
> --
> 1.7.10.4
>
On Wed, May 15, 2013 at 10:51:56AM +0100, Lee Jones wrote:
> The aim is to make the code that little more readable.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Acked-by: Vinod Koul <[email protected]>
Hopefully all the BIT conversion in the driver are done in this
--
~Vinod
> ---
> drivers/dma/ste_dma40_ll.c | 44 ++++++++++++++++++++++----------------------
> 1 file changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index 121c0ce..5ddd724 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -20,28 +20,28 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
> /* src is mem? -> increase address pos */
> if (cfg->dir == DMA_MEM_TO_DEV ||
> cfg->dir == DMA_MEM_TO_MEM)
> - l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
> + l1 |= BIT(D40_MEM_LCSP1_SCFG_INCR_POS);
>
> /* dst is mem? -> increase address pos */
> if (cfg->dir == DMA_DEV_TO_MEM ||
> cfg->dir == DMA_MEM_TO_MEM)
> - l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
> + l3 |= BIT(D40_MEM_LCSP3_DCFG_INCR_POS);
>
> /* src is hw? -> master port 1 */
> if (cfg->dir == DMA_DEV_TO_MEM ||
> cfg->dir == DMA_DEV_TO_DEV)
> - l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
> + l1 |= BIT(D40_MEM_LCSP1_SCFG_MST_POS);
>
> /* dst is hw? -> master port 1 */
> if (cfg->dir == DMA_MEM_TO_DEV ||
> cfg->dir == DMA_DEV_TO_DEV)
> - l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
> + l3 |= BIT(D40_MEM_LCSP3_DCFG_MST_POS);
>
> - l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
> + l3 |= BIT(D40_MEM_LCSP3_DCFG_EIM_POS);
> l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
> l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
>
> - l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
> + l1 |= BIT(D40_MEM_LCSP1_SCFG_EIM_POS);
> l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
> l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
>
> @@ -58,39 +58,39 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
> if ((cfg->dir == DMA_DEV_TO_MEM) ||
> (cfg->dir == DMA_DEV_TO_DEV)) {
> /* Set master port to 1 */
> - src |= 1 << D40_SREG_CFG_MST_POS;
> + src |= BIT(D40_SREG_CFG_MST_POS);
> src |= D40_TYPE_TO_EVENT(cfg->dev_type);
>
> if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> - src |= 1 << D40_SREG_CFG_PHY_TM_POS;
> + src |= BIT(D40_SREG_CFG_PHY_TM_POS);
> else
> src |= 3 << D40_SREG_CFG_PHY_TM_POS;
> }
> if ((cfg->dir == DMA_MEM_TO_DEV) ||
> (cfg->dir == DMA_DEV_TO_DEV)) {
> /* Set master port to 1 */
> - dst |= 1 << D40_SREG_CFG_MST_POS;
> + dst |= BIT(D40_SREG_CFG_MST_POS);
> dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
>
> if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
> - dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
> + dst |= BIT(D40_SREG_CFG_PHY_TM_POS);
> else
> dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
> }
> /* Interrupt on end of transfer for destination */
> - dst |= 1 << D40_SREG_CFG_TIM_POS;
> + dst |= BIT(D40_SREG_CFG_TIM_POS);
>
> /* Generate interrupt on error */
> - src |= 1 << D40_SREG_CFG_EIM_POS;
> - dst |= 1 << D40_SREG_CFG_EIM_POS;
> + src |= BIT(D40_SREG_CFG_EIM_POS);
> + dst |= BIT(D40_SREG_CFG_EIM_POS);
>
> /* PSIZE */
> if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
> - src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> + src |= BIT(D40_SREG_CFG_PHY_PEN_POS);
> src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
> }
> if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
> - dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
> + dst |= BIT(D40_SREG_CFG_PHY_PEN_POS);
> dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
> }
>
> @@ -100,14 +100,14 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
>
> /* Set the priority bit to high for the physical channel */
> if (cfg->high_priority) {
> - src |= 1 << D40_SREG_CFG_PRI_POS;
> - dst |= 1 << D40_SREG_CFG_PRI_POS;
> + src |= BIT(D40_SREG_CFG_PRI_POS);
> + dst |= BIT(D40_SREG_CFG_PRI_POS);
> }
>
> if (cfg->src_info.big_endian)
> - src |= 1 << D40_SREG_CFG_LBE_POS;
> + src |= BIT(D40_SREG_CFG_LBE_POS);
> if (cfg->dst_info.big_endian)
> - dst |= 1 << D40_SREG_CFG_LBE_POS;
> + dst |= BIT(D40_SREG_CFG_LBE_POS);
>
> *src_cfg = src;
> *dst_cfg = dst;
> @@ -157,15 +157,15 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
>
> /* If this scatter list entry is the last one, no next link */
> if (next_lli == 0)
> - lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
> + lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);
> else
> lli->reg_lnk = next_lli;
>
> /* Set/clear interrupt generation on this link item.*/
> if (term_int)
> - lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
> + lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);
> else
> - lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
> + lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
>
> /* Post link */
> lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
> --
> 1.7.10.4
>
On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Nice :)
1) I dont see the STE macro getting removed, why do we need it
2) last i checked the direction values had a bit idfference b/w what you are
using and what dmaengine defines, so hopefully that is taken care of..
--
~Vinod
> ---
> drivers/dma/ste_dma40.c | 56 ++++++++++++++++++++++----------------------
> drivers/dma/ste_dma40_ll.c | 24 +++++++++----------
> 2 files changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 08bc58a..483da16 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -78,7 +78,7 @@ static int dma40_memcpy_channels[] = {
> /* Default configuration for physcial memcpy */
> struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
> .mode = STEDMA40_MODE_PHYSICAL,
> - .dir = STEDMA40_MEM_TO_MEM,
> + .dir = DMA_MEM_TO_MEM,
>
> .src_info.data_width = STEDMA40_BYTE_WIDTH,
> .src_info.psize = STEDMA40_PSIZE_PHY_1,
> @@ -92,7 +92,7 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
> /* Default configuration for logical memcpy */
> struct stedma40_chan_cfg dma40_memcpy_conf_log = {
> .mode = STEDMA40_MODE_LOGICAL,
> - .dir = STEDMA40_MEM_TO_MEM,
> + .dir = DMA_MEM_TO_MEM,
>
> .src_info.data_width = STEDMA40_BYTE_WIDTH,
> .src_info.psize = STEDMA40_PSIZE_LOG_1,
> @@ -843,7 +843,7 @@ static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
> * that uses linked lists.
> */
> if (!(chan->phy_chan->use_soft_lli &&
> - chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM))
> + chan->dma_cfg.dir == DMA_DEV_TO_MEM))
> curr_lcla = d40_lcla_alloc_one(chan, desc);
>
> first_lcla = curr_lcla;
> @@ -1311,12 +1311,12 @@ static void d40_config_set_event(struct d40_chan *d40c,
> u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
>
> /* Enable event line connected to device (or memcpy) */
> - if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
> - (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
> + if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
> + (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
> __d40_config_set_event(d40c, event_type, event,
> D40_CHAN_REG_SSLNK);
>
> - if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM)
> + if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
> __d40_config_set_event(d40c, event_type, event,
> D40_CHAN_REG_SDLNK);
> }
> @@ -1774,7 +1774,7 @@ static int d40_validate_conf(struct d40_chan *d40c,
> res = -EINVAL;
> }
>
> - if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
> + if (conf->dir == DMA_DEV_TO_DEV) {
> /*
> * DMAC HW supports it. Will be added to this driver,
> * in case any dma client requires it.
> @@ -1905,11 +1905,11 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
> phys = d40c->base->phy_res;
> num_phy_chans = d40c->base->num_phy_chans;
>
> - if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
> + if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
> log_num = 2 * dev_type;
> is_src = true;
> - } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
> - d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
> + } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
> + d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
> /* dst event lines are used for logical memcpy */
> log_num = 2 * dev_type + 1;
> is_src = false;
> @@ -1920,7 +1920,7 @@ static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
> event_line = D40_TYPE_TO_EVENT(dev_type);
>
> if (!is_log) {
> - if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
> + if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
> /* Find physical half channel */
> if (d40c->dma_cfg.use_fixed_channel) {
> i = d40c->dma_cfg.phy_channel;
> @@ -2068,10 +2068,10 @@ static int d40_free_dma(struct d40_chan *d40c)
> return -EINVAL;
> }
>
> - if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
> - d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
> + if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
> + d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
> is_src = false;
> - else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
> + else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
> is_src = true;
> else {
> chan_err(d40c, "Unknown direction\n");
> @@ -2133,10 +2133,10 @@ static bool d40_is_paused(struct d40_chan *d40c)
> goto _exit;
> }
>
> - if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
> - d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
> + if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
> + d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
> status = readl(chanbase + D40_CHAN_REG_SDLNK);
> - } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
> + } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
> status = readl(chanbase + D40_CHAN_REG_SSLNK);
> } else {
> chan_err(d40c, "Unknown direction\n");
> @@ -2387,12 +2387,12 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
> if (d40c->base->rev < 3)
> return;
>
> - if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
> - (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
> + if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
> + (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
> __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
>
> - if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
> - (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
> + if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
> + (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
> __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
> }
>
> @@ -2423,11 +2423,11 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
>
> switch (D40_DT_FLAGS_DIR(flags)) {
> case 0:
> - cfg.dir = STEDMA40_MEM_TO_PERIPH;
> + cfg.dir = DMA_MEM_TO_DEV;
> cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
> break;
> case 1:
> - cfg.dir = STEDMA40_PERIPH_TO_MEM;
> + cfg.dir = DMA_DEV_TO_MEM;
> cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
> break;
> }
> @@ -2473,7 +2473,7 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
> d40_set_prio_realtime(d40c);
>
> if (chan_is_logical(d40c)) {
> - if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
> + if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
> d40c->lcpa = d40c->base->lcpa_base +
> d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
> else
> @@ -2746,12 +2746,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> if (config->direction == DMA_DEV_TO_MEM) {
> config_addr = config->src_addr;
>
> - if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
> + if (cfg->dir != DMA_DEV_TO_MEM)
> dev_dbg(d40c->base->dev,
> "channel was not configured for peripheral "
> "to memory transfer (%d) overriding\n",
> cfg->dir);
> - cfg->dir = STEDMA40_PERIPH_TO_MEM;
> + cfg->dir = DMA_DEV_TO_MEM;
>
> /* Configure the memory side */
> if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
> @@ -2762,12 +2762,12 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> } else if (config->direction == DMA_MEM_TO_DEV) {
> config_addr = config->dst_addr;
>
> - if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
> + if (cfg->dir != DMA_MEM_TO_DEV)
> dev_dbg(d40c->base->dev,
> "channel was not configured for memory "
> "to peripheral transfer (%d) overriding\n",
> cfg->dir);
> - cfg->dir = STEDMA40_MEM_TO_PERIPH;
> + cfg->dir = DMA_MEM_TO_DEV;
>
> /* Configure the memory side */
> if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index ab5a2a7..121c0ce 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -18,23 +18,23 @@ void d40_log_cfg(struct stedma40_chan_cfg *cfg,
> u32 l1 = 0; /* src */
>
> /* src is mem? -> increase address pos */
> - if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
> - cfg->dir == STEDMA40_MEM_TO_MEM)
> + if (cfg->dir == DMA_MEM_TO_DEV ||
> + cfg->dir == DMA_MEM_TO_MEM)
> l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
>
> /* dst is mem? -> increase address pos */
> - if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
> - cfg->dir == STEDMA40_MEM_TO_MEM)
> + if (cfg->dir == DMA_DEV_TO_MEM ||
> + cfg->dir == DMA_MEM_TO_MEM)
> l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
>
> /* src is hw? -> master port 1 */
> - if (cfg->dir == STEDMA40_PERIPH_TO_MEM ||
> - cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
> + if (cfg->dir == DMA_DEV_TO_MEM ||
> + cfg->dir == DMA_DEV_TO_DEV)
> l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
>
> /* dst is hw? -> master port 1 */
> - if (cfg->dir == STEDMA40_MEM_TO_PERIPH ||
> - cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
> + if (cfg->dir == DMA_MEM_TO_DEV ||
> + cfg->dir == DMA_DEV_TO_DEV)
> l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
>
> l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
> @@ -55,8 +55,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
> u32 src = 0;
> u32 dst = 0;
>
> - if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) ||
> - (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> + if ((cfg->dir == DMA_DEV_TO_MEM) ||
> + (cfg->dir == DMA_DEV_TO_DEV)) {
> /* Set master port to 1 */
> src |= 1 << D40_SREG_CFG_MST_POS;
> src |= D40_TYPE_TO_EVENT(cfg->dev_type);
> @@ -66,8 +66,8 @@ void d40_phy_cfg(struct stedma40_chan_cfg *cfg, u32 *src_cfg, u32 *dst_cfg)
> else
> src |= 3 << D40_SREG_CFG_PHY_TM_POS;
> }
> - if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) ||
> - (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
> + if ((cfg->dir == DMA_MEM_TO_DEV) ||
> + (cfg->dir == DMA_DEV_TO_DEV)) {
> /* Set master port to 1 */
> dst |= 1 << D40_SREG_CFG_MST_POS;
> dst |= D40_TYPE_TO_EVENT(cfg->dev_type);
> --
> 1.7.10.4
>
On Wed, May 15, 2013 at 10:51:58AM +0100, Lee Jones wrote:
> Unsure of the author's intentions, rather than just removing the nop,
> we're replacing it with a comment containing the possible intention
> of the statement OR:ing with 0.
Would be worthwhile to check w/ Linus W on this (or check whom to blame)
--
~Vinod
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <per.forlin-0IS4wlFg1OjSUeElwK9/[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
> ---
> drivers/dma/ste_dma40_ll.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index a035dfe..27b818d 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -182,8 +182,10 @@ static int d40_phy_fill_lli(struct d40_phy_lli *lli,
> else
> lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);
>
> - /* Post link */
> - lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;
> + /*
> + * Post link - D40_SREG_LNK_PHY_PRE_POS = 0
> + * Relink happens after transfer completion.
> + */
>
> return 0;
> }
> --
> 1.7.10.4
>
On Wed, May 15, 2013 at 10:52:02AM +0100, Lee Jones wrote:
> Some platforms have channels which are not available for normal use.
> This information is currently passed though platform data in internal
> BSP kernels. Once those platforms land, they'll need to configure them
> appropriately, so we may as well add the infrastructure.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Acked-by: Vinod Koul <[email protected]>
> ---
> Documentation/devicetree/bindings/dma/ste-dma40.txt | 2 ++
> drivers/dma/ste_dma40.c | 17 ++++++++++++++++-
> 2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> index aa272d8..bea5b73 100644
> --- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
> +++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
> @@ -11,6 +11,7 @@ Required properties:
> Optional properties:
> - dma-channels: Number of channels supported by hardware - if not present
> the driver will attempt to obtain the information from H/W
> +- disabled-channels: Channels which can not be used
>
> Example:
>
> @@ -23,6 +24,7 @@ Example:
>
> #dma-cells = <2>;
> memcpy-channels = <56 57 58 59 60>;
> + disabled-channels = <12>;
> dma-channels = <8>;
> };
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 4e528dd..ffac822 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -3482,7 +3482,7 @@ static int __init d40_of_probe(struct platform_device *pdev,
> struct device_node *np)
> {
> struct stedma40_platform_data *pdata;
> - int num_phy = 0, num_memcpy = 0;
> + int num_phy = 0, num_memcpy = 0, num_disabled = 0;
> const const __be32 *list;
>
> pdata = devm_kzalloc(&pdev->dev,
> @@ -3511,6 +3511,21 @@ static int __init d40_of_probe(struct platform_device *pdev,
> dma40_memcpy_channels,
> num_memcpy);
>
> + list = of_get_property(np, "disabled-channels", &num_disabled);
> + num_disabled /= sizeof(*list);
> +
> + if (num_disabled > STEDMA40_MAX_PHYS || num_disabled < 0) {
> + d40_err(&pdev->dev,
> + "Invalid number of disabled channels specified (%d)\n",
> + num_disabled);
> + return -EINVAL;
> + }
> +
> + of_property_read_u32_array(np, "disabled-channels",
> + pdata->disabled_channels,
> + num_disabled);
> + pdata->disabled_channels[num_disabled] = -1;
> +
> pdev->dev.platform_data = pdata;
>
> return 0;
> --
> 1.7.10.4
>
On Wed, 15 May 2013, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>
> > If we fail to prepare the ux500-hash clock before enabling it the
> > platform will fail to boot. Here we insure this happens.
> >
> > Cc: Herbert Xu <[email protected]>
> > Cc: David S. Miller <davem-fT/PcQaiUtIeIZ0/[email protected]>
> > Cc: Andreas Westin <andreas.westin-0IS4wlFg1OjSUeElwK9/[email protected]>
> > Cc: [email protected]
> > Acked-by: Arnd Bergmann <[email protected]>
> > Acked-by: Ulf Hansson <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
>
> This patch seems to be totally independent of the other stuff
> in the patch series, and it even seems like an -rc fix to me
> (I don't think the crypto device works without this).
>
> This should go into the crypto tree?
I agree.
> Else please convince Herbert to give his ACK on this
> before I apply it.
Pleeeeaasseee Herbert, take this patch! :)
How's that?
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
> > Unsure of the author's intentions, rather than just removing the nop,
> > we're replacing it with a comment containing the possible intention
> > of the statement OR:ing with 0.
> Would be worthwhile to check w/ Linus W on this (or check whom to blame)
I did already. It was his idea to place the comment in.
The original author will on parental leave for the foreseeable future.
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Thu, May 16, 2013 at 07:53:55AM +0100, Lee Jones wrote:
> On Wed, 15 May 2013, Linus Walleij wrote:
>
> > On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> >
> > > If we fail to prepare the ux500-hash clock before enabling it the
> > > platform will fail to boot. Here we insure this happens.
> > >
> > > Cc: Herbert Xu <[email protected]>
> > > Cc: David S. Miller <[email protected]>
> > > Cc: Andreas Westin <[email protected]>
> > > Cc: [email protected]
> > > Acked-by: Arnd Bergmann <[email protected]>
> > > Acked-by: Ulf Hansson <[email protected]>
> > > Signed-off-by: Lee Jones <[email protected]>
> >
> > This patch seems to be totally independent of the other stuff
> > in the patch series, and it even seems like an -rc fix to me
> > (I don't think the crypto device works without this).
> >
> > This should go into the crypto tree?
>
> I agree.
>
> > Else please convince Herbert to give his ACK on this
> > before I apply it.
>
> Pleeeeaasseee Herbert, take this patch! :)
Acked-by: Herbert Xu <[email protected]>
Thanks,
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Wed, May 15, 2013 at 10:51:38AM +0100, Lee Jones wrote:
> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Ulf Hansson <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Acked-by: Herbert Xu <[email protected]>
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Wed, May 15, 2013 at 10:51:39AM +0100, Lee Jones wrote:
> The DMA controller currently takes configuration information from
> information passed though dma_channel_request(), but it shouldn't.
> Using the API, the DMA channel should only be configured during
> a dma_slave_config() call.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Arnd Bergmann <[email protected]>
> Acked-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Acked-by: Herbert Xu <[email protected]>
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Wed, May 15, 2013 at 10:51:41AM +0100, Lee Jones wrote:
> The Cryp driver is currently silent and the Hash driver prints the
> name of its probe function unnecessarily. Let's just put a nice
> descriptive one-liner there instead.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Arnd Bergmann <[email protected]>
> Reviewed-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Acked-by: Herbert Xu <[email protected]>
--
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
On Thu, 16 May 2013, Vinod Koul wrote:
> On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> > duplicating such things.
> >
> > Cc: Vinod Koul <[email protected]>
> > Cc: Dan Williams <[email protected]>
> > Cc: Per Forlin <[email protected]>
> > Cc: Rabin Vincent <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
> Nice :)
:)
> 1) I dont see the STE macro getting removed, why do we need it
They are removed later in the set, once their use has been removed
from platform code and all the other drivers.
> 2) last i checked the direction values had a bit idfference b/w what you are
> using and what dmaengine defines, so hopefully that is taken care of..
Yes, no problem.
<place Ack here> ;)
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
> When a DMA client requests and configures a DMA channel, it requests
> data_width in Bytes. The DMA40 driver then swiftly converts it over to
> the necessary register bit value. Unfortunately, for any subsequent
> calculations we have to shift '1' by the bit pattern (1 << data_width)
> times to make any sense of it.
>
> This patch flips the semantics on its head and only converts the value
> to its respective register bit pattern when writing to registers. This
> way we can use the true data_width (in Bytes) value.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
> ---
> @@ -2804,14 +2781,24 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
> }
>
> + /* Only valid widths are; 1, 2, 4 and 8. */
> + if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> + src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
> + dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> + dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
> + ((src_addr_width > 1) && (src_addr_width & 1)) ||
> + ((dst_addr_width > 1) && (dst_addr_width & 1)))
> + return -EINVAL;
how about a simple macro to check above..
> +
> + cfg->src_info.data_width = src_addr_width;
> + cfg->dst_info.data_width = dst_addr_width;
> +
> ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
> - src_addr_width,
> src_maxburst);
> if (ret)
> return ret;
>
> ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
> - dst_addr_width,
> dst_maxburst);
> if (ret)
> return ret;
> diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> index 5ddd724..a035dfe 100644
> --- a/drivers/dma/ste_dma40_ll.c
> +++ b/drivers/dma/ste_dma40_ll.c
> @@ -10,6 +10,18 @@
>
> #include "ste_dma40_ll.h"
>
> +u8 d40_width_to_bits(enum dma_slave_buswidth width)
> +{
> + if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> + return STEDMA40_ESIZE_8_BIT;
> + else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> + return STEDMA40_ESIZE_16_BIT;
> + else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> + return STEDMA40_ESIZE_64_BIT;
> + else
> + return STEDMA40_ESIZE_32_BIT;
> +}
> +
Switch looks better for this and how about
return fls(width);
as your defines are 0...3 and dmaengine define 1,2,..8 for same thing
then you can also get rid of STEDMA40_XXX_WIDTH macros!
> @@ -70,13 +70,6 @@ enum stedma40_flow_ctrl {
> STEDMA40_FLOW_CTRL,
> };
>
> -enum stedma40_periph_data_width {
> - STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
> - STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
> - STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
> - STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
> -};
nice
--
~Vinod
On Wed, May 15, 2013 at 06:29:51PM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>
> > During the initial setup of a logical channel, it is necessary to unmask
> > the GIM in order to receive generated terminal count and error interrupts.
> > We're separating out this required code so it will be possible to move
> > the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> > into the runtime_config() routine.
> >
> > Cc: Vinod Koul <[email protected]>
> > Cc: Dan Williams <[email protected]>
> > Cc: Per Forlin <[email protected]>
> > Cc: Rabin Vincent <[email protected]>
> > Acked-by: Arnd Bergmann <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
>
> Tentatively applied to my ux500-dma40 branch.
>
> This lacks an ACK from Vinod...
Acked-by: Vinod Koul <[email protected]>
>
> I cannot get any of this stack of patches up to ARM SoC
> before I have Vinod's ACK on all hitting drivers/dma/*
Wip ... :)
>
> Yours,
> Linus Walleij
On Wed, May 15, 2013 at 10:51:26AM +0100, Lee Jones wrote:
> Using the dmaengine API, allocating and configuring a channel are two
> separate actions. Here we're removing logical channel configuration from
> the channel allocating routines.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
> ---
Acked-by: Vinod Koul <[email protected]>
--
~Vinod
> drivers/dma/ste_dma40.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index b7fe46b..ba84df8 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -2040,6 +2040,9 @@ static int d40_config_memcpy(struct d40_chan *d40c)
> d40c->dma_cfg = dma40_memcpy_conf_log;
> d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
>
> + d40_log_cfg(&d40c->dma_cfg,
> + &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> +
> } else if (dma_has_cap(DMA_MEMCPY, cap) &&
> dma_has_cap(DMA_SLAVE, cap)) {
> d40c->dma_cfg = dma40_memcpy_conf_phy;
> @@ -2508,9 +2511,6 @@ static int d40_alloc_chan_resources(struct dma_chan *chan)
> d40_set_prio_realtime(d40c);
>
> if (chan_is_logical(d40c)) {
> - d40_log_cfg(&d40c->dma_cfg,
> - &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
> -
> if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
> d40c->lcpa = d40c->base->lcpa_base +
> d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
> --
> 1.7.10.4
>
On Wed, May 15, 2013 at 10:51:31AM +0100, Lee Jones wrote:
> Addresses are now stored in local data structures and are easy to
> obtain, thus a specialist function used to fetch them is now surplus
> to requirement.
>
> Signed-off-by: Lee Jones <[email protected]>
> ---
Acked-by: Vinod Koul <[email protected]>
--
~Vinod
> drivers/dma/ste_dma40.c | 18 ------------------
> 1 file changed, 18 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 57a127e..6ed7757 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -2267,24 +2267,6 @@ err:
> return NULL;
> }
>
> -static dma_addr_t
> -d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
> -{
> - struct stedma40_platform_data *plat = chan->base->plat_data;
> - struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
> - dma_addr_t addr = 0;
> -
> - if (chan->runtime_addr)
> - return chan->runtime_addr;
> -
> - if (direction == DMA_DEV_TO_MEM)
> - addr = plat->dev_rx[cfg->dev_type];
> - else if (direction == DMA_MEM_TO_DEV)
> - addr = plat->dev_tx[cfg->dev_type];
> -
> - return addr;
> -}
> -
> static struct dma_async_tx_descriptor *
> d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
> struct scatterlist *sg_dst, unsigned int sg_len,
> --
> 1.7.10.4
>
On Wed, May 15, 2013 at 10:51:30AM +0100, Lee Jones wrote:
> Addresses are passed in from the client's driver via the invocation of
> dmaengine_slave_config(), so there's no need to fetch them from platform
> data too, hardwired or otherwise. This is a great step forward, as it
> elevates a large burden from platform data in the way of a look-up
> table.
>
> Signed-off-by: Lee Jones <[email protected]>
> ---
Good code size reduction, always a good template for code improvements
Acked-by: Vinod Koul <[email protected]>
--
~Vinod
> drivers/dma/ste_dma40.c | 51 ++++++++++-------------------------------------
> 1 file changed, 11 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index ba84df8..57a127e 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
> @@ -1774,22 +1774,6 @@ static int d40_validate_conf(struct d40_chan *d40c,
> res = -EINVAL;
> }
>
> - if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
> - d40c->base->plat_data->dev_tx[conf->dev_type] == 0 &&
> - d40c->runtime_addr == 0) {
> - chan_err(d40c, "Invalid TX channel address (%d)\n",
> - conf->dev_type);
> - res = -EINVAL;
> - }
> -
> - if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
> - d40c->base->plat_data->dev_rx[conf->dev_type] == 0 &&
> - d40c->runtime_addr == 0) {
> - chan_err(d40c, "Invalid RX channel address (%d)\n",
> - conf->dev_type);
> - res = -EINVAL;
> - }
> -
> if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
> /*
> * DMAC HW supports it. Will be added to this driver,
> @@ -2327,14 +2311,10 @@ d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
> if (sg_next(&sg_src[sg_len - 1]) == sg_src)
> desc->cyclic = true;
>
> - if (direction != DMA_TRANS_NONE) {
> - dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
> -
> - if (direction == DMA_DEV_TO_MEM)
> - src_dev_addr = dev_addr;
> - else if (direction == DMA_MEM_TO_DEV)
> - dst_dev_addr = dev_addr;
> - }
> + if (direction == DMA_DEV_TO_MEM)
> + src_dev_addr = chan->runtime_addr;
> + else if (direction == DMA_MEM_TO_DEV)
> + dst_dev_addr = chan->runtime_addr;
>
> if (chan_is_logical(chan))
> ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
> @@ -2782,15 +2762,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> dst_maxburst = config->dst_maxburst;
>
> if (config->direction == DMA_DEV_TO_MEM) {
> - dma_addr_t dev_addr_rx =
> - d40c->base->plat_data->dev_rx[cfg->dev_type];
> -
> config_addr = config->src_addr;
> - if (dev_addr_rx)
> - dev_dbg(d40c->base->dev,
> - "channel has a pre-wired RX address %08x "
> - "overriding with %08x\n",
> - dev_addr_rx, config_addr);
> +
> if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
> dev_dbg(d40c->base->dev,
> "channel was not configured for peripheral "
> @@ -2805,15 +2778,8 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> dst_maxburst = src_maxburst;
>
> } else if (config->direction == DMA_MEM_TO_DEV) {
> - dma_addr_t dev_addr_tx =
> - d40c->base->plat_data->dev_tx[cfg->dev_type];
> -
> config_addr = config->dst_addr;
> - if (dev_addr_tx)
> - dev_dbg(d40c->base->dev,
> - "channel has a pre-wired TX address %08x "
> - "overriding with %08x\n",
> - dev_addr_tx, config_addr);
> +
> if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
> dev_dbg(d40c->base->dev,
> "channel was not configured for memory "
> @@ -2833,6 +2799,11 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> return -EINVAL;
> }
>
> + if (config_addr <= 0) {
> + dev_err(d40c->base->dev, "no address supplied\n");
> + return -EINVAL;
> + }
> +
> if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
> dev_err(d40c->base->dev,
> "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
> --
> 1.7.10.4
>
On Wed, May 15, 2013 at 10:51:33AM +0100, Lee Jones wrote:
> 'struct stedma40_half_channel_info's header comment says that it's
> called 'struct stedma40_chan_cfg'. Let's straighten that out.
>
> Signed-off-by: Lee Jones <[email protected]>
> ---
Acked-by: Vinod Koul <[email protected]>
--
~Vinod
> include/linux/platform_data/dma-ste-dma40.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/platform_data/dma-ste-dma40.h b/include/linux/platform_data/dma-ste-dma40.h
> index af0064e..288dc24 100644
> --- a/include/linux/platform_data/dma-ste-dma40.h
> +++ b/include/linux/platform_data/dma-ste-dma40.h
> @@ -86,7 +86,7 @@ enum stedma40_xfer_dir {
>
>
> /**
> - * struct stedma40_chan_cfg - dst/src channel configuration
> + * struct stedma40_half_channel_info - dst/src channel configuration
> *
> * @big_endian: true if the src/dst should be read as big endian
> * @data_width: Data width of the src/dst hardware
> --
> 1.7.10.4
>
On Thu, May 16, 2013 at 08:06:38AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
>
> > On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> > > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > > the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> > > duplicating such things.
> > >
> > > Cc: Vinod Koul <[email protected]>
> > > Cc: Dan Williams <[email protected]>
> > > Cc: Per Forlin <[email protected]>
> > > Cc: Rabin Vincent <[email protected]>
> > > Signed-off-by: Lee Jones <[email protected]>
> > Nice :)
>
> :)
>
> > 1) I dont see the STE macro getting removed, why do we need it
>
> They are removed later in the set, once their use has been removed
> from platform code and all the other drivers.
>
> > 2) last i checked the direction values had a bit idfference b/w what you are
> > using and what dmaengine defines, so hopefully that is taken care of..
>
> Yes, no problem.
>
> <place Ack here> ;)
Acked-by: Vinod Koul <[email protected]>
--
~Vinod
>
> --
> Lee Jones
> Linaro ST-Ericsson Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
On Thu, 16 May 2013, Vinod Koul wrote:
> On Wed, May 15, 2013 at 06:29:51PM +0200, Linus Walleij wrote:
> > On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> >
> > > During the initial setup of a logical channel, it is necessary to unmask
> > > the GIM in order to receive generated terminal count and error interrupts.
> > > We're separating out this required code so it will be possible to move
> > > the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> > > into the runtime_config() routine.
> > >
> > > Cc: Vinod Koul <[email protected]>
> > > Cc: Dan Williams <[email protected]>
> > > Cc: Per Forlin <[email protected]>
> > > Cc: Rabin Vincent <[email protected]>
> > > Acked-by: Arnd Bergmann <[email protected]>
> > > Signed-off-by: Lee Jones <[email protected]>
> >
> > Tentatively applied to my ux500-dma40 branch.
> >
> > This lacks an ACK from Vinod...
> Acked-by: Vinod Koul <[email protected]>
> >
> > I cannot get any of this stack of patches up to ARM SoC
> > before I have Vinod's ACK on all hitting drivers/dma/*
> Wip ... :)
Nice! :)
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Thu, 16 May 2013, Vinod Koul wrote:
> On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
> > When a DMA client requests and configures a DMA channel, it requests
> > data_width in Bytes. The DMA40 driver then swiftly converts it over to
> > the necessary register bit value. Unfortunately, for any subsequent
> > calculations we have to shift '1' by the bit pattern (1 << data_width)
> > times to make any sense of it.
> >
> > This patch flips the semantics on its head and only converts the value
> > to its respective register bit pattern when writing to registers. This
> > way we can use the true data_width (in Bytes) value.
> >
> > Cc: Vinod Koul <[email protected]>
> > Cc: Dan Williams <[email protected]>
> > Cc: Per Forlin <[email protected]>
> > Cc: Rabin Vincent <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
> > ---
>
> > @@ -2804,14 +2781,24 @@ static int d40_set_runtime_config(struct dma_chan *chan,
> > src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
> > }
> >
> > + /* Only valid widths are; 1, 2, 4 and 8. */
> > + if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> > + src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
> > + dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
> > + dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
> > + ((src_addr_width > 1) && (src_addr_width & 1)) ||
> > + ((dst_addr_width > 1) && (dst_addr_width & 1)))
> > + return -EINVAL;
> how about a simple macro to check above..
I thought about it, but as this code appears only once, I considered
it to be unnecessary abstraction.
> > +
> > + cfg->src_info.data_width = src_addr_width;
> > + cfg->dst_info.data_width = dst_addr_width;
> > +
> > ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
> > - src_addr_width,
> > src_maxburst);
> > if (ret)
> > return ret;
> >
> > ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
> > - dst_addr_width,
> > dst_maxburst);
> > if (ret)
> > return ret;
> > diff --git a/drivers/dma/ste_dma40_ll.c b/drivers/dma/ste_dma40_ll.c
> > index 5ddd724..a035dfe 100644
> > --- a/drivers/dma/ste_dma40_ll.c
> > +++ b/drivers/dma/ste_dma40_ll.c
> > @@ -10,6 +10,18 @@
> >
> > #include "ste_dma40_ll.h"
> >
> > +u8 d40_width_to_bits(enum dma_slave_buswidth width)
> > +{
> > + if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> > + return STEDMA40_ESIZE_8_BIT;
> > + else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> > + return STEDMA40_ESIZE_16_BIT;
> > + else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> > + return STEDMA40_ESIZE_64_BIT;
> > + else
> > + return STEDMA40_ESIZE_32_BIT;
> > +}
> > +
> Switch looks better for this and how about
> return fls(width);
>
> as your defines are 0...3 and dmaengine define 1,2,..8 for same thing
> then you can also get rid of STEDMA40_XXX_WIDTH macros!
I like it.
Will you let me do it as a follow-up patch?
> > @@ -70,13 +70,6 @@ enum stedma40_flow_ctrl {
> > STEDMA40_FLOW_CTRL,
> > };
> >
> > -enum stedma40_periph_data_width {
> > - STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
> > - STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
> > - STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
> > - STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
> > -};
> nice
>
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Thu, May 16, 2013 at 08:35:53AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
>
> > On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
> > > +u8 d40_width_to_bits(enum dma_slave_buswidth width)
> > > +{
> > > + if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
> > > + return STEDMA40_ESIZE_8_BIT;
> > > + else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
> > > + return STEDMA40_ESIZE_16_BIT;
> > > + else if (width == DMA_SLAVE_BUSWIDTH_8_BYTES)
> > > + return STEDMA40_ESIZE_64_BIT;
> > > + else
> > > + return STEDMA40_ESIZE_32_BIT;
> > > +}
> > > +
> > Switch looks better for this and how about
> > return fls(width);
> >
> > as your defines are 0...3 and dmaengine define 1,2,..8 for same thing
> > then you can also get rid of STEDMA40_XXX_WIDTH macros!
>
> I like it.
>
> Will you let me do it as a follow-up patch?
Okay...
--
~Vinod
On Wed, May 15, 2013 at 10:14 PM, Fabio Baltieri
<[email protected]> wrote:
> On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:
>> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>>
>> > For all ux500 based platforms the maximum number of end-points are used.
>> > Move this knowledge into the driver so we can relinquish the burden from
>> > platform data. This also removes quite a bit of complexity from the driver
>> > and will aid us when we come to enable the driver for Device Tree.
>> >
>> > Cc: Felipe Balbi <[email protected]>
>> > Cc: [email protected]
>> > Acked-by: Linus Walleij <[email protected]>
>> > Acked-by: Fabio Baltieri <[email protected]>
>> > Signed-off-by: Lee Jones <[email protected]>
>>
>> I guess this stuff is dependent on the stuff Fabio has recently sent to
>> Felipe for the ux500 musb DMA so these musb patches should
>> primarily go through his tree.
>
> Not really, I only sent some coding style fix for the dma driver, as
> almost all of my work was in the usb phy files. I also checked my
> latest series against Lee's tree and the two seems to merge without any
> conflict, so as far as I'm concerned it's really up to you and Felipe.
OK so Felipe can merge these smallish patches to musb, fine...
The other (DMA) stuff needs to be merged together with the rest
of the DMA40 series, so here basically Felipe needs an indication
if he can ACK it so I merge it through ARM SoC without colissions
and it sounds like we can make the assumption that this will work.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> If we fail to prepare the ux500-hash clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Arnd Bergmann <[email protected]>
> Acked-by: Ulf Hansson <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied to my dma40 branch with Herbert's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> DMA channel configuration information should be setup in the driver.
> The Ux500 Hash driver now does this, so there's no need to send it
> though here too.
>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied now that the deps are in!
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> If we fail to prepare the ux500-cryp clock before enabling it the
> platform will fail to boot. Here we insure this happens.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Ulf Hansson <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied with Herbert's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> The DMA controller currently takes configuration information from
> information passed though dma_channel_request(), but it shouldn't.
> Using the API, the DMA channel should only be configured during
> a dma_slave_config() call.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Arnd Bergmann <[email protected]>
> Acked-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied with Herbert's ACK.
Thanks,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> The Cryp driver is currently silent and the Hash driver prints the
> name of its probe function unnecessarily. Let's just put a nice
> descriptive one-liner there instead.
>
> Cc: Herbert Xu <[email protected]>
> Cc: David S. Miller <[email protected]>
> Cc: Andreas Westin <[email protected]>
> Cc: [email protected]
> Acked-by: Arnd Bergmann <[email protected]>
> Reviewed-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied with Herbert's ACK.
Thanks,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> These drivers are now operational and even use the latest common clk
> and DMA APIs. There's no reason why we shouldn't start them up now.
>
> Reviewed-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied now that the deps are in place.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
I have now gone over and collected ACKs etc for the patches up until here.
Now you need Felipe's consent to proceed with the MUSB changes
through my tree.
Yours,
Linus Walleij
Hi,
On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>
> > For all ux500 based platforms the maximum number of end-points are used.
> > Move this knowledge into the driver so we can relinquish the burden from
> > platform data. This also removes quite a bit of complexity from the driver
> > and will aid us when we come to enable the driver for Device Tree.
> >
> > Cc: Felipe Balbi <[email protected]>
> > Cc: [email protected]
> > Acked-by: Linus Walleij <[email protected]>
> > Acked-by: Fabio Baltieri <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
>
> I guess this stuff is dependent on the stuff Fabio has recently sent to
> Felipe for the ux500 musb DMA so these musb patches should
> primarily go through his tree.
>
> It seems like the later changes to the platform code
> (arch/arm/mach-ux500) may be sufficiently orthogonal
> so it can be done out-of-order?
>
> I can't merge any of this without Felipes ACKs in any
> case.
Do you want to take this yourself ? I haven't fully read the series yet,
but seems like this depends on the rest of the series. If you want to
take it, let me know I can ack the patches as soon as I'm done
reviewing.
--
balbi
Hi Felipe
> > > For all ux500 based platforms the maximum number of end-points are used.
> > > Move this knowledge into the driver so we can relinquish the burden from
> > > platform data. This also removes quite a bit of complexity from the driver
> > > and will aid us when we come to enable the driver for Device Tree.
> > >
> > > Cc: Felipe Balbi <[email protected]>
> > > Cc: [email protected]
> > > Acked-by: Linus Walleij <[email protected]>
> > > Acked-by: Fabio Baltieri <[email protected]>
> > > Signed-off-by: Lee Jones <[email protected]>
> >
> > I guess this stuff is dependent on the stuff Fabio has recently sent to
> > Felipe for the ux500 musb DMA so these musb patches should
> > primarily go through his tree.
> >
> > It seems like the later changes to the platform code
> > (arch/arm/mach-ux500) may be sufficiently orthogonal
> > so it can be done out-of-order?
> >
> > I can't merge any of this without Felipes ACKs in any
> > case.
>
> Do you want to take this yourself ? I haven't fully read the series yet,
> but seems like this depends on the rest of the series. If you want to
> take it, let me know I can ack the patches as soon as I'm done
> reviewing.
Yes that would be ideal, if you wouldn't mind.
Kind regards,
Lee
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Tue, May 28, 2013 at 6:27 PM, Felipe Balbi <[email protected]> wrote:
> On Wed, May 15, 2013 at 07:18:01PM +0200, Linus Walleij wrote:
>> I can't merge any of this without Felipes ACKs in any
>> case.
>
> Do you want to take this yourself ? I haven't fully read the series yet,
> but seems like this depends on the rest of the series. If you want to
> take it, let me know I can ack the patches as soon as I'm done
> reviewing.
Yes please. They are dependent on a stash of patches that that
has recently landed in the ARM SoC tree, so currently they need
to follow those through the same tree, which is where I funnel
all the ux500 stuff.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
for drivers/usb/musb
Acked-by: Felipe Balbi <[email protected]>
--
balbi
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> For all ux500 based platforms the maximum number of end-points are used.
> Move this knowledge into the driver so we can relinquish the burden from
> platform data. This also removes quite a bit of complexity from the driver
> and will aid us when we come to enable the driver for Device Tree.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied to my dma40 branch with Felipe's ACK.
Thanks!
Linus Walleij
On Wed, May 29, 2013 at 7:57 PM, Felipe Balbi <[email protected]> wrote:
> On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
>> For all ux500 based platforms the maximum number of end-points are used.
>> Move this knowledge into the driver so we can relinquish the burden from
>> platform data. This also removes quite a bit of complexity from the driver
>> and will aid us when we come to enable the driver for Device Tree.
>>
>> Cc: Felipe Balbi <[email protected]>
>> Cc: [email protected]
>> Acked-by: Linus Walleij <[email protected]>
>> Acked-by: Fabio Baltieri <[email protected]>
>> Signed-off-by: Lee Jones <[email protected]>
>
> for drivers/usb/musb
>
> Acked-by: Felipe Balbi <[email protected]>
Is that only for this patch 20/39 or also 21, 22 & 23?
Poke us if we should re-send them...
Yours,
Linus Walleij
On Thu, 30 May 2013, Linus Walleij wrote:
> On Wed, May 29, 2013 at 7:57 PM, Felipe Balbi <[email protected]> wrote:
> > On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
> >> For all ux500 based platforms the maximum number of end-points are used.
> >> Move this knowledge into the driver so we can relinquish the burden from
> >> platform data. This also removes quite a bit of complexity from the driver
> >> and will aid us when we come to enable the driver for Device Tree.
> >>
> >> Cc: Felipe Balbi <[email protected]>
> >> Cc: [email protected]
> >> Acked-by: Linus Walleij <[email protected]>
> >> Acked-by: Fabio Baltieri <[email protected]>
> >> Signed-off-by: Lee Jones <[email protected]>
> >
> > for drivers/usb/musb
> >
> > Acked-by: Felipe Balbi <[email protected]>
>
> Is that only for this patch 20/39 or also 21, 22 & 23?
>
> Poke us if we should re-send them...
I read this as all patches in the series "for drivers/usb/musb".
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> The MUSB HDRC configuration never changes between each of the ux500
> supported platforms, so there's little point passing it though platform
> data. If we set it in the driver instead, we can make good use of it
> when booting with either ATAGs or Device Tree.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Tentatively applied with Felipe's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> The dma_mask will always be the same as the coherent_dma_mask, so let's
> cut down on the platform_data burden and set it as such in the driver.
> This also saves us from supporting it separately when we come to enable
> this driver for Device Tree.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Tentatively applied with Felipe's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> In its current state, the ux500-musb driver uses platform data pointers
> blindly with no prior checking. If no platform data pointer is passed
> this will Oops the kernel. In this patch we ensure platform data and
> board data are present prior to using them.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Tentatively applied with Felipe's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> If we can ever get to a state where we can solely search for DMA channels
> by name, this will almost completely alleviate the requirement to pass
> copious amounts of information though platform data. Here we take the
> first step towards this. The next step will be to enable Device Tree
> complete with name<->event_line mapping.
>
> Cc: Felipe Balbi <[email protected]>
> Cc: [email protected]
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Tentatively applied with Felipe's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> The recently DT:ed MUSB driver will require clock-name by device-name
> look-up capability, until common clk has is properly supported by the
> ux500 platform.
>
> Acked-by: Linus Walleij <[email protected]>
> Acked-by: Fabio Baltieri <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Applied to my ux500-devicetree branch.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> The aim is to make the code that little more readable.
>
> Acked-by: Vinod Koul <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Reviewed-by: Linus Walleij <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied to my ux500-dma40 branch.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
>
> Signed-off-by: Lee Jones <[email protected]>
Vinod, I'm lacking your ACK on this patch, but have tentatively
queued it anyway. Maybe you missed it?
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <per.forlin-0IS4wlFg1OjSUeElwK9/[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied to my dma40 branch with Vinod's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> We're now using the transfer direction definitions provided by the DMA
> sub-system, so the home-brew ones have become obsolete.
>
> Signed-off-by: Lee Jones <[email protected]>
Tentatively applied, also missing Vinod's ACK on this, but it seems
it was implicitly ACKed in the discussion on patch 31.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> The aim is to make the code that little more readable.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied with Vinod's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> When a DMA client requests and configures a DMA channel, it requests
> data_width in Bytes. The DMA40 driver then swiftly converts it over to
> the necessary register bit value. Unfortunately, for any subsequent
> calculations we have to shift '1' by the bit pattern (1 << data_width)
> times to make any sense of it.
>
> This patch flips the semantics on its head and only converts the value
> to its respective register bit pattern when writing to registers. This
> way we can use the true data_width (in Bytes) value.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied with what I interpret as Vinod's ACK
("okay..." statement on last reply.)
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> Unsure of the author's intentions, rather than just removing the nop,
> we're replacing it with a comment containing the possible intention
> of the statement OR:ing with 0.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Tentatively applied. Missing Vinod's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
> At this moment in time the memcpy channels which can be used by the D40
> are fixed, as each supported platform in Mainline uses the same ones.
> However, platforms do exist which don't follow this convention, so
> these will need to be tailored. Fortunately, these platforms will be DT
> only, so this change has very little impact on platform data.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied with Vinod's ACK.
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:52 AM, Lee Jones <[email protected]> wrote:
> The DMA platform data is now empty due to some recent refactoring,
> so there is no longer a requirement to pass it though.
>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Applied to dma40 branch, hm now I may get a conflict with all
the AUXDATA changes in the devicetree branch. Oh well, I'll
figure it out...
Yours,
Linus Walleij
On Wed, May 15, 2013 at 11:52 AM, Lee Jones <[email protected]> wrote:
> Some platforms have channels which are not available for normal use.
> This information is currently passed though platform data in internal
> BSP kernels. Once those platforms land, they'll need to configure them
> appropriately, so we may as well add the infrastructure.
>
> Cc: Vinod Koul <[email protected]>
> Cc: Dan Williams <[email protected]>
> Cc: Per Forlin <[email protected]>
> Cc: Rabin Vincent <[email protected]>
> Acked-by: Arnd Bergmann <[email protected]>
> Signed-off-by: Lee Jones <[email protected]>
Patch applied with Vinod's ACK.
Yours,
Linus Walleij
On Thu, May 30, 2013 at 11:04:23AM +0200, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>
> > Unsure of the author's intentions, rather than just removing the nop,
> > we're replacing it with a comment containing the possible intention
> > of the statement OR:ing with 0.
> >
> > Cc: Vinod Koul <[email protected]>
> > Cc: Dan Williams <[email protected]>
> > Cc: Per Forlin <[email protected]>
> > Cc: Rabin Vincent <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
>
> Tentatively applied. Missing Vinod's ACK.
Acked-by: Vinod Koul <[email protected]>
--
~Vinod
HI
On Thu, May 30, 2013 at 09:12:11AM +0100, Lee Jones wrote:
> On Thu, 30 May 2013, Linus Walleij wrote:
>
> > On Wed, May 29, 2013 at 7:57 PM, Felipe Balbi <[email protected]> wrote:
> > > On Wed, May 15, 2013 at 10:51:43AM +0100, Lee Jones wrote:
> > >> For all ux500 based platforms the maximum number of end-points are used.
> > >> Move this knowledge into the driver so we can relinquish the burden from
> > >> platform data. This also removes quite a bit of complexity from the driver
> > >> and will aid us when we come to enable the driver for Device Tree.
> > >>
> > >> Cc: Felipe Balbi <[email protected]>
> > >> Cc: [email protected]
> > >> Acked-by: Linus Walleij <[email protected]>
> > >> Acked-by: Fabio Baltieri <[email protected]>
> > >> Signed-off-by: Lee Jones <[email protected]>
> > >
> > > for drivers/usb/musb
> > >
> > > Acked-by: Felipe Balbi <[email protected]>
> >
> > Is that only for this patch 20/39 or also 21, 22 & 23?
> >
> > Poke us if we should re-send them...
>
> I read this as all patches in the series "for drivers/usb/musb".
right :-) Should've sent on patch 0/39, my bad.
cheers
--
balbi
On Wed, 15 May 2013, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>
> > It was required to pass DMA channel configuration information to the
> > MMC driver before the new DMA API was in place. Now that it is, and
> > is fully compatible with Device Tree we can stop doing that.
> >
> > Reviewed-by: Linus Walleij <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
>
> So since the use of dma_request_slave_channel() is not upstream,
> I guess this will break DMA use (i.e slow down transfers!) on all
> device tree boots?
>
> I'd be happy to apply it once the MMCI patch is in linux-next
> indicating there may just be a window in the merge period
> where it falls back to IRQ mode, but I don't want to disable
> DMA on DT boots for an entire kernel cycle just like that.
>
> Not applied as of yet.
I believe it's now okay to apply this.
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Wed, 15 May 2013, Linus Walleij wrote:
> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>
> > Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
> > should be possible to remove them from the auxdata structure. However,
> > after doing so the drivers fail. Common clk is still reliant on the
> > dev_name() call to do device name matching, which will fail due to the
> > fact that Device Tree naming differs somewhat do the more traditional
> > conventions.
> >
> > Reviewed-by: Linus Walleij <[email protected]>
> > Signed-off-by: Lee Jones <[email protected]>
>
> Cannot be applied due to dependency on 5/39.
I think this can be applied now (if it hasn't already).
--
Lee Jones
Linaro ST-Ericsson Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Mon, Jun 10, 2013 at 11:15 AM, Lee Jones <[email protected]> wrote:
> On Wed, 15 May 2013, Linus Walleij wrote:
>
>> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>>
>> > It was required to pass DMA channel configuration information to the
>> > MMC driver before the new DMA API was in place. Now that it is, and
>> > is fully compatible with Device Tree we can stop doing that.
>> >
>> > Reviewed-by: Linus Walleij <[email protected]>
>> > Signed-off-by: Lee Jones <[email protected]>
>>
>> So since the use of dma_request_slave_channel() is not upstream,
>> I guess this will break DMA use (i.e slow down transfers!) on all
>> device tree boots?
>>
>> I'd be happy to apply it once the MMCI patch is in linux-next
>> indicating there may just be a window in the merge period
>> where it falls back to IRQ mode, but I don't want to disable
>> DMA on DT boots for an entire kernel cycle just like that.
>>
>> Not applied as of yet.
>
> I believe it's now okay to apply this.
Yep, I've rebased and applied it to the ux500-devicetree
branch.
I have some stuff on this branch which is queued up but may
miss v3.11, because I need the 5 outstanding pull requests
to land in ARM SoC so I get a merge base there before I
can send any more stuff.
It's mainly because this stuff isn't any orthogonal, everything
just conflicts in the AUXDATA all the time.
Yours,
Linus Walleij
On Mon, Jun 10, 2013 at 11:17 AM, Lee Jones <[email protected]> wrote:
> On Wed, 15 May 2013, Linus Walleij wrote:
>
>> On Wed, May 15, 2013 at 11:51 AM, Lee Jones <[email protected]> wrote:
>>
>> > Now DMA DT bindings exist and are in use by he MMC and UART drivers, it
>> > should be possible to remove them from the auxdata structure. However,
>> > after doing so the drivers fail. Common clk is still reliant on the
>> > dev_name() call to do device name matching, which will fail due to the
>> > fact that Device Tree naming differs somewhat do the more traditional
>> > conventions.
>> >
>> > Reviewed-by: Linus Walleij <[email protected]>
>> > Signed-off-by: Lee Jones <[email protected]>
>>
>> Cannot be applied due to dependency on 5/39.
>
> I think this can be applied now (if it hasn't already).
I really need a clean mergebase for this to merge ...
This patch requires both the dma40 and devicetree
branches to land in a common place before it can be
applied.
I want the DMA40 branch to be closed down now as I
have sent all pull requests on it, so pls ping me again on
this when we have something in the ARM SoC tree we
can work on.
Yours,
Linus Walleij