Hi,
this simple series improve handling of RAC and CBR address and try to
upstream these simple patch we have in OpenWrt for a while.
The first patch fix a straight kernel panic where some Bootloader might
enable RAC but misconfigure the CBR address. The current logic only
check if RAC is enabled but doesn't verify if the CBR address is usable.
The DMA sync function cause a kernel panic for invalid write. (as CBR is
0 or something like 0xa)
The second is preparation for making the CBR address configurable in DT.
Since this address doesn't change, we can cache it and reference it with
a local variable instead of calling the register to access the value.
The 4th patch make it configurable with 2 DT property, one to actually
set the reg and the other to force set it.
The first property is used when CBR is set to 0. The second property is
to force it if the Bootloader sets it to something wrong.
If the CBR value is not 0 and is not forced with the second property a
WARN is printed and the DT value is ignored.
The 4th patch enable RAC on BMIPS4350.
These has been tested on BCM6358 (HG556a) and BCM6368 (VH4032N) and
reported correct functionality.
Changes v4:
- Fix compilation error with legacy brcm target
- Improve property description in DT commit (give
CBR meaning and drop reference to linux functions)
- Use only __read_mostly as we can't add variable to
multiple data sections
- In patch 4 use local cbr variable instead of global
one.
Changes v3:
- Drop broken-cbr-reg property
- Fix anyOf+const with enum
Changes v2:
- Prefix brcm vendor in the added property
- Drop last patch (cpu switch from DMA sync)
- Validate CBR addr from DT to be outside DRAM
- Reduce indentation in DT CBR check
- Reduce delta and use local variable for CBR where possible
- Fix and improve typo and spelling mistake
- Use 0xf instead of 0xa for BCM6358 RAC enable
Christian Marangi (3):
mips: bmips: rework and cache CBR addr handling
dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
mips: bmips: setup: make CBR address configurable
Daniel González Cabanelas (1):
mips: bmips: enable RAC on BMIPS4350
.../devicetree/bindings/mips/brcm/soc.yaml | 24 ++++++++++++++++
arch/mips/bcm47xx/prom.c | 2 ++
arch/mips/bcm63xx/prom.c | 3 ++
arch/mips/bmips/dma.c | 2 +-
arch/mips/bmips/setup.c | 28 +++++++++++++++++--
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 27 ++++++++++++++++--
7 files changed, 82 insertions(+), 5 deletions(-)
--
2.43.0
Document brcm,bmips-cbr-reg property.
Some SoC suffer from a BUG where CBR(Core Base Register)
address might badly/never inizialized by the Bootloader or
reaching it from co-processor registers if the system
boots from secondary CPU results in invalid address.
The CBR address is always the same on the SoC.
Usage of this property is to give an address also in these broken
configuration/bootloader.
Signed-off-by: Christian Marangi <[email protected]>
---
.../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
index 975945ca2888..6b961b62aff2 100644
--- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
+++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
@@ -55,6 +55,16 @@ properties:
under the "cpus" node.
$ref: /schemas/types.yaml#/definitions/uint32
+ brcm,bmips-cbr-reg:
+ description: Reference address of the CBR.
+ Some SoC suffer from a BUG where CBR(Core Base Register)
+ address might badly/never inizialized by the Bootloader or
+ reaching it from co-processor registers if the system
+ boots from secondary CPU results in invalid address.
+ The CBR address is always the same on the SoC hence it
+ can be provided in DT to handle these broken case.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
patternProperties:
"^cpu@[0-9]$":
type: object
@@ -64,6 +74,20 @@ properties:
required:
- mips-hpt-frequency
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,bcm6358
+ - brcm,bcm6368
+
+then:
+ properties:
+ cpus:
+ required:
+ - brcm,bmips-cbr-reg
+
additionalProperties: true
examples:
--
2.43.0
Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.
This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.
bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with
legacy brcm47xx/brcm63xx and generic BMIPS target.
Signed-off-by: Christian Marangi <[email protected]>
---
arch/mips/bcm47xx/prom.c | 2 ++
arch/mips/bcm63xx/prom.c | 3 +++
arch/mips/bmips/dma.c | 2 +-
arch/mips/bmips/setup.c | 4 +++-
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 6 ++++--
6 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index 99a1ba5394e0..49fe4c535161 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -109,6 +109,8 @@ static __init void prom_init_mem(void)
void __init prom_init(void)
{
+ /* Cache CBR addr before CPU/DMA setup */
+ bmips_cbr_addr = BMIPS_GET_CBR();
prom_init_mem();
setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
}
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index c3a2ea62c5c3..f21dd168171a 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -22,6 +22,9 @@ void __init prom_init(void)
{
u32 reg, mask;
+ /* Cache CBR addr before CPU/DMA setup */
+ bmips_cbr_addr = BMIPS_GET_CBR();
+
bcm63xx_cpu_init();
/* stop any running watchdog */
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
index 3779e7855bd7..2bc9c0d4402f 100644
--- a/arch/mips/bmips/dma.c
+++ b/arch/mips/bmips/dma.c
@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable;
void arch_sync_dma_for_cpu_all(void)
{
- void __iomem *cbr = BMIPS_GET_CBR();
+ void __iomem *cbr = bmips_cbr_addr;
u32 cfg;
if (boot_cpu_type() != CPU_BMIPS3300 &&
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 66a8ba19c287..dba789ec75b3 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -111,7 +111,7 @@ static void bcm6358_quirks(void)
* because the bootloader is not initializing it properly.
*/
bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
- !!BMIPS_GET_CBR();
+ !!bmips_cbr_addr;
}
static void bcm6368_quirks(void)
@@ -144,6 +144,8 @@ static void __init bmips_init_cfe(void)
void __init prom_init(void)
{
+ /* Cache CBR addr before CPU/DMA setup */
+ bmips_cbr_addr = BMIPS_GET_CBR();
bmips_init_cfe();
bmips_cpu_setup();
register_bmips_smp_ops();
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 581a6a3c66e4..3a1cdfddb987 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[];
extern char bmips_smp_int_vec[];
extern char bmips_smp_int_vec_end[];
+extern void __iomem *bmips_cbr_addr;
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
extern cpumask_t bmips_booted_mask;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index b3dbf9ecb0d6..555a5b449ca8 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -46,6 +46,8 @@ int bmips_smp_enabled = 1;
int bmips_cpu_offset;
cpumask_t bmips_booted_mask;
unsigned long bmips_tp1_irqs = IE_IRQ1;
+/* CBR addr doesn't change and we can cache it */
+void __iomem *bmips_cbr_addr __read_mostly;
#define RESET_FROM_KSEG0 0x80080800
#define RESET_FROM_KSEG1 0xa0080800
@@ -518,7 +520,7 @@ static void bmips_set_reset_vec(int cpu, u32 val)
info.val = val;
bmips_set_reset_vec_remote(&info);
} else {
- void __iomem *cbr = BMIPS_GET_CBR();
+ void __iomem *cbr = bmips_cbr_addr;
if (cpu == 0)
__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
@@ -591,7 +593,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void)
void bmips_cpu_setup(void)
{
- void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
+ void __iomem __maybe_unused *cbr = bmips_cbr_addr;
u32 __maybe_unused cfg;
switch (current_cpu_type()) {
--
2.43.0
Add support to provide CBR address from DT to handle broken
SoC/Bootloader that doesn't correctly init it. This permits to use the
RAC flush even in these condition.
To provide a CBR address from DT, the property "brcm,bmips-cbr-reg"
needs to be set in the "cpus" node. On DT init, this property presence
will be checked and will set the bmips_cbr_addr value accordingly. Also
bmips_rac_flush_disable will be set to false as RAC flush can be
correctly supported.
The CBR address from DT will overwrite the cached one and the
one set in the CBR register will be ignored.
Also the DT CBR address is validated on being outside DRAM window.
Signed-off-by: Christian Marangi <[email protected]>
---
arch/mips/bmips/setup.c | 24 +++++++++++++++++++++++-
arch/mips/kernel/smp-bmips.c | 6 +++++-
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index dba789ec75b3..c7d83f0c7b05 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -205,13 +205,35 @@ void __init plat_mem_setup(void)
void __init device_tree_init(void)
{
struct device_node *np;
+ u32 addr;
unflatten_and_copy_device_tree();
/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
np = of_find_node_by_name(NULL, "cpus");
- if (np && of_get_available_child_count(np) <= 1)
+ if (!np)
+ return;
+
+ if (of_get_available_child_count(np) <= 1)
bmips_smp_enabled = 0;
+
+ /* Check if DT provide a CBR address */
+ if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))
+ goto exit;
+
+ /* Make sure CBR address is outside DRAM window */
+ if (addr >= (u32)memblock_start_of_DRAM() &&
+ addr < (u32)memblock_end_of_DRAM()) {
+ WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",
+ addr);
+ goto exit;
+ }
+
+ bmips_cbr_addr = (void __iomem *)addr;
+ /* Since CBR is provided by DT, enable RAC flush */
+ bmips_rac_flush_disable = false;
+
+exit:
of_node_put(np);
}
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 555a5b449ca8..20e2fb10022d 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -46,7 +46,11 @@ int bmips_smp_enabled = 1;
int bmips_cpu_offset;
cpumask_t bmips_booted_mask;
unsigned long bmips_tp1_irqs = IE_IRQ1;
-/* CBR addr doesn't change and we can cache it */
+/*
+ * CBR addr doesn't change and we can cache it.
+ * For broken SoC/Bootloader CBR addr might also be provided via DT
+ * with "brcm,bmips-cbr-reg" in the "cpus" node.
+ */
void __iomem *bmips_cbr_addr __read_mostly;
#define RESET_FROM_KSEG0 0x80080800
--
2.43.0
From: Daniel González Cabanelas <[email protected]>
The data RAC is left disabled by the bootloader in some SoCs, at least in
the core it boots from.
Enabling this feature increases the performance up to +30% depending on the
task.
Signed-off-by: Daniel González Cabanelas <[email protected]>
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
[ rework code and reduce code duplication ]
Signed-off-by: Christian Marangi <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
arch/mips/kernel/smp-bmips.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 20e2fb10022d..52324738cbb3 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -626,6 +626,23 @@ void bmips_cpu_setup(void)
__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
break;
+ case CPU_BMIPS4350:
+ u32 rac_addr = BMIPS_RAC_CONFIG_1;
+
+ if (!(read_c0_brcm_cmt_local() & (1 << 31)))
+ rac_addr = BMIPS_RAC_CONFIG;
+
+ /* Enable data RAC */
+ cfg = __raw_readl(cbr + rac_addr);
+ __raw_writel(cfg | 0xf, cbr + rac_addr);
+ __raw_readl(cbr + rac_addr);
+
+ /* Flush stale data out of the readahead cache */
+ cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
+ __raw_readl(cbr + BMIPS_RAC_CONFIG);
+ break;
+
case CPU_BMIPS4380:
/* CBG workaround for early BMIPS4380 CPUs */
switch (read_c0_prid()) {
--
2.43.0
On 5/9/24 13:47, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
>
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
>
> bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with
> legacy brcm47xx/brcm63xx and generic BMIPS target.
>
> Signed-off-by: Christian Marangi <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On 5/9/24 13:47, Christian Marangi wrote:
> Add support to provide CBR address from DT to handle broken
> SoC/Bootloader that doesn't correctly init it. This permits to use the
> RAC flush even in these condition.
>
> To provide a CBR address from DT, the property "brcm,bmips-cbr-reg"
> needs to be set in the "cpus" node. On DT init, this property presence
> will be checked and will set the bmips_cbr_addr value accordingly. Also
> bmips_rac_flush_disable will be set to false as RAC flush can be
> correctly supported.
>
> The CBR address from DT will overwrite the cached one and the
> one set in the CBR register will be ignored.
>
> Also the DT CBR address is validated on being outside DRAM window.
>
> Signed-off-by: Christian Marangi <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On Thu, May 09, 2024 at 10:47:46PM +0200, Christian Marangi wrote:
> Document brcm,bmips-cbr-reg property.
>
> Some SoC suffer from a BUG where CBR(Core Base Register)
> address might badly/never inizialized by the Bootloader or
> reaching it from co-processor registers if the system
> boots from secondary CPU results in invalid address.
>
> The CBR address is always the same on the SoC.
>
> Usage of this property is to give an address also in these broken
> configuration/bootloader.
>
> Signed-off-by: Christian Marangi <[email protected]>
> ---
> .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> index 975945ca2888..6b961b62aff2 100644
> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> @@ -55,6 +55,16 @@ properties:
> under the "cpus" node.
> $ref: /schemas/types.yaml#/definitions/uint32
>
> + brcm,bmips-cbr-reg:
> + description: Reference address of the CBR.
> + Some SoC suffer from a BUG where CBR(Core Base Register)
> + address might badly/never inizialized by the Bootloader or
"be badly or never initialized"
> + reaching it from co-processor registers if the system
"reading"?
Otherwise,
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
> + boots from secondary CPU results in invalid address.
> + The CBR address is always the same on the SoC hence it
> + can be provided in DT to handle these broken case.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> patternProperties:
> "^cpu@[0-9]$":
> type: object
> @@ -64,6 +74,20 @@ properties:
> required:
> - mips-hpt-frequency
>
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - brcm,bcm6358
> + - brcm,bcm6368
> +
> +then:
> + properties:
> + cpus:
> + required:
> + - brcm,bmips-cbr-reg
> +
> additionalProperties: true
>
> examples:
> --
> 2.43.0
>