This patch series adds support for PWM for DRA7. The IP is same as that
present in AM33XX and AM437XX.
However, before doing so remove unnecessary hwmod entries for eCAP, ePWM
and eQEP.
This series is almost identical to v4. Only difference is the addition of
eCAP DT nodes in the dra7.dtsi file.
This series was tested on AM335x GP, AM437x GP and X15 + LCD screen for
PWM based backlight.
This series was also verified to be backwards compatible with old dtbs.
This series depends on the below patch series for PWM bindings cleanup:
https://patchwork.ozlabs.org/patch/593171/
https://patchwork.ozlabs.org/patch/593168/
https://patchwork.ozlabs.org/patch/593165/
https://patchwork.ozlabs.org/patch/593166/
https://patchwork.ozlabs.org/patch/593169/
V3 series:
https://patchwork.ozlabs.org/patch/588432/
https://patchwork.ozlabs.org/patch/588434/
https://patchwork.ozlabs.org/patch/588433/
https://patchwork.ozlabs.org/patch/588429/
https://patchwork.ozlabs.org/patch/588431/
Franklin S Cooper Jr (3):
pwms: pwm-ti*: Get the clock from the PWMSS (parent)
ARM: dts: am437x/am33xx: Remove eCAP and ePWM hwmod properties
ARM: AM335x/AM437x: hwmod: Remove eQEP, ePWM and eCAP hwmod entries
Vignesh R (3):
ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS
ARM: dts: DRA7: Add TBCLK for PWMSS
ARM: dts: DRA7: Add dt nodes for PWMSS
.../devicetree/bindings/pwm/pwm-tiecap.txt | 10 ++-
.../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 16 ++++-
.../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++-
arch/arm/boot/dts/am33xx.dtsi | 12 ++--
arch/arm/boot/dts/am4372.dtsi | 21 +++---
arch/arm/boot/dts/dra7.dtsi | 84 ++++++++++++++++++++++
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 +++++++
.../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 18 -----
.../omap_hwmod_33xx_43xx_interconnect_data.c | 64 -----------------
.../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 84 ----------------------
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 9 ---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 54 --------------
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 83 +++++++++++++++++++++
drivers/pwm/pwm-tiecap.c | 2 +-
drivers/pwm/pwm-tiehrpwm.c | 2 +-
15 files changed, 247 insertions(+), 251 deletions(-)
--
2.7.0
The eCAP and ePWM doesn't have their own separate clocks. They simply
utilize the clock provided directly by the PWMSS. Therefore, they simply
need to grab a reference to their parent's clock.
Signed-off-by: Franklin S Cooper Jr <[email protected]>
---
drivers/pwm/pwm-tiecap.c | 2 +-
drivers/pwm/pwm-tiehrpwm.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
index 616af76..9418159 100644
--- a/drivers/pwm/pwm-tiecap.c
+++ b/drivers/pwm/pwm-tiecap.c
@@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
if (!pc)
return -ENOMEM;
- clk = devm_clk_get(&pdev->dev, "fck");
+ clk = devm_clk_get(pdev->dev.parent, "fck");
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "failed to get clock\n");
return PTR_ERR(clk);
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 6a41e66..09dc1bc 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -443,7 +443,7 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
if (!pc)
return -ENOMEM;
- clk = devm_clk_get(&pdev->dev, "fck");
+ clk = devm_clk_get(pdev->dev.parent, "fck");
if (IS_ERR(clk)) {
dev_err(&pdev->dev, "failed to get clock\n");
return PTR_ERR(clk);
--
2.7.0
From: Vignesh R <[email protected]>
Add hwmod entries for the PWMSS on DRA7.
Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
Signed-off-by: Vignesh R <[email protected]>
[[email protected]: Do not add eQEP, ePWM and eCAP hwmod entries]
Signed-off-by: Franklin S Cooper Jr <[email protected]>
---
Version 5 changes:
None
Version 4 changes:
Do not include eQEP, ePWM and eCAP hwmod entries.
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 83 +++++++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 848356e..f8f5aa2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -383,6 +383,65 @@ static struct omap_hwmod dra7xx_dcan2_hwmod = {
},
};
+/* pwmss */
+static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
+ .name = "epwmss",
+ .sysc = &dra7xx_epwmss_sysc,
+};
+
+/* epwmss0 */
+struct omap_hwmod dra7xx_epwmss0_hwmod = {
+ .name = "epwmss0",
+ .class = &dra7xx_epwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* epwmss1 */
+struct omap_hwmod dra7xx_epwmss1_hwmod = {
+ .name = "epwmss1",
+ .class = &dra7xx_epwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* epwmss2 */
+struct omap_hwmod dra7xx_epwmss2_hwmod = {
+ .name = "epwmss2",
+ .class = &dra7xx_epwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
+ },
+ },
+};
+
/*
* 'dma' class
*
@@ -2676,6 +2735,27 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_epwmss0_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_epwmss1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU,
+};
+
+struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_epwmss2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU,
+};
+
/* l4_per1 -> gpio7 */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
.master = &dra7xx_l4_per1_hwmod,
@@ -3452,6 +3532,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__vcp2,
&dra7xx_l4_per2__vcp2,
&dra7xx_l4_wkup__wd_timer2,
+ &dra7xx_l4_per2__epwmss0,
+ &dra7xx_l4_per2__epwmss1,
+ &dra7xx_l4_per2__epwmss2,
NULL,
};
--
2.7.0
ECAP and ePWM do not have OCP integration registers, have L3/L4 ports, etc.
Therefore, they shouldn't be using hwmod at all. Remove their hwmod
properties.
For ePWM add the tbclk to the node rather than depending on hwmod to do so.
Signed-off-by: Franklin S Cooper Jr <[email protected]>
---
arch/arm/boot/dts/am33xx.dtsi | 12 ++++++------
arch/arm/boot/dts/am4372.dtsi | 21 ++++++++++++---------
2 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 82c0976..1dd6c78 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -682,7 +682,6 @@
reg = <0x48300100 0x80>;
interrupts = <31>;
interrupt-names = "ecap0";
- ti,hwmods = "ecap0";
status = "disabled";
};
@@ -690,7 +689,8 @@
compatible = "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
- ti,hwmods = "ehrpwm0";
+ clocks = <&ehrpwm0_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
@@ -710,7 +710,6 @@
reg = <0x48302100 0x80>;
interrupts = <47>;
interrupt-names = "ecap1";
- ti,hwmods = "ecap1";
status = "disabled";
};
@@ -718,7 +717,8 @@
compatible = "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
- ti,hwmods = "ehrpwm1";
+ clocks = <&ehrpwm1_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
@@ -738,7 +738,6 @@
reg = <0x48304100 0x80>;
interrupts = <61>;
interrupt-names = "ecap2";
- ti,hwmods = "ecap2";
status = "disabled";
};
@@ -746,7 +745,8 @@
compatible = "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
- ti,hwmods = "ehrpwm2";
+ clocks = <&ehrpwm2_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 33f417c..685c8db 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -675,7 +675,6 @@
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
- ti,hwmods = "ecap0";
status = "disabled";
};
@@ -683,7 +682,8 @@
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
- ti,hwmods = "ehrpwm0";
+ clocks = <&ehrpwm0_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
@@ -701,7 +701,6 @@
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
- ti,hwmods = "ecap1";
status = "disabled";
};
@@ -709,7 +708,8 @@
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
- ti,hwmods = "ehrpwm1";
+ clocks = <&ehrpwm1_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
@@ -727,7 +727,6 @@
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
- ti,hwmods = "ecap2";
status = "disabled";
};
@@ -735,7 +734,8 @@
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
- ti,hwmods = "ehrpwm2";
+ clocks = <&ehrpwm2_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
@@ -753,7 +753,8 @@
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48306200 0x80>;
- ti,hwmods = "ehrpwm3";
+ clocks = <&ehrpwm3_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
@@ -771,7 +772,8 @@
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48308200 0x80>;
- ti,hwmods = "ehrpwm4";
+ clocks = <&ehrpwm4_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
@@ -789,7 +791,8 @@
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x4830a200 0x80>;
- ti,hwmods = "ehrpwm5";
+ clocks = <&ehrpwm5_tbclk>;
+ clock-names = "tbclk";
status = "disabled";
};
};
--
2.7.0
Devices that utilize the OCP registers and/or PRCM registers and
register bit fields should be modelled using hwmod. Since eQEP, ePWM and
eCAP don't fall under this category, remove their hwmod entries.
Instead these clocks simply use the clock that is pass through by its
parent PWMSS. Therefore, PWMSS handles the clock for itself and its
subdevices.
Signed-off-by: Franklin S Cooper Jr <[email protected]>
---
.../devicetree/bindings/pwm/pwm-tiecap.txt | 1 -
.../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 7 +-
.../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 18 -----
.../omap_hwmod_33xx_43xx_interconnect_data.c | 64 -----------------
.../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 84 ----------------------
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 9 ---
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 54 --------------
7 files changed, 4 insertions(+), 233 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
index fb81179..72a8f26 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
@@ -19,7 +19,6 @@ ecap0: ecap@0 { /* ECAP on am33xx */
compatible = "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
- ti,hwmods = "ecap0";
};
ecap0: ecap@0 { /* ECAP on da850 */
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
index 20211ed..345d3f6 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
@@ -10,8 +10,8 @@ Required properties:
- reg: physical base address and size of the registers map.
Optional properties:
-- ti,hwmods: Name of the hwmod associated to the EHRPWM:
- "ehrpwm<x>", <x> being the 0-based instance number from the HW spec
+- clocks: Handle to the PWM's time-base clock.
+- clock-names: Must be set to "tbclk".
Example:
@@ -19,7 +19,8 @@ ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
compatible = "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x100>;
- ti,hwmods = "ehrpwm0";
+ clocks = <&ehrpwm0_tbclk>;
+ clock-names = "tbclk";
};
ehrpwm0: pwm@01f00000 { /* EHRPWM on da850 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
index 7f73796..d3e61d1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -36,17 +36,8 @@ extern struct omap_hwmod_ocp_if am33xx_l4_per__gpio3;
extern struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
-extern struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0;
-extern struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0;
-extern struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
-extern struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1;
-extern struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1;
-extern struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
-extern struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2;
-extern struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2;
-extern struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c2;
extern struct omap_hwmod_ocp_if am33xx_l4_per__i2c3;
@@ -98,17 +89,8 @@ extern struct omap_hwmod am33xx_dcan0_hwmod;
extern struct omap_hwmod am33xx_dcan1_hwmod;
extern struct omap_hwmod am33xx_elm_hwmod;
extern struct omap_hwmod am33xx_epwmss0_hwmod;
-extern struct omap_hwmod am33xx_ecap0_hwmod;
-extern struct omap_hwmod am33xx_eqep0_hwmod;
-extern struct omap_hwmod am33xx_ehrpwm0_hwmod;
extern struct omap_hwmod am33xx_epwmss1_hwmod;
-extern struct omap_hwmod am33xx_ecap1_hwmod;
-extern struct omap_hwmod am33xx_eqep1_hwmod;
-extern struct omap_hwmod am33xx_ehrpwm1_hwmod;
extern struct omap_hwmod am33xx_epwmss2_hwmod;
-extern struct omap_hwmod am33xx_ecap2_hwmod;
-extern struct omap_hwmod am33xx_eqep2_hwmod;
-extern struct omap_hwmod am33xx_ehrpwm2_hwmod;
extern struct omap_hwmod am33xx_gpio1_hwmod;
extern struct omap_hwmod am33xx_gpio2_hwmod;
extern struct omap_hwmod am33xx_gpio3_hwmod;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
index 1c210cb..10dff2f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
@@ -176,28 +176,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
.user = OCP_USER_MPU,
};
-struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
- .master = &am33xx_epwmss0_hwmod,
- .slave = &am33xx_ecap0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
- .master = &am33xx_epwmss0_hwmod,
- .slave = &am33xx_eqep0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
- .master = &am33xx_epwmss0_hwmod,
- .slave = &am33xx_ehrpwm0_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-
static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
{
.pa_start = 0x48302000,
@@ -215,27 +193,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
.user = OCP_USER_MPU,
};
-struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
- .master = &am33xx_epwmss1_hwmod,
- .slave = &am33xx_ecap1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
- .master = &am33xx_epwmss1_hwmod,
- .slave = &am33xx_eqep1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
- .master = &am33xx_epwmss1_hwmod,
- .slave = &am33xx_ehrpwm1_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
{
.pa_start = 0x48304000,
@@ -253,27 +210,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
.user = OCP_USER_MPU,
};
-struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
- .master = &am33xx_epwmss2_hwmod,
- .slave = &am33xx_ecap2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
- .master = &am33xx_epwmss2_hwmod,
- .slave = &am33xx_eqep2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
-struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
- .master = &am33xx_epwmss2_hwmod,
- .slave = &am33xx_ehrpwm2_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
/* l3s cfg -> gpmc */
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 907a452b..4b18ff3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -449,18 +449,6 @@ struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
.sysc = &am33xx_epwmss_sysc,
};
-static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
- .name = "ecap",
-};
-
-static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
- .name = "eqep",
-};
-
-struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
- .name = "ehrpwm",
-};
-
/* epwmss0 */
struct omap_hwmod am33xx_epwmss0_hwmod = {
.name = "epwmss0",
@@ -474,30 +462,6 @@ struct omap_hwmod am33xx_epwmss0_hwmod = {
},
};
-/* ecap0 */
-struct omap_hwmod am33xx_ecap0_hwmod = {
- .name = "ecap0",
- .class = &am33xx_ecap_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
-/* eqep0 */
-struct omap_hwmod am33xx_eqep0_hwmod = {
- .name = "eqep0",
- .class = &am33xx_eqep_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
-/* ehrpwm0 */
-struct omap_hwmod am33xx_ehrpwm0_hwmod = {
- .name = "ehrpwm0",
- .class = &am33xx_ehrpwm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
/* epwmss1 */
struct omap_hwmod am33xx_epwmss1_hwmod = {
.name = "epwmss1",
@@ -511,30 +475,6 @@ struct omap_hwmod am33xx_epwmss1_hwmod = {
},
};
-/* ecap1 */
-struct omap_hwmod am33xx_ecap1_hwmod = {
- .name = "ecap1",
- .class = &am33xx_ecap_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
-/* eqep1 */
-struct omap_hwmod am33xx_eqep1_hwmod = {
- .name = "eqep1",
- .class = &am33xx_eqep_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
-/* ehrpwm1 */
-struct omap_hwmod am33xx_ehrpwm1_hwmod = {
- .name = "ehrpwm1",
- .class = &am33xx_ehrpwm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
/* epwmss2 */
struct omap_hwmod am33xx_epwmss2_hwmod = {
.name = "epwmss2",
@@ -548,30 +488,6 @@ struct omap_hwmod am33xx_epwmss2_hwmod = {
},
};
-/* ecap2 */
-struct omap_hwmod am33xx_ecap2_hwmod = {
- .name = "ecap2",
- .class = &am33xx_ecap_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
-/* eqep2 */
-struct omap_hwmod am33xx_eqep2_hwmod = {
- .name = "eqep2",
- .class = &am33xx_eqep_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
-/* ehrpwm2 */
-struct omap_hwmod am33xx_ehrpwm2_hwmod = {
- .name = "ehrpwm2",
- .class = &am33xx_ehrpwm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
/*
* 'gpio' class: for gpio 0,1,2,3
*/
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index cc0791d..e1c2025 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -593,17 +593,8 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_ls__spinlock,
&am33xx_l4_ls__elm,
&am33xx_l4_ls__epwmss0,
- &am33xx_epwmss0__ecap0,
- &am33xx_epwmss0__eqep0,
- &am33xx_epwmss0__ehrpwm0,
&am33xx_l4_ls__epwmss1,
- &am33xx_epwmss1__ecap1,
- &am33xx_epwmss1__eqep1,
- &am33xx_epwmss1__ehrpwm1,
&am33xx_l4_ls__epwmss2,
- &am33xx_epwmss2__ecap2,
- &am33xx_epwmss2__eqep2,
- &am33xx_epwmss2__ehrpwm2,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__lcdc,
&am33xx_l4_ls__mcspi0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
index e97a894..2feb1f9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -202,13 +202,6 @@ static struct omap_hwmod am43xx_epwmss3_hwmod = {
},
};
-static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
- .name = "ehrpwm3",
- .class = &am33xx_ehrpwm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
static struct omap_hwmod am43xx_epwmss4_hwmod = {
.name = "epwmss4",
.class = &am33xx_epwmss_hwmod_class,
@@ -222,13 +215,6 @@ static struct omap_hwmod am43xx_epwmss4_hwmod = {
},
};
-static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
- .name = "ehrpwm4",
- .class = &am33xx_ehrpwm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
static struct omap_hwmod am43xx_epwmss5_hwmod = {
.name = "epwmss5",
.class = &am33xx_epwmss_hwmod_class,
@@ -242,13 +228,6 @@ static struct omap_hwmod am43xx_epwmss5_hwmod = {
},
};
-static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
- .name = "ehrpwm5",
- .class = &am33xx_ehrpwm_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .main_clk = "l4ls_gclk",
-};
-
static struct omap_hwmod am43xx_spi2_hwmod = {
.name = "spi2",
.class = &am33xx_spi_hwmod_class,
@@ -744,13 +723,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
- .master = &am43xx_epwmss3_hwmod,
- .slave = &am43xx_ehrpwm3_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_epwmss4_hwmod,
@@ -758,13 +730,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
- .master = &am43xx_epwmss4_hwmod,
- .slave = &am43xx_ehrpwm4_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_epwmss5_hwmod,
@@ -772,13 +737,6 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
- .master = &am43xx_epwmss5_hwmod,
- .slave = &am43xx_ehrpwm5_hwmod,
- .clk = "l4ls_gclk",
- .user = OCP_USER_MPU,
-};
-
static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am43xx_spi2_hwmod,
@@ -919,11 +877,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am43xx_l4_ls__timer10,
&am43xx_l4_ls__timer11,
&am43xx_l4_ls__epwmss3,
- &am43xx_epwmss3__ehrpwm3,
&am43xx_l4_ls__epwmss4,
- &am43xx_epwmss4__ehrpwm4,
&am43xx_l4_ls__epwmss5,
- &am43xx_epwmss5__ehrpwm5,
&am43xx_l4_ls__mcspi2,
&am43xx_l4_ls__mcspi3,
&am43xx_l4_ls__mcspi4,
@@ -982,17 +937,8 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_ls__spinlock,
&am33xx_l4_ls__elm,
&am33xx_l4_ls__epwmss0,
- &am33xx_epwmss0__ecap0,
- &am33xx_epwmss0__eqep0,
- &am33xx_epwmss0__ehrpwm0,
&am33xx_l4_ls__epwmss1,
- &am33xx_epwmss1__ecap1,
- &am33xx_epwmss1__eqep1,
- &am33xx_epwmss1__ehrpwm1,
&am33xx_l4_ls__epwmss2,
- &am33xx_epwmss2__ecap2,
- &am33xx_epwmss2__eqep2,
- &am33xx_epwmss2__ehrpwm2,
&am33xx_l3_s__gpmc,
&am33xx_l4_ls__mcspi0,
&am33xx_l4_ls__mcspi1,
--
2.7.0
From: Vignesh R <[email protected]>
tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
clock to control ehrpwm tbclk.
The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but
ehrpwm functional clock derived from the gateable interface and
functional clock of PWMSS(l4_root_clk_div).
Refer AM57x TRM SPRUHZ6E[1], Janurary 2016, Table 29-4 and
Section 29.2.2.1, Table 29-19 and the NOTE at the end of the table.
[1] http://www.ti.com/lit/ug/spruhz6e/spruhz6e.pdf
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Franklin S Cooper Jr <[email protected]>
---
Version 5 changes:
None
Version v4 changes:
Updated link to latest documentation
arch/arm/boot/dts/dra7xx-clocks.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bede..d0bae06 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -2146,4 +2146,28 @@
ti,bit-shift = <0>;
reg = <0x558>;
};
+
+ ehrpwm0_tbclk: ehrpwm0_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <20>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm1_tbclk: ehrpwm1_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <21>;
+ reg = <0x0558>;
+ };
+
+ ehrpwm2_tbclk: ehrpwm2_tbclk {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&l4_root_clk_div>;
+ ti,bit-shift = <22>;
+ reg = <0x0558>;
+ };
};
--
2.7.0
From: Vignesh R <[email protected]>
Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <[email protected]>
[[email protected]: Add eCAP and use updated bindings for PWMSS and ePWM]
Signed-off-by: Franklin S Cooper Jr <[email protected]>
---
Version 5 changes:
Add DT node for eCAP and update eCAP binding documentation
Version 4 changes:
Updated link to the latest documentation
.../devicetree/bindings/pwm/pwm-tiecap.txt | 9 +++
.../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 +++
.../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++-
arch/arm/boot/dts/dra7.dtsi | 84 ++++++++++++++++++++++
4 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
index 72a8f26..fb9ea89 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Must be "ti,<soc>-ecap".
for am33xx - compatible = "ti,am33xx-ecap";
for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap";
+ for dra7xx - compatible = "ti,dra7xx-ecap", "ti,am33xx-ecap";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The PWM channel index ranges from 0 to 4. The only third
cell flag supported by this binding is PWM_POLARITY_INVERTED.
@@ -26,3 +27,11 @@ ecap0: ecap@0 { /* ECAP on da850 */
#pwm-cells = <3>;
reg = <0x306000 0x80>;
};
+
+ecap0: ecap@4843e100 {
+ compatible = "ti,dra7xx-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x4843e100 0x80>;
+};
+
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
index 345d3f6..5965b9d 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
@@ -4,6 +4,7 @@ Required properties:
- compatible: Must be "ti,<soc>-ehrpwm".
for am33xx - compatible = "ti,am33xx-ehrpwm";
for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+ for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
@@ -28,3 +29,11 @@ ehrpwm0: pwm@01f00000 { /* EHRPWM on da850 */
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
};
+
+ehrpwm0: pwm@4843e200 { /* EHRPWM on dra7xx */
+ compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ clocks = <&ehrpwm0_tbclk>;
+ clock-names = "tbclk";
+};
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
index 672fa71..f137d0b 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
@@ -1,7 +1,9 @@
TI SOC based PWM Subsystem
Required properties:
-- compatible: Must be "ti,am33xx-pwmss";
+- compatible: Must be "ti,<soc>-pwmss".
+ for am33xx - compatible = "ti,am33xx-pwmss"
+ for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"
- reg: physical base address and size of the registers map.
- address-cells: Specify the number of u32 entries needed in child nodes.
Should set to 1.
@@ -25,3 +27,14 @@ pwmss0: pwmss@48300000 {
/* child nodes go here */
};
+
+epwmss0: epwmss@4843e000 { /* On DRA7xx */
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* child nodes go here */
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c4d9175..db62f55 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1597,6 +1597,90 @@
clock-names = "fck", "sys_clk";
};
};
+
+ epwmss0: epwmss@4843e000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x4843e000 0x30>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm0: pwm@4843e200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x4843e200 0x80>;
+ clocks = <&ehrpwm0_tbclk>;
+ clock-names = "tbclk";
+ status = "disabled";
+ };
+
+ ecap0: ecap@4843e100 {
+ compatible = "ti,dra7xx-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x4843e100 0x80>;
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss@48440000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48440000 0x30>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm1: pwm@48440200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48440200 0x80>;
+ clocks = <&ehrpwm1_tbclk>;
+ clock-names = "tbclk";
+ status = "disabled";
+ };
+
+ ecap1: ecap@48440100 {
+ compatible = "ti,dra7xx-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48440100 0x80>;
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss@48442000 {
+ compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
+ reg = <0x48442000 0x30>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges;
+
+ ehrpwm2: pwm@48442200 {
+ compatible = "ti,dra7xx-ehrpwm",
+ "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48442200 0x80>;
+ clocks = <&ehrpwm2_tbclk>;
+ clock-names = "tbclk";
+ status = "disabled";
+ };
+
+ ecap2: ecap@48442100 {
+ compatible = "ti,dra7xx-ecap",
+ "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48442100 0x80>;
+ status = "disabled";
+ };
+ };
};
thermal_zones: thermal-zones {
--
2.7.0
On Mon, 7 Mar 2016, Franklin S Cooper Jr wrote:
> From: Vignesh R <[email protected]>
>
> Add hwmod entries for the PWMSS on DRA7.
>
> Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
> equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
>
> Signed-off-by: Vignesh R <[email protected]>
> [[email protected]: Do not add eQEP, ePWM and eCAP hwmod entries]
> Signed-off-by: Franklin S Cooper Jr <[email protected]>
Thanks, queued for v4.7.
- Paul
Hi Franklin
On Mon, 7 Mar 2016, Franklin S Cooper Jr wrote:
> This patch series adds support for PWM for DRA7. The IP is same as that
> present in AM33XX and AM437XX.
>
> However, before doing so remove unnecessary hwmod entries for eCAP, ePWM
> and eQEP.
>
> This series is almost identical to v4. Only difference is the addition of
> eCAP DT nodes in the dra7.dtsi file.
>
> This series was tested on AM335x GP, AM437x GP and X15 + LCD screen for
> PWM based backlight.
>
> This series was also verified to be backwards compatible with old dtbs.
Looking at these to see what I can pick for v4.7, I'm curious about the
dependencies. Can I take patches 2 and 3 before 1 is merged, or does 1
need to be merged first?
- Paul
On 03/08/2016 12:55 AM, Paul Walmsley wrote:
> Hi Franklin
>
> On Mon, 7 Mar 2016, Franklin S Cooper Jr wrote:
>
>> This patch series adds support for PWM for DRA7. The IP is same as that
>> present in AM33XX and AM437XX.
>>
>> However, before doing so remove unnecessary hwmod entries for eCAP, ePWM
>> and eQEP.
>>
>> This series is almost identical to v4. Only difference is the addition of
>> eCAP DT nodes in the dra7.dtsi file.
>>
>> This series was tested on AM335x GP, AM437x GP and X15 + LCD screen for
>> PWM based backlight.
>>
>> This series was also verified to be backwards compatible with old dtbs.
> Looking at these to see what I can pick for v4.7, I'm curious about the
> dependencies. Can I take patches 2 and 3 before 1 is merged, or does 1
> need to be merged first?
>
> - Paul
1 needs to be merged first.
On Mon, Mar 07, 2016 at 07:23:41PM -0600, Franklin S Cooper Jr wrote:
> Devices that utilize the OCP registers and/or PRCM registers and
> register bit fields should be modelled using hwmod. Since eQEP, ePWM and
s/modelled/modeled/
> eCAP don't fall under this category, remove their hwmod entries.
>
> Instead these clocks simply use the clock that is pass through by its
> parent PWMSS. Therefore, PWMSS handles the clock for itself and its
> subdevices.
Are you breaking compatibility with old DTs here?
> Signed-off-by: Franklin S Cooper Jr <[email protected]>
> ---
> .../devicetree/bindings/pwm/pwm-tiecap.txt | 1 -
> .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 7 +-
> .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 18 -----
> .../omap_hwmod_33xx_43xx_interconnect_data.c | 64 -----------------
> .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 84 ----------------------
> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 9 ---
> arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 54 --------------
> 7 files changed, 4 insertions(+), 233 deletions(-)
On Mon, Mar 07, 2016 at 07:23:44PM -0600, Franklin S Cooper Jr wrote:
> From: Vignesh R <[email protected]>
>
> Add PWMSS device tree nodes for DRA7 SoC family and add documentation
> for dt bindings.
>
> Signed-off-by: Vignesh R <[email protected]>
> [[email protected]: Add eCAP and use updated bindings for PWMSS and ePWM]
> Signed-off-by: Franklin S Cooper Jr <[email protected]>
> ---
> Version 5 changes:
> Add DT node for eCAP and update eCAP binding documentation
>
> Version 4 changes:
> Updated link to the latest documentation
>
> .../devicetree/bindings/pwm/pwm-tiecap.txt | 9 +++
> .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 +++
> .../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++-
> arch/arm/boot/dts/dra7.dtsi | 84 ++++++++++++++++++++++
> 4 files changed, 116 insertions(+), 1 deletion(-)
> + ehrpwm1: pwm@48440200 {
> + compatible = "ti,dra7xx-ehrpwm",
> + "ti,am33xx-ehrpwm";
> + #pwm-cells = <3>;
> + reg = <0x48440200 0x80>;
> + clocks = <&ehrpwm1_tbclk>;
> + clock-names = "tbclk";
> + status = "disabled";
> + };
> +
> + ecap1: ecap@48440100 {
This also is a PWM? Then it should also be pwm@...
> + compatible = "ti,dra7xx-ecap",
> + "ti,am33xx-ecap";
> + #pwm-cells = <3>;
> + reg = <0x48440100 0x80>;
> + status = "disabled";
> + };
> + };
> +
> + epwmss2: epwmss@48442000 {
> + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
> + reg = <0x48442000 0x30>;
> + ti,hwmods = "epwmss2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + status = "disabled";
> + ranges;
> +
> + ehrpwm2: pwm@48442200 {
> + compatible = "ti,dra7xx-ehrpwm",
> + "ti,am33xx-ehrpwm";
> + #pwm-cells = <3>;
> + reg = <0x48442200 0x80>;
> + clocks = <&ehrpwm2_tbclk>;
> + clock-names = "tbclk";
> + status = "disabled";
> + };
> +
> + ecap2: ecap@48442100 {
And here.
> + compatible = "ti,dra7xx-ecap",
> + "ti,am33xx-ecap";
> + #pwm-cells = <3>;
> + reg = <0x48442100 0x80>;
> + status = "disabled";
> + };
> + };
> };
>
> thermal_zones: thermal-zones {
> --
> 2.7.0
>
On 03/17/2016 10:06 AM, Rob Herring wrote:
> On Mon, Mar 07, 2016 at 07:23:41PM -0600, Franklin S Cooper Jr wrote:
>> Devices that utilize the OCP registers and/or PRCM registers and
>> register bit fields should be modelled using hwmod. Since eQEP, ePWM and
> s/modelled/modeled/
Will fix.
>
>> eCAP don't fall under this category, remove their hwmod entries.
>>
>> Instead these clocks simply use the clock that is pass through by its
>> parent PWMSS. Therefore, PWMSS handles the clock for itself and its
>> subdevices.
> Are you breaking compatibility with old DTs here?
No. The first patch makes sure that the ecap and ehrpwm get
their clocks from their parent which is all they care about.
Old dtbs will have hwmod entries for ecap and ehrpwm which
will end up not doing anything.
>
>> Signed-off-by: Franklin S Cooper Jr <[email protected]>
>> ---
>> .../devicetree/bindings/pwm/pwm-tiecap.txt | 1 -
>> .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 7 +-
>> .../mach-omap2/omap_hwmod_33xx_43xx_common_data.h | 18 -----
>> .../omap_hwmod_33xx_43xx_interconnect_data.c | 64 -----------------
>> .../mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 84 ----------------------
>> arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 9 ---
>> arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 54 --------------
>> 7 files changed, 4 insertions(+), 233 deletions(-)
On 03/17/2016 10:11 AM, Rob Herring wrote:
> On Mon, Mar 07, 2016 at 07:23:44PM -0600, Franklin S Cooper Jr wrote:
>> From: Vignesh R <[email protected]>
>>
>> Add PWMSS device tree nodes for DRA7 SoC family and add documentation
>> for dt bindings.
>>
>> Signed-off-by: Vignesh R <[email protected]>
>> [[email protected]: Add eCAP and use updated bindings for PWMSS and ePWM]
>> Signed-off-by: Franklin S Cooper Jr <[email protected]>
>> ---
>> Version 5 changes:
>> Add DT node for eCAP and update eCAP binding documentation
>>
>> Version 4 changes:
>> Updated link to the latest documentation
>>
>> .../devicetree/bindings/pwm/pwm-tiecap.txt | 9 +++
>> .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 +++
>> .../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++-
>> arch/arm/boot/dts/dra7.dtsi | 84 ++++++++++++++++++++++
>> 4 files changed, 116 insertions(+), 1 deletion(-)
>
>> + ehrpwm1: pwm@48440200 {
>> + compatible = "ti,dra7xx-ehrpwm",
>> + "ti,am33xx-ehrpwm";
>> + #pwm-cells = <3>;
>> + reg = <0x48440200 0x80>;
>> + clocks = <&ehrpwm1_tbclk>;
>> + clock-names = "tbclk";
>> + status = "disabled";
>> + };
>> +
>> + ecap1: ecap@48440100 {
> This also is a PWM? Then it should also be pwm@...
The enhanced capture module primary purpose is to measure
time between external signals which is called capture mode.
It also has a PWM mode. So I wouldn't recommend generalizing
the entire node to pwm.
>
>> + compatible = "ti,dra7xx-ecap",
>> + "ti,am33xx-ecap";
>> + #pwm-cells = <3>;
>> + reg = <0x48440100 0x80>;
>> + status = "disabled";
>> + };
>> + };
>> +
>> + epwmss2: epwmss@48442000 {
>> + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss";
>> + reg = <0x48442000 0x30>;
>> + ti,hwmods = "epwmss2";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + status = "disabled";
>> + ranges;
>> +
>> + ehrpwm2: pwm@48442200 {
>> + compatible = "ti,dra7xx-ehrpwm",
>> + "ti,am33xx-ehrpwm";
>> + #pwm-cells = <3>;
>> + reg = <0x48442200 0x80>;
>> + clocks = <&ehrpwm2_tbclk>;
>> + clock-names = "tbclk";
>> + status = "disabled";
>> + };
>> +
>> + ecap2: ecap@48442100 {
> And here.
>
>> + compatible = "ti,dra7xx-ecap",
>> + "ti,am33xx-ecap";
>> + #pwm-cells = <3>;
>> + reg = <0x48442100 0x80>;
>> + status = "disabled";
>> + };
>> + };
>> };
>>
>> thermal_zones: thermal-zones {
>> --
>> 2.7.0
>>
On Thu, Mar 17, 2016 at 10:45 AM, Franklin S Cooper Jr. <[email protected]> wrote:
>
>
> On 03/17/2016 10:06 AM, Rob Herring wrote:
>> On Mon, Mar 07, 2016 at 07:23:41PM -0600, Franklin S Cooper Jr wrote:
>>> Devices that utilize the OCP registers and/or PRCM registers and
>>> register bit fields should be modelled using hwmod. Since eQEP, ePWM and
>> s/modelled/modeled/
>
> Will fix.
>>
>>> eCAP don't fall under this category, remove their hwmod entries.
>>>
>>> Instead these clocks simply use the clock that is pass through by its
>>> parent PWMSS. Therefore, PWMSS handles the clock for itself and its
>>> subdevices.
>> Are you breaking compatibility with old DTs here?
>
> No. The first patch makes sure that the ecap and ehrpwm get
> their clocks from their parent which is all they care about.
> Old dtbs will have hwmod entries for ecap and ehrpwm which
> will end up not doing anything.
Okay.
Acked-by: Rob Herring <[email protected]>
Gentle ping on this
On 03/07/2016 07:23 PM, Franklin S Cooper Jr wrote:
> The eCAP and ePWM doesn't have their own separate clocks. They simply
> utilize the clock provided directly by the PWMSS. Therefore, they simply
> need to grab a reference to their parent's clock.
>
> Signed-off-by: Franklin S Cooper Jr <[email protected]>
> ---
> drivers/pwm/pwm-tiecap.c | 2 +-
> drivers/pwm/pwm-tiehrpwm.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
> index 616af76..9418159 100644
> --- a/drivers/pwm/pwm-tiecap.c
> +++ b/drivers/pwm/pwm-tiecap.c
> @@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
> if (!pc)
> return -ENOMEM;
>
> - clk = devm_clk_get(&pdev->dev, "fck");
> + clk = devm_clk_get(pdev->dev.parent, "fck");
> if (IS_ERR(clk)) {
> dev_err(&pdev->dev, "failed to get clock\n");
> return PTR_ERR(clk);
> diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
> index 6a41e66..09dc1bc 100644
> --- a/drivers/pwm/pwm-tiehrpwm.c
> +++ b/drivers/pwm/pwm-tiehrpwm.c
> @@ -443,7 +443,7 @@ static int ehrpwm_pwm_probe(struct platform_device *pdev)
> if (!pc)
> return -ENOMEM;
>
> - clk = devm_clk_get(&pdev->dev, "fck");
> + clk = devm_clk_get(pdev->dev.parent, "fck");
> if (IS_ERR(clk)) {
> dev_err(&pdev->dev, "failed to get clock\n");
> return PTR_ERR(clk);
On Tuesday 08 March 2016 06:53 AM, Franklin S Cooper Jr wrote:
> The eCAP and ePWM doesn't have their own separate clocks. They simply
> utilize the clock provided directly by the PWMSS. Therefore, they simply
> need to grab a reference to their parent's clock.
>
> Signed-off-by: Franklin S Cooper Jr <[email protected]>
So this assumes that eCAP and eHRPWM are always under the PWMSS
umbrella. But on TI AM18x, thats not true. These IPs exist independently
and receive functional clock from PLL sysclk outputs.
> ---
> drivers/pwm/pwm-tiecap.c | 2 +-
> drivers/pwm/pwm-tiehrpwm.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
> index 616af76..9418159 100644
> --- a/drivers/pwm/pwm-tiecap.c
> +++ b/drivers/pwm/pwm-tiecap.c
> @@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
> if (!pc)
> return -ENOMEM;
>
> - clk = devm_clk_get(&pdev->dev, "fck");
> + clk = devm_clk_get(pdev->dev.parent, "fck");
Even keeping the AM18x usecase aside, this seems to be pushing too much
platform information into the driver. The "fck" is a valid connection id
for the eCAP IP. Whether its valid for the parent device too is not
something this driver should need to know.
So it looks like what you need is for the clock hierarchy for the
platform to have clocks for eHRPWM and eCAP derived out of PWMSS clock?
Thanks,
Sekhar
On 04/05/2016 01:08 AM, Sekhar Nori wrote:
> On Tuesday 08 March 2016 06:53 AM, Franklin S Cooper Jr wrote:
> > The eCAP and ePWM doesn't have their own separate clocks. They simply
> > utilize the clock provided directly by the PWMSS. Therefore, they simply
> > need to grab a reference to their parent's clock.
> >
> > Signed-off-by: Franklin S Cooper Jr <[email protected]>
>
> So this assumes that eCAP and eHRPWM are always under the PWMSS
> umbrella. But on TI AM18x, thats not true. These IPs exist independently
> and receive functional clock from PLL sysclk outputs.
>
> > ---
> > drivers/pwm/pwm-tiecap.c | 2 +-
> > drivers/pwm/pwm-tiehrpwm.c | 2 +-
> > 2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
> > index 616af76..9418159 100644
> > --- a/drivers/pwm/pwm-tiecap.c
> > +++ b/drivers/pwm/pwm-tiecap.c
> > @@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
> > if (!pc)
> > return -ENOMEM;
> >
> > - clk = devm_clk_get(&pdev->dev, "fck");
> > + clk = devm_clk_get(pdev->dev.parent, "fck");
>
> Even keeping the AM18x usecase aside, this seems to be pushing too much
> platform information into the driver. The "fck" is a valid connection id
> for the eCAP IP. Whether its valid for the parent device too is not
> something this driver should need to know.
>
> So it looks like what you need is for the clock hierarchy for the
> platform to have clocks for eHRPWM and eCAP derived out of PWMSS clock?
So I believe this is a question on if we want to hide the minor
delta between AM18 vs AM335x, AM437x and AM57x/DRA7 in the driver
or within the DT.
Note that handling this by defining new clocks in DT will then
result in older DTBs not working. I don't think its worth breaking
backwards compatibility for AM335x and AM437x DTBs for fixing support
for AM18 based SOCs. Especially since those SOCs haven't worked with
this driver for several years. By handling things within the driver rather
than DT we can atleast insure that we can get everything working while
avoiding breaking backwards compatibility.
>
> Thanks,
> Sekhar
>
Vignesh, Franklin,
On Tue, 8 Mar 2016, Paul Walmsley wrote:
> On Mon, 7 Mar 2016, Franklin S Cooper Jr wrote:
>
> > From: Vignesh R <[email protected]>
> >
> > Add hwmod entries for the PWMSS on DRA7.
> >
> > Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
> > equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
> >
> > Signed-off-by: Vignesh R <[email protected]>
> > [[email protected]: Do not add eQEP, ePWM and eCAP hwmod entries]
> > Signed-off-by: Franklin S Cooper Jr <[email protected]>
>
> Thanks, queued for v4.7.
I took a closer look at this while preparing to merge it and it adds a
bunch of sparse warnings:
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c:3104:26: warning: symbol 'dra7xx_l4_per2__epwmss0' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c:3111:26: warning: symbol 'dra7xx_l4_per2__epwmss1' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c:3118:26: warning: symbol 'dra7xx_l4_per2__epwmss2' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c:395:25: warning: symbol 'dra7xx_epwmss_hwmod_class' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c:401:19: warning: symbol 'dra7xx_epwmss0_hwmod' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c:416:19: warning: symbol 'dra7xx_epwmss1_hwmod' was not declared. Should it be static?
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c:431:19: warning: symbol 'dra7xx_epwmss2_hwmod' was not declared. Should it be static?
It's also missing the one-line comments above each OCP interface record,
e.g.
/* l4_per1 -> gpio6 */
and a few other hwmod comments. I've added those too.
By courtesy, I've fixed these issues for this patch. But in the future,
please check your patches before sending to make sure that they don't add
new sparse warnings. If you need help running sparse, let us know (or
Nishanth can probably help you out; I think he's got some scripts that
test patch sets for common pre-submission problems). And please try to
align with the comment style of the rest of the hwmod files.
- Paul
From: Vignesh R <[email protected]>
Date: Sun, 10 Apr 2016 11:54:24 -0600
Subject: [PATCH] ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS
Add hwmod entries for the PWMSS on DRA7.
Set l4_root_clk_div as the main_clk of PWMSS. It is fixed-factored clock
equal to L4PER2_L3_GICLK/2(l3_iclk_div/2).
Signed-off-by: Vignesh R <[email protected]>
[[email protected]: Do not add eQEP, ePWM and eCAP hwmod entries]
Signed-off-by: Franklin S Cooper Jr <[email protected]>
[[email protected]: fixed sparse warnings; added missing comments]
Signed-off-by: Paul Walmsley <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 89 +++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 7610f3ef28b7..2f15cf13e0d7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -383,6 +383,68 @@ static struct omap_hwmod dra7xx_dcan2_hwmod = {
},
};
+/* pwmss */
+static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+/*
+ * epwmss class
+ */
+static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
+ .name = "epwmss",
+ .sysc = &dra7xx_epwmss_sysc,
+};
+
+/* epwmss0 */
+static struct omap_hwmod dra7xx_epwmss0_hwmod = {
+ .name = "epwmss0",
+ .class = &dra7xx_epwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* epwmss1 */
+static struct omap_hwmod dra7xx_epwmss1_hwmod = {
+ .name = "epwmss1",
+ .class = &dra7xx_epwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* epwmss2 */
+static struct omap_hwmod dra7xx_epwmss2_hwmod = {
+ .name = "epwmss2",
+ .class = &dra7xx_epwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .modulemode = MODULEMODE_SWCTRL,
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
+ },
+ },
+};
+
/*
* 'dma' class
*
@@ -3693,6 +3755,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_per2 -> epwmss0 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_epwmss0_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_per2 -> epwmss1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_epwmss1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l4_per2 -> epwmss2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_epwmss2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__dmm,
&dra7xx_l3_main_2__l3_instr,
@@ -3814,6 +3900,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__vcp2,
&dra7xx_l4_per2__vcp2,
&dra7xx_l4_wkup__wd_timer2,
+ &dra7xx_l4_per2__epwmss0,
+ &dra7xx_l4_per2__epwmss1,
+ &dra7xx_l4_per2__epwmss2,
NULL,
};
--
2.8.0.rc3
Hi guys
On Tue, 5 Apr 2016, Franklin S Cooper Jr. wrote:
> On 04/05/2016 01:08 AM, Sekhar Nori wrote:
> > On Tuesday 08 March 2016 06:53 AM, Franklin S Cooper Jr wrote:
> > > The eCAP and ePWM doesn't have their own separate clocks. They simply
> > > utilize the clock provided directly by the PWMSS. Therefore, they simply
> > > need to grab a reference to their parent's clock.
> > >
> > > Signed-off-by: Franklin S Cooper Jr <[email protected]>
> >
> > So this assumes that eCAP and eHRPWM are always under the PWMSS
> > umbrella. But on TI AM18x, thats not true. These IPs exist independently
> > and receive functional clock from PLL sysclk outputs.
> >
> > > ---
> > > drivers/pwm/pwm-tiecap.c | 2 +-
> > > drivers/pwm/pwm-tiehrpwm.c | 2 +-
> > > 2 files changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
> > > index 616af76..9418159 100644
> > > --- a/drivers/pwm/pwm-tiecap.c
> > > +++ b/drivers/pwm/pwm-tiecap.c
> > > @@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
> > > if (!pc)
> > > return -ENOMEM;
> > >
> > > - clk = devm_clk_get(&pdev->dev, "fck");
> > > + clk = devm_clk_get(pdev->dev.parent, "fck");
> >
> > Even keeping the AM18x usecase aside, this seems to be pushing too much
> > platform information into the driver. The "fck" is a valid connection id
> > for the eCAP IP. Whether its valid for the parent device too is not
> > something this driver should need to know.
> >
> > So it looks like what you need is for the clock hierarchy for the
> > platform to have clocks for eHRPWM and eCAP derived out of PWMSS clock?
>
> So I believe this is a question on if we want to hide the minor
> delta between AM18 vs AM335x, AM437x and AM57x/DRA7 in the driver
> or within the DT.
>
> Note that handling this by defining new clocks in DT will then
> result in older DTBs not working. I don't think its worth breaking
> backwards compatibility for AM335x and AM437x DTBs for fixing support
> for AM18 based SOCs. Especially since those SOCs haven't worked with
> this driver for several years. By handling things within the driver rather
> than DT we can atleast insure that we can get everything working while
> avoiding breaking backwards compatibility.
I agree with Sekhar that we shouldn't embed this parent clock quirk
into the driver.
Can you just define a new compatibility string such that the driver can be
written with no embedded integration quirks? Then add a workaround in the
driver that will use pdev->dev.parent for the old (deprecated)
compatibility string and log a warning to the kernel console that the DT
needs to be updated.
- Paul
On Monday 11 April 2016 02:21 AM, Paul Walmsley wrote:
> Hi guys
>
> On Tue, 5 Apr 2016, Franklin S Cooper Jr. wrote:
>
>> On 04/05/2016 01:08 AM, Sekhar Nori wrote:
>>> On Tuesday 08 March 2016 06:53 AM, Franklin S Cooper Jr wrote:
>>>> The eCAP and ePWM doesn't have their own separate clocks. They simply
>>>> utilize the clock provided directly by the PWMSS. Therefore, they simply
>>>> need to grab a reference to their parent's clock.
>>>>
>>>> Signed-off-by: Franklin S Cooper Jr <[email protected]>
>>>
>>> So this assumes that eCAP and eHRPWM are always under the PWMSS
>>> umbrella. But on TI AM18x, thats not true. These IPs exist independently
>>> and receive functional clock from PLL sysclk outputs.
>>>
>>>> ---
>>>> drivers/pwm/pwm-tiecap.c | 2 +-
>>>> drivers/pwm/pwm-tiehrpwm.c | 2 +-
>>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
>>>> index 616af76..9418159 100644
>>>> --- a/drivers/pwm/pwm-tiecap.c
>>>> +++ b/drivers/pwm/pwm-tiecap.c
>>>> @@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
>>>> if (!pc)
>>>> return -ENOMEM;
>>>>
>>>> - clk = devm_clk_get(&pdev->dev, "fck");
>>>> + clk = devm_clk_get(pdev->dev.parent, "fck");
>>>
>>> Even keeping the AM18x usecase aside, this seems to be pushing too much
>>> platform information into the driver. The "fck" is a valid connection id
>>> for the eCAP IP. Whether its valid for the parent device too is not
>>> something this driver should need to know.
>>>
>>> So it looks like what you need is for the clock hierarchy for the
>>> platform to have clocks for eHRPWM and eCAP derived out of PWMSS clock?
>>
>> So I believe this is a question on if we want to hide the minor
>> delta between AM18 vs AM335x, AM437x and AM57x/DRA7 in the driver
>> or within the DT.
>>
>> Note that handling this by defining new clocks in DT will then
>> result in older DTBs not working. I don't think its worth breaking
>> backwards compatibility for AM335x and AM437x DTBs for fixing support
>> for AM18 based SOCs. Especially since those SOCs haven't worked with
>> this driver for several years. By handling things within the driver rather
>> than DT we can atleast insure that we can get everything working while
>> avoiding breaking backwards compatibility.
>
> I agree with Sekhar that we shouldn't embed this parent clock quirk
> into the driver.
>
> Can you just define a new compatibility string such that the driver can be
> written with no embedded integration quirks? Then add a workaround in the
> driver that will use pdev->dev.parent for the old (deprecated)
> compatibility string and log a warning to the kernel console that the DT
> needs to be updated.
Thanks Paul! Although not sure if adding a new compatible for the IP is
the best way (since that would denote a different version of the IP).
How about checking for parent clock iff clk_get() on own device fails
and of_machine_is_compatible() matches the platforms where backward
compatibility needs to be maintained?
Thanks,
Sekhar
On Mon, Apr 11, 2016 at 6:49 AM, Sekhar Nori <[email protected]> wrote:
> On Monday 11 April 2016 02:21 AM, Paul Walmsley wrote:
>> Hi guys
>>
>> On Tue, 5 Apr 2016, Franklin S Cooper Jr. wrote:
>>
>>> On 04/05/2016 01:08 AM, Sekhar Nori wrote:
>>>> On Tuesday 08 March 2016 06:53 AM, Franklin S Cooper Jr wrote:
>>>>> The eCAP and ePWM doesn't have their own separate clocks. They simply
>>>>> utilize the clock provided directly by the PWMSS. Therefore, they simply
>>>>> need to grab a reference to their parent's clock.
>>>>>
>>>>> Signed-off-by: Franklin S Cooper Jr <[email protected]>
>>>>
>>>> So this assumes that eCAP and eHRPWM are always under the PWMSS
>>>> umbrella. But on TI AM18x, thats not true. These IPs exist independently
>>>> and receive functional clock from PLL sysclk outputs.
>>>>
>>>>> ---
>>>>> drivers/pwm/pwm-tiecap.c | 2 +-
>>>>> drivers/pwm/pwm-tiehrpwm.c | 2 +-
>>>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
>>>>> index 616af76..9418159 100644
>>>>> --- a/drivers/pwm/pwm-tiecap.c
>>>>> +++ b/drivers/pwm/pwm-tiecap.c
>>>>> @@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
>>>>> if (!pc)
>>>>> return -ENOMEM;
>>>>>
>>>>> - clk = devm_clk_get(&pdev->dev, "fck");
>>>>> + clk = devm_clk_get(pdev->dev.parent, "fck");
>>>>
>>>> Even keeping the AM18x usecase aside, this seems to be pushing too much
>>>> platform information into the driver. The "fck" is a valid connection id
>>>> for the eCAP IP. Whether its valid for the parent device too is not
>>>> something this driver should need to know.
>>>>
>>>> So it looks like what you need is for the clock hierarchy for the
>>>> platform to have clocks for eHRPWM and eCAP derived out of PWMSS clock?
>>>
>>> So I believe this is a question on if we want to hide the minor
>>> delta between AM18 vs AM335x, AM437x and AM57x/DRA7 in the driver
>>> or within the DT.
>>>
>>> Note that handling this by defining new clocks in DT will then
>>> result in older DTBs not working. I don't think its worth breaking
>>> backwards compatibility for AM335x and AM437x DTBs for fixing support
>>> for AM18 based SOCs. Especially since those SOCs haven't worked with
>>> this driver for several years. By handling things within the driver rather
>>> than DT we can atleast insure that we can get everything working while
>>> avoiding breaking backwards compatibility.
>>
>> I agree with Sekhar that we shouldn't embed this parent clock quirk
>> into the driver.
>>
>> Can you just define a new compatibility string such that the driver can be
>> written with no embedded integration quirks? Then add a workaround in the
>> driver that will use pdev->dev.parent for the old (deprecated)
>> compatibility string and log a warning to the kernel console that the DT
>> needs to be updated.
>
> Thanks Paul! Although not sure if adding a new compatible for the IP is
> the best way (since that would denote a different version of the IP).
> How about checking for parent clock iff clk_get() on own device fails
> and of_machine_is_compatible() matches the platforms where backward
> compatibility needs to be maintained?
New compatible strings are acceptable.
Rob
* Franklin S Cooper Jr. <[email protected]> [160317 08:55]:
>
>
> On 03/17/2016 10:11 AM, Rob Herring wrote:
> > On Mon, Mar 07, 2016 at 07:23:44PM -0600, Franklin S Cooper Jr wrote:
> >> From: Vignesh R <[email protected]>
> >>
> >> Add PWMSS device tree nodes for DRA7 SoC family and add documentation
> >> for dt bindings.
> >>
> >> Signed-off-by: Vignesh R <[email protected]>
> >> [[email protected]: Add eCAP and use updated bindings for PWMSS and ePWM]
> >> Signed-off-by: Franklin S Cooper Jr <[email protected]>
> >> ---
> >> Version 5 changes:
> >> Add DT node for eCAP and update eCAP binding documentation
> >>
> >> Version 4 changes:
> >> Updated link to the latest documentation
> >>
> >> .../devicetree/bindings/pwm/pwm-tiecap.txt | 9 +++
> >> .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 +++
> >> .../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++-
> >> arch/arm/boot/dts/dra7.dtsi | 84 ++++++++++++++++++++++
> >> 4 files changed, 116 insertions(+), 1 deletion(-)
> >
> >> + ehrpwm1: pwm@48440200 {
> >> + compatible = "ti,dra7xx-ehrpwm",
> >> + "ti,am33xx-ehrpwm";
> >> + #pwm-cells = <3>;
> >> + reg = <0x48440200 0x80>;
> >> + clocks = <&ehrpwm1_tbclk>;
> >> + clock-names = "tbclk";
> >> + status = "disabled";
> >> + };
> >> +
> >> + ecap1: ecap@48440100 {
> > This also is a PWM? Then it should also be pwm@...
>
> The enhanced capture module primary purpose is to measure
> time between external signals which is called capture mode.
> It also has a PWM mode. So I wouldn't recommend generalizing
> the entire node to pwm.
So is this patch safe for me to apply now or do we need more
changes?
Regards,
Tony
* Franklin S Cooper Jr <[email protected]> [160307 17:24]:
> From: Vignesh R <[email protected]>
>
> tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
> clock to control ehrpwm tbclk.
> The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but
> ehrpwm functional clock derived from the gateable interface and
> functional clock of PWMSS(l4_root_clk_div).
> Refer AM57x TRM SPRUHZ6E[1], Janurary 2016, Table 29-4 and
> Section 29.2.2.1, Table 29-19 and the NOTE at the end of the table.
Applying this one into omap-for-v4.7/dt thanks.
Tony
* Tony Lindgren <[email protected]> [160411 13:24]:
> * Franklin S Cooper Jr <[email protected]> [160307 17:24]:
> > From: Vignesh R <[email protected]>
> >
> > tbclk is used by ehrpwm to generate PWM waveform on DRA7 SoC. Add Linux
> > clock to control ehrpwm tbclk.
> > The TRM says, tbclk is derived from SYSCLKOUT. SYSCLKOUT is nothing but
> > ehrpwm functional clock derived from the gateable interface and
> > functional clock of PWMSS(l4_root_clk_div).
> > Refer AM57x TRM SPRUHZ6E[1], Janurary 2016, Table 29-4 and
> > Section 29.2.2.1, Table 29-19 and the NOTE at the end of the table.
>
> Applying this one into omap-for-v4.7/dt thanks.
Never mind, we already have these with commit c60f9e29805e ("ARM: dts:
DRA7: Add TBCLK for PWMSS").
Tony
On Monday 11 April 2016 06:15 PM, Rob Herring wrote:
> On Mon, Apr 11, 2016 at 6:49 AM, Sekhar Nori <[email protected]> wrote:
>> On Monday 11 April 2016 02:21 AM, Paul Walmsley wrote:
>>> On Tue, 5 Apr 2016, Franklin S Cooper Jr. wrote:
>>>> On 04/05/2016 01:08 AM, Sekhar Nori wrote:
>>>>> On Tuesday 08 March 2016 06:53 AM, Franklin S Cooper Jr wrote:
>>>>>> The eCAP and ePWM doesn't have their own separate clocks. They simply
>>>>>> utilize the clock provided directly by the PWMSS. Therefore, they simply
>>>>>> need to grab a reference to their parent's clock.
>>>>>>
>>>>>> Signed-off-by: Franklin S Cooper Jr <[email protected]>
>>>>>
>>>>> So this assumes that eCAP and eHRPWM are always under the PWMSS
>>>>> umbrella. But on TI AM18x, thats not true. These IPs exist independently
>>>>> and receive functional clock from PLL sysclk outputs.
>>>>>
>>>>>> ---
>>>>>> drivers/pwm/pwm-tiecap.c | 2 +-
>>>>>> drivers/pwm/pwm-tiehrpwm.c | 2 +-
>>>>>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/pwm/pwm-tiecap.c b/drivers/pwm/pwm-tiecap.c
>>>>>> index 616af76..9418159 100644
>>>>>> --- a/drivers/pwm/pwm-tiecap.c
>>>>>> +++ b/drivers/pwm/pwm-tiecap.c
>>>>>> @@ -212,7 +212,7 @@ static int ecap_pwm_probe(struct platform_device *pdev)
>>>>>> if (!pc)
>>>>>> return -ENOMEM;
>>>>>>
>>>>>> - clk = devm_clk_get(&pdev->dev, "fck");
>>>>>> + clk = devm_clk_get(pdev->dev.parent, "fck");
>>>>>
>>>>> Even keeping the AM18x usecase aside, this seems to be pushing too much
>>>>> platform information into the driver. The "fck" is a valid connection id
>>>>> for the eCAP IP. Whether its valid for the parent device too is not
>>>>> something this driver should need to know.
>>>>>
>>>>> So it looks like what you need is for the clock hierarchy for the
>>>>> platform to have clocks for eHRPWM and eCAP derived out of PWMSS clock?
>>>>
>>>> So I believe this is a question on if we want to hide the minor
>>>> delta between AM18 vs AM335x, AM437x and AM57x/DRA7 in the driver
>>>> or within the DT.
>>>>
>>>> Note that handling this by defining new clocks in DT will then
>>>> result in older DTBs not working. I don't think its worth breaking
>>>> backwards compatibility for AM335x and AM437x DTBs for fixing support
>>>> for AM18 based SOCs. Especially since those SOCs haven't worked with
>>>> this driver for several years. By handling things within the driver rather
>>>> than DT we can atleast insure that we can get everything working while
>>>> avoiding breaking backwards compatibility.
>>>
>>> I agree with Sekhar that we shouldn't embed this parent clock quirk
>>> into the driver.
>>>
>>> Can you just define a new compatibility string such that the driver can be
>>> written with no embedded integration quirks? Then add a workaround in the
>>> driver that will use pdev->dev.parent for the old (deprecated)
>>> compatibility string and log a warning to the kernel console that the DT
>>> needs to be updated.
>>
>> Thanks Paul! Although not sure if adding a new compatible for the IP is
>> the best way (since that would denote a different version of the IP).
>> How about checking for parent clock iff clk_get() on own device fails
>> and of_machine_is_compatible() matches the platforms where backward
>> compatibility needs to be maintained?
>
> New compatible strings are acceptable.
Alright, thanks for clarifying that.
Regards,
Sekhar
On 04/11/2016 03:21 PM, Tony Lindgren wrote:
> * Franklin S Cooper Jr. <[email protected]> [160317 08:55]:
>>
>>
>> On 03/17/2016 10:11 AM, Rob Herring wrote:
>>> On Mon, Mar 07, 2016 at 07:23:44PM -0600, Franklin S Cooper Jr wrote:
>>>> From: Vignesh R <[email protected]>
>>>>
>>>> Add PWMSS device tree nodes for DRA7 SoC family and add documentation
>>>> for dt bindings.
>>>>
>>>> Signed-off-by: Vignesh R <[email protected]>
>>>> [[email protected]: Add eCAP and use updated bindings for PWMSS and ePWM]
>>>> Signed-off-by: Franklin S Cooper Jr <[email protected]>
>>>> ---
>>>> Version 5 changes:
>>>> Add DT node for eCAP and update eCAP binding documentation
>>>>
>>>> Version 4 changes:
>>>> Updated link to the latest documentation
>>>>
>>>> .../devicetree/bindings/pwm/pwm-tiecap.txt | 9 +++
>>>> .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 +++
>>>> .../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++-
>>>> arch/arm/boot/dts/dra7.dtsi | 84 ++++++++++++++++++++++
>>>> 4 files changed, 116 insertions(+), 1 deletion(-)
>>>
>>>> + ehrpwm1: pwm@48440200 {
>>>> + compatible = "ti,dra7xx-ehrpwm",
>>>> + "ti,am33xx-ehrpwm";
>>>> + #pwm-cells = <3>;
>>>> + reg = <0x48440200 0x80>;
>>>> + clocks = <&ehrpwm1_tbclk>;
>>>> + clock-names = "tbclk";
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + ecap1: ecap@48440100 {
>>> This also is a PWM? Then it should also be pwm@...
>>
>> The enhanced capture module primary purpose is to measure
>> time between external signals which is called capture mode.
>> It also has a PWM mode. So I wouldn't recommend generalizing
>> the entire node to pwm.
>
> So is this patch safe for me to apply now or do we need more
> changes?
No. This patch will change based on changes I will make to handle patch
1 comments. I will send a new rev.
>
> Regards,
>
> Tony
>