From: Sean Wang <[email protected]>
Hi,
The series adds a required resource setup to allow Mali-450 to work on
MT7623. This also can benefits other MediaTek SoCs having Mali-450 device.
In order to prove the setup is proper, I also have added mediatek port to
linux-lima at [1] and make a few of tests along with off-screen rendering
[2][3][4][5][6][7] through mesa-lima [8]. All work correctly.
[1] https://github.com/objelf/linux-lima/tree/mediatek-lima-4.16-rc5
[2] simple triangle: https://github.com/yuq/gfx/tree/master/gbm-surface
[3] vertex shader uniform: https://github.com/yuq/gfx/tree/master/gbm-surface-move
[4] multi varying: https://github.com/yuq/gfx/tree/master/gbm-surface-color
[5] multi draw: https://github.com/yuq/gfx/tree/master/gbm-surface-draw
[6] FBO: https://github.com/yuq/gfx/tree/master/gbm-surface-fbo
[7] kmscube: https://github.com/yuq/kmscube
[8] https://github.com/yuq/mesa-lima
Hope these patches can help people working on BPI-R2.
Sean
Sean Wang (4):
dt-bindings: gpu: mali-utgard: add mediatek,mt7623-mali compatible
dt-bindings: clock: mediatek: add g3dsys bindings
clk: mediatek: add g3dsys support for MT2701 and MT7623
arm: dts: mt7623: add Mali-450 and related device nodes
.../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 +++++++
.../devicetree/bindings/gpu/arm,mali-utgard.txt | 9 ++
arch/arm/boot/dts/mt7623.dtsi | 70 ++++++++++++++++
arch/arm/boot/dts/mt7623a.dtsi | 4 +
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt2701-g3d.c | 95 ++++++++++++++++++++++
include/dt-bindings/clock/mt2701-clk.h | 4 +
include/dt-bindings/reset/mt2701-resets.h | 3 +
9 files changed, 222 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
create mode 100644 drivers/clk/mediatek/clk-mt2701-g3d.c
--
2.7.4
From: Sean Wang <[email protected]>
Add nodes for Mali-450 device, g3dsys device providing required clock
gate and reset control and larb3 offering an arbiter through iommu for
controlling access to external memory requested from Mali-450.
Signed-off-by: Sean Wang <[email protected]>
---
arch/arm/boot/dts/mt7623.dtsi | 70 ++++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/mt7623a.dtsi | 4 +++
2 files changed, 74 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index d1eb123..ace92b3 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -274,6 +274,17 @@
clock-names = "system-clk", "rtc-clk";
};
+ smi_common: smi@1000c000 {
+ compatible = "mediatek,mt7623-smi-common",
+ "mediatek,mt2701-smi-common";
+ reg = <0 0x1000c000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_SMI>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&infracfg CLK_INFRA_SMI>;
+ clock-names = "apb", "smi", "async";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt7623-pwrap",
"mediatek,mt2701-pwrap";
@@ -305,6 +316,17 @@
reg = <0 0x10200100 0 0x1c>;
};
+ iommu: iommu@10205000 {
+ compatible = "mediatek,mt7623-m4u",
+ "mediatek,mt2701-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ mediatek,larbs = <&larb3>;
+ #iommu-cells = <1>;
+ };
+
efuse: efuse@10206000 {
compatible = "mediatek,mt7623-efuse",
"mediatek,mt8173-efuse";
@@ -680,6 +702,54 @@
status = "disabled";
};
+ g3dsys: clock-controller@13000000 {
+ compatible = "mediatek,mt7623-g3dsys",
+ "mediatek,mt2701-g3dsys",
+ "syscon";
+ reg = <0 0x13000000 0 0x200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ larb3: larb@13010000 {
+ compatible = "mediatek,mt7623-smi-larb",
+ "mediatek,mt2701-smi-larb";
+ reg = <0 0x13010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <3>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+ };
+
+ mali: gpu@13040000 {
+ compatible = "mediatek,mt7623-mali", "arm,mali-450";
+ reg = <0 0x13040000 0 0x30000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
+ "ppmmu1", "pp2", "ppmmu2", "pp";
+ clocks = <&topckgen CLK_TOP_MMPLL>,
+ <&g3dsys CLK_G3DSYS_CORE>;
+ clock-names = "bus", "core";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+ mediatek,larb = <&larb3>;
+ resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt2701-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
hifsys: syscon@1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
diff --git a/arch/arm/boot/dts/mt7623a.dtsi b/arch/arm/boot/dts/mt7623a.dtsi
index 0735a1fb8..a42fd46 100644
--- a/arch/arm/boot/dts/mt7623a.dtsi
+++ b/arch/arm/boot/dts/mt7623a.dtsi
@@ -21,6 +21,10 @@
power-domains = <&scpsys MT7623A_POWER_DOMAIN_ETH>;
};
+&mali {
+ status = "disabled";
+};
+
&nandc {
power-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;
};
--
2.7.4
From: Sean Wang <[email protected]>
Add bindings to g3dsys providing necessary clock and reset control to
Mali-450.
Signed-off-by: Sean Wang <[email protected]>
---
.../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
new file mode 100644
index 0000000..ff2d70c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
@@ -0,0 +1,30 @@
+MediaTek g3dsys controller
+============================
+
+The MediaTek g3dsys controller provides various clocks and reset controller to
+the GPU.
+
+Required Properties:
+
+- compatible: Should be:
+ - "mediatek,mt2701-g3dsys", "syscon":
+ for MT2701 SoC
+ - "mediatek,mt7623-ethsys", "mediatek,mt2701-g3dsys", "syscon":
+ for MT7623 SoC
+- #clock-cells: Must be 1
+- #reset-cells: Must be 1
+
+The ethsys controller uses the common clk binding from
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
+
+Example:
+
+g3dsys: clock-controller@13000000 {
+ compatible = "mediatek,mt7623-g3dsys",
+ "mediatek,mt2701-g3dsys",
+ "syscon";
+ reg = <0 0x13000000 0 0x200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
--
2.7.4
From: Sean Wang <[email protected]>
The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it
and define its own vendor-specific properties.
Signed-off-by: Sean Wang <[email protected]>
---
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index c1f65d1..e149995 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -20,6 +20,7 @@ Required properties:
+ rockchip,rk3228-mali
+ rockchip,rk3328-mali
+ stericsson,db8500-mali
+ + mediatek,mt7623-mali
- reg: Physical base address and length of the GPU registers
@@ -86,6 +87,14 @@ to specify one more vendor-specific compatible, among:
* interrupt-names and interrupts:
+ combined: combined interrupt of all of the above lines
+ - mediatek,mt7623-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+ * mediatek,larb: phandle pointed to the local arbiter used to control the
+ access to external memory on the SoC.
+ see Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+ for details
+
Example:
mali: gpu@1c40000 {
--
2.7.4
From: Sean Wang <[email protected]>
Add clock driver support for g3dsys on MT2701 and MT7623, which is
providing essential clock gate and reset controller to Mali-450.
Signed-off-by: Sean Wang <[email protected]>
---
drivers/clk/mediatek/Kconfig | 6 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt2701-g3d.c | 95 +++++++++++++++++++++++++++++++
include/dt-bindings/clock/mt2701-clk.h | 4 ++
include/dt-bindings/reset/mt2701-resets.h | 3 +
5 files changed, 109 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt2701-g3d.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 92afe59..3dd1dab 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -60,6 +60,12 @@ config COMMON_CLK_MT2701_AUDSYS
---help---
This driver supports Mediatek MT2701 audsys clocks.
+config COMMON_CLK_MT2701_G3DSYS
+ bool "Clock driver for MediaTek MT2701 g3dsys"
+ depends on COMMON_CLK_MT2701
+ ---help---
+ This driver supports MediaTek MT2701 g3dsys clocks.
+
config COMMON_CLK_MT2712
bool "Clock driver for MediaTek MT2712"
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index b80eff2..844b55d 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
+obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c
new file mode 100644
index 0000000..1328c11
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Sean Wang <[email protected]>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt2701-clk.h>
+
+#define GATE_G3D(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &g3d_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ }
+
+static const struct mtk_gate_regs g3d_cg_regs = {
+ .sta_ofs = 0x0,
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+};
+
+static const struct mtk_gate g3d_clks[] = {
+ GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
+};
+
+static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ int r;
+
+ clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
+
+ mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
+ clk_data);
+
+ r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ mtk_register_reset_controller(node, 1, 0xc);
+
+ return r;
+}
+
+static const struct of_device_id of_match_clk_mt2701_g3d[] = {
+ {
+ .compatible = "mediatek,mt2701-g3dsys",
+ .data = clk_mt2701_g3dsys_init,
+ }, {
+ /* sentinel */
+ }
+};
+
+static int clk_mt2701_g3d_probe(struct platform_device *pdev)
+{
+ int (*clk_init)(struct platform_device *);
+ int r;
+
+ clk_init = of_device_get_match_data(&pdev->dev);
+ if (!clk_init)
+ return -EINVAL;
+
+ r = clk_init(pdev);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_mt2701_g3d_drv = {
+ .probe = clk_mt2701_g3d_probe,
+ .driver = {
+ .name = "clk-mt2701-g3d",
+ .of_match_table = of_match_clk_mt2701_g3d,
+ },
+};
+
+builtin_platform_driver(clk_mt2701_g3d_drv);
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h
index 24e93df..2ac62a6 100644
--- a/include/dt-bindings/clock/mt2701-clk.h
+++ b/include/dt-bindings/clock/mt2701-clk.h
@@ -431,6 +431,10 @@
#define CLK_ETHSYS_CRYPTO 8
#define CLK_ETHSYS_NR 9
+/* G3DSYS */
+#define CLK_G3DSYS_CORE 1
+#define CLK_G3DSYS_NR 2
+
/* BDP */
#define CLK_BDP_BRG_BA 1
diff --git a/include/dt-bindings/reset/mt2701-resets.h b/include/dt-bindings/reset/mt2701-resets.h
index 21deb54..50b7f06 100644
--- a/include/dt-bindings/reset/mt2701-resets.h
+++ b/include/dt-bindings/reset/mt2701-resets.h
@@ -87,4 +87,7 @@
#define MT2701_ETHSYS_GMAC_RST 23
#define MT2701_ETHSYS_PPE_RST 31
+/* G3DSYS resets */
+#define MT2701_G3DSYS_CORE_RST 0
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
--
2.7.4
Quoting [email protected] (2018-04-18 03:24:54)
> From: Sean Wang <[email protected]>
>
> Add bindings to g3dsys providing necessary clock and reset control to
> Mali-450.
>
> Signed-off-by: Sean Wang <[email protected]>
> ---
> .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++
Why isn't this under bindings/clock/ ?
On Wed, 2018-04-18 at 20:18 -0700, Stephen Boyd wrote:
> Quoting [email protected] (2018-04-18 03:24:54)
> > From: Sean Wang <[email protected]>
> >
> > Add bindings to g3dsys providing necessary clock and reset control to
> > Mali-450.
> >
> > Signed-off-by: Sean Wang <[email protected]>
> > ---
> > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++
>
> Why isn't this under bindings/clock/ ?
>
Tons of bindings for clock controller have been present at
binding/arm/mediatek. g3dsys just have a follow-up to them.
It's worth another patch moving them all from bindings/arm/mediatek/ to
bindings/clock/mediatek.
what's your opinion for either doing it prior to g3dsys binding being
added or doing it in the future ?
>
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Quoting Sean Wang (2018-04-18 20:50:02)
> On Wed, 2018-04-18 at 20:18 -0700, Stephen Boyd wrote:
> > Quoting [email protected] (2018-04-18 03:24:54)
> > > From: Sean Wang <[email protected]>
> > >
> > > Add bindings to g3dsys providing necessary clock and reset control to
> > > Mali-450.
> > >
> > > Signed-off-by: Sean Wang <[email protected]>
> > > ---
> > > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++
> >
> > Why isn't this under bindings/clock/ ?
> >
>
> Tons of bindings for clock controller have been present at
> binding/arm/mediatek. g3dsys just have a follow-up to them.
>
> It's worth another patch moving them all from bindings/arm/mediatek/ to
> bindings/clock/mediatek.
>
> what's your opinion for either doing it prior to g3dsys binding being
> added or doing it in the future ?
>
Doing it at a later time is fine. Just wondering why they're all getting
dumped into the arm/ directory.
On Wed, Apr 18, 2018 at 06:24:53PM +0800, [email protected] wrote:
> From: Sean Wang <[email protected]>
>
> The MediaTek MT7623 SoC contains a Mali-450, so add a compatible for it
> and define its own vendor-specific properties.
>
> Signed-off-by: Sean Wang <[email protected]>
> ---
> Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Rob Herring <[email protected]>
On Wed, Apr 18, 2018 at 06:24:54PM +0800, [email protected] wrote:
> From: Sean Wang <[email protected]>
>
> Add bindings to g3dsys providing necessary clock and reset control to
> Mali-450.
>
> Signed-off-by: Sean Wang <[email protected]>
> ---
> .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
> new file mode 100644
> index 0000000..ff2d70c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
> @@ -0,0 +1,30 @@
> +MediaTek g3dsys controller
> +============================
> +
> +The MediaTek g3dsys controller provides various clocks and reset controller to
> +the GPU.
> +
> +Required Properties:
> +
> +- compatible: Should be:
> + - "mediatek,mt2701-g3dsys", "syscon":
> + for MT2701 SoC
> + - "mediatek,mt7623-ethsys", "mediatek,mt2701-g3dsys", "syscon":
> + for MT7623 SoC
ethsys?
> +- #clock-cells: Must be 1
> +- #reset-cells: Must be 1
> +
> +The ethsys controller uses the common clk binding from
> +Documentation/devicetree/bindings/clock/clock-bindings.txt
> +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
> +
> +Example:
> +
> +g3dsys: clock-controller@13000000 {
> + compatible = "mediatek,mt7623-g3dsys",
> + "mediatek,mt2701-g3dsys",
> + "syscon";
> + reg = <0 0x13000000 0 0x200>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +};
> --
> 2.7.4
>
On Wed, Apr 18, 2018 at 06:24:55PM +0800, [email protected] wrote:
> From: Sean Wang <[email protected]>
>
> Add clock driver support for g3dsys on MT2701 and MT7623, which is
> providing essential clock gate and reset controller to Mali-450.
>
> Signed-off-by: Sean Wang <[email protected]>
> ---
> drivers/clk/mediatek/Kconfig | 6 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt2701-g3d.c | 95 +++++++++++++++++++++++++++++++
> include/dt-bindings/clock/mt2701-clk.h | 4 ++
> include/dt-bindings/reset/mt2701-resets.h | 3 +
These below in the binding patch.
> 5 files changed, 109 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt2701-g3d.c
On Tue, 2018-04-24 at 09:40 -0500, Rob Herring wrote:
> On Wed, Apr 18, 2018 at 06:24:55PM +0800, [email protected] wrote:
> > From: Sean Wang <[email protected]>
> >
> > Add clock driver support for g3dsys on MT2701 and MT7623, which is
> > providing essential clock gate and reset controller to Mali-450.
> >
> > Signed-off-by: Sean Wang <[email protected]>
> > ---
> > drivers/clk/mediatek/Kconfig | 6 ++
> > drivers/clk/mediatek/Makefile | 1 +
> > drivers/clk/mediatek/clk-mt2701-g3d.c | 95 +++++++++++++++++++++++++++++++
>
> > include/dt-bindings/clock/mt2701-clk.h | 4 ++
> > include/dt-bindings/reset/mt2701-resets.h | 3 +
>
> These below in the binding patch.
>
Thanks, I will split them out in the next version.
> > 5 files changed, 109 insertions(+)
> > create mode 100644 drivers/clk/mediatek/clk-mt2701-g3d.c
On Tue, 2018-04-24 at 09:39 -0500, Rob Herring wrote:
> On Wed, Apr 18, 2018 at 06:24:54PM +0800, [email protected] wrote:
> > From: Sean Wang <[email protected]>
> >
> > Add bindings to g3dsys providing necessary clock and reset control to
> > Mali-450.
> >
> > Signed-off-by: Sean Wang <[email protected]>
> > ---
> > .../bindings/arm/mediatek/mediatek,g3dsys.txt | 30 ++++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
> > new file mode 100644
> > index 0000000..ff2d70c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
> > @@ -0,0 +1,30 @@
> > +MediaTek g3dsys controller
> > +============================
> > +
> > +The MediaTek g3dsys controller provides various clocks and reset controller to
> > +the GPU.
> > +
> > +Required Properties:
> > +
> > +- compatible: Should be:
> > + - "mediatek,mt2701-g3dsys", "syscon":
> > + for MT2701 SoC
> > + - "mediatek,mt7623-ethsys", "mediatek,mt2701-g3dsys", "syscon":
> > + for MT7623 SoC
>
> ethsys?
>
thanks! I'll also fix it up in the next version.
> > +- #clock-cells: Must be 1
> > +- #reset-cells: Must be 1
> > +
> > +The ethsys controller uses the common clk binding from
> > +Documentation/devicetree/bindings/clock/clock-bindings.txt
> > +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
> > +
> > +Example:
> > +
> > +g3dsys: clock-controller@13000000 {
> > + compatible = "mediatek,mt7623-g3dsys",
> > + "mediatek,mt2701-g3dsys",
> > + "syscon";
> > + reg = <0 0x13000000 0 0x200>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > +};
> > --
> > 2.7.4
> >