MT8183 is a SoC based on 64bit ARMv8 architecture.
It contains 4 CA53 and 4 CA73 cores.
MT8183 share many HW IP with MT65xx series.
This patchset was tested on MT8183 evaluation board and use correct clock to shell.
Based on v5.2-rc1
Change in v11:
New add spi node, efuse node, pinctrl node, auxadc node, and capacity-dmips-mhz field
Change in v10:
Add the L2 cache node to prevent warning on unable to detect cache
hierarchy.
Change in v9:
Remove pio node since binding is not documented yet
Change in v8:
1. Fix interrupt-parent of pio node
2. Remove pinfunc.h and spi node patches
Change in v7:
1. Place all the MMIO peripherals under one or more simple-bus nodes
2. Make the pinfunc.h and spi node into seperate patch
3. Modify SPIs pamerater from 4 back to 3
and remove patch "support 4 interrupt parameters for sysirq"
4. Rename intpol-controller to interrupt-controller
5. Rename pinctrl@1000b000 to pinctrl@10005000
Change in v6:
1. Remove power and iommu nodes
2. Fix dtb build warning
3. Fix pinctrl binding doc
4. Fix '_' in node names
Change in v5:
1. Collect all device tree nodes to the last patch
2. Add PMU
3. Add Signed-off-by
4. Remove clock driver code and binding doc
5. Add pinctrl, iommu, spi, and pwrap nodes
Change in v4:
1. Correct syntax error in dtsi
2. Add MT8183 clock support
Change in v3:
1. Fill out GICC, GICH, GICV regions
2. Update Copyright to 2018
Change in v2:
1. Split dt-bindings into different patches
2. Correct bindings for supported SoCs (mtk-uart.txt)
Ben Ho (1):
arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and
Makefile
Erin Lo (1):
arm64: dts: mt8183: add spi node
Hsin-Yi, Wang (1):
arm64: dts: mt8183: add capacity-dmips-mhz
Michael Mei (1):
arm64: dts: mt8183: add efuse and Mediatek Chip id node to read
Zhiyong Tao (2):
arm64: dts: mt8183: add pinctrl device node
arm64: dts: mt8183: Add auxadc device node
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 140 ++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 447 ++++++++++++++++++++
3 files changed, 588 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
--
1.8.1.1.dirty
From: Zhiyong Tao <[email protected]>
Add auxadc device node for MT8183
Signed-off-by: Zhiyong Tao <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
This patch is based on patch "https://patchwork.kernel.org/patch/10913941/".
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 10 ++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 9b52559..49909ac 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -26,6 +26,10 @@
};
};
+&auxadc {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index e74ea21..5672c18 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -245,6 +245,16 @@
clock-names = "spi", "wrap";
};
+ auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt8183-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8183-uart",
"mediatek,mt6577-uart";
--
1.8.1.1.dirty
From: Ben Ho <[email protected]>
Add basic chip support for Mediatek 8183, include
uart node with correct uart clocks, pwrap device
Add clock controller nodes, include topckgen, infracfg,
apmixedsys and subsystem.
Signed-off-by: Ben Ho <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
Signed-off-by: Seiya Wang <[email protected]>
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Hsin-Hsiung Wang <[email protected]>
Signed-off-by: Eddie Huang <[email protected]>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 311 ++++++++++++++++++++++++++++
3 files changed, 343 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index e8f952f..458bbc4 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
new file mode 100644
index 0000000..9b52559
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ben Ho <[email protected]>
+ * Erin Lo <[email protected]>
+ */
+
+/dts-v1/;
+#include "mt8183.dtsi"
+
+/ {
+ model = "MediaTek MT8183 evaluation board";
+ compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
new file mode 100644
index 0000000..08274bf
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ben Ho <[email protected]>
+ * Erin Lo <[email protected]>
+ */
+
+#include <dt-bindings/clock/mt8183-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "mediatek,mt8183";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x102>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x103>;
+ enable-method = "psci";
+ };
+ };
+
+ pmu-a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
+ };
+
+ pmu-a73 {
+ compatible = "arm,cortex-a73-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ mcucfg: syscon@c530000 {
+ compatible = "mediatek,mt8183-mcucfg", "syscon";
+ reg = <0 0x0c530000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@c530a80 {
+ compatible = "mediatek,mt8183-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x0c530a80 0 0x50>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8183-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8183-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8183-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8183-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
+ <&infracfg CLK_INFRA_PMIC_AP>;
+ clock-names = "spi", "wrap";
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8183-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ audiosys: syscon@11220000 {
+ compatible = "mediatek,mt8183-audiosys", "syscon";
+ reg = <0 0x11220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt8183-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8183-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15020000 {
+ compatible = "mediatek,mt8183-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8183-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8183-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_conn: syscon@19000000 {
+ compatible = "mediatek,mt8183-ipu_conn", "syscon";
+ reg = <0 0x19000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_adl: syscon@19010000 {
+ compatible = "mediatek,mt8183-ipu_adl", "syscon";
+ reg = <0 0x19010000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_core0: syscon@19180000 {
+ compatible = "mediatek,mt8183-ipu_core0", "syscon";
+ reg = <0 0x19180000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipu_core1: syscon@19280000 {
+ compatible = "mediatek,mt8183-ipu_core1", "syscon";
+ reg = <0 0x19280000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@1a000000 {
+ compatible = "mediatek,mt8183-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
--
1.8.1.1.dirty
From: Michael Mei <[email protected]>
support for reading chip ID and efuse
Signed-off-by: Michael Mei <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
This patch is based on this patch:
https://patchwork.kernel.org/patch/10953029/
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 2e3063f..c2749c4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -156,6 +156,15 @@
compatible = "simple-bus";
ranges;
+ soc_data: soc_data@8000000 {
+ compatible = "mediatek,mt8183-efuse",
+ "mediatek,efuse";
+ reg = <0 0x08000000 0 0x0010>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
@@ -369,6 +378,12 @@
#clock-cells = <1>;
};
+ efuse: efuse@11f10000 {
+ compatible = "mediatek,mt8183-efuse",
+ "mediatek,efuse";
+ reg = <0 0x11f10000 0 0x1000>;
+ };
+
mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
--
1.8.1.1.dirty
From: "Hsin-Yi, Wang" <[email protected]>
Pinned the frequency to the max and run dhrystone to get the value.
little cpu: 11071 (max freq: 1989000)
big cpu: 15293 (max freq: 1989000)
11071 : 15293 ~= 741 : 1024
Signed-off-by: Erin Lo <[email protected]>
Signed-off-by: Hsin-Yi Wang <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 08274bf..5b34ec6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -56,6 +56,7 @@
compatible = "arm,cortex-a53";
reg = <0x000>;
enable-method = "psci";
+ capacity-dmips-mhz = <741>;
};
cpu1: cpu@1 {
@@ -63,6 +64,7 @@
compatible = "arm,cortex-a53";
reg = <0x001>;
enable-method = "psci";
+ capacity-dmips-mhz = <741>;
};
cpu2: cpu@2 {
@@ -70,6 +72,7 @@
compatible = "arm,cortex-a53";
reg = <0x002>;
enable-method = "psci";
+ capacity-dmips-mhz = <741>;
};
cpu3: cpu@3 {
@@ -77,6 +80,7 @@
compatible = "arm,cortex-a53";
reg = <0x003>;
enable-method = "psci";
+ capacity-dmips-mhz = <741>;
};
cpu4: cpu@100 {
@@ -84,6 +88,7 @@
compatible = "arm,cortex-a73";
reg = <0x100>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
};
cpu5: cpu@101 {
@@ -91,6 +96,7 @@
compatible = "arm,cortex-a73";
reg = <0x101>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
};
cpu6: cpu@102 {
@@ -98,6 +104,7 @@
compatible = "arm,cortex-a73";
reg = <0x102>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
};
cpu7: cpu@103 {
@@ -105,6 +112,7 @@
compatible = "arm,cortex-a73";
reg = <0x103>;
enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
};
};
--
1.8.1.1.dirty
From: Zhiyong Tao <[email protected]>
The commit adds pinctrl device node for mt8183
Signed-off-by: Zhiyong Tao <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b34ec6..e74ea21 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include "mt8183-pinfunc.h"
/ {
compatible = "mediatek,mt8183";
@@ -204,6 +205,30 @@
#clock-cells = <1>;
};
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8183-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11f20000 0 0x1000>,
+ <0 0x11e80000 0 0x1000>,
+ <0 0x11e70000 0 0x1000>,
+ <0 0x11e90000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d20000 0 0x1000>,
+ <0 0x11c50000 0 0x1000>,
+ <0 0x11f30000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "iocfg0", "iocfg1", "iocfg2",
+ "iocfg3", "iocfg4", "iocfg5",
+ "iocfg6", "iocfg7", "iocfg8",
+ "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 192>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ };
+
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8183-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
--
1.8.1.1.dirty
Add spi DTS node to the mt8183 and mt8183-evb.
Signed-off-by: Mengqi Zhang <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 105 ++++++++++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 78 +++++++++++++++++++++
2 files changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 49909ac..d8e555c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -30,6 +30,111 @@
status = "okay";
};
+&pio {
+ spi_pins_0: spi0{
+ pins_spi{
+ pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
+ <PINMUX_GPIO86__FUNC_SPI0_CSB>,
+ <PINMUX_GPIO87__FUNC_SPI0_MO>,
+ <PINMUX_GPIO88__FUNC_SPI0_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi_pins_1: spi1{
+ pins_spi{
+ pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
+ <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
+ <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
+ <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi_pins_2: spi2{
+ pins_spi{
+ pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
+ <PINMUX_GPIO1__FUNC_SPI2_MO>,
+ <PINMUX_GPIO2__FUNC_SPI2_CLK>,
+ <PINMUX_GPIO94__FUNC_SPI2_MI>;
+ bias-disable;
+ };
+ };
+
+ spi_pins_3: spi3{
+ pins_spi{
+ pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
+ <PINMUX_GPIO22__FUNC_SPI3_CSB>,
+ <PINMUX_GPIO23__FUNC_SPI3_MO>,
+ <PINMUX_GPIO24__FUNC_SPI3_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi_pins_4: spi4{
+ pins_spi{
+ pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
+ <PINMUX_GPIO18__FUNC_SPI4_CSB>,
+ <PINMUX_GPIO19__FUNC_SPI4_MO>,
+ <PINMUX_GPIO20__FUNC_SPI4_CLK>;
+ bias-disable;
+ };
+ };
+
+ spi_pins_5: spi5{
+ pins_spi{
+ pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
+ <PINMUX_GPIO14__FUNC_SPI5_CSB>,
+ <PINMUX_GPIO15__FUNC_SPI5_MO>,
+ <PINMUX_GPIO16__FUNC_SPI5_CLK>;
+ bias-disable;
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins_0>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins_1>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins_2>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&spi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins_3>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&spi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins_4>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+};
+
+&spi5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins_5>;
+ mediatek,pad-select = <0>;
+ status = "okay";
+
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5672c18..2e3063f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -285,6 +285,84 @@
status = "disabled";
};
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt8183-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
+ <&topckgen CLK_TOP_MUX_SPI>,
+ <&infracfg CLK_INFRA_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi1: spi@11010000 {
+ compatible = "mediatek,mt8183-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
+ <&topckgen CLK_TOP_MUX_SPI>,
+ <&infracfg CLK_INFRA_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi@11012000 {
+ compatible = "mediatek,mt8183-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
+ <&topckgen CLK_TOP_MUX_SPI>,
+ <&infracfg CLK_INFRA_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi3: spi@11013000 {
+ compatible = "mediatek,mt8183-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
+ <&topckgen CLK_TOP_MUX_SPI>,
+ <&infracfg CLK_INFRA_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi4: spi@11018000 {
+ compatible = "mediatek,mt8183-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
+ <&topckgen CLK_TOP_MUX_SPI>,
+ <&infracfg CLK_INFRA_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi5: spi@11019000 {
+ compatible = "mediatek,mt8183-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
+ <&topckgen CLK_TOP_MUX_SPI>,
+ <&infracfg CLK_INFRA_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
audiosys: syscon@11220000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
--
1.8.1.1.dirty
On 27/05/2019 11:04, Erin Lo wrote:
> MT8183 is a SoC based on 64bit ARMv8 architecture.
> It contains 4 CA53 and 4 CA73 cores.
> MT8183 share many HW IP with MT65xx series.
> This patchset was tested on MT8183 evaluation board and use correct clock to shell.
>
> Based on v5.2-rc1
>
Pushed all to v5.2-next/dts64
Please send patches to update the bindings of auxadc and efuse. They use the
fallback right now, but we should make sure to have the binding in sync.
Regards,
Matthias
> Change in v11:
> New add spi node, efuse node, pinctrl node, auxadc node, and capacity-dmips-mhz field
>
> Change in v10:
> Add the L2 cache node to prevent warning on unable to detect cache
> hierarchy.
>
> Change in v9:
> Remove pio node since binding is not documented yet
>
> Change in v8:
> 1. Fix interrupt-parent of pio node
> 2. Remove pinfunc.h and spi node patches
>
> Change in v7:
> 1. Place all the MMIO peripherals under one or more simple-bus nodes
> 2. Make the pinfunc.h and spi node into seperate patch
> 3. Modify SPIs pamerater from 4 back to 3
> and remove patch "support 4 interrupt parameters for sysirq"
> 4. Rename intpol-controller to interrupt-controller
> 5. Rename pinctrl@1000b000 to pinctrl@10005000
>
> Change in v6:
> 1. Remove power and iommu nodes
> 2. Fix dtb build warning
> 3. Fix pinctrl binding doc
> 4. Fix '_' in node names
>
> Change in v5:
> 1. Collect all device tree nodes to the last patch
> 2. Add PMU
> 3. Add Signed-off-by
> 4. Remove clock driver code and binding doc
> 5. Add pinctrl, iommu, spi, and pwrap nodes
>
> Change in v4:
> 1. Correct syntax error in dtsi
> 2. Add MT8183 clock support
>
> Change in v3:
> 1. Fill out GICC, GICH, GICV regions
> 2. Update Copyright to 2018
>
> Change in v2:
> 1. Split dt-bindings into different patches
> 2. Correct bindings for supported SoCs (mtk-uart.txt)
>
> Ben Ho (1):
> arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and
> Makefile
>
> Erin Lo (1):
> arm64: dts: mt8183: add spi node
>
> Hsin-Yi, Wang (1):
> arm64: dts: mt8183: add capacity-dmips-mhz
>
> Michael Mei (1):
> arm64: dts: mt8183: add efuse and Mediatek Chip id node to read
>
> Zhiyong Tao (2):
> arm64: dts: mt8183: add pinctrl device node
> arm64: dts: mt8183: Add auxadc device node
>
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 140 ++++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 447 ++++++++++++++++++++
> 3 files changed, 588 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
>
> --
> 1.8.1.1.dirty
>