The native timers IP block found on Tegra SoCs implements a watchdog
timer that can be used to recover from system hangs. This series of
patches adds support for watchdog timers available on Tegra186,
Tegra194 and Tegra234 SOC's.
To keep the history intact, I added Tegra234 driver change as separate.
The original patchset is an old one authored by Thierry.
Kartik (4):
dt-bindings: timer: Add Tegra186 & Tegra234 Timer
clocksource/drivers/timer-tegra186: Add support for Tegra234 SoC
arm64: tegra: Enable native timers on Tegra186
arm64: tegra: Enable native timers on Tegra234
Thierry Reding (2):
clocksource: Add Tegra186 timers support
arm64: tegra: Enable native timers on Tegra194
.../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 22 +
drivers/clocksource/Kconfig | 8 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-tegra186.c | 514 ++++++++++++++++++
7 files changed, 673 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
create mode 100644 drivers/clocksource/timer-tegra186.c
--
2.17.1
From: Thierry Reding <[email protected]>
The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add and
enable the device tree node on Tegra194.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Kartik <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 9566c6388ed9..4b37aec69448 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -698,6 +698,22 @@
};
};
+ timer@3010000 {
+ compatible = "nvidia,tegra186-timer";
+ reg = <0x03010000 0x000e0000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
uarta: serial@3100000 {
compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
reg = <0x03100000 0x40>;
--
2.17.1
The timer IP block present on Tegra234 SoC supports watchdog timer
functionality that can be used to recover from system hangs. The
watchdog timer uses a timer in the background for countdown.
Signed-off-by: Kartik <[email protected]>
---
drivers/clocksource/timer-tegra186.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c
index 4515517c87a5..ea742889ee06 100644
--- a/drivers/clocksource/timer-tegra186.c
+++ b/drivers/clocksource/timer-tegra186.c
@@ -486,8 +486,14 @@ static const struct tegra186_timer_soc tegra186_timer = {
.num_wdts = 3,
};
+static const struct tegra186_timer_soc tegra234_timer = {
+ .num_timers = 16,
+ .num_wdts = 3,
+};
+
static const struct of_device_id tegra186_timer_of_match[] = {
{ .compatible = "nvidia,tegra186-timer", .data = &tegra186_timer },
+ { .compatible = "nvidia,tegra234-timer", .data = &tegra234_timer },
{ }
};
MODULE_DEVICE_TABLE(of, tegra186_timer_of_match);
--
2.17.1
The Tegra186 timer provides ten 29-bit timer counters and one 32-bit
timestamp counter. The Tegra234 timer provides sixteen 29-bit timer
counters and one 32-bit timestamp counter. Each NV timer selects its
timing reference signal from the 1 MHz reference generated by USEC,
TSC or either clk_m or OSC. Each TMR can be programmed to generate
one-shot, periodic, or watchdog interrupts.
Signed-off-by: Kartik <[email protected]>
---
.../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++
1 file changed, 111 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
new file mode 100644
index 000000000000..5dc091532cd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
@@ -0,0 +1,111 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra186 timer
+
+maintainers:
+ - Thierry Reding <[email protected]>
+
+description: >
+ The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
+ counter. Each NV timer selects its timing reference signal from the 1 MHz
+ reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
+ programmed to generate one-shot, periodic, or watchdog interrupts.
+
+
+properties:
+ compatible:
+ oneOf:
+ - const: nvidia,tegra186-timer
+ description: >
+ The Tegra186 timer provides ten 29-bit timer counters.
+ - const: nvidia,tegra234-timer
+ description: >
+ The Tegra234 timer provides sixteen 29-bit timer counters.
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra186-timer
+ then:
+ properties:
+ interrupts:
+ minItems: 1
+ maxItems: 10
+ description: >
+ A list of 10 interrupts; one per each timer channels 0 through 9.
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra234-timer
+ then:
+ properties:
+ interrupts:
+ minItems: 1
+ maxItems: 16
+ description: >
+ A list of 16 interrupts; one per each timer channels 0 through 15.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ timer@3010000 {
+ compatible = "nvidia,tegra186-timer";
+ reg = <0x03010000 0x000e0000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ timer@2080000 {
+ compatible = "nvidia,tegra234-timer";
+ reg = <0x02080000 0x00121000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.17.1
The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add and
enable the device tree node on Tegra234.
Signed-off-by: Kartik <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index cf611eff7f6b..aa8ceb3c329b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -519,6 +519,28 @@
status = "okay";
};
+ timer@2080000 {
+ compatible = "nvidia,tegra234-timer";
+ reg = <0x02080000 0x00121000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+ };
+
gpio: gpio@2200000 {
compatible = "nvidia,tegra234-gpio";
reg-names = "security", "gpio";
--
2.17.1
On Wed, Jun 29, 2022 at 11:58:59PM +0530, Kartik wrote:
> The Tegra186 timer provides ten 29-bit timer counters and one 32-bit
> timestamp counter. The Tegra234 timer provides sixteen 29-bit timer
> counters and one 32-bit timestamp counter. Each NV timer selects its
> timing reference signal from the 1 MHz reference generated by USEC,
> TSC or either clk_m or OSC. Each TMR can be programmed to generate
> one-shot, periodic, or watchdog interrupts.
>
> Signed-off-by: Kartik <[email protected]>
> ---
> .../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++
> 1 file changed, 111 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
Rob, I've been wondering about patch application with these DT bindings.
In the past I've preferred to apply these along with the driver changes
that implement the bindings. I realize now that that's perhaps a bit
naive because we've had cases where the driver doesn't fully implement
everything in the binding as well as cases where the bindings are
upstreamed without the driver necessarily being upstreamed at the same
time.
So I'm thinking that it makes more sense to apply the DT bindings to the
same tree as the DT changes that add corresponding DT nodes. This would
also get rid of the (usually temporary) inconsistencies when running the
DT validation (and even just something like checkpatch) on a DT tree
that doesn't have corresponding DT bindings.
Do you have any strong preference on this?
Thierry
On Wed, Jun 29, 2022 at 11:59:01PM +0530, Kartik wrote:
> The timer IP block present on Tegra234 SoC supports watchdog timer
> functionality that can be used to recover from system hangs. The
> watchdog timer uses a timer in the background for countdown.
>
> Signed-off-by: Kartik <[email protected]>
> ---
> drivers/clocksource/timer-tegra186.c | 6 ++++++
> 1 file changed, 6 insertions(+)
Acked-by: Thierry Reding <[email protected]>
On 29/06/2022 19:28, Kartik wrote:
> The Tegra186 timer provides ten 29-bit timer counters and one 32-bit
> timestamp counter. The Tegra234 timer provides sixteen 29-bit timer
> counters and one 32-bit timestamp counter. Each NV timer selects its
> timing reference signal from the 1 MHz reference generated by USEC,
> TSC or either clk_m or OSC. Each TMR can be programmed to generate
> one-shot, periodic, or watchdog interrupts.
>
> Signed-off-by: Kartik <[email protected]>
> ---
> .../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++
> 1 file changed, 111 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> new file mode 100644
> index 000000000000..5dc091532cd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> @@ -0,0 +1,111 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: NVIDIA Tegra186 timer
> +
> +maintainers:
> + - Thierry Reding <[email protected]>
> +
> +description: >
> + The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
> + counter. Each NV timer selects its timing reference signal from the 1 MHz
> + reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
> + programmed to generate one-shot, periodic, or watchdog interrupts.
> +
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: nvidia,tegra186-timer
> + description: >
> + The Tegra186 timer provides ten 29-bit timer counters.
> + - const: nvidia,tegra234-timer
> + description: >
> + The Tegra234 timer provides sixteen 29-bit timer counters.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra186-timer
> + then:
> + properties:
> + interrupts:
> + minItems: 1
> + maxItems: 10
> + description: >
> + A list of 10 interrupts; one per each timer channels 0 through 9.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra234-timer
> + then:
> + properties:
> + interrupts:
> + minItems: 1
> + maxItems: 16
> + description: >
> + A list of 16 interrupts; one per each timer channels 0 through 15.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + timer@3010000 {
> + compatible = "nvidia,tegra186-timer";
> + reg = <0x03010000 0x000e0000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + timer@2080000 {
> + compatible = "nvidia,tegra234-timer";
> + reg = <0x02080000 0x00121000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
Reviewed-by: Jon Hunter <[email protected]>
Thanks!
Jon
--
nvpublic
On 29/06/2022 19:29, Kartik wrote:
> The timer IP block present on Tegra234 SoC supports watchdog timer
> functionality that can be used to recover from system hangs. The
> watchdog timer uses a timer in the background for countdown.
>
> Signed-off-by: Kartik <[email protected]>
> ---
> drivers/clocksource/timer-tegra186.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c
> index 4515517c87a5..ea742889ee06 100644
> --- a/drivers/clocksource/timer-tegra186.c
> +++ b/drivers/clocksource/timer-tegra186.c
> @@ -486,8 +486,14 @@ static const struct tegra186_timer_soc tegra186_timer = {
> .num_wdts = 3,
> };
>
> +static const struct tegra186_timer_soc tegra234_timer = {
> + .num_timers = 16,
> + .num_wdts = 3,
> +};
> +
> static const struct of_device_id tegra186_timer_of_match[] = {
> { .compatible = "nvidia,tegra186-timer", .data = &tegra186_timer },
> + { .compatible = "nvidia,tegra234-timer", .data = &tegra234_timer },
> { }
> };
> MODULE_DEVICE_TABLE(of, tegra186_timer_of_match);
Reviewed-by: Jon Hunter <[email protected]>
Thanks!
Jon
--
nvpublic
On 29/06/2022 19:29, Kartik wrote:
> The native timers IP block found on NVIDIA Tegra SoCs implements a
> watchdog timer that can be used to recover from system hangs. Add and
> enable the device tree node on Tegra234.
>
> Signed-off-by: Kartik <[email protected]>
> ---
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index cf611eff7f6b..aa8ceb3c329b 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -519,6 +519,28 @@
> status = "okay";
> };
>
> + timer@2080000 {
> + compatible = "nvidia,tegra234-timer";
> + reg = <0x02080000 0x00121000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> +
> gpio: gpio@2200000 {
> compatible = "nvidia,tegra234-gpio";
> reg-names = "security", "gpio";
Reviewed-by: Jon Hunter <[email protected]>
Thanks!
Jon
--
nvpublic
On 29/06/2022 19:29, Kartik wrote:
> From: Thierry Reding <[email protected]>
>
> The native timers IP block found on NVIDIA Tegra SoCs implements a
> watchdog timer that can be used to recover from system hangs. Add and
> enable the device tree node on Tegra194.
>
> Signed-off-by: Thierry Reding <[email protected]>
> Signed-off-by: Kartik <[email protected]>
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 9566c6388ed9..4b37aec69448 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -698,6 +698,22 @@
> };
> };
>
> + timer@3010000 {
> + compatible = "nvidia,tegra186-timer";
> + reg = <0x03010000 0x000e0000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> + };
> +
> uarta: serial@3100000 {
> compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
> reg = <0x03100000 0x40>;
Reviewed-by: Jon Hunter <[email protected]>
Thanks!
Jon
--
nvpublic
On Wed, Jun 29, 2022 at 11:58:59PM +0530, Kartik wrote:
> The Tegra186 timer provides ten 29-bit timer counters and one 32-bit
> timestamp counter. The Tegra234 timer provides sixteen 29-bit timer
> counters and one 32-bit timestamp counter. Each NV timer selects its
> timing reference signal from the 1 MHz reference generated by USEC,
> TSC or either clk_m or OSC. Each TMR can be programmed to generate
> one-shot, periodic, or watchdog interrupts.
>
> Signed-off-by: Kartik <[email protected]>
> ---
> .../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++
> 1 file changed, 111 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> new file mode 100644
> index 000000000000..5dc091532cd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
> @@ -0,0 +1,111 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: NVIDIA Tegra186 timer
> +
> +maintainers:
> + - Thierry Reding <[email protected]>
> +
> +description: >
> + The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
> + counter. Each NV timer selects its timing reference signal from the 1 MHz
> + reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
> + programmed to generate one-shot, periodic, or watchdog interrupts.
> +
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: nvidia,tegra186-timer
> + description: >
> + The Tegra186 timer provides ten 29-bit timer counters.
> + - const: nvidia,tegra234-timer
> + description: >
> + The Tegra234 timer provides sixteen 29-bit timer counters.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts: true
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra186-timer
> + then:
> + properties:
> + interrupts:
> + minItems: 1
> + maxItems: 10
> + description: >
> + A list of 10 interrupts; one per each timer channels 0 through 9.
The schema says it is a list of 1 to 10 interrupts. Which is it. Surely
the h/w is fixed. If so, drop 'minItems' and the first sentence.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nvidia,tegra234-timer
> + then:
> + properties:
> + interrupts:
> + minItems: 1
> + maxItems: 16
> + description: >
> + A list of 16 interrupts; one per each timer channels 0 through 15.
ditto
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + timer@3010000 {
> + compatible = "nvidia,tegra186-timer";
> + reg = <0x03010000 0x000e0000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + timer@2080000 {
> + compatible = "nvidia,tegra234-timer";
> + reg = <0x02080000 0x00121000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
> --
> 2.17.1
>
>
On Thu, Jun 30, 2022 at 11:13:50AM +0200, Thierry Reding wrote:
> On Wed, Jun 29, 2022 at 11:58:59PM +0530, Kartik wrote:
> > The Tegra186 timer provides ten 29-bit timer counters and one 32-bit
> > timestamp counter. The Tegra234 timer provides sixteen 29-bit timer
> > counters and one 32-bit timestamp counter. Each NV timer selects its
> > timing reference signal from the 1 MHz reference generated by USEC,
> > TSC or either clk_m or OSC. Each TMR can be programmed to generate
> > one-shot, periodic, or watchdog interrupts.
> >
> > Signed-off-by: Kartik <[email protected]>
> > ---
> > .../bindings/timer/nvidia,tegra186-timer.yaml | 111 ++++++++++++++++++
> > 1 file changed, 111 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml
>
> Rob, I've been wondering about patch application with these DT bindings.
> In the past I've preferred to apply these along with the driver changes
> that implement the bindings. I realize now that that's perhaps a bit
> naive because we've had cases where the driver doesn't fully implement
> everything in the binding as well as cases where the bindings are
> upstreamed without the driver necessarily being upstreamed at the same
> time.
>
> So I'm thinking that it makes more sense to apply the DT bindings to the
> same tree as the DT changes that add corresponding DT nodes. This would
> also get rid of the (usually temporary) inconsistencies when running the
> DT validation (and even just something like checkpatch) on a DT tree
> that doesn't have corresponding DT bindings.
The checkpatch warnings apply for the driver too. Though the current
checks are pretty hacky (extract the compatible and grep the tree for
it). I'm working on some more exact checks, but they will depend on
processing the schemas and probably a built kernel/modules.
> Do you have any strong preference on this?
Well, the documented process is for bindings go via subsystem trees, so
that's a wider discussion to change.
I prefer the bindings get accepted by subsystem maintainers that know
that class of h/w and also have little motivation to accept them.
Granted, some don't even look at bindings or only look if DT maintainers
reviewed. If anyone else is going to look for what could be common or
not, it's the subsystem maintainers, not sub-arch maintainers.
Obviously, this is all generalizations and there's exceptions. It's
similar reasons why I don't want to see bindings moved out of the
kernel. We'd lose the subsystem maintainers review.
That being said, I might feel differently when platforms have 0 warnings
and any temporary warnings are problematic.
Rob