This series of patches will add initial supports
for QPIC SPI NAND driver.
Currently this driver support following commands
-- RESET
-- READ ID
-- BLOCK ERASE
-- PAGE READ
-- PAGE WRITE
-- GET FEATURE
-- SET FEATURE
-- BAD BLOCK CHECK
This driver has been tested with dd command with read/write page
with multiple file size 1MiB, 10MiB,40MiB etc.
Also tested with "mtd" command like mtd erase, mtd write, mtd verify etc.
Need help to test these all patches on SDX65 and SDX75 platform.
Md Sadre Alam (5):
spi: dt-bindings: add binding doc for spi-qpic-snand
drivers: mtd: nand: Add qpic_common API file
spi: spi-qpic: Add qpic spi nand driver support
arm64: dts: qcom: ipq9574: Add SPI nand support
arm64: dts: qcom: ipq9574: Disable eMMC node
.../bindings/spi/qcom,spi-qpic-snand.yaml | 82 ++
.../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +
arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 2 +-
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qpic_common.c | 794 +++++++++++
drivers/mtd/nand/raw/qcom_nandc.c | 1226 +----------------
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-qpic-snand.c | 1025 ++++++++++++++
include/linux/mtd/nand-qpic-common.h | 548 ++++++++
11 files changed, 2547 insertions(+), 1211 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
create mode 100644 drivers/mtd/nand/qpic_common.c
create mode 100644 drivers/spi/spi-qpic-snand.c
create mode 100644 include/linux/mtd/nand-qpic-common.h
--
2.34.1
Add qpic spi nand driver support. The spi nand
driver currently supported the below commands.
-- RESET
-- READ ID
-- SET FEATURE
-- GET FEATURE
-- READ PAGE
-- WRITE PAGE
-- ERASE PAGE
Co-developed-by: Sricharan Ramabadhran <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Md Sadre Alam <[email protected]>
---
drivers/mtd/nand/qpic_common.c | 8 +
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-qpic-snand.c | 1025 ++++++++++++++++++++++++++
include/linux/mtd/nand-qpic-common.h | 62 +-
5 files changed, 1104 insertions(+), 1 deletion(-)
create mode 100644 drivers/spi/spi-qpic-snand.c
diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
index 4d74ba888028..7aa3c56d210a 100644
--- a/drivers/mtd/nand/qpic_common.c
+++ b/drivers/mtd/nand/qpic_common.c
@@ -132,6 +132,14 @@ __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
return ®s->read_location_last2;
case NAND_READ_LOCATION_LAST_CW_3:
return ®s->read_location_last3;
+ case NAND_FLASH_SPI_CFG:
+ return ®s->spi_cfg;
+ case NAND_NUM_ADDR_CYCLES:
+ return ®s->num_addr_cycle;
+ case NAND_BUSY_CHECK_WAIT_CNT:
+ return ®s->busy_wait_cnt;
+ case NAND_FLASH_FEATURES:
+ return ®s->flash_feature;
default:
return NULL;
}
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bc7021da2fe9..536448700d7b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -882,6 +882,15 @@ config SPI_QCOM_QSPI
help
QSPI(Quad SPI) driver for Qualcomm QSPI controller.
+config SPI_QPIC_SNAND
+ tristate "QPIC SNAND controller"
+ default y
+ depends on ARCH_QCOM
+ help
+ QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
+ QPIC controller supports both parallel nand and serial nand.
+ This config will enable serial nand driver for QPIC controller.
+
config SPI_QUP
tristate "Qualcomm SPI controller with QUP interface"
depends on ARCH_QCOM || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..1ac3bac35007 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -153,6 +153,7 @@ obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
obj-$(CONFIG_SPI_ZYNQ_QSPI) += spi-zynq-qspi.o
obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o
obj-$(CONFIG_SPI_AMD) += spi-amd.o
+obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
# SPI slave protocol handlers
obj-$(CONFIG_SPI_SLAVE_TIME) += spi-slave-time.o
diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
new file mode 100644
index 000000000000..0fc529eed3e3
--- /dev/null
+++ b/drivers/spi/spi-qpic-snand.c
@@ -0,0 +1,1025 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Authors:
+ * Md Sadre Alam <[email protected]>
+ * Sricharan R <[email protected]>
+ * Varadarajan Narayanan <[email protected]>
+ */
+
+#include <linux/mtd/spinand.h>
+#include <linux/mtd/nand-qpic-common.h>
+
+/* QSPI NAND config reg bits */
+#define LOAD_CLK_CNTR_INIT_EN BIT(28)
+#define CLK_CNTR_INIT_VAL_VEC 0x924
+#define FEA_STATUS_DEV_ADDR 0xc0
+#define SPI_CFG BIT(0)
+#define SPI_NUM_ADDR 0xDA4DB
+#define SPI_WAIT_CNT 0x10
+#define QPIC_QSPI_NUM_CS 1
+#define SPI_TRANSFER_MODE_x1 BIT(29)
+#define SPI_TRANSFER_MODE_x4 (3 << 29)
+#define SPI_WP BIT(28)
+#define SPI_HOLD BIT(27)
+#define QPIC_SET_FEATURE BIT(31)
+
+#define SPINAND_RESET 0xff
+#define SPINAND_READID 0x9f
+#define SPINAND_GET_FEATURE 0x0f
+#define SPINAND_SET_FEATURE 0x1f
+#define SPINAND_READ 0x13
+#define SPINAND_ERASE 0xd8
+#define SPINAND_WRITE_EN 0x06
+#define SPINAND_PROGRAM_EXECUTE 0x10
+#define SPINAND_PROGRAM_LOAD 0x84
+
+#define snandc_set_read_loc_first(snandc, reg, cw_offset, read_size, is_last_read_loc) \
+snandc_set_reg(snandc, reg, \
+ ((cw_offset) << READ_LOCATION_OFFSET) | \
+ ((read_size) << READ_LOCATION_SIZE) | \
+ ((is_last_read_loc) << READ_LOCATION_LAST))
+
+#define snandc_set_read_loc_last(snandc, reg, cw_offset, read_size, is_last_read_loc) \
+snandc_set_reg(snandc, reg, \
+ ((cw_offset) << READ_LOCATION_OFFSET) | \
+ ((read_size) << READ_LOCATION_SIZE) | \
+ ((is_last_read_loc) << READ_LOCATION_LAST))
+
+struct qpic_snand_op {
+ u32 cmd_reg;
+ u32 addr1_reg;
+ u32 addr2_reg;
+};
+
+struct snandc_read_status {
+ __le32 snandc_flash;
+ __le32 snandc_buffer;
+ __le32 snandc_erased_cw;
+};
+
+void snandc_set_reg(struct qcom_nand_controller *snandc, int offset, u32 val)
+{
+ struct nandc_regs *regs = snandc->regs;
+ __le32 *reg;
+
+ reg = offset_to_nandc_reg(regs, offset);
+
+ if (reg)
+ *reg = cpu_to_le32(val);
+}
+
+static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
+{
+ struct nand_ecc_engine *eng = nand->ecc.engine;
+
+ return container_of(eng, struct qcom_nand_controller, ecc_eng);
+}
+
+static int qcom_snand_init(struct qcom_nand_controller *snandc)
+{
+ u32 snand_cfg_val = 0x0;
+ int ret;
+
+ snand_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | (CLK_CNTR_INIT_VAL_VEC << 16)
+ | (FEA_STATUS_DEV_ADDR << 8) | SPI_CFG);
+
+ snandc_set_reg(snandc, NAND_FLASH_SPI_CFG, 0);
+ snandc_set_reg(snandc, NAND_FLASH_SPI_CFG, snand_cfg_val);
+ snandc_set_reg(snandc, NAND_NUM_ADDR_CYCLES, SPI_NUM_ADDR);
+ snandc_set_reg(snandc, NAND_BUSY_CHECK_WAIT_CNT, SPI_WAIT_CNT);
+
+ write_reg_dma(snandc, NAND_FLASH_SPI_CFG, 1, 0);
+ write_reg_dma(snandc, NAND_FLASH_SPI_CFG, 1, 0);
+
+ snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
+ snandc_set_reg(snandc, NAND_FLASH_SPI_CFG, snand_cfg_val);
+
+ write_reg_dma(snandc, NAND_FLASH_SPI_CFG, 1, 0);
+
+ write_reg_dma(snandc, NAND_NUM_ADDR_CYCLES, 1, 0);
+ write_reg_dma(snandc, NAND_BUSY_CHECK_WAIT_CNT, 1, NAND_BAM_NEXT_SGL);
+
+ ret = submit_descs(snandc);
+ if (ret)
+ dev_err(snandc->dev, "failure in sbumitting spiinit descriptor\n");
+
+ return 0;
+}
+
+static int qcom_snand_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
+ struct qpic_ecc *qecc = snandc->ecc;
+
+ if (section > 1)
+ return -ERANGE;
+
+ if (!section) {
+ oobregion->length = (qecc->bytes * (qecc->steps - 1)) + qecc->bbm_size;
+ oobregion->offset = 0;
+ } else {
+ oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
+ oobregion->offset = mtd->oobsize - oobregion->length;
+ }
+
+ return 0;
+}
+
+static int qcom_snand_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
+ struct qpic_ecc *qecc = snandc->ecc;
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->length = qecc->steps * 4;
+ oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops qcom_snand_ooblayout = {
+ .ecc = qcom_snand_ooblayout_ecc,
+ .free = qcom_snand_ooblayout_free,
+};
+
+static int qpic_snand_ecc_init_ctx_pipelined(struct nand_device *nand)
+{
+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
+ struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
+ struct nand_ecc_props *reqs = &nand->ecc.requirements;
+ struct nand_ecc_props *user = &nand->ecc.user_conf;
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+ int step_size = 0, strength = 0, desired_correction = 0, steps;
+ bool ecc_user = false;
+ int cwperpage, bad_block_byte;
+ struct qpic_ecc *ecc_cfg;
+
+ cwperpage = mtd->writesize / NANDC_STEP_SIZE;
+
+ ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
+ if (!ecc_cfg)
+ return -ENOMEM;
+
+ nand->ecc.ctx.priv = ecc_cfg;
+
+ if (user->step_size && user->strength) {
+ step_size = user->step_size;
+ strength = user->strength;
+ ecc_user = true;
+ } else if (reqs->step_size && reqs->strength) {
+ step_size = reqs->step_size;
+ strength = reqs->strength;
+ }
+
+ if (step_size && strength) {
+ steps = mtd->writesize / step_size;
+ desired_correction = steps * strength;
+ }
+
+ ecc_cfg->ecc_bytes_hw = 7;
+ ecc_cfg->spare_bytes = 4;
+ ecc_cfg->bbm_size = 1;
+ ecc_cfg->bch_enabled = true;
+ ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
+
+ ecc_cfg->steps = 4;
+ ecc_cfg->strength = 4;
+ ecc_cfg->step_size = 512;
+
+ mtd_set_ooblayout(mtd, &qcom_snand_ooblayout);
+
+ ecc_cfg->cw_data = 516;
+ ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
+ bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
+
+ ecc_cfg->cfg0 = (cwperpage - 1) << CW_PER_PAGE
+ | ecc_cfg->cw_data << UD_SIZE_BYTES
+ | 1 << DISABLE_STATUS_AFTER_WRITE
+ | 3 << NUM_ADDR_CYCLES
+ | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
+ | 0 << STATUS_BFR_READ
+ | 1 << SET_RD_MODE_AFTER_STATUS
+ | ecc_cfg->spare_bytes << SPARE_SIZE_BYTES;
+
+ ecc_cfg->cfg1 = 0 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | bad_block_byte << BAD_BLOCK_BYTE_NUM
+ | 0 << BAD_BLOCK_IN_SPARE_AREA
+ | 20 << WR_RD_BSY_GAP
+ | 0 << WIDE_FLASH
+ | ecc_cfg->bch_enabled << ENABLE_BCH_ECC;
+
+ ecc_cfg->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
+ | ecc_cfg->cw_size << UD_SIZE_BYTES
+ | 3 << NUM_ADDR_CYCLES
+ | 0 << SPARE_SIZE_BYTES;
+
+ ecc_cfg->cfg1_raw = 0 << NAND_RECOVERY_CYCLES
+ | 0 << CS_ACTIVE_BSY
+ | 17 << BAD_BLOCK_BYTE_NUM
+ | 1 << BAD_BLOCK_IN_SPARE_AREA
+ | 20 << WR_RD_BSY_GAP
+ | 0 << WIDE_FLASH
+ | 1 << DEV0_CFG1_ECC_DISABLE;
+
+ ecc_cfg->ecc_bch_cfg = !ecc_cfg->bch_enabled << ECC_CFG_ECC_DISABLE
+ | 0 << ECC_SW_RESET
+ | ecc_cfg->cw_data << ECC_NUM_DATA_BYTES
+ | 1 << ECC_FORCE_CLK_OPEN
+ | 0 << ECC_MODE
+ | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
+
+ ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
+ ecc_cfg->clrflashstatus = FS_READY_BSY_N;
+ ecc_cfg->clrreadstatus = 0xc0;
+
+ conf->step_size = ecc_cfg->step_size;
+ conf->strength = ecc_cfg->strength;
+
+ if (ecc_cfg->strength < strength)
+ dev_warn(snandc->dev, "Unable to fulfill ECC requirements of %u bits.\n", strength);
+
+ dev_info(snandc->dev, "ECC strength: %u bits per %u bytes\n",
+ ecc_cfg->strength, ecc_cfg->step_size);
+
+ return 0;
+}
+
+static void qpic_snand_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
+{
+ struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
+
+ kfree(ecc_cfg);
+}
+
+static int qpic_snand_ecc_prepare_io_req_pipelined(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
+ struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
+
+ snandc->ecc = ecc_cfg;
+ snandc->raw = false;
+ snandc->oob_read = false;
+
+ if (req->mode == MTD_OPS_RAW) {
+ if (req->ooblen)
+ snandc->oob_read = true;
+ snandc->raw = true;
+ }
+
+ return 0;
+}
+
+static int qpic_snand_ecc_finish_io_req_pipelined(struct nand_device *nand,
+ struct nand_page_io_req *req)
+{
+ struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
+ struct mtd_info *mtd = nanddev_to_mtd(nand);
+
+ if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
+ return 0;
+
+ if (snandc->ecc_stats.failed)
+ mtd->ecc_stats.failed += snandc->ecc_stats.failed;
+ mtd->ecc_stats.corrected += snandc->ecc_stats.corrected;
+
+ return snandc->ecc_stats.failed ? -EBADMSG : snandc->ecc_stats.bitflips;
+}
+
+static struct nand_ecc_engine_ops qcom_snand_ecc_engine_ops_pipelined = {
+ .init_ctx = qpic_snand_ecc_init_ctx_pipelined,
+ .cleanup_ctx = qpic_snand_ecc_cleanup_ctx_pipelined,
+ .prepare_io_req = qpic_snand_ecc_prepare_io_req_pipelined,
+ .finish_io_req = qpic_snand_ecc_finish_io_req_pipelined,
+};
+
+/* helper to configure location register values */
+static void snandc_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
+ int cw_offset, int read_size, int is_last_read_loc)
+{
+ int reg_base = NAND_READ_LOCATION_0;
+
+ if (cw == 3)
+ reg_base = NAND_READ_LOCATION_LAST_CW_0;
+
+ reg_base += reg * 4;
+
+ if (cw == 3)
+ return snandc_set_read_loc_last(snandc, reg_base, cw_offset,
+ read_size, is_last_read_loc);
+ else
+ return snandc_set_read_loc_first(snandc, reg_base, cw_offset,
+ read_size, is_last_read_loc);
+}
+
+static void
+snandc_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
+{
+ int reg = NAND_READ_LOCATION_0;
+
+ if (cw == 3)
+ reg = NAND_READ_LOCATION_LAST_CW_0;
+
+ if (snandc->props->is_bam)
+ write_reg_dma(snandc, reg, 4, NAND_BAM_NEXT_SGL);
+
+ write_reg_dma(snandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(snandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
+
+ read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
+ read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+ NAND_BAM_NEXT_SGL);
+}
+
+static int qpic_snand_block_erase(struct qcom_nand_controller *snandc)
+{
+ struct qpic_ecc *ecc_cfg = snandc->ecc;
+ int ret;
+
+ snandc->buf_count = 0;
+ snandc->buf_start = 0;
+ clear_read_regs(snandc);
+ clear_bam_transaction(snandc);
+
+ snandc_set_reg(snandc, NAND_FLASH_CMD, snandc->cmd);
+ snandc_set_reg(snandc, NAND_ADDR0, snandc->addr1);
+ snandc_set_reg(snandc, NAND_ADDR1, snandc->addr2);
+ snandc_set_reg(snandc, NAND_DEV0_CFG0, ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE));
+ snandc_set_reg(snandc, NAND_DEV0_CFG1, ecc_cfg->cfg1_raw);
+ snandc_set_reg(snandc, NAND_EXEC_CMD, 1);
+
+ write_reg_dma(snandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
+ write_reg_dma(snandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
+ write_reg_dma(snandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
+
+ ret = submit_descs(snandc);
+ if (ret) {
+ dev_err(snandc->dev, "failure to erase block\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void config_snand_single_cw_page_read(struct qcom_nand_controller *snandc,
+ bool use_ecc, int cw)
+{
+ int reg;
+
+ write_reg_dma(snandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(snandc, NAND_DEV0_CFG0, 3, 0);
+ write_reg_dma(snandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+ write_reg_dma(snandc, NAND_ERASED_CW_DETECT_CFG, 1,
+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
+
+ reg = NAND_READ_LOCATION_0;
+ if (cw == 3)
+ reg = NAND_READ_LOCATION_LAST_CW_0;
+ write_reg_dma(snandc, reg, 4, NAND_BAM_NEXT_SGL);
+ write_reg_dma(snandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(snandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
+
+ read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
+ read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, NAND_BAM_NEXT_SGL);
+}
+
+static int qpic_snand_read_oob(struct qcom_nand_controller *snandc,
+ const struct spi_mem_op *op)
+{
+ struct qpic_ecc *ecc_cfg = snandc->ecc;
+ u8 *oob_buf;
+ int size, ret;
+ int col, num_cw = 4, bbpos;
+ u32 cfg0, cfg1, ecc_bch_cfg;
+
+ oob_buf = op->data.buf.in;
+
+ clear_bam_transaction(snandc);
+ clear_read_regs(snandc);
+
+ size = ecc_cfg->cw_size;
+ col = ecc_cfg->cw_size * (num_cw - 1);
+
+ /* prepare a clean read buffer */
+ memset(snandc->data_buffer, 0xff, size);
+ snandc_set_reg(snandc, NAND_ADDR0, (snandc->addr1 | col));
+ snandc_set_reg(snandc, NAND_ADDR1, snandc->addr2);
+
+ cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
+ 0 << CW_PER_PAGE;
+ cfg1 = ecc_cfg->cfg1_raw;
+ ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
+
+ snandc_set_reg(snandc, NAND_FLASH_CMD, snandc->cmd);
+ snandc_set_reg(snandc, NAND_DEV0_CFG0, cfg0);
+ snandc_set_reg(snandc, NAND_DEV0_CFG1, cfg1);
+ snandc_set_reg(snandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
+ snandc_set_reg(snandc, NAND_EXEC_CMD, 1);
+
+ config_snand_single_cw_page_read(snandc, false, num_cw - 1);
+
+ read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
+
+ ret = submit_descs(snandc);
+ if (ret)
+ dev_err(snandc->dev, "failed to read oob\n");
+
+ nandc_read_buffer_sync(snandc, true);
+ u32 flash = le32_to_cpu(snandc->reg_read_buf[0]);
+
+ if (flash & (FS_OP_ERR | FS_MPU_ERR))
+ return -EIO;
+
+ bbpos = 2048 - ecc_cfg->cw_size * (num_cw - 1);
+ memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
+
+ return ret;
+}
+
+static int snandc_check_error(struct qcom_nand_controller *snandc)
+{
+ struct snandc_read_status *buf;
+ int i, num_cw = 4;
+ bool serial_op_err = false, erased;
+
+ nandc_read_buffer_sync(snandc, true);
+ buf = (struct snandc_read_status *)snandc->reg_read_buf;
+
+ for (i = 0; i < num_cw; i++, buf++) {
+ u32 flash, buffer, erased_cw;
+
+ flash = le32_to_cpu(buf->snandc_flash);
+ buffer = le32_to_cpu(buf->snandc_buffer);
+ erased_cw = le32_to_cpu(buf->snandc_erased_cw);
+
+ if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
+ erased = (erased_cw & ERASED_CW) == ERASED_CW ?
+ true : false;
+ } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
+ serial_op_err = true;
+ }
+ }
+
+ if (serial_op_err)
+ return -EIO;
+
+ return 0;
+}
+
+static int qpic_snand_read_page_cache(struct qcom_nand_controller *snandc,
+ const struct spi_mem_op *op)
+{
+ struct qpic_ecc *ecc_cfg = snandc->ecc;
+ u8 *data_buf;
+ int ret, i;
+ u32 cfg0, cfg1, ecc_bch_cfg, num_cw = 4;
+
+ data_buf = op->data.buf.in;
+
+ if (snandc->oob_read) {
+ return qpic_snand_read_oob(snandc, op);
+ snandc->oob_read = false;
+ }
+
+ snandc->buf_count = 0;
+ snandc->buf_start = 0;
+ clear_read_regs(snandc);
+
+ cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+ cfg1 = ecc_cfg->cfg1;
+ ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
+
+ snandc_set_reg(snandc, NAND_ADDR0, snandc->addr1);
+ snandc_set_reg(snandc, NAND_ADDR1, snandc->addr2);
+ snandc_set_reg(snandc, NAND_FLASH_CMD, snandc->cmd);
+ snandc_set_reg(snandc, NAND_DEV0_CFG0, cfg0);
+ snandc_set_reg(snandc, NAND_DEV0_CFG1, cfg1);
+ snandc_set_reg(snandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
+ snandc_set_reg(snandc, NAND_FLASH_STATUS, ecc_cfg->clrflashstatus);
+ snandc_set_reg(snandc, NAND_READ_STATUS, ecc_cfg->clrreadstatus);
+ snandc_set_reg(snandc, NAND_EXEC_CMD, 1);
+ snandc_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
+
+ clear_bam_transaction(snandc);
+
+ write_reg_dma(snandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(snandc, NAND_DEV0_CFG0, 3, 0);
+ write_reg_dma(snandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+ write_reg_dma(snandc, NAND_ERASED_CW_DETECT_CFG, 1,
+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
+
+ for (i = 0; i < num_cw; i++) {
+ int data_size;
+
+ if (i == (num_cw - 1))
+ data_size = 512 - ((num_cw - 1) << 2);
+ else
+ data_size = ecc_cfg->cw_data;
+
+ if (data_buf)
+ snandc_set_read_loc(snandc, i, 0, 0, data_size, 1);
+
+ snandc_config_cw_read(snandc, true, i);
+
+ if (data_buf)
+ read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
+ data_size, 0);
+
+ if (data_buf)
+ data_buf += data_size;
+ }
+
+ ret = submit_descs(snandc);
+ if (ret) {
+ dev_err(snandc->dev, "failure to read page/oob\n");
+ return ret;
+ }
+
+ return snandc_check_error(snandc);
+}
+
+static void config_snand_page_write(struct qcom_nand_controller *snandc)
+{
+ write_reg_dma(snandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(snandc, NAND_DEV0_CFG0, 3, 0);
+ write_reg_dma(snandc, NAND_EBI2_ECC_BUF_CFG, 1, NAND_BAM_NEXT_SGL);
+}
+
+static void config_snand_cw_write(struct qcom_nand_controller *snandc)
+{
+ write_reg_dma(snandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
+ write_reg_dma(snandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
+}
+
+static int qpic_snand_program_execute(struct qcom_nand_controller *snandc,
+ const struct spi_mem_op *op)
+{
+ struct qpic_ecc *ecc_cfg = snandc->ecc;
+ u8 *data_buf;
+ int i, ret;
+ int num_cw = 4;
+ u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
+
+ cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
+ (num_cw - 1) << CW_PER_PAGE;
+ cfg1 = ecc_cfg->cfg1;
+ ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
+ ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
+
+ data_buf = (u8 *)snandc->wbuf;
+
+ snandc->buf_count = 0;
+ snandc->buf_start = 0;
+ clear_read_regs(snandc);
+ clear_bam_transaction(snandc);
+
+ snandc_set_reg(snandc, NAND_ADDR0, snandc->addr1);
+ snandc_set_reg(snandc, NAND_ADDR1, snandc->addr2);
+ snandc_set_reg(snandc, NAND_FLASH_CMD, snandc->cmd);
+
+ snandc_set_reg(snandc, NAND_DEV0_CFG0, cfg0);
+ snandc_set_reg(snandc, NAND_DEV0_CFG1, cfg1);
+ snandc_set_reg(snandc, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
+
+ snandc_set_reg(snandc, NAND_EBI2_ECC_BUF_CFG, ecc_buf_cfg);
+
+ snandc_set_reg(snandc, NAND_EXEC_CMD, 1);
+
+ config_snand_page_write(snandc);
+
+ for (i = 0; i < num_cw; i++) {
+ int data_size;
+
+ if (i == (num_cw - 1))
+ data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
+ else
+ data_size = ecc_cfg->cw_data;
+
+ write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
+ i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
+
+ config_snand_cw_write(snandc);
+ if (data_buf)
+ data_buf += data_size;
+ }
+
+ ret = submit_descs(snandc);
+ if (ret) {
+ dev_err(snandc->dev, "failure to write page\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static u32 qpic_snand_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
+{
+ u32 cmd = 0x0;
+
+ switch (opcode) {
+ case SPINAND_RESET:
+ cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
+ break;
+ case SPINAND_READID:
+ cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
+ break;
+ case SPINAND_GET_FEATURE:
+ cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
+ break;
+ case SPINAND_SET_FEATURE:
+ cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
+ QPIC_SET_FEATURE);
+ break;
+ case SPINAND_READ:
+ if (snandc->raw)
+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+ SPI_WP | SPI_HOLD | OP_PAGE_READ);
+ else
+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+ SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
+ break;
+ case SPINAND_ERASE:
+ cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
+ SPI_HOLD | SPI_TRANSFER_MODE_x1;
+ break;
+ case SPINAND_WRITE_EN:
+ cmd = SPINAND_WRITE_EN;
+ break;
+ case SPINAND_PROGRAM_EXECUTE:
+ cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+ SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
+ break;
+ case SPINAND_PROGRAM_LOAD:
+ cmd = SPINAND_PROGRAM_LOAD;
+ break;
+ default:
+ break;
+ }
+
+ return cmd;
+}
+
+static int qpic_snand_write_page_cache(struct qcom_nand_controller *snandc,
+ const struct spi_mem_op *op)
+{
+ struct qpic_snand_op s_op = {};
+ u32 cmd;
+
+ cmd = qpic_snand_cmd_mapping(snandc, op->cmd.opcode);
+ s_op.cmd_reg = cmd;
+
+ if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) {
+ snandc->wbuf = op->data.buf.out;
+ snandc->wlen = op->data.nbytes;
+ }
+
+ return 0;
+}
+
+static int qpic_snand_send_cmdaddr(struct qcom_nand_controller *snandc,
+ const struct spi_mem_op *op)
+{
+ struct qpic_snand_op s_op = {};
+ u32 cmd;
+ int ret;
+
+ cmd = qpic_snand_cmd_mapping(snandc, op->cmd.opcode);
+
+ s_op.cmd_reg = cmd;
+ s_op.addr1_reg = op->addr.val;
+ s_op.addr2_reg = 0;
+
+ if (op->cmd.opcode == SPINAND_WRITE_EN)
+ return 0;
+
+ if (op->cmd.opcode == SPINAND_PROGRAM_EXECUTE) {
+ s_op.addr1_reg = op->addr.val << 16;
+ s_op.addr2_reg = op->addr.val >> 16 & 0xff;
+ snandc->addr1 = s_op.addr1_reg;
+ snandc->addr2 = s_op.addr2_reg;
+ snandc->cmd = cmd;
+ return qpic_snand_program_execute(snandc, op);
+ }
+
+ if (op->cmd.opcode == SPINAND_READ) {
+ s_op.addr1_reg = (op->addr.val << 16);
+ s_op.addr2_reg = op->addr.val >> 16 & 0xff;
+ snandc->addr1 = s_op.addr1_reg;
+ snandc->addr2 = s_op.addr2_reg;
+ snandc->cmd = cmd;
+ return 0;
+ }
+
+ if (op->cmd.opcode == SPINAND_ERASE) {
+ s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
+ s_op.addr1_reg = op->addr.val;
+ snandc->addr1 = s_op.addr1_reg;
+ snandc->addr1 <<= 16;
+ snandc->addr2 = s_op.addr2_reg;
+ snandc->cmd = cmd;
+ qpic_snand_block_erase(snandc);
+ return 0;
+ }
+
+ snandc->buf_count = 0;
+ snandc->buf_start = 0;
+ clear_read_regs(snandc);
+ clear_bam_transaction(snandc);
+
+ snandc_set_reg(snandc, NAND_FLASH_CMD, s_op.cmd_reg);
+ snandc_set_reg(snandc, NAND_EXEC_CMD, 0x1);
+ snandc_set_reg(snandc, NAND_ADDR0, s_op.addr1_reg);
+ snandc_set_reg(snandc, NAND_ADDR1, s_op.addr2_reg);
+
+ write_reg_dma(snandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
+ write_reg_dma(snandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
+
+ ret = submit_descs(snandc);
+ if (ret)
+ dev_err(snandc->dev, "failure in sbumitting cmd descriptor\n");
+
+ return ret;
+}
+
+static int qpic_snand_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
+{
+ int ret, val;
+
+ ret = qpic_snand_send_cmdaddr(snandc, op);
+ if (ret)
+ return ret;
+
+ snandc->buf_count = 0;
+ snandc->buf_start = 0;
+ clear_read_regs(snandc);
+ clear_bam_transaction(snandc);
+
+ if (op->cmd.opcode == SPINAND_READID) {
+ snandc->buf_count = 4;
+ read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
+
+ ret = submit_descs(snandc);
+ if (ret)
+ dev_err(snandc->dev, "failure in submitting descriptor for readid\n");
+
+ nandc_read_buffer_sync(snandc, true);
+ memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
+
+ return ret;
+ }
+
+ if (op->cmd.opcode == SPINAND_GET_FEATURE) {
+ snandc->buf_count = 4;
+ read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
+
+ ret = submit_descs(snandc);
+ if (ret)
+ dev_err(snandc->dev, "failure in submitting descriptor for get feature\n");
+
+ nandc_read_buffer_sync(snandc, true);
+
+ val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
+ val >>= 8;
+ memcpy(op->data.buf.in, &val, snandc->buf_count);
+ }
+
+ if (op->cmd.opcode == SPINAND_SET_FEATURE) {
+ snandc_set_reg(snandc, NAND_FLASH_FEATURES, *(u32 *)op->data.buf.out);
+ write_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
+ ret = submit_descs(snandc);
+ if (ret)
+ dev_err(snandc->dev, "failure in submitting descriptor for set feature\n");
+ }
+
+ return ret;
+}
+
+static bool qpic_snand_is_page_op(const struct spi_mem_op *op)
+{
+ if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
+ return false;
+
+ if (op->data.dir == SPI_MEM_DATA_IN) {
+ if (op->addr.buswidth == 4 && op->data.buswidth == 4)
+ return true;
+
+ if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
+ return true;
+
+ } else if (op->data.dir == SPI_MEM_DATA_OUT) {
+ if (op->data.buswidth == 4)
+ return true;
+ if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
+ return true;
+ }
+
+ return false;
+}
+
+static bool qpic_snand_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ if (!spi_mem_default_supports_op(mem, op))
+ return false;
+
+ if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
+ return false;
+
+ if (qpic_snand_is_page_op(op))
+ return true;
+
+ return ((op->addr.nbytes == 0 || op->addr.buswidth == 1) &&
+ (op->dummy.nbytes == 0 || op->dummy.buswidth == 1) &&
+ (op->data.nbytes == 0 || op->data.buswidth == 1));
+}
+
+static int qpic_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
+
+ dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
+ op->addr.val, op->addr.buswidth, op->addr.nbytes,
+ op->data.buswidth, op->data.nbytes);
+
+ if (qpic_snand_is_page_op(op)) {
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ return qpic_snand_read_page_cache(snandc, op);
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ return qpic_snand_write_page_cache(snandc, op);
+ } else {
+ return qpic_snand_io_op(snandc, op);
+ }
+
+ return 0;
+}
+
+static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
+ .supports_op = qpic_snand_supports_op,
+ .exec_op = qpic_snand_exec_op,
+};
+
+static const struct spi_controller_mem_caps qcom_snand_mem_caps = {
+ .ecc = true,
+};
+
+static int qcom_snand_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spi_controller *ctlr;
+ struct qcom_nand_controller *snandc;
+ struct resource *res;
+ const void *dev_data;
+ struct qpic_ecc *ecc;
+ int ret;
+
+ ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
+ if (!ecc)
+ return -ENOMEM;
+
+ ctlr = devm_spi_alloc_master(dev, sizeof(*snandc));
+ if (!ctlr)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, ctlr);
+
+ snandc = spi_controller_get_devdata(ctlr);
+
+ snandc->ctlr = ctlr;
+ snandc->dev = dev;
+ snandc->ecc = ecc;
+
+ dev_data = of_device_get_match_data(dev);
+ if (!dev_data) {
+ dev_err(&pdev->dev, "failed to get device data\n");
+ return -ENODEV;
+ }
+
+ snandc->props = dev_data;
+ snandc->dev = &pdev->dev;
+
+ snandc->core_clk = devm_clk_get(dev, "core");
+ if (IS_ERR(snandc->core_clk))
+ return PTR_ERR(snandc->core_clk);
+
+ snandc->aon_clk = devm_clk_get(dev, "aon");
+ if (IS_ERR(snandc->aon_clk))
+ return PTR_ERR(snandc->aon_clk);
+
+ snandc->iomacro_clk = devm_clk_get(dev, "iom");
+ if (IS_ERR(snandc->iomacro_clk))
+ return PTR_ERR(snandc->iomacro_clk);
+
+ snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(snandc->base))
+ return PTR_ERR(snandc->base);
+
+ snandc->base_phys = res->start;
+ snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
+ DMA_BIDIRECTIONAL, 0);
+ if (dma_mapping_error(dev, snandc->base_dma))
+ return -ENXIO;
+
+ ret = clk_prepare_enable(snandc->core_clk);
+ if (ret)
+ goto err_core_clk;
+
+ ret = clk_prepare_enable(snandc->aon_clk);
+ if (ret)
+ goto err_aon_clk;
+
+ ret = clk_prepare_enable(snandc->iomacro_clk);
+ if (ret)
+ goto err_snandc_alloc;
+
+ ret = qcom_nandc_alloc(snandc);
+ if (ret)
+ goto err_snandc_alloc;
+
+ ret = qcom_snand_init(snandc);
+ if (ret)
+ goto err_init;
+
+ /* setup ECC engine */
+ snandc->ecc_eng.dev = &pdev->dev;
+ snandc->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
+ snandc->ecc_eng.ops = &qcom_snand_ecc_engine_ops_pipelined;
+ snandc->ecc_eng.priv = snandc;
+
+ ret = nand_ecc_register_on_host_hw_engine(&snandc->ecc_eng);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register ecc engine.\n");
+ goto err_init;
+ }
+
+ ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
+ ctlr->mem_ops = &qcom_spi_mem_ops;
+ ctlr->mem_caps = &qcom_snand_mem_caps;
+ ctlr->dev.of_node = pdev->dev.of_node;
+ ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
+ SPI_TX_QUAD | SPI_RX_QUAD;
+
+ ret = spi_register_controller(ctlr);
+ if (ret) {
+ dev_err(&pdev->dev, "spi_register_controller failed.\n");
+ goto err_init;
+ }
+
+ return 0;
+
+err_init:
+ qcom_nandc_unalloc(snandc);
+err_snandc_alloc:
+ clk_disable_unprepare(snandc->aon_clk);
+err_aon_clk:
+ clk_disable_unprepare(snandc->core_clk);
+err_core_clk:
+ dma_unmap_resource(dev, res->start, resource_size(res),
+ DMA_BIDIRECTIONAL, 0);
+ return ret;
+}
+
+static int qcom_snand_remove(struct platform_device *pdev)
+{
+ struct spi_controller *ctlr = platform_get_drvdata(pdev);
+
+ spi_unregister_controller(ctlr);
+
+ return 0;
+}
+
+static const struct qcom_nandc_props ipq9574_snandc_props = {
+ .dev_cmd_reg_start = 0x7000,
+ .is_bam = true,
+};
+
+static const struct of_device_id qcom_snandc_of_match[] = {
+ {
+ .compatible = "qcom,ipq9574-snand",
+ .data = &ipq9574_snandc_props,
+ },
+ {}
+}
+MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
+
+static struct platform_driver qcom_snand_driver = {
+ .driver = {
+ .name = "qcom_snand",
+ .of_match_table = qcom_snandc_of_match,
+ },
+ .probe = qcom_snand_probe,
+ .remove = qcom_snand_remove,
+};
+module_platform_driver(qcom_snand_driver);
+
+MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
+MODULE_AUTHOR("Md Sadre Alam <[email protected]>");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
index 891f975ca173..76083561ea58 100644
--- a/include/linux/mtd/nand-qpic-common.h
+++ b/include/linux/mtd/nand-qpic-common.h
@@ -45,6 +45,9 @@
#define NAND_DEV_CMD1 0xa4
#define NAND_DEV_CMD2 0xa8
#define NAND_DEV_CMD_VLD 0xac
+#define NAND_FLASH_SPI_CFG 0xc0
+#define NAND_NUM_ADDR_CYCLES 0xc4
+#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
#define SFLASHC_BURST_CFG 0xe0
#define NAND_ERASED_CW_DETECT_CFG 0xe8
#define NAND_ERASED_CW_DETECT_STATUS 0xec
@@ -61,6 +64,7 @@
#define NAND_READ_LOCATION_LAST_CW_1 0xf44
#define NAND_READ_LOCATION_LAST_CW_2 0xf48
#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
+#define NAND_FLASH_FEATURES 0xf64
/* dummy register offsets, used by write_reg_dma */
#define NAND_DEV_CMD1_RESTORE 0xdead
@@ -169,6 +173,7 @@
#define OP_CHECK_STATUS 0xc
#define OP_FETCH_ID 0xb
#define OP_RESET_DEVICE 0xd
+#define ACC_FEATURE 0xe
/* Default Value for NAND_DEV_CMD_VLD */
#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
@@ -329,11 +334,53 @@ struct nandc_regs {
__le32 read_location_last1;
__le32 read_location_last2;
__le32 read_location_last3;
+ __le32 spi_cfg;
+ __le32 num_addr_cycle;
+ __le32 busy_wait_cnt;
+ __le32 flash_feature;
__le32 erased_cw_detect_cfg_clr;
__le32 erased_cw_detect_cfg_set;
};
+struct qcom_ecc_stats {
+ u32 corrected;
+ u32 bitflips;
+ u32 failed;
+};
+
+/*
+ * QPIC ECC data struct
+ *
+ */
+struct qpic_ecc {
+ struct device *dev;
+ const struct qpic_ecc_caps *caps;
+ struct completion done;
+ u32 sectors;
+ u8 *eccdata;
+ bool use_ecc;
+ u32 ecc_modes;
+ int ecc_bytes_hw;
+ int spare_bytes;
+ int bbm_size;
+ int ecc_mode;
+ int bytes;
+ int steps;
+ int step_size;
+ int strength;
+ int cw_size;
+ int cw_data;
+ u32 cfg0, cfg1;
+ u32 cfg0_raw, cfg1_raw;
+ u32 ecc_buf_cfg;
+ u32 ecc_bch_cfg;
+ u32 clrflashstatus;
+ u32 clrreadstatus;
+ bool bch_enabled;
+};
+
+struct qpic_ecc;
/*
* NAND controller data struct
*
@@ -352,6 +399,7 @@ struct nandc_regs {
* initialized via DT match data
*
* @controller: base controller structure
+ * @ctlr: spi controller structure
* @host_list: list containing all the chips attached to the
* controller
*
@@ -389,6 +437,7 @@ struct qcom_nand_controller {
struct clk *core_clk;
struct clk *aon_clk;
+ struct clk *iomacro_clk;
struct nandc_regs *regs;
struct bam_transaction *bam_txn;
@@ -396,6 +445,7 @@ struct qcom_nand_controller {
const struct qcom_nandc_props *props;
struct nand_controller controller;
+ struct spi_controller *ctlr;
struct list_head host_list;
union {
@@ -432,6 +482,16 @@ struct qcom_nand_controller {
u32 cmd1, vld;
bool exec_opwrite;
+ struct qpic_ecc *ecc;
+ struct qcom_ecc_stats ecc_stats;
+ struct nand_ecc_engine ecc_eng;
+ u8 *wbuf;
+ u32 wlen;
+ u32 addr1;
+ u32 addr2;
+ u32 cmd;
+ bool oob_read;
+ bool raw;
};
/*
@@ -484,5 +544,5 @@ void clear_bam_transaction(struct qcom_nand_controller *nandc);
void qcom_nandc_unalloc(struct qcom_nand_controller *nandc);
int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
struct qcom_nand_controller *get_qcom_nand_controller(struct nand_chip *chip);
-
+void snandc_set_reg(struct qcom_nand_controller *snandc, int offset, u32 val);
#endif
--
2.34.1
Add qpic_common.c file which hold all the common
qpic APIs which will be used by both qpic raw nand
driver and qpic spi nand driver.
Co-developed-by: Sricharan Ramabadhran <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Md Sadre Alam <[email protected]>
---
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
4 files changed, 1291 insertions(+), 1210 deletions(-)
create mode 100644 drivers/mtd/nand/qpic_common.c
create mode 100644 include/linux/mtd/nand-qpic-common.h
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 19e1291ac4d5..131707a41293 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
+obj-y += qpic_common.o
diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
new file mode 100644
index 000000000000..4d74ba888028
--- /dev/null
+++ b/drivers/mtd/nand/qpic_common.c
@@ -0,0 +1,786 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * QPIC Controller common API file.
+ * Copyright (C) 2023 Qualcomm Inc.
+ * Authors: Md sadre Alam <[email protected]>
+ * Sricharan R <[email protected]>
+ * Varadarajan Narayanan <[email protected]>
+ *
+ */
+
+#include <linux/mtd/nand-qpic-common.h>
+
+struct qcom_nand_controller *
+get_qcom_nand_controller(struct nand_chip *chip)
+{
+ return container_of(chip->controller, struct qcom_nand_controller,
+ controller);
+}
+EXPORT_SYMBOL(get_qcom_nand_controller);
+
+/*
+ * Helper to prepare DMA descriptors for configuring registers
+ * before reading a NAND page.
+ */
+void config_nand_page_read(struct nand_chip *chip)
+{
+ struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+
+ write_reg_dma(nandc, NAND_ADDR0, 2, 0);
+ write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
+ if (!nandc->props->qpic_v2)
+ write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
+ write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
+ NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
+}
+EXPORT_SYMBOL(config_nand_page_read);
+
+/* Frees the BAM transaction memory */
+void free_bam_transaction(struct qcom_nand_controller *nandc)
+{
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ devm_kfree(nandc->dev, bam_txn);
+}
+EXPORT_SYMBOL(free_bam_transaction);
+
+/* Callback for DMA descriptor completion */
+void qpic_bam_dma_done(void *data)
+{
+ struct bam_transaction *bam_txn = data;
+
+ /*
+ * In case of data transfer with NAND, 2 callbacks will be generated.
+ * One for command channel and another one for data channel.
+ * If current transaction has data descriptors
+ * (i.e. wait_second_completion is true), then set this to false
+ * and wait for second DMA descriptor completion.
+ */
+ if (bam_txn->wait_second_completion)
+ bam_txn->wait_second_completion = false;
+ else
+ complete(&bam_txn->txn_done);
+}
+EXPORT_SYMBOL(qpic_bam_dma_done);
+
+void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
+ bool is_cpu)
+{
+ if (!nandc->props->is_bam)
+ return;
+
+ if (is_cpu)
+ dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+ else
+ dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+}
+EXPORT_SYMBOL(nandc_read_buffer_sync);
+
+__le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
+{
+ switch (offset) {
+ case NAND_FLASH_CMD:
+ return ®s->cmd;
+ case NAND_ADDR0:
+ return ®s->addr0;
+ case NAND_ADDR1:
+ return ®s->addr1;
+ case NAND_FLASH_CHIP_SELECT:
+ return ®s->chip_sel;
+ case NAND_EXEC_CMD:
+ return ®s->exec;
+ case NAND_FLASH_STATUS:
+ return ®s->clrflashstatus;
+ case NAND_DEV0_CFG0:
+ return ®s->cfg0;
+ case NAND_DEV0_CFG1:
+ return ®s->cfg1;
+ case NAND_DEV0_ECC_CFG:
+ return ®s->ecc_bch_cfg;
+ case NAND_READ_STATUS:
+ return ®s->clrreadstatus;
+ case NAND_DEV_CMD1:
+ return ®s->cmd1;
+ case NAND_DEV_CMD1_RESTORE:
+ return ®s->orig_cmd1;
+ case NAND_DEV_CMD_VLD:
+ return ®s->vld;
+ case NAND_DEV_CMD_VLD_RESTORE:
+ return ®s->orig_vld;
+ case NAND_EBI2_ECC_BUF_CFG:
+ return ®s->ecc_buf_cfg;
+ case NAND_READ_LOCATION_0:
+ return ®s->read_location0;
+ case NAND_READ_LOCATION_1:
+ return ®s->read_location1;
+ case NAND_READ_LOCATION_2:
+ return ®s->read_location2;
+ case NAND_READ_LOCATION_3:
+ return ®s->read_location3;
+ case NAND_READ_LOCATION_LAST_CW_0:
+ return ®s->read_location_last0;
+ case NAND_READ_LOCATION_LAST_CW_1:
+ return ®s->read_location_last1;
+ case NAND_READ_LOCATION_LAST_CW_2:
+ return ®s->read_location_last2;
+ case NAND_READ_LOCATION_LAST_CW_3:
+ return ®s->read_location_last3;
+ default:
+ return NULL;
+ }
+}
+EXPORT_SYMBOL(offset_to_nandc_reg);
+
+/* reset the register read buffer for next NAND operation */
+void clear_read_regs(struct qcom_nand_controller *nandc)
+{
+ nandc->reg_read_pos = 0;
+ nandc_read_buffer_sync(nandc, false);
+}
+EXPORT_SYMBOL(clear_read_regs);
+
+int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr, int size,
+ bool flow_control)
+{
+ struct desc_info *desc;
+ struct dma_async_tx_descriptor *dma_desc;
+ struct scatterlist *sgl;
+ struct dma_slave_config slave_conf;
+ struct qcom_adm_peripheral_config periph_conf = {};
+ enum dma_transfer_direction dir_eng;
+ int ret;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ sgl = &desc->adm_sgl;
+
+ sg_init_one(sgl, vaddr, size);
+
+ if (read) {
+ dir_eng = DMA_DEV_TO_MEM;
+ desc->dir = DMA_FROM_DEVICE;
+ } else {
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ }
+
+ ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
+ if (ret == 0) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ memset(&slave_conf, 0x00, sizeof(slave_conf));
+
+ slave_conf.device_fc = flow_control;
+ if (read) {
+ slave_conf.src_maxburst = 16;
+ slave_conf.src_addr = nandc->base_dma + reg_off;
+ if (nandc->data_crci) {
+ periph_conf.crci = nandc->data_crci;
+ slave_conf.peripheral_config = &periph_conf;
+ slave_conf.peripheral_size = sizeof(periph_conf);
+ }
+ } else {
+ slave_conf.dst_maxburst = 16;
+ slave_conf.dst_addr = nandc->base_dma + reg_off;
+ if (nandc->cmd_crci) {
+ periph_conf.crci = nandc->cmd_crci;
+ slave_conf.peripheral_config = &periph_conf;
+ slave_conf.peripheral_size = sizeof(periph_conf);
+ }
+ }
+
+ ret = dmaengine_slave_config(nandc->chan, &slave_conf);
+ if (ret) {
+ dev_err(nandc->dev, "failed to configure dma channel\n");
+ goto err;
+ }
+
+ dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
+ if (!dma_desc) {
+ dev_err(nandc->dev, "failed to prepare desc\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ list_add_tail(&desc->node, &nandc->desc_list);
+
+ return 0;
+err:
+ kfree(desc);
+
+ return ret;
+}
+EXPORT_SYMBOL(prep_adm_dma_desc);
+
+/* helpers to submit/free our list of dma descriptors */
+int submit_descs(struct qcom_nand_controller *nandc)
+{
+ struct desc_info *desc, *n;
+ dma_cookie_t cookie = 0;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+ int ret = 0;
+
+ if (nandc->props->is_bam) {
+ if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
+ ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
+ if (ret)
+ goto err_unmap_free_desc;
+ }
+
+ if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
+ ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
+ DMA_PREP_INTERRUPT);
+ if (ret)
+ goto err_unmap_free_desc;
+ }
+
+ if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
+ ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+ DMA_PREP_CMD);
+ if (ret)
+ goto err_unmap_free_desc;
+ }
+ }
+
+ list_for_each_entry(desc, &nandc->desc_list, node)
+ cookie = dmaengine_submit(desc->dma_desc);
+
+ if (nandc->props->is_bam) {
+ bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
+ bam_txn->last_cmd_desc->callback_param = bam_txn;
+ if (bam_txn->last_data_desc) {
+ bam_txn->last_data_desc->callback = qpic_bam_dma_done;
+ bam_txn->last_data_desc->callback_param = bam_txn;
+ bam_txn->wait_second_completion = true;
+ }
+
+ dma_async_issue_pending(nandc->tx_chan);
+ dma_async_issue_pending(nandc->rx_chan);
+ dma_async_issue_pending(nandc->cmd_chan);
+
+ if (!wait_for_completion_timeout(&bam_txn->txn_done,
+ QPIC_NAND_COMPLETION_TIMEOUT))
+ ret = -ETIMEDOUT;
+ } else {
+ if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
+ ret = -ETIMEDOUT;
+ }
+
+err_unmap_free_desc:
+ /*
+ * Unmap the dma sg_list and free the desc allocated by both
+ * prepare_bam_async_desc() and prep_adm_dma_desc() functions.
+ */
+ list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
+ list_del(&desc->node);
+
+ if (nandc->props->is_bam)
+ dma_unmap_sg(nandc->dev, desc->bam_sgl,
+ desc->sgl_cnt, desc->dir);
+ else
+ dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
+ desc->dir);
+
+ kfree(desc);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(submit_descs);
+
+/*
+ * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
+ * for BAM. This descriptor will be added in the NAND DMA descriptor queue
+ * which will be submitted to DMA engine.
+ */
+int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
+ struct dma_chan *chan,
+ unsigned long flags)
+{
+ struct desc_info *desc;
+ struct scatterlist *sgl;
+ unsigned int sgl_cnt;
+ int ret;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+ enum dma_transfer_direction dir_eng;
+ struct dma_async_tx_descriptor *dma_desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return -ENOMEM;
+
+ if (chan == nandc->cmd_chan) {
+ sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
+ sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
+ bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ } else if (chan == nandc->tx_chan) {
+ sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
+ sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
+ bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
+ dir_eng = DMA_MEM_TO_DEV;
+ desc->dir = DMA_TO_DEVICE;
+ } else {
+ sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
+ sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
+ bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
+ dir_eng = DMA_DEV_TO_MEM;
+ desc->dir = DMA_FROM_DEVICE;
+ }
+
+ sg_mark_end(sgl + sgl_cnt - 1);
+ ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
+ if (ret == 0) {
+ dev_err(nandc->dev, "failure in mapping desc\n");
+ kfree(desc);
+ return -ENOMEM;
+ }
+
+ desc->sgl_cnt = sgl_cnt;
+ desc->bam_sgl = sgl;
+
+ dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
+ flags);
+
+ if (!dma_desc) {
+ dev_err(nandc->dev, "failure in prep desc\n");
+ dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
+ kfree(desc);
+ return -EINVAL;
+ }
+
+ desc->dma_desc = dma_desc;
+
+ /* update last data/command descriptor */
+ if (chan == nandc->cmd_chan)
+ bam_txn->last_cmd_desc = dma_desc;
+ else
+ bam_txn->last_data_desc = dma_desc;
+
+ list_add_tail(&desc->node, &nandc->desc_list);
+
+ return 0;
+}
+EXPORT_SYMBOL(prepare_bam_async_desc);
+
+/*
+ * Prepares the command descriptor for BAM DMA which will be used for NAND
+ * register reads and writes. The command descriptor requires the command
+ * to be formed in command element type so this function uses the command
+ * element from bam transaction ce array and fills the same with required
+ * data. A single SGL can contain multiple command elements so
+ * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
+ * after the current command element.
+ */
+int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr,
+ int size, unsigned int flags)
+{
+ int bam_ce_size;
+ int i, ret;
+ struct bam_cmd_element *bam_ce_buffer;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
+
+ /* fill the command desc */
+ for (i = 0; i < size; i++) {
+ if (read)
+ bam_prep_ce(&bam_ce_buffer[i],
+ nandc_reg_phys(nandc, reg_off + 4 * i),
+ BAM_READ_COMMAND,
+ reg_buf_dma_addr(nandc,
+ (__le32 *)vaddr + i));
+ else
+ bam_prep_ce_le32(&bam_ce_buffer[i],
+ nandc_reg_phys(nandc, reg_off + 4 * i),
+ BAM_WRITE_COMMAND,
+ *((__le32 *)vaddr + i));
+ }
+
+ bam_txn->bam_ce_pos += size;
+
+ /* use the separate sgl after this command */
+ if (flags & NAND_BAM_NEXT_SGL) {
+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
+ bam_ce_size = (bam_txn->bam_ce_pos -
+ bam_txn->bam_ce_start) *
+ sizeof(struct bam_cmd_element);
+ sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
+ bam_ce_buffer, bam_ce_size);
+ bam_txn->cmd_sgl_pos++;
+ bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
+
+ if (flags & NAND_BAM_NWD) {
+ ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
+ DMA_PREP_FENCE |
+ DMA_PREP_CMD);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(prep_bam_dma_desc_cmd);
+
+/*
+ * Prepares the data descriptor for BAM DMA which will be used for NAND
+ * data reads and writes.
+ */
+int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
+ const void *vaddr,
+ int size, unsigned int flags)
+{
+ int ret;
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ if (read) {
+ sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
+ vaddr, size);
+ bam_txn->rx_sgl_pos++;
+ } else {
+ sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
+ vaddr, size);
+ bam_txn->tx_sgl_pos++;
+
+ /*
+ * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
+ * is not set, form the DMA descriptor
+ */
+ if (!(flags & NAND_BAM_NO_EOT)) {
+ ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
+ DMA_PREP_INTERRUPT);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(prep_bam_dma_desc_data);
+
+/*
+ * read_reg_dma: prepares a descriptor to read a given number of
+ * contiguous registers to the reg_read_buf pointer
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to read
+ * @flags: flags to control DMA descriptor preparation
+ */
+int read_reg_dma(struct qcom_nand_controller *nandc, int first,
+ int num_regs, unsigned int flags)
+{
+ bool flow_control = false;
+ void *vaddr;
+
+ vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
+ nandc->reg_read_pos += num_regs;
+
+ if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
+ first = dev_cmd_reg_addr(nandc, first);
+
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
+ num_regs, flags);
+
+ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
+ flow_control = true;
+
+ return prep_adm_dma_desc(nandc, true, first, vaddr,
+ num_regs * sizeof(u32), flow_control);
+}
+EXPORT_SYMBOL(read_reg_dma);
+
+/*
+ * write_reg_dma: prepares a descriptor to write a given number of
+ * contiguous registers
+ *
+ * @first: offset of the first register in the contiguous block
+ * @num_regs: number of registers to write
+ * @flags: flags to control DMA descriptor preparation
+ */
+int write_reg_dma(struct qcom_nand_controller *nandc, int first,
+ int num_regs, unsigned int flags)
+{
+ bool flow_control = false;
+ struct nandc_regs *regs = nandc->regs;
+ void *vaddr;
+
+ vaddr = offset_to_nandc_reg(regs, first);
+
+ if (first == NAND_ERASED_CW_DETECT_CFG) {
+ if (flags & NAND_ERASED_CW_SET)
+ vaddr = ®s->erased_cw_detect_cfg_set;
+ else
+ vaddr = ®s->erased_cw_detect_cfg_clr;
+ }
+
+ if (first == NAND_EXEC_CMD)
+ flags |= NAND_BAM_NWD;
+
+ if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
+ first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
+
+ if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
+ first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
+
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
+ num_regs, flags);
+
+ if (first == NAND_FLASH_CMD)
+ flow_control = true;
+
+ return prep_adm_dma_desc(nandc, false, first, vaddr,
+ num_regs * sizeof(u32), flow_control);
+}
+EXPORT_SYMBOL(write_reg_dma);
+
+/*
+ * read_data_dma: prepares a DMA descriptor to transfer data from the
+ * controller's internal buffer to the buffer 'vaddr'
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to write to
+ * @size: DMA transaction size in bytes
+ * @flags: flags to control DMA descriptor preparation
+ */
+int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
+ const u8 *vaddr, int size, unsigned int flags)
+{
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
+
+ return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
+}
+EXPORT_SYMBOL(read_data_dma);
+
+/*
+ * write_data_dma: prepares a DMA descriptor to transfer data from
+ * 'vaddr' to the controller's internal buffer
+ *
+ * @reg_off: offset within the controller's data buffer
+ * @vaddr: virtual address of the buffer we want to read from
+ * @size: DMA transaction size in bytes
+ * @flags: flags to control DMA descriptor preparation
+ */
+int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
+ const u8 *vaddr, int size, unsigned int flags)
+{
+ if (nandc->props->is_bam)
+ return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
+
+ return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
+}
+EXPORT_SYMBOL(write_data_dma);
+
+/* Allocates and Initializes the BAM transaction */
+struct bam_transaction *
+alloc_bam_transaction(struct qcom_nand_controller *nandc)
+{
+ struct bam_transaction *bam_txn;
+ size_t bam_txn_size;
+ unsigned int num_cw = nandc->max_cwperpage;
+ void *bam_txn_buf;
+
+ bam_txn_size =
+ sizeof(*bam_txn) + num_cw *
+ ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
+ (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
+ (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
+
+ bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
+ if (!bam_txn_buf)
+ return NULL;
+
+ bam_txn = bam_txn_buf;
+ bam_txn_buf += sizeof(*bam_txn);
+
+ bam_txn->bam_ce = bam_txn_buf;
+ bam_txn_buf +=
+ sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
+
+ bam_txn->cmd_sgl = bam_txn_buf;
+ bam_txn_buf +=
+ sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
+
+ bam_txn->data_sgl = bam_txn_buf;
+
+ init_completion(&bam_txn->txn_done);
+
+ return bam_txn;
+}
+EXPORT_SYMBOL(alloc_bam_transaction);
+
+/* Clears the BAM transaction indexes */
+void clear_bam_transaction(struct qcom_nand_controller *nandc)
+{
+ struct bam_transaction *bam_txn = nandc->bam_txn;
+
+ if (!nandc->props->is_bam)
+ return;
+
+ bam_txn->bam_ce_pos = 0;
+ bam_txn->bam_ce_start = 0;
+ bam_txn->cmd_sgl_pos = 0;
+ bam_txn->cmd_sgl_start = 0;
+ bam_txn->tx_sgl_pos = 0;
+ bam_txn->tx_sgl_start = 0;
+ bam_txn->rx_sgl_pos = 0;
+ bam_txn->rx_sgl_start = 0;
+ bam_txn->last_data_desc = NULL;
+ bam_txn->wait_second_completion = false;
+
+ sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_CMD_SGL);
+ sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
+ QPIC_PER_CW_DATA_SGL);
+
+ reinit_completion(&bam_txn->txn_done);
+}
+EXPORT_SYMBOL(clear_bam_transaction);
+
+void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
+{
+ if (nandc->props->is_bam) {
+ if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
+ dma_unmap_single(nandc->dev, nandc->reg_read_dma,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+
+ if (nandc->tx_chan)
+ dma_release_channel(nandc->tx_chan);
+
+ if (nandc->rx_chan)
+ dma_release_channel(nandc->rx_chan);
+
+ if (nandc->cmd_chan)
+ dma_release_channel(nandc->cmd_chan);
+ } else {
+ if (nandc->chan)
+ dma_release_channel(nandc->chan);
+ }
+}
+EXPORT_SYMBOL(qcom_nandc_unalloc);
+
+int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
+{
+ int ret;
+
+ ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
+ if (ret) {
+ dev_err(nandc->dev, "failed to set DMA mask\n");
+ return ret;
+ }
+
+ /*
+ * we use the internal buffer for reading ONFI params, reading small
+ * data like ID and status, and preforming read-copy-write operations
+ * when writing to a codeword partially. 532 is the maximum possible
+ * size of a codeword for our nand controller
+ */
+ nandc->buf_size = 532;
+
+ nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
+ if (!nandc->data_buffer)
+ return -ENOMEM;
+
+ nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
+ if (!nandc->regs)
+ return -ENOMEM;
+
+ nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
+ sizeof(*nandc->reg_read_buf),
+ GFP_KERNEL);
+ if (!nandc->reg_read_buf)
+ return -ENOMEM;
+
+ if (nandc->props->is_bam) {
+ nandc->reg_read_dma =
+ dma_map_single(nandc->dev, nandc->reg_read_buf,
+ MAX_REG_RD *
+ sizeof(*nandc->reg_read_buf),
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
+ dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
+ return -EIO;
+ }
+
+ nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
+ if (IS_ERR(nandc->tx_chan)) {
+ ret = PTR_ERR(nandc->tx_chan);
+ nandc->tx_chan = NULL;
+ dev_err_probe(nandc->dev, ret,
+ "tx DMA channel request failed\n");
+ goto unalloc;
+ }
+
+ nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
+ if (IS_ERR(nandc->rx_chan)) {
+ ret = PTR_ERR(nandc->rx_chan);
+ nandc->rx_chan = NULL;
+ dev_err_probe(nandc->dev, ret,
+ "rx DMA channel request failed\n");
+ goto unalloc;
+ }
+
+ nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
+ if (IS_ERR(nandc->cmd_chan)) {
+ ret = PTR_ERR(nandc->cmd_chan);
+ nandc->cmd_chan = NULL;
+ dev_err_probe(nandc->dev, ret,
+ "cmd DMA channel request failed\n");
+ goto unalloc;
+ }
+
+ /*
+ * Initially allocate BAM transaction to read ONFI param page.
+ * After detecting all the devices, this BAM transaction will
+ * be freed and the next BAM transaction will be allocated with
+ * maximum codeword size
+ */
+ nandc->max_cwperpage = 1;
+ nandc->bam_txn = alloc_bam_transaction(nandc);
+ if (!nandc->bam_txn) {
+ dev_err(nandc->dev,
+ "failed to allocate bam transaction\n");
+ ret = -ENOMEM;
+ goto unalloc;
+ }
+ } else {
+ nandc->chan = dma_request_chan(nandc->dev, "rxtx");
+ if (IS_ERR(nandc->chan)) {
+ ret = PTR_ERR(nandc->chan);
+ nandc->chan = NULL;
+ dev_err_probe(nandc->dev, ret,
+ "rxtx DMA channel request failed\n");
+ return ret;
+ }
+ }
+
+ INIT_LIST_HEAD(&nandc->desc_list);
+ INIT_LIST_HEAD(&nandc->host_list);
+
+ return 0;
+unalloc:
+ qcom_nandc_unalloc(nandc);
+ return ret;
+}
+EXPORT_SYMBOL(qcom_nandc_alloc);
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index b079605c84d3..75c6ca698c85 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2,186 +2,7 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*/
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-#include <linux/dma/qcom_adm.h>
-#include <linux/dma/qcom_bam_dma.h>
-#include <linux/module.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-/* NANDc reg offsets */
-#define NAND_FLASH_CMD 0x00
-#define NAND_ADDR0 0x04
-#define NAND_ADDR1 0x08
-#define NAND_FLASH_CHIP_SELECT 0x0c
-#define NAND_EXEC_CMD 0x10
-#define NAND_FLASH_STATUS 0x14
-#define NAND_BUFFER_STATUS 0x18
-#define NAND_DEV0_CFG0 0x20
-#define NAND_DEV0_CFG1 0x24
-#define NAND_DEV0_ECC_CFG 0x28
-#define NAND_AUTO_STATUS_EN 0x2c
-#define NAND_DEV1_CFG0 0x30
-#define NAND_DEV1_CFG1 0x34
-#define NAND_READ_ID 0x40
-#define NAND_READ_STATUS 0x44
-#define NAND_DEV_CMD0 0xa0
-#define NAND_DEV_CMD1 0xa4
-#define NAND_DEV_CMD2 0xa8
-#define NAND_DEV_CMD_VLD 0xac
-#define SFLASHC_BURST_CFG 0xe0
-#define NAND_ERASED_CW_DETECT_CFG 0xe8
-#define NAND_ERASED_CW_DETECT_STATUS 0xec
-#define NAND_EBI2_ECC_BUF_CFG 0xf0
-#define FLASH_BUF_ACC 0x100
-
-#define NAND_CTRL 0xf00
-#define NAND_VERSION 0xf08
-#define NAND_READ_LOCATION_0 0xf20
-#define NAND_READ_LOCATION_1 0xf24
-#define NAND_READ_LOCATION_2 0xf28
-#define NAND_READ_LOCATION_3 0xf2c
-#define NAND_READ_LOCATION_LAST_CW_0 0xf40
-#define NAND_READ_LOCATION_LAST_CW_1 0xf44
-#define NAND_READ_LOCATION_LAST_CW_2 0xf48
-#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
-
-/* dummy register offsets, used by write_reg_dma */
-#define NAND_DEV_CMD1_RESTORE 0xdead
-#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
-
-/* NAND_FLASH_CMD bits */
-#define PAGE_ACC BIT(4)
-#define LAST_PAGE BIT(5)
-
-/* NAND_FLASH_CHIP_SELECT bits */
-#define NAND_DEV_SEL 0
-#define DM_EN BIT(2)
-
-/* NAND_FLASH_STATUS bits */
-#define FS_OP_ERR BIT(4)
-#define FS_READY_BSY_N BIT(5)
-#define FS_MPU_ERR BIT(8)
-#define FS_DEVICE_STS_ERR BIT(16)
-#define FS_DEVICE_WP BIT(23)
-
-/* NAND_BUFFER_STATUS bits */
-#define BS_UNCORRECTABLE_BIT BIT(8)
-#define BS_CORRECTABLE_ERR_MSK 0x1f
-
-/* NAND_DEVn_CFG0 bits */
-#define DISABLE_STATUS_AFTER_WRITE 4
-#define CW_PER_PAGE 6
-#define UD_SIZE_BYTES 9
-#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
-#define ECC_PARITY_SIZE_BYTES_RS 19
-#define SPARE_SIZE_BYTES 23
-#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
-#define NUM_ADDR_CYCLES 27
-#define STATUS_BFR_READ 30
-#define SET_RD_MODE_AFTER_STATUS 31
-
-/* NAND_DEVn_CFG0 bits */
-#define DEV0_CFG1_ECC_DISABLE 0
-#define WIDE_FLASH 1
-#define NAND_RECOVERY_CYCLES 2
-#define CS_ACTIVE_BSY 5
-#define BAD_BLOCK_BYTE_NUM 6
-#define BAD_BLOCK_IN_SPARE_AREA 16
-#define WR_RD_BSY_GAP 17
-#define ENABLE_BCH_ECC 27
-
-/* NAND_DEV0_ECC_CFG bits */
-#define ECC_CFG_ECC_DISABLE 0
-#define ECC_SW_RESET 1
-#define ECC_MODE 4
-#define ECC_PARITY_SIZE_BYTES_BCH 8
-#define ECC_NUM_DATA_BYTES 16
-#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
-#define ECC_FORCE_CLK_OPEN 30
-
-/* NAND_DEV_CMD1 bits */
-#define READ_ADDR 0
-
-/* NAND_DEV_CMD_VLD bits */
-#define READ_START_VLD BIT(0)
-#define READ_STOP_VLD BIT(1)
-#define WRITE_START_VLD BIT(2)
-#define ERASE_START_VLD BIT(3)
-#define SEQ_READ_START_VLD BIT(4)
-
-/* NAND_EBI2_ECC_BUF_CFG bits */
-#define NUM_STEPS 0
-
-/* NAND_ERASED_CW_DETECT_CFG bits */
-#define ERASED_CW_ECC_MASK 1
-#define AUTO_DETECT_RES 0
-#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
-#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
-#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
-#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
-#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
-
-/* NAND_ERASED_CW_DETECT_STATUS bits */
-#define PAGE_ALL_ERASED BIT(7)
-#define CODEWORD_ALL_ERASED BIT(6)
-#define PAGE_ERASED BIT(5)
-#define CODEWORD_ERASED BIT(4)
-#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
-#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
-
-/* NAND_READ_LOCATION_n bits */
-#define READ_LOCATION_OFFSET 0
-#define READ_LOCATION_SIZE 16
-#define READ_LOCATION_LAST 31
-
-/* Version Mask */
-#define NAND_VERSION_MAJOR_MASK 0xf0000000
-#define NAND_VERSION_MAJOR_SHIFT 28
-#define NAND_VERSION_MINOR_MASK 0x0fff0000
-#define NAND_VERSION_MINOR_SHIFT 16
-
-/* NAND OP_CMDs */
-#define OP_PAGE_READ 0x2
-#define OP_PAGE_READ_WITH_ECC 0x3
-#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
-#define OP_PAGE_READ_ONFI_READ 0x5
-#define OP_PROGRAM_PAGE 0x6
-#define OP_PAGE_PROGRAM_WITH_ECC 0x7
-#define OP_PROGRAM_PAGE_SPARE 0x9
-#define OP_BLOCK_ERASE 0xa
-#define OP_CHECK_STATUS 0xc
-#define OP_FETCH_ID 0xb
-#define OP_RESET_DEVICE 0xd
-
-/* Default Value for NAND_DEV_CMD_VLD */
-#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
- ERASE_START_VLD | SEQ_READ_START_VLD)
-
-/* NAND_CTRL bits */
-#define BAM_MODE_EN BIT(0)
-
-/*
- * the NAND controller performs reads/writes with ECC in 516 byte chunks.
- * the driver calls the chunks 'step' or 'codeword' interchangeably
- */
-#define NANDC_STEP_SIZE 512
-
-/*
- * the largest page size we support is 8K, this will have 16 steps/codewords
- * of 512 bytes each
- */
-#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
-
-/* we read at most 3 registers per codeword scan */
-#define MAX_REG_RD (3 * MAX_NUM_STEPS)
+#include <linux/mtd/nand-qpic-common.h>
/* ECC modes supported by the controller */
#define ECC_NONE BIT(0)
@@ -200,247 +21,6 @@ nandc_set_reg(chip, reg, \
((cw_offset) << READ_LOCATION_OFFSET) | \
((read_size) << READ_LOCATION_SIZE) | \
((is_last_read_loc) << READ_LOCATION_LAST))
-/*
- * Returns the actual register address for all NAND_DEV_ registers
- * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
- */
-#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
-
-/* Returns the NAND register physical address */
-#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
-
-/* Returns the dma address for reg read buffer */
-#define reg_buf_dma_addr(chip, vaddr) \
- ((chip)->reg_read_dma + \
- ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
-
-#define QPIC_PER_CW_CMD_ELEMENTS 32
-#define QPIC_PER_CW_CMD_SGL 32
-#define QPIC_PER_CW_DATA_SGL 8
-
-#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
-
-/*
- * Flags used in DMA descriptor preparation helper functions
- * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
- */
-/* Don't set the EOT in current tx BAM sgl */
-#define NAND_BAM_NO_EOT BIT(0)
-/* Set the NWD flag in current BAM sgl */
-#define NAND_BAM_NWD BIT(1)
-/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
-#define NAND_BAM_NEXT_SGL BIT(2)
-/*
- * Erased codeword status is being used two times in single transfer so this
- * flag will determine the current value of erased codeword status register
- */
-#define NAND_ERASED_CW_SET BIT(4)
-
-#define MAX_ADDRESS_CYCLE 5
-
-/*
- * This data type corresponds to the BAM transaction which will be used for all
- * NAND transfers.
- * @bam_ce - the array of BAM command elements
- * @cmd_sgl - sgl for NAND BAM command pipe
- * @data_sgl - sgl for NAND BAM consumer/producer pipe
- * @last_data_desc - last DMA desc in data channel (tx/rx).
- * @last_cmd_desc - last DMA desc in command channel.
- * @txn_done - completion for NAND transfer.
- * @bam_ce_pos - the index in bam_ce which is available for next sgl
- * @bam_ce_start - the index in bam_ce which marks the start position ce
- * for current sgl. It will be used for size calculation
- * for current sgl
- * @cmd_sgl_pos - current index in command sgl.
- * @cmd_sgl_start - start index in command sgl.
- * @tx_sgl_pos - current index in data sgl for tx.
- * @tx_sgl_start - start index in data sgl for tx.
- * @rx_sgl_pos - current index in data sgl for rx.
- * @rx_sgl_start - start index in data sgl for rx.
- * @wait_second_completion - wait for second DMA desc completion before making
- * the NAND transfer completion.
- */
-struct bam_transaction {
- struct bam_cmd_element *bam_ce;
- struct scatterlist *cmd_sgl;
- struct scatterlist *data_sgl;
- struct dma_async_tx_descriptor *last_data_desc;
- struct dma_async_tx_descriptor *last_cmd_desc;
- struct completion txn_done;
- u32 bam_ce_pos;
- u32 bam_ce_start;
- u32 cmd_sgl_pos;
- u32 cmd_sgl_start;
- u32 tx_sgl_pos;
- u32 tx_sgl_start;
- u32 rx_sgl_pos;
- u32 rx_sgl_start;
- bool wait_second_completion;
-};
-
-/*
- * This data type corresponds to the nand dma descriptor
- * @dma_desc - low level DMA engine descriptor
- * @list - list for desc_info
- *
- * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
- * ADM
- * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
- * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
- * @dir - DMA transfer direction
- */
-struct desc_info {
- struct dma_async_tx_descriptor *dma_desc;
- struct list_head node;
-
- union {
- struct scatterlist adm_sgl;
- struct {
- struct scatterlist *bam_sgl;
- int sgl_cnt;
- };
- };
- enum dma_data_direction dir;
-};
-
-/*
- * holds the current register values that we want to write. acts as a contiguous
- * chunk of memory which we use to write the controller registers through DMA.
- */
-struct nandc_regs {
- __le32 cmd;
- __le32 addr0;
- __le32 addr1;
- __le32 chip_sel;
- __le32 exec;
-
- __le32 cfg0;
- __le32 cfg1;
- __le32 ecc_bch_cfg;
-
- __le32 clrflashstatus;
- __le32 clrreadstatus;
-
- __le32 cmd1;
- __le32 vld;
-
- __le32 orig_cmd1;
- __le32 orig_vld;
-
- __le32 ecc_buf_cfg;
- __le32 read_location0;
- __le32 read_location1;
- __le32 read_location2;
- __le32 read_location3;
- __le32 read_location_last0;
- __le32 read_location_last1;
- __le32 read_location_last2;
- __le32 read_location_last3;
-
- __le32 erased_cw_detect_cfg_clr;
- __le32 erased_cw_detect_cfg_set;
-};
-
-/*
- * NAND controller data struct
- *
- * @dev: parent device
- *
- * @base: MMIO base
- *
- * @core_clk: controller clock
- * @aon_clk: another controller clock
- *
- * @regs: a contiguous chunk of memory for DMA register
- * writes. contains the register values to be
- * written to controller
- *
- * @props: properties of current NAND controller,
- * initialized via DT match data
- *
- * @controller: base controller structure
- * @host_list: list containing all the chips attached to the
- * controller
- *
- * @chan: dma channel
- * @cmd_crci: ADM DMA CRCI for command flow control
- * @data_crci: ADM DMA CRCI for data flow control
- *
- * @desc_list: DMA descriptor list (list of desc_infos)
- *
- * @data_buffer: our local DMA buffer for page read/writes,
- * used when we can't use the buffer provided
- * by upper layers directly
- * @reg_read_buf: local buffer for reading back registers via DMA
- *
- * @base_phys: physical base address of controller registers
- * @base_dma: dma base address of controller registers
- * @reg_read_dma: contains dma address for register read buffer
- *
- * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
- * functions
- * @max_cwperpage: maximum QPIC codewords required. calculated
- * from all connected NAND devices pagesize
- *
- * @reg_read_pos: marker for data read in reg_read_buf
- *
- * @cmd1/vld: some fixed controller register values
- *
- * @exec_opwrite: flag to select correct number of code word
- * while reading status
- */
-struct qcom_nand_controller {
- struct device *dev;
-
- void __iomem *base;
-
- struct clk *core_clk;
- struct clk *aon_clk;
-
- struct nandc_regs *regs;
- struct bam_transaction *bam_txn;
-
- const struct qcom_nandc_props *props;
-
- struct nand_controller controller;
- struct list_head host_list;
-
- union {
- /* will be used only by QPIC for BAM DMA */
- struct {
- struct dma_chan *tx_chan;
- struct dma_chan *rx_chan;
- struct dma_chan *cmd_chan;
- };
-
- /* will be used only by EBI2 for ADM DMA */
- struct {
- struct dma_chan *chan;
- unsigned int cmd_crci;
- unsigned int data_crci;
- };
- };
-
- struct list_head desc_list;
-
- u8 *data_buffer;
- __le32 *reg_read_buf;
-
- phys_addr_t base_phys;
- dma_addr_t base_dma;
- dma_addr_t reg_read_dma;
-
- int buf_size;
- int buf_count;
- int buf_start;
- unsigned int max_cwperpage;
-
- int reg_read_pos;
-
- u32 cmd1, vld;
- bool exec_opwrite;
-};
-
/*
* NAND special boot partitions
*
@@ -544,113 +124,17 @@ struct qcom_nand_host {
bool bch_enabled;
};
-/*
- * This data type corresponds to the NAND controller properties which varies
- * among different NAND controllers.
- * @ecc_modes - ecc mode for NAND
- * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
- * @is_bam - whether NAND controller is using BAM
- * @is_qpic - whether NAND CTRL is part of qpic IP
- * @qpic_v2 - flag to indicate QPIC IP version 2
- * @use_codeword_fixup - whether NAND has different layout for boot partitions
- */
-struct qcom_nandc_props {
- u32 ecc_modes;
- u32 dev_cmd_reg_start;
- bool is_bam;
- bool is_qpic;
- bool qpic_v2;
- bool use_codeword_fixup;
-};
-
-/* Frees the BAM transaction memory */
-static void free_bam_transaction(struct qcom_nand_controller *nandc)
-{
- struct bam_transaction *bam_txn = nandc->bam_txn;
-
- devm_kfree(nandc->dev, bam_txn);
-}
-
-/* Allocates and Initializes the BAM transaction */
-static struct bam_transaction *
-alloc_bam_transaction(struct qcom_nand_controller *nandc)
-{
- struct bam_transaction *bam_txn;
- size_t bam_txn_size;
- unsigned int num_cw = nandc->max_cwperpage;
- void *bam_txn_buf;
-
- bam_txn_size =
- sizeof(*bam_txn) + num_cw *
- ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
- (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
- (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
-
- bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
- if (!bam_txn_buf)
- return NULL;
-
- bam_txn = bam_txn_buf;
- bam_txn_buf += sizeof(*bam_txn);
-
- bam_txn->bam_ce = bam_txn_buf;
- bam_txn_buf +=
- sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
-
- bam_txn->cmd_sgl = bam_txn_buf;
- bam_txn_buf +=
- sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
-
- bam_txn->data_sgl = bam_txn_buf;
-
- init_completion(&bam_txn->txn_done);
-
- return bam_txn;
-}
-
-/* Clears the BAM transaction indexes */
-static void clear_bam_transaction(struct qcom_nand_controller *nandc)
+static void nandc_set_reg(struct nand_chip *chip, int offset,
+ u32 val)
{
- struct bam_transaction *bam_txn = nandc->bam_txn;
-
- if (!nandc->props->is_bam)
- return;
-
- bam_txn->bam_ce_pos = 0;
- bam_txn->bam_ce_start = 0;
- bam_txn->cmd_sgl_pos = 0;
- bam_txn->cmd_sgl_start = 0;
- bam_txn->tx_sgl_pos = 0;
- bam_txn->tx_sgl_start = 0;
- bam_txn->rx_sgl_pos = 0;
- bam_txn->rx_sgl_start = 0;
- bam_txn->last_data_desc = NULL;
- bam_txn->wait_second_completion = false;
-
- sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
- QPIC_PER_CW_CMD_SGL);
- sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
- QPIC_PER_CW_DATA_SGL);
-
- reinit_completion(&bam_txn->txn_done);
-}
+ struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+ struct nandc_regs *regs = nandc->regs;
+ __le32 *reg;
-/* Callback for DMA descriptor completion */
-static void qpic_bam_dma_done(void *data)
-{
- struct bam_transaction *bam_txn = data;
+ reg = offset_to_nandc_reg(regs, offset);
- /*
- * In case of data transfer with NAND, 2 callbacks will be generated.
- * One for command channel and another one for data channel.
- * If current transaction has data descriptors
- * (i.e. wait_second_completion is true), then set this to false
- * and wait for second DMA descriptor completion.
- */
- if (bam_txn->wait_second_completion)
- bam_txn->wait_second_completion = false;
- else
- complete(&bam_txn->txn_done);
+ if (reg)
+ *reg = cpu_to_le32(val);
}
static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
@@ -658,13 +142,6 @@ static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
return container_of(chip, struct qcom_nand_host, chip);
}
-static inline struct qcom_nand_controller *
-get_qcom_nand_controller(struct nand_chip *chip)
-{
- return container_of(chip->controller, struct qcom_nand_controller,
- controller);
-}
-
static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
{
return ioread32(nandc->base + offset);
@@ -676,91 +153,6 @@ static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
iowrite32(val, nandc->base + offset);
}
-static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
- bool is_cpu)
-{
- if (!nandc->props->is_bam)
- return;
-
- if (is_cpu)
- dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
- MAX_REG_RD *
- sizeof(*nandc->reg_read_buf),
- DMA_FROM_DEVICE);
- else
- dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
- MAX_REG_RD *
- sizeof(*nandc->reg_read_buf),
- DMA_FROM_DEVICE);
-}
-
-static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
-{
- switch (offset) {
- case NAND_FLASH_CMD:
- return ®s->cmd;
- case NAND_ADDR0:
- return ®s->addr0;
- case NAND_ADDR1:
- return ®s->addr1;
- case NAND_FLASH_CHIP_SELECT:
- return ®s->chip_sel;
- case NAND_EXEC_CMD:
- return ®s->exec;
- case NAND_FLASH_STATUS:
- return ®s->clrflashstatus;
- case NAND_DEV0_CFG0:
- return ®s->cfg0;
- case NAND_DEV0_CFG1:
- return ®s->cfg1;
- case NAND_DEV0_ECC_CFG:
- return ®s->ecc_bch_cfg;
- case NAND_READ_STATUS:
- return ®s->clrreadstatus;
- case NAND_DEV_CMD1:
- return ®s->cmd1;
- case NAND_DEV_CMD1_RESTORE:
- return ®s->orig_cmd1;
- case NAND_DEV_CMD_VLD:
- return ®s->vld;
- case NAND_DEV_CMD_VLD_RESTORE:
- return ®s->orig_vld;
- case NAND_EBI2_ECC_BUF_CFG:
- return ®s->ecc_buf_cfg;
- case NAND_READ_LOCATION_0:
- return ®s->read_location0;
- case NAND_READ_LOCATION_1:
- return ®s->read_location1;
- case NAND_READ_LOCATION_2:
- return ®s->read_location2;
- case NAND_READ_LOCATION_3:
- return ®s->read_location3;
- case NAND_READ_LOCATION_LAST_CW_0:
- return ®s->read_location_last0;
- case NAND_READ_LOCATION_LAST_CW_1:
- return ®s->read_location_last1;
- case NAND_READ_LOCATION_LAST_CW_2:
- return ®s->read_location_last2;
- case NAND_READ_LOCATION_LAST_CW_3:
- return ®s->read_location_last3;
- default:
- return NULL;
- }
-}
-
-static void nandc_set_reg(struct nand_chip *chip, int offset,
- u32 val)
-{
- struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
- struct nandc_regs *regs = nandc->regs;
- __le32 *reg;
-
- reg = offset_to_nandc_reg(regs, offset);
-
- if (reg)
- *reg = cpu_to_le32(val);
-}
-
/* Helper to check the code word, whether it is last cw or not */
static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
{
@@ -852,383 +244,6 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
host->cw_data : host->cw_size, 1);
}
-/*
- * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
- * for BAM. This descriptor will be added in the NAND DMA descriptor queue
- * which will be submitted to DMA engine.
- */
-static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
- struct dma_chan *chan,
- unsigned long flags)
-{
- struct desc_info *desc;
- struct scatterlist *sgl;
- unsigned int sgl_cnt;
- int ret;
- struct bam_transaction *bam_txn = nandc->bam_txn;
- enum dma_transfer_direction dir_eng;
- struct dma_async_tx_descriptor *dma_desc;
-
- desc = kzalloc(sizeof(*desc), GFP_KERNEL);
- if (!desc)
- return -ENOMEM;
-
- if (chan == nandc->cmd_chan) {
- sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
- sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
- bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
- dir_eng = DMA_MEM_TO_DEV;
- desc->dir = DMA_TO_DEVICE;
- } else if (chan == nandc->tx_chan) {
- sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
- sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
- bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
- dir_eng = DMA_MEM_TO_DEV;
- desc->dir = DMA_TO_DEVICE;
- } else {
- sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
- sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
- bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
- dir_eng = DMA_DEV_TO_MEM;
- desc->dir = DMA_FROM_DEVICE;
- }
-
- sg_mark_end(sgl + sgl_cnt - 1);
- ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
- if (ret == 0) {
- dev_err(nandc->dev, "failure in mapping desc\n");
- kfree(desc);
- return -ENOMEM;
- }
-
- desc->sgl_cnt = sgl_cnt;
- desc->bam_sgl = sgl;
-
- dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
- flags);
-
- if (!dma_desc) {
- dev_err(nandc->dev, "failure in prep desc\n");
- dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
- kfree(desc);
- return -EINVAL;
- }
-
- desc->dma_desc = dma_desc;
-
- /* update last data/command descriptor */
- if (chan == nandc->cmd_chan)
- bam_txn->last_cmd_desc = dma_desc;
- else
- bam_txn->last_data_desc = dma_desc;
-
- list_add_tail(&desc->node, &nandc->desc_list);
-
- return 0;
-}
-
-/*
- * Prepares the command descriptor for BAM DMA which will be used for NAND
- * register reads and writes. The command descriptor requires the command
- * to be formed in command element type so this function uses the command
- * element from bam transaction ce array and fills the same with required
- * data. A single SGL can contain multiple command elements so
- * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
- * after the current command element.
- */
-static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
- int reg_off, const void *vaddr,
- int size, unsigned int flags)
-{
- int bam_ce_size;
- int i, ret;
- struct bam_cmd_element *bam_ce_buffer;
- struct bam_transaction *bam_txn = nandc->bam_txn;
-
- bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
-
- /* fill the command desc */
- for (i = 0; i < size; i++) {
- if (read)
- bam_prep_ce(&bam_ce_buffer[i],
- nandc_reg_phys(nandc, reg_off + 4 * i),
- BAM_READ_COMMAND,
- reg_buf_dma_addr(nandc,
- (__le32 *)vaddr + i));
- else
- bam_prep_ce_le32(&bam_ce_buffer[i],
- nandc_reg_phys(nandc, reg_off + 4 * i),
- BAM_WRITE_COMMAND,
- *((__le32 *)vaddr + i));
- }
-
- bam_txn->bam_ce_pos += size;
-
- /* use the separate sgl after this command */
- if (flags & NAND_BAM_NEXT_SGL) {
- bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
- bam_ce_size = (bam_txn->bam_ce_pos -
- bam_txn->bam_ce_start) *
- sizeof(struct bam_cmd_element);
- sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
- bam_ce_buffer, bam_ce_size);
- bam_txn->cmd_sgl_pos++;
- bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
-
- if (flags & NAND_BAM_NWD) {
- ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
- DMA_PREP_FENCE |
- DMA_PREP_CMD);
- if (ret)
- return ret;
- }
- }
-
- return 0;
-}
-
-/*
- * Prepares the data descriptor for BAM DMA which will be used for NAND
- * data reads and writes.
- */
-static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
- const void *vaddr,
- int size, unsigned int flags)
-{
- int ret;
- struct bam_transaction *bam_txn = nandc->bam_txn;
-
- if (read) {
- sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
- vaddr, size);
- bam_txn->rx_sgl_pos++;
- } else {
- sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
- vaddr, size);
- bam_txn->tx_sgl_pos++;
-
- /*
- * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
- * is not set, form the DMA descriptor
- */
- if (!(flags & NAND_BAM_NO_EOT)) {
- ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
- DMA_PREP_INTERRUPT);
- if (ret)
- return ret;
- }
- }
-
- return 0;
-}
-
-static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
- int reg_off, const void *vaddr, int size,
- bool flow_control)
-{
- struct desc_info *desc;
- struct dma_async_tx_descriptor *dma_desc;
- struct scatterlist *sgl;
- struct dma_slave_config slave_conf;
- struct qcom_adm_peripheral_config periph_conf = {};
- enum dma_transfer_direction dir_eng;
- int ret;
-
- desc = kzalloc(sizeof(*desc), GFP_KERNEL);
- if (!desc)
- return -ENOMEM;
-
- sgl = &desc->adm_sgl;
-
- sg_init_one(sgl, vaddr, size);
-
- if (read) {
- dir_eng = DMA_DEV_TO_MEM;
- desc->dir = DMA_FROM_DEVICE;
- } else {
- dir_eng = DMA_MEM_TO_DEV;
- desc->dir = DMA_TO_DEVICE;
- }
-
- ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
- if (ret == 0) {
- ret = -ENOMEM;
- goto err;
- }
-
- memset(&slave_conf, 0x00, sizeof(slave_conf));
-
- slave_conf.device_fc = flow_control;
- if (read) {
- slave_conf.src_maxburst = 16;
- slave_conf.src_addr = nandc->base_dma + reg_off;
- if (nandc->data_crci) {
- periph_conf.crci = nandc->data_crci;
- slave_conf.peripheral_config = &periph_conf;
- slave_conf.peripheral_size = sizeof(periph_conf);
- }
- } else {
- slave_conf.dst_maxburst = 16;
- slave_conf.dst_addr = nandc->base_dma + reg_off;
- if (nandc->cmd_crci) {
- periph_conf.crci = nandc->cmd_crci;
- slave_conf.peripheral_config = &periph_conf;
- slave_conf.peripheral_size = sizeof(periph_conf);
- }
- }
-
- ret = dmaengine_slave_config(nandc->chan, &slave_conf);
- if (ret) {
- dev_err(nandc->dev, "failed to configure dma channel\n");
- goto err;
- }
-
- dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
- if (!dma_desc) {
- dev_err(nandc->dev, "failed to prepare desc\n");
- ret = -EINVAL;
- goto err;
- }
-
- desc->dma_desc = dma_desc;
-
- list_add_tail(&desc->node, &nandc->desc_list);
-
- return 0;
-err:
- kfree(desc);
-
- return ret;
-}
-
-/*
- * read_reg_dma: prepares a descriptor to read a given number of
- * contiguous registers to the reg_read_buf pointer
- *
- * @first: offset of the first register in the contiguous block
- * @num_regs: number of registers to read
- * @flags: flags to control DMA descriptor preparation
- */
-static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs, unsigned int flags)
-{
- bool flow_control = false;
- void *vaddr;
-
- vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
- nandc->reg_read_pos += num_regs;
-
- if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
- first = dev_cmd_reg_addr(nandc, first);
-
- if (nandc->props->is_bam)
- return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
- num_regs, flags);
-
- if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
- flow_control = true;
-
- return prep_adm_dma_desc(nandc, true, first, vaddr,
- num_regs * sizeof(u32), flow_control);
-}
-
-/*
- * write_reg_dma: prepares a descriptor to write a given number of
- * contiguous registers
- *
- * @first: offset of the first register in the contiguous block
- * @num_regs: number of registers to write
- * @flags: flags to control DMA descriptor preparation
- */
-static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
- int num_regs, unsigned int flags)
-{
- bool flow_control = false;
- struct nandc_regs *regs = nandc->regs;
- void *vaddr;
-
- vaddr = offset_to_nandc_reg(regs, first);
-
- if (first == NAND_ERASED_CW_DETECT_CFG) {
- if (flags & NAND_ERASED_CW_SET)
- vaddr = ®s->erased_cw_detect_cfg_set;
- else
- vaddr = ®s->erased_cw_detect_cfg_clr;
- }
-
- if (first == NAND_EXEC_CMD)
- flags |= NAND_BAM_NWD;
-
- if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
- first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
-
- if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
- first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
-
- if (nandc->props->is_bam)
- return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
- num_regs, flags);
-
- if (first == NAND_FLASH_CMD)
- flow_control = true;
-
- return prep_adm_dma_desc(nandc, false, first, vaddr,
- num_regs * sizeof(u32), flow_control);
-}
-
-/*
- * read_data_dma: prepares a DMA descriptor to transfer data from the
- * controller's internal buffer to the buffer 'vaddr'
- *
- * @reg_off: offset within the controller's data buffer
- * @vaddr: virtual address of the buffer we want to write to
- * @size: DMA transaction size in bytes
- * @flags: flags to control DMA descriptor preparation
- */
-static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
- const u8 *vaddr, int size, unsigned int flags)
-{
- if (nandc->props->is_bam)
- return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
-
- return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
-}
-
-/*
- * write_data_dma: prepares a DMA descriptor to transfer data from
- * 'vaddr' to the controller's internal buffer
- *
- * @reg_off: offset within the controller's data buffer
- * @vaddr: virtual address of the buffer we want to read from
- * @size: DMA transaction size in bytes
- * @flags: flags to control DMA descriptor preparation
- */
-static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
- const u8 *vaddr, int size, unsigned int flags)
-{
- if (nandc->props->is_bam)
- return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
-
- return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
-}
-
-/*
- * Helper to prepare DMA descriptors for configuring registers
- * before reading a NAND page.
- */
-static void config_nand_page_read(struct nand_chip *chip)
-{
- struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
-
- write_reg_dma(nandc, NAND_ADDR0, 2, 0);
- write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
- if (!nandc->props->qpic_v2)
- write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
- write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
- write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
- NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
-}
-
/*
* Helper to prepare DMA descriptors for configuring registers
* before reading each codeword in NAND page.
@@ -1303,88 +318,6 @@ static void config_nand_cw_write(struct nand_chip *chip)
write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
}
-/* helpers to submit/free our list of dma descriptors */
-static int submit_descs(struct qcom_nand_controller *nandc)
-{
- struct desc_info *desc, *n;
- dma_cookie_t cookie = 0;
- struct bam_transaction *bam_txn = nandc->bam_txn;
- int ret = 0;
-
- if (nandc->props->is_bam) {
- if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
- ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
- if (ret)
- goto err_unmap_free_desc;
- }
-
- if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
- ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
- DMA_PREP_INTERRUPT);
- if (ret)
- goto err_unmap_free_desc;
- }
-
- if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
- ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
- DMA_PREP_CMD);
- if (ret)
- goto err_unmap_free_desc;
- }
- }
-
- list_for_each_entry(desc, &nandc->desc_list, node)
- cookie = dmaengine_submit(desc->dma_desc);
-
- if (nandc->props->is_bam) {
- bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
- bam_txn->last_cmd_desc->callback_param = bam_txn;
- if (bam_txn->last_data_desc) {
- bam_txn->last_data_desc->callback = qpic_bam_dma_done;
- bam_txn->last_data_desc->callback_param = bam_txn;
- bam_txn->wait_second_completion = true;
- }
-
- dma_async_issue_pending(nandc->tx_chan);
- dma_async_issue_pending(nandc->rx_chan);
- dma_async_issue_pending(nandc->cmd_chan);
-
- if (!wait_for_completion_timeout(&bam_txn->txn_done,
- QPIC_NAND_COMPLETION_TIMEOUT))
- ret = -ETIMEDOUT;
- } else {
- if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
- ret = -ETIMEDOUT;
- }
-
-err_unmap_free_desc:
- /*
- * Unmap the dma sg_list and free the desc allocated by both
- * prepare_bam_async_desc() and prep_adm_dma_desc() functions.
- */
- list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
- list_del(&desc->node);
-
- if (nandc->props->is_bam)
- dma_unmap_sg(nandc->dev, desc->bam_sgl,
- desc->sgl_cnt, desc->dir);
- else
- dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
- desc->dir);
-
- kfree(desc);
- }
-
- return ret;
-}
-
-/* reset the register read buffer for next NAND operation */
-static void clear_read_regs(struct qcom_nand_controller *nandc)
-{
- nandc->reg_read_pos = 0;
- nandc_read_buffer_sync(nandc, false);
-}
-
/*
* when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
* an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
@@ -3016,136 +1949,6 @@ static const struct nand_controller_ops qcom_nandc_ops = {
.exec_op = qcom_nand_exec_op,
};
-static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
-{
- if (nandc->props->is_bam) {
- if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
- dma_unmap_single(nandc->dev, nandc->reg_read_dma,
- MAX_REG_RD *
- sizeof(*nandc->reg_read_buf),
- DMA_FROM_DEVICE);
-
- if (nandc->tx_chan)
- dma_release_channel(nandc->tx_chan);
-
- if (nandc->rx_chan)
- dma_release_channel(nandc->rx_chan);
-
- if (nandc->cmd_chan)
- dma_release_channel(nandc->cmd_chan);
- } else {
- if (nandc->chan)
- dma_release_channel(nandc->chan);
- }
-}
-
-static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
-{
- int ret;
-
- ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
- if (ret) {
- dev_err(nandc->dev, "failed to set DMA mask\n");
- return ret;
- }
-
- /*
- * we use the internal buffer for reading ONFI params, reading small
- * data like ID and status, and preforming read-copy-write operations
- * when writing to a codeword partially. 532 is the maximum possible
- * size of a codeword for our nand controller
- */
- nandc->buf_size = 532;
-
- nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
- if (!nandc->data_buffer)
- return -ENOMEM;
-
- nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
- if (!nandc->regs)
- return -ENOMEM;
-
- nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
- sizeof(*nandc->reg_read_buf),
- GFP_KERNEL);
- if (!nandc->reg_read_buf)
- return -ENOMEM;
-
- if (nandc->props->is_bam) {
- nandc->reg_read_dma =
- dma_map_single(nandc->dev, nandc->reg_read_buf,
- MAX_REG_RD *
- sizeof(*nandc->reg_read_buf),
- DMA_FROM_DEVICE);
- if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
- dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
- return -EIO;
- }
-
- nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
- if (IS_ERR(nandc->tx_chan)) {
- ret = PTR_ERR(nandc->tx_chan);
- nandc->tx_chan = NULL;
- dev_err_probe(nandc->dev, ret,
- "tx DMA channel request failed\n");
- goto unalloc;
- }
-
- nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
- if (IS_ERR(nandc->rx_chan)) {
- ret = PTR_ERR(nandc->rx_chan);
- nandc->rx_chan = NULL;
- dev_err_probe(nandc->dev, ret,
- "rx DMA channel request failed\n");
- goto unalloc;
- }
-
- nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
- if (IS_ERR(nandc->cmd_chan)) {
- ret = PTR_ERR(nandc->cmd_chan);
- nandc->cmd_chan = NULL;
- dev_err_probe(nandc->dev, ret,
- "cmd DMA channel request failed\n");
- goto unalloc;
- }
-
- /*
- * Initially allocate BAM transaction to read ONFI param page.
- * After detecting all the devices, this BAM transaction will
- * be freed and the next BAM transaction will be allocated with
- * maximum codeword size
- */
- nandc->max_cwperpage = 1;
- nandc->bam_txn = alloc_bam_transaction(nandc);
- if (!nandc->bam_txn) {
- dev_err(nandc->dev,
- "failed to allocate bam transaction\n");
- ret = -ENOMEM;
- goto unalloc;
- }
- } else {
- nandc->chan = dma_request_chan(nandc->dev, "rxtx");
- if (IS_ERR(nandc->chan)) {
- ret = PTR_ERR(nandc->chan);
- nandc->chan = NULL;
- dev_err_probe(nandc->dev, ret,
- "rxtx DMA channel request failed\n");
- return ret;
- }
- }
-
- INIT_LIST_HEAD(&nandc->desc_list);
- INIT_LIST_HEAD(&nandc->host_list);
-
- nand_controller_init(&nandc->controller);
- nandc->controller.ops = &qcom_nandc_ops;
-
- return 0;
-unalloc:
- qcom_nandc_unalloc(nandc);
- return ret;
-}
-
/* one time setup of a few nand controller registers */
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
{
@@ -3427,6 +2230,9 @@ static int qcom_nandc_probe(struct platform_device *pdev)
if (ret)
goto err_nandc_alloc;
+ nand_controller_init(&nandc->controller);
+ nandc->controller.ops = &qcom_nandc_ops;
+
ret = qcom_nandc_setup(nandc);
if (ret)
goto err_setup;
@@ -3473,28 +2279,28 @@ static void qcom_nandc_remove(struct platform_device *pdev)
DMA_BIDIRECTIONAL, 0);
}
-static const struct qcom_nandc_props ipq806x_nandc_props = {
+static struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
.use_codeword_fixup = true,
.dev_cmd_reg_start = 0x0,
};
-static const struct qcom_nandc_props ipq4019_nandc_props = {
+static struct qcom_nandc_props ipq4019_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
.is_qpic = true,
.dev_cmd_reg_start = 0x0,
};
-static const struct qcom_nandc_props ipq8074_nandc_props = {
+static struct qcom_nandc_props ipq8074_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
.is_qpic = true,
.dev_cmd_reg_start = 0x7000,
};
-static const struct qcom_nandc_props sdx55_nandc_props = {
+static struct qcom_nandc_props sdx55_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
.is_qpic = true,
diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
new file mode 100644
index 000000000000..891f975ca173
--- /dev/null
+++ b/include/linux/mtd/nand-qpic-common.h
@@ -0,0 +1,488 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * QCOM QPIC common APIs header file
+ *
+ * Copyright (c) 2023 Qualcomm Inc.
+ * Authors: Md sadre Alam <[email protected]>
+ * Sricharan R <[email protected]>
+ * Varadarajan Narayanan <[email protected]>
+ *
+ */
+#ifndef __MTD_NAND_QPIC_COMMON_H__
+#define __MTD_NAND_QPIC_COMMON_H__
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/dma/qcom_adm.h>
+#include <linux/dma/qcom_bam_dma.h>
+#include <linux/module.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/* NANDc reg offsets */
+#define NAND_FLASH_CMD 0x00
+#define NAND_ADDR0 0x04
+#define NAND_ADDR1 0x08
+#define NAND_FLASH_CHIP_SELECT 0x0c
+#define NAND_EXEC_CMD 0x10
+#define NAND_FLASH_STATUS 0x14
+#define NAND_BUFFER_STATUS 0x18
+#define NAND_DEV0_CFG0 0x20
+#define NAND_DEV0_CFG1 0x24
+#define NAND_DEV0_ECC_CFG 0x28
+#define NAND_AUTO_STATUS_EN 0x2c
+#define NAND_DEV1_CFG0 0x30
+#define NAND_DEV1_CFG1 0x34
+#define NAND_READ_ID 0x40
+#define NAND_READ_STATUS 0x44
+#define NAND_DEV_CMD0 0xa0
+#define NAND_DEV_CMD1 0xa4
+#define NAND_DEV_CMD2 0xa8
+#define NAND_DEV_CMD_VLD 0xac
+#define SFLASHC_BURST_CFG 0xe0
+#define NAND_ERASED_CW_DETECT_CFG 0xe8
+#define NAND_ERASED_CW_DETECT_STATUS 0xec
+#define NAND_EBI2_ECC_BUF_CFG 0xf0
+#define FLASH_BUF_ACC 0x100
+
+#define NAND_CTRL 0xf00
+#define NAND_VERSION 0xf08
+#define NAND_READ_LOCATION_0 0xf20
+#define NAND_READ_LOCATION_1 0xf24
+#define NAND_READ_LOCATION_2 0xf28
+#define NAND_READ_LOCATION_3 0xf2c
+#define NAND_READ_LOCATION_LAST_CW_0 0xf40
+#define NAND_READ_LOCATION_LAST_CW_1 0xf44
+#define NAND_READ_LOCATION_LAST_CW_2 0xf48
+#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
+
+/* dummy register offsets, used by write_reg_dma */
+#define NAND_DEV_CMD1_RESTORE 0xdead
+#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
+
+/* NAND_FLASH_CMD bits */
+#define PAGE_ACC BIT(4)
+#define LAST_PAGE BIT(5)
+
+/* NAND_FLASH_CHIP_SELECT bits */
+#define NAND_DEV_SEL 0
+#define DM_EN BIT(2)
+
+/* NAND_FLASH_STATUS bits */
+#define FS_OP_ERR BIT(4)
+#define FS_READY_BSY_N BIT(5)
+#define FS_MPU_ERR BIT(8)
+#define FS_DEVICE_STS_ERR BIT(16)
+#define FS_DEVICE_WP BIT(23)
+
+/* NAND_BUFFER_STATUS bits */
+#define BS_UNCORRECTABLE_BIT BIT(8)
+#define BS_CORRECTABLE_ERR_MSK 0x1f
+
+/* NAND_DEVn_CFG0 bits */
+#define DISABLE_STATUS_AFTER_WRITE 4
+#define CW_PER_PAGE 6
+#define UD_SIZE_BYTES 9
+#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
+#define ECC_PARITY_SIZE_BYTES_RS 19
+#define SPARE_SIZE_BYTES 23
+#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
+#define NUM_ADDR_CYCLES 27
+#define STATUS_BFR_READ 30
+#define SET_RD_MODE_AFTER_STATUS 31
+
+/* NAND_DEVn_CFG0 bits */
+#define DEV0_CFG1_ECC_DISABLE 0
+#define WIDE_FLASH 1
+#define NAND_RECOVERY_CYCLES 2
+#define CS_ACTIVE_BSY 5
+#define BAD_BLOCK_BYTE_NUM 6
+#define BAD_BLOCK_IN_SPARE_AREA 16
+#define WR_RD_BSY_GAP 17
+#define ENABLE_BCH_ECC 27
+
+/* NAND_DEV0_ECC_CFG bits */
+#define ECC_CFG_ECC_DISABLE 0
+#define ECC_SW_RESET 1
+#define ECC_MODE 4
+#define ECC_PARITY_SIZE_BYTES_BCH 8
+#define ECC_NUM_DATA_BYTES 16
+#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
+#define ECC_FORCE_CLK_OPEN 30
+
+/* NAND_DEV_CMD1 bits */
+#define READ_ADDR 0
+
+/* NAND_DEV_CMD_VLD bits */
+#define READ_START_VLD BIT(0)
+#define READ_STOP_VLD BIT(1)
+#define WRITE_START_VLD BIT(2)
+#define ERASE_START_VLD BIT(3)
+#define SEQ_READ_START_VLD BIT(4)
+
+/* NAND_EBI2_ECC_BUF_CFG bits */
+#define NUM_STEPS 0
+
+/* NAND_ERASED_CW_DETECT_CFG bits */
+#define ERASED_CW_ECC_MASK 1
+#define AUTO_DETECT_RES 0
+#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
+#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
+#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
+#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
+#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
+
+/* NAND_ERASED_CW_DETECT_STATUS bits */
+#define PAGE_ALL_ERASED BIT(7)
+#define CODEWORD_ALL_ERASED BIT(6)
+#define PAGE_ERASED BIT(5)
+#define CODEWORD_ERASED BIT(4)
+#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
+#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
+
+/* NAND_READ_LOCATION_n bits */
+#define READ_LOCATION_OFFSET 0
+#define READ_LOCATION_SIZE 16
+#define READ_LOCATION_LAST 31
+
+/* Version Mask */
+#define NAND_VERSION_MAJOR_MASK 0xf0000000
+#define NAND_VERSION_MAJOR_SHIFT 28
+#define NAND_VERSION_MINOR_MASK 0x0fff0000
+#define NAND_VERSION_MINOR_SHIFT 16
+
+/* NAND OP_CMDs */
+#define OP_PAGE_READ 0x2
+#define OP_PAGE_READ_WITH_ECC 0x3
+#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
+#define OP_PAGE_READ_ONFI_READ 0x5
+#define OP_PROGRAM_PAGE 0x6
+#define OP_PAGE_PROGRAM_WITH_ECC 0x7
+#define OP_PROGRAM_PAGE_SPARE 0x9
+#define OP_BLOCK_ERASE 0xa
+#define OP_CHECK_STATUS 0xc
+#define OP_FETCH_ID 0xb
+#define OP_RESET_DEVICE 0xd
+
+/* Default Value for NAND_DEV_CMD_VLD */
+#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
+ ERASE_START_VLD | SEQ_READ_START_VLD)
+
+/* NAND_CTRL bits */
+#define BAM_MODE_EN BIT(0)
+
+/*
+ * the NAND controller performs reads/writes with ECC in 516 byte chunks.
+ * the driver calls the chunks 'step' or 'codeword' interchangeably
+ */
+#define NANDC_STEP_SIZE 512
+
+/*
+ * the largest page size we support is 8K, this will have 16 steps/codewords
+ * of 512 bytes each
+ */
+#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
+
+/* we read at most 3 registers per codeword scan */
+#define MAX_REG_RD (3 * MAX_NUM_STEPS)
+
+#define QPIC_PER_CW_CMD_ELEMENTS 32
+#define QPIC_PER_CW_CMD_SGL 32
+#define QPIC_PER_CW_DATA_SGL 8
+
+#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
+
+/*
+ * Flags used in DMA descriptor preparation helper functions
+ * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
+ */
+/* Don't set the EOT in current tx BAM sgl */
+#define NAND_BAM_NO_EOT BIT(0)
+/* Set the NWD flag in current BAM sgl */
+#define NAND_BAM_NWD BIT(1)
+/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
+#define NAND_BAM_NEXT_SGL BIT(2)
+
+/*
+ * Returns the actual register address for all NAND_DEV_ registers
+ * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
+ */
+#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
+
+/* Returns the NAND register physical address */
+#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
+
+/* Returns the dma address for reg read buffer */
+#define reg_buf_dma_addr(chip, vaddr) \
+ ((chip)->reg_read_dma + \
+ ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
+
+/*
+ * Erased codeword status is being used two times in single transfer so this
+ * flag will determine the current value of erased codeword status register
+ */
+#define NAND_ERASED_CW_SET BIT(4)
+
+#define MAX_ADDRESS_CYCLE 5
+
+/*
+ * This data type corresponds to the BAM transaction which will be used for all
+ * NAND transfers.
+ * @bam_ce - the array of BAM command elements
+ * @cmd_sgl - sgl for NAND BAM command pipe
+ * @data_sgl - sgl for NAND BAM consumer/producer pipe
+ * @last_data_desc - last DMA desc in data channel (tx/rx).
+ * @last_cmd_desc - last DMA desc in command channel.
+ * @txn_done - completion for NAND transfer.
+ * @bam_ce_pos - the index in bam_ce which is available for next sgl
+ * @bam_ce_start - the index in bam_ce which marks the start position ce
+ * for current sgl. It will be used for size calculation
+ * for current sgl
+ * @cmd_sgl_pos - current index in command sgl.
+ * @cmd_sgl_start - start index in command sgl.
+ * @tx_sgl_pos - current index in data sgl for tx.
+ * @tx_sgl_start - start index in data sgl for tx.
+ * @rx_sgl_pos - current index in data sgl for rx.
+ * @rx_sgl_start - start index in data sgl for rx.
+ * @wait_second_completion - wait for second DMA desc completion before making
+ * the NAND transfer completion.
+ */
+struct bam_transaction {
+ struct bam_cmd_element *bam_ce;
+ struct scatterlist *cmd_sgl;
+ struct scatterlist *data_sgl;
+ struct dma_async_tx_descriptor *last_data_desc;
+ struct dma_async_tx_descriptor *last_cmd_desc;
+ struct completion txn_done;
+ u32 bam_ce_pos;
+ u32 bam_ce_start;
+ u32 cmd_sgl_pos;
+ u32 cmd_sgl_start;
+ u32 tx_sgl_pos;
+ u32 tx_sgl_start;
+ u32 rx_sgl_pos;
+ u32 rx_sgl_start;
+ bool wait_second_completion;
+};
+
+/*
+ * This data type corresponds to the nand dma descriptor
+ * @dma_desc - low level DMA engine descriptor
+ * @list - list for desc_info
+ *
+ * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
+ * ADM
+ * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
+ * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
+ * @dir - DMA transfer direction
+ */
+struct desc_info {
+ struct dma_async_tx_descriptor *dma_desc;
+ struct list_head node;
+
+ union {
+ struct scatterlist adm_sgl;
+ struct {
+ struct scatterlist *bam_sgl;
+ int sgl_cnt;
+ };
+ };
+ enum dma_data_direction dir;
+};
+
+/*
+ * holds the current register values that we want to write. acts as a contiguous
+ * chunk of memory which we use to write the controller registers through DMA.
+ */
+struct nandc_regs {
+ __le32 cmd;
+ __le32 addr0;
+ __le32 addr1;
+ __le32 chip_sel;
+ __le32 exec;
+
+ __le32 cfg0;
+ __le32 cfg1;
+ __le32 ecc_bch_cfg;
+
+ __le32 clrflashstatus;
+ __le32 clrreadstatus;
+
+ __le32 cmd1;
+ __le32 vld;
+
+ __le32 orig_cmd1;
+ __le32 orig_vld;
+
+ __le32 ecc_buf_cfg;
+ __le32 read_location0;
+ __le32 read_location1;
+ __le32 read_location2;
+ __le32 read_location3;
+ __le32 read_location_last0;
+ __le32 read_location_last1;
+ __le32 read_location_last2;
+ __le32 read_location_last3;
+
+ __le32 erased_cw_detect_cfg_clr;
+ __le32 erased_cw_detect_cfg_set;
+};
+
+/*
+ * NAND controller data struct
+ *
+ * @dev: parent device
+ *
+ * @base: MMIO base
+ *
+ * @core_clk: controller clock
+ * @aon_clk: another controller clock
+ *
+ * @regs: a contiguous chunk of memory for DMA register
+ * writes. contains the register values to be
+ * written to controller
+ *
+ * @props: properties of current NAND controller,
+ * initialized via DT match data
+ *
+ * @controller: base controller structure
+ * @host_list: list containing all the chips attached to the
+ * controller
+ *
+ * @chan: dma channel
+ * @cmd_crci: ADM DMA CRCI for command flow control
+ * @data_crci: ADM DMA CRCI for data flow control
+ *
+ * @desc_list: DMA descriptor list (list of desc_infos)
+ *
+ * @data_buffer: our local DMA buffer for page read/writes,
+ * used when we can't use the buffer provided
+ * by upper layers directly
+ * @reg_read_buf: local buffer for reading back registers via DMA
+ *
+ * @base_phys: physical base address of controller registers
+ * @base_dma: dma base address of controller registers
+ * @reg_read_dma: contains dma address for register read buffer
+ *
+ * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
+ * functions
+ * @max_cwperpage: maximum QPIC codewords required. calculated
+ * from all connected NAND devices pagesize
+ *
+ * @reg_read_pos: marker for data read in reg_read_buf
+ *
+ * @cmd1/vld: some fixed controller register values
+ *
+ * @exec_opwrite: flag to select correct number of code word
+ * while reading status
+ */
+struct qcom_nand_controller {
+ struct device *dev;
+
+ void __iomem *base;
+
+ struct clk *core_clk;
+ struct clk *aon_clk;
+
+ struct nandc_regs *regs;
+ struct bam_transaction *bam_txn;
+
+ const struct qcom_nandc_props *props;
+
+ struct nand_controller controller;
+ struct list_head host_list;
+
+ union {
+ /* will be used only by QPIC for BAM DMA */
+ struct {
+ struct dma_chan *tx_chan;
+ struct dma_chan *rx_chan;
+ struct dma_chan *cmd_chan;
+ };
+
+ /* will be used only by EBI2 for ADM DMA */
+ struct {
+ struct dma_chan *chan;
+ unsigned int cmd_crci;
+ unsigned int data_crci;
+ };
+ };
+
+ struct list_head desc_list;
+
+ u8 *data_buffer;
+ __le32 *reg_read_buf;
+
+ phys_addr_t base_phys;
+ dma_addr_t base_dma;
+ dma_addr_t reg_read_dma;
+
+ int buf_size;
+ int buf_count;
+ int buf_start;
+ unsigned int max_cwperpage;
+
+ int reg_read_pos;
+
+ u32 cmd1, vld;
+ bool exec_opwrite;
+};
+
+/*
+ * This data type corresponds to the NAND controller properties which varies
+ * among different NAND controllers.
+ * @ecc_modes - ecc mode for NAND
+ * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
+ * @is_bam - whether NAND controller is using BAM
+ * @is_qpic - whether NAND CTRL is part of qpic IP
+ * @qpic_v2 - flag to indicate QPIC IP version 2
+ * @use_codeword_fixup - whether NAND has different layout for boot partitions
+ */
+struct qcom_nandc_props {
+ u32 ecc_modes;
+ u32 dev_cmd_reg_start;
+ bool is_bam;
+ bool is_qpic;
+ bool qpic_v2;
+ bool use_codeword_fixup;
+};
+
+void config_nand_page_read(struct nand_chip *chip);
+void free_bam_transaction(struct qcom_nand_controller *nandc);
+void qpic_bam_dma_done(void *data);
+void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, bool is_cpu);
+__le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset);
+void clear_read_regs(struct qcom_nand_controller *nandc);
+int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr, int size,
+ bool flow_control);
+int submit_descs(struct qcom_nand_controller *nandc);
+int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
+ struct dma_chan *chan, unsigned long flags);
+int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
+ int reg_off, const void *vaddr,
+ int size, unsigned int flags);
+int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
+ const void *vaddr,
+ int size, unsigned int flags);
+int read_reg_dma(struct qcom_nand_controller *nandc, int first,
+ int num_regs, unsigned int flags);
+int write_reg_dma(struct qcom_nand_controller *nandc, int first,
+ int num_regs, unsigned int flags);
+int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
+ const u8 *vaddr, int size, unsigned int flags);
+int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
+ const u8 *vaddr, int size, unsigned int flags);
+struct bam_transaction *alloc_bam_transaction(struct qcom_nand_controller *nandc);
+void clear_bam_transaction(struct qcom_nand_controller *nandc);
+void qcom_nandc_unalloc(struct qcom_nand_controller *nandc);
+int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
+struct qcom_nand_controller *get_qcom_nand_controller(struct nand_chip *chip);
+
+#endif
--
2.34.1
Add device-tree binding documentation for QCOM QPIC-SNAND-NAND Flash
Interface.
Co-developed-by: Sricharan Ramabadhran <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Md Sadre Alam <[email protected]>
---
.../bindings/spi/qcom,spi-qpic-snand.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
new file mode 100644
index 000000000000..fa7484ce1319
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QPIC NAND controller
+
+maintainers:
+ - Md sadre Alam <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq9574-snand
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+allOf:
+ - $ref: /schemas/spi/spi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq9574-snand
+
+ then:
+ properties:
+ dmas:
+ items:
+ - description: tx DMA channel
+ - description: rx DMA channel
+ - description: cmd DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ - const: cmd
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+ qpic_nand: spi@79b0000 {
+ compatible = "qcom,ipq9574-snand";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>,
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
+ clock-names = "core", "aon", "iom";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-ecc-engine = <&qpic_nand>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ };
+ };
--
2.34.1
On Thu, Feb 15, 2024 at 07:18:54PM +0530, Md Sadre Alam wrote:
> +config SPI_QPIC_SNAND
> + tristate "QPIC SNAND controller"
> + default y
Why is this driver so special it should be enabled by default?
> + depends on ARCH_QCOM
Please add an || COMPILE_TEST so this gets some build coverage.
> + help
> + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
> + QPIC controller supports both parallel nand and serial nand.
> + This config will enable serial nand driver for QPIC controller.
> +
> config SPI_QUP
> tristate "Qualcomm SPI controller with QUP interface"
> depends on ARCH_QCOM || COMPILE_TEST
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 4ff8d725ba5e..1ac3bac35007 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -153,6 +153,7 @@ obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
> obj-$(CONFIG_SPI_ZYNQ_QSPI) += spi-zynq-qspi.o
> obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o
> obj-$(CONFIG_SPI_AMD) += spi-amd.o
> +obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
Please keep this sorted.
> --- /dev/null
> +++ b/drivers/spi/spi-qpic-snand.c
> @@ -0,0 +1,1025 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
Please make the entire comment a C++ one so things look more
intentional.
> +#define snandc_set_read_loc_first(snandc, reg, cw_offset, read_size, is_last_read_loc) \
> +snandc_set_reg(snandc, reg, \
> + ((cw_offset) << READ_LOCATION_OFFSET) | \
> + ((read_size) << READ_LOCATION_SIZE) | \
> + ((is_last_read_loc) << READ_LOCATION_LAST))
> +
> +#define snandc_set_read_loc_last(snandc, reg, cw_offset, read_size, is_last_read_loc) \
> +snandc_set_reg(snandc, reg, \
> + ((cw_offset) << READ_LOCATION_OFFSET) | \
> + ((read_size) << READ_LOCATION_SIZE) | \
> + ((is_last_read_loc) << READ_LOCATION_LAST))
For type safety and legibility please write these as functions, mark
them as static inline if needed.
> +void snandc_set_reg(struct qcom_nand_controller *snandc, int offset, u32 val)
> +{
> + struct nandc_regs *regs = snandc->regs;
> + __le32 *reg;
> +
> + reg = offset_to_nandc_reg(regs, offset);
> +
> + if (reg)
> + *reg = cpu_to_le32(val);
> +}
This silently ignores writes to invalid registers, that doesn't seem
great.
> + return snandc->ecc_stats.failed ? -EBADMSG : snandc->ecc_stats.bitflips;
For legibility please just write normal conditional statements.
> +static int qpic_snand_program_execute(struct qcom_nand_controller *snandc,
> + const struct spi_mem_op *op)
> +{
> + int num_cw = 4;
> + data_buf = (u8 *)snandc->wbuf;
Why the cast? If it's needed that smells like it's masking a bug, it
looks like it's casting from a u8 * to a u8 *.
> + for (i = 0; i < num_cw; i++) {
> + int data_size;
All these functions appear to hard code "num_cw" to 4. What is "num_cw"
and why are we doing this per function?
> +static int qpic_snand_program_execute(struct qcom_nand_controller *snandc,
> + const struct spi_mem_op *op)
> + if (op->cmd.opcode == SPINAND_READID) {
> + snandc->buf_count = 4;
> + read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
> +
> + ret = submit_descs(snandc);
> + if (ret)
> + dev_err(snandc->dev, "failure in submitting descriptor for readid\n");
> +
> + nandc_read_buffer_sync(snandc, true);
> + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
These memcpy()s don't seem great, why aren't we just reading directly
into the output buffer?
> + if (op->cmd.opcode == SPINAND_GET_FEATURE) {
This function looks like it should be a switch statement.
> +static bool qpic_snand_is_page_op(const struct spi_mem_op *op)
> +{
> + if (op->data.dir == SPI_MEM_DATA_IN) {
> + if (op->addr.buswidth == 4 && op->data.buswidth == 4)
> + return true;
> +
> + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
> + return true;
> +
> + } else if (op->data.dir == SPI_MEM_DATA_OUT) {
> + if (op->data.buswidth == 4)
> + return true;
> + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
> + return true;
> + }
Again looks like a switch statement.
> + ctlr = devm_spi_alloc_master(dev, sizeof(*snandc));
> + if (!ctlr)
> + return -ENOMEM;
Please use _alloc_controller.
> +static int qcom_snand_remove(struct platform_device *pdev)
> +{
> + struct spi_controller *ctlr = platform_get_drvdata(pdev);
> +
> + spi_unregister_controller(ctlr);
> +
> + return 0;
> +}
We don't disable any of the clocks in the remove path.
On Thu, Feb 15, 2024 at 07:18:52PM +0530, Md Sadre Alam wrote:
> + clocks:
> + minItems: 2
> + maxItems: 3
> +
> + clock-names:
> + minItems: 2
> + maxItems: 3
The driver requests the clocks by name but this does not document the
expected set of names. The driver also unconditionally requests all
three clocks so won't work with only two clocks.
On Thu, Feb 15, 2024 at 07:18:52PM +0530, Md Sadre Alam wrote:
> Add device-tree binding documentation for QCOM QPIC-SNAND-NAND Flash
> Interface.
>
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Co-developed-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Md Sadre Alam <[email protected]>
> ---
> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 +++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
> new file mode 100644
> index 000000000000..fa7484ce1319
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QPIC NAND controller
> +
> +maintainers:
> + - Md sadre Alam <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq9574-snand
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
> +
> + clock-names:
> + minItems: 2
> + maxItems: 3
> +
> +allOf:
> + - $ref: /schemas/spi/spi-controller.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq9574-snand
> +
> + then:
> + properties:
> + dmas:
> + items:
> + - description: tx DMA channel
> + - description: rx DMA channel
> + - description: cmd DMA channel
> +
> + dma-names:
> + items:
> + - const: tx
> + - const: rx
> + - const: cmd
None of this complexity here is needed, you have only one device in this
binding and therefore can define these properties at the top level.
Cheers,
Conor.
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> + qpic_nand: spi@79b0000 {
> + compatible = "qcom,ipq9574-snand";
> + reg = <0x1ac00000 0x800>;
> +
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>,
> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
> + clock-names = "core", "aon", "iom";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "spi-nand";
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-ecc-engine = <&qpic_nand>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + };
> + };
> --
> 2.34.1
>
On Thu, 15 Feb 2024 at 15:53, Md Sadre Alam <[email protected]> wrote:
>
> Add qpic_common.c file which hold all the common
> qpic APIs which will be used by both qpic raw nand
> driver and qpic spi nand driver.
>
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Co-developed-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Md Sadre Alam <[email protected]>
> ---
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
> 4 files changed, 1291 insertions(+), 1210 deletions(-)
> create mode 100644 drivers/mtd/nand/qpic_common.c
> create mode 100644 include/linux/mtd/nand-qpic-common.h
>
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 19e1291ac4d5..131707a41293 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
> +obj-y += qpic_common.o
> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
> new file mode 100644
> index 000000000000..4d74ba888028
> --- /dev/null
> +++ b/drivers/mtd/nand/qpic_common.c
> @@ -0,0 +1,786 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * QPIC Controller common API file.
> + * Copyright (C) 2023 Qualcomm Inc.
> + * Authors: Md sadre Alam <[email protected]>
> + * Sricharan R <[email protected]>
> + * Varadarajan Narayanan <[email protected]>
This is a bit of an exaggeration. You are moving code, not writing new
code. Please retain the existing copyrights for the moved code.
> + *
> + */
> +
> +#include <linux/mtd/nand-qpic-common.h>
> +
> +struct qcom_nand_controller *
> +get_qcom_nand_controller(struct nand_chip *chip)
> +{
> + return container_of(chip->controller, struct qcom_nand_controller,
> + controller);
> +}
> +EXPORT_SYMBOL(get_qcom_nand_controller);
NAK for adding functions to the global export namespace without a
proper driver-specific prefix.
Also, a bunch of the code here seems not so well thought. It was fine
for an internal interface, but it doesn't look so good as a common
wrapper. Please consider defining a sensible common code module
interface instead.
At least each function that is being exported should get a kerneldoc.
Last, but not least, please use EXPORT_SYMBOL_GPL.
> +
> +/*
> + * Helper to prepare DMA descriptors for configuring registers
> + * before reading a NAND page.
> + */
> +void config_nand_page_read(struct nand_chip *chip)
> +{
> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +
> + write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> + write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> +}
> +EXPORT_SYMBOL(config_nand_page_read);
> +
> +/* Frees the BAM transaction memory */
> +void free_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> + devm_kfree(nandc->dev, bam_txn);
devm_kfree is usually a bad sign. Either the devm_kfree should be
dropped (because the memory area is allocated only during probe / init
and doesn't need to be freed manually) or use kalloc/kfree directly
without devres wrapping.
> +}
> +EXPORT_SYMBOL(free_bam_transaction);
> +
[skipped the rest]
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
On 15.02.2024 14:48, Md Sadre Alam wrote:
> Add qpic_common.c file which hold all the common
> qpic APIs which will be used by both qpic raw nand
> driver and qpic spi nand driver.
>
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Co-developed-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Md Sadre Alam <[email protected]>
> ---
IIUC this is mostly moving code around?
I do however have some suggestions..
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
> 4 files changed, 1291 insertions(+), 1210 deletions(-)
> create mode 100644 drivers/mtd/nand/qpic_common.c
> create mode 100644 include/linux/mtd/nand-qpic-common.h
>
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 19e1291ac4d5..131707a41293 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
> +obj-y += qpic_common.o
> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
> new file mode 100644
> index 000000000000..4d74ba888028
> --- /dev/null
> +++ b/drivers/mtd/nand/qpic_common.c
> @@ -0,0 +1,786 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * QPIC Controller common API file.
> + * Copyright (C) 2023 Qualcomm Inc.
> + * Authors: Md sadre Alam <[email protected]>
> + * Sricharan R <[email protected]>
> + * Varadarajan Narayanan <[email protected]>
> + *
> + */
> +
> +#include <linux/mtd/nand-qpic-common.h>
> +
> +struct qcom_nand_controller *
> +get_qcom_nand_controller(struct nand_chip *chip)
> +{
> + return container_of(chip->controller, struct qcom_nand_controller,
> + controller);
> +}
> +EXPORT_SYMBOL(get_qcom_nand_controller);
#define to_qcom_nand_controller()?
> +
> +/*
> + * Helper to prepare DMA descriptors for configuring registers
> + * before reading a NAND page.
> + */
Can you convert these to kerneldoc instead?
> +void config_nand_page_read(struct nand_chip *chip)
> +{
> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +
> + write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> + write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> + if (!nandc->props->qpic_v2)
This is not going to scale going forward.. please include a version
enum instead.
[...]
> +
> +int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
> + int reg_off, const void *vaddr, int size,
> + bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + struct dma_slave_config slave_conf;
> + struct qcom_adm_peripheral_config periph_conf = {};
> + enum dma_transfer_direction dir_eng;
> + int ret;
Revertse-christmas-tree, please
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + sgl = &desc->adm_sgl;
> +
> + sg_init_one(sgl, vaddr, size);
> +
> + if (read) {
> + dir_eng = DMA_DEV_TO_MEM;
> + desc->dir = DMA_FROM_DEVICE;
> + } else {
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + }
> +
> + ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
> + if (ret == 0) {
if (!ret)
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + memset(&slave_conf, 0x00, sizeof(slave_conf));
Just zero-initialize it (= { 0 }) at declaration time
Konrad
On 15.02.2024 14:48, Md Sadre Alam wrote:
> Add qpic spi nand driver support. The spi nand
> driver currently supported the below commands.
>
> -- RESET
> -- READ ID
> -- SET FEATURE
> -- GET FEATURE
> -- READ PAGE
> -- WRITE PAGE
> -- ERASE PAGE
>
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Co-developed-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Md Sadre Alam <[email protected]>
> ---
[...]
> +void snandc_set_reg(struct qcom_nand_controller *snandc, int offset, u32 val)
> +{
> + struct nandc_regs *regs = snandc->regs;
> + __le32 *reg;
> +
> + reg = offset_to_nandc_reg(regs, offset);
> +
> + if (reg)
> + *reg = cpu_to_le32(val);
if (WARN_ON(!reg))
return;
instead?
This would be tragic..
[...]
> +
> + ecc_cfg->cfg0 = (cwperpage - 1) << CW_PER_PAGE
> + | ecc_cfg->cw_data << UD_SIZE_BYTES
> + | 1 << DISABLE_STATUS_AFTER_WRITE
> + | 3 << NUM_ADDR_CYCLES
> + | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
> + | 0 << STATUS_BFR_READ
> + | 1 << SET_RD_MODE_AFTER_STATUS
> + | ecc_cfg->spare_bytes << SPARE_SIZE_BYTES;
Let me introduce you to FIELD_PREP/GET and GENMASK().. Many assignments
in this file could use these.
Konrad
On 15/02/2024 14:48, Md Sadre Alam wrote:
> Add device-tree binding documentation for QCOM QPIC-SNAND-NAND Flash
> Interface.
>
A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Co-developed-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Md Sadre Alam <[email protected]>
> ---
> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 +++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
> new file mode 100644
> index 000000000000..fa7484ce1319
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
Filename like compatible.
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm QPIC NAND controller
> +
> +maintainers:
> + - Md sadre Alam <[email protected]>
> +
Provide description which will describe hardware.
> +properties:
> + compatible:
> + enum:
> + - qcom,ipq9574-snand
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 3
You must document the items (could be sufficient in clock-names if the
names are obvious).
Why the clocks are flexible? This given IPQ9574 has variable clock
inputs? Please explain.
> +
> + clock-names:
> + minItems: 2
> + maxItems: 3
> +
required goes here.
> +allOf:
> + - $ref: /schemas/spi/spi-controller.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,ipq9574-snand
> +
> + then:
> + properties:
> + dmas:
> + items:
> + - description: tx DMA channel
> + - description: rx DMA channel
> + - description: cmd DMA channel
> +
> + dma-names:
> + items:
> + - const: tx
> + - const: rx
> + - const: cmd
No clue why it is here, move it to top level.
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
> + qpic_nand: spi@79b0000 {
Drop unused label
> + compatible = "qcom,ipq9574-snand";
> + reg = <0x1ac00000 0x800>;
> +
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>,
> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
> + clock-names = "core", "aon", "iom";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash@0 {
> + compatible = "spi-nand";
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nand-ecc-engine = <&qpic_nand>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + };
Fix indentation.
> + };
Best regards,
Krzysztof
On 2/15/2024 7:18 PM, Md Sadre Alam wrote:
> Add qpic_common.c file which hold all the common
> qpic APIs which will be used by both qpic raw nand
> driver and qpic spi nand driver.
>
> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> Co-developed-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> Signed-off-by: Md Sadre Alam <[email protected]>
> ---
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
> 4 files changed, 1291 insertions(+), 1210 deletions(-)
> create mode 100644 drivers/mtd/nand/qpic_common.c
> create mode 100644 include/linux/mtd/nand-qpic-common.h
>
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index 19e1291ac4d5..131707a41293 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
> +obj-y += qpic_common.o
> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
> new file mode 100644
> index 000000000000..4d74ba888028
> --- /dev/null
> +++ b/drivers/mtd/nand/qpic_common.c
> @@ -0,0 +1,786 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * QPIC Controller common API file.
> + * Copyright (C) 2023 Qualcomm Inc.
Copyright should be repharsed?
> + * Authors: Md sadre Alam <[email protected]>
> + * Sricharan R <[email protected]>
> + * Varadarajan Narayanan <[email protected]>
> + *
> + */
> +
> +#include <linux/mtd/nand-qpic-common.h>
> +
> +struct qcom_nand_controller *
> +get_qcom_nand_controller(struct nand_chip *chip)
> +{
> + return container_of(chip->controller, struct qcom_nand_controller,
> + controller);
> +}
> +EXPORT_SYMBOL(get_qcom_nand_controller);
> +
> +/*
> + * Helper to prepare DMA descriptors for configuring registers
> + * before reading a NAND page.
> + */
> +void config_nand_page_read(struct nand_chip *chip)
> +{
> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +
> + write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> + write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> + if (!nandc->props->qpic_v2)
> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> +}
> +EXPORT_SYMBOL(config_nand_page_read);
> +
> +/* Frees the BAM transaction memory */
> +void free_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> + devm_kfree(nandc->dev, bam_txn);
> +}
> +EXPORT_SYMBOL(free_bam_transaction);
> +
> +/* Callback for DMA descriptor completion */
> +void qpic_bam_dma_done(void *data)
> +{
> + struct bam_transaction *bam_txn = data;
> +
> + /*
> + * In case of data transfer with NAND, 2 callbacks will be generated.
> + * One for command channel and another one for data channel.
> + * If current transaction has data descriptors
> + * (i.e. wait_second_completion is true), then set this to false
> + * and wait for second DMA descriptor completion.
> + */
> + if (bam_txn->wait_second_completion)
> + bam_txn->wait_second_completion = false;
> + else
> + complete(&bam_txn->txn_done);
> +}
> +EXPORT_SYMBOL(qpic_bam_dma_done);
> +
> +void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
> + bool is_cpu)
> +{
> + if (!nandc->props->is_bam)
> + return;
> +
> + if (is_cpu)
> + dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> + else
> + dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> +}
> +EXPORT_SYMBOL(nandc_read_buffer_sync);
> +
> +__le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
> +{
> + switch (offset) {
> + case NAND_FLASH_CMD:
> + return ®s->cmd;
> + case NAND_ADDR0:
> + return ®s->addr0;
> + case NAND_ADDR1:
> + return ®s->addr1;
> + case NAND_FLASH_CHIP_SELECT:
> + return ®s->chip_sel;
> + case NAND_EXEC_CMD:
> + return ®s->exec;
> + case NAND_FLASH_STATUS:
> + return ®s->clrflashstatus;
> + case NAND_DEV0_CFG0:
> + return ®s->cfg0;
> + case NAND_DEV0_CFG1:
> + return ®s->cfg1;
> + case NAND_DEV0_ECC_CFG:
> + return ®s->ecc_bch_cfg;
> + case NAND_READ_STATUS:
> + return ®s->clrreadstatus;
> + case NAND_DEV_CMD1:
> + return ®s->cmd1;
> + case NAND_DEV_CMD1_RESTORE:
> + return ®s->orig_cmd1;
> + case NAND_DEV_CMD_VLD:
> + return ®s->vld;
> + case NAND_DEV_CMD_VLD_RESTORE:
> + return ®s->orig_vld;
> + case NAND_EBI2_ECC_BUF_CFG:
> + return ®s->ecc_buf_cfg;
> + case NAND_READ_LOCATION_0:
> + return ®s->read_location0;
> + case NAND_READ_LOCATION_1:
> + return ®s->read_location1;
> + case NAND_READ_LOCATION_2:
> + return ®s->read_location2;
> + case NAND_READ_LOCATION_3:
> + return ®s->read_location3;
> + case NAND_READ_LOCATION_LAST_CW_0:
> + return ®s->read_location_last0;
> + case NAND_READ_LOCATION_LAST_CW_1:
> + return ®s->read_location_last1;
> + case NAND_READ_LOCATION_LAST_CW_2:
> + return ®s->read_location_last2;
> + case NAND_READ_LOCATION_LAST_CW_3:
> + return ®s->read_location_last3;
> + default:
> + return NULL;
> + }
> +}
> +EXPORT_SYMBOL(offset_to_nandc_reg);
> +
> +/* reset the register read buffer for next NAND operation */
> +void clear_read_regs(struct qcom_nand_controller *nandc)
> +{
> + nandc->reg_read_pos = 0;
> + nandc_read_buffer_sync(nandc, false);
> +}
> +EXPORT_SYMBOL(clear_read_regs);
> +
> +int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
> + int reg_off, const void *vaddr, int size,
> + bool flow_control)
> +{
> + struct desc_info *desc;
> + struct dma_async_tx_descriptor *dma_desc;
> + struct scatterlist *sgl;
> + struct dma_slave_config slave_conf;
> + struct qcom_adm_peripheral_config periph_conf = {};
> + enum dma_transfer_direction dir_eng;
> + int ret;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + sgl = &desc->adm_sgl;
> +
> + sg_init_one(sgl, vaddr, size);
> +
> + if (read) {
> + dir_eng = DMA_DEV_TO_MEM;
> + desc->dir = DMA_FROM_DEVICE;
> + } else {
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + }
> +
> + ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
> + if (ret == 0) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + memset(&slave_conf, 0x00, sizeof(slave_conf));
> +
> + slave_conf.device_fc = flow_control;
> + if (read) {
> + slave_conf.src_maxburst = 16;
> + slave_conf.src_addr = nandc->base_dma + reg_off;
> + if (nandc->data_crci) {
> + periph_conf.crci = nandc->data_crci;
> + slave_conf.peripheral_config = &periph_conf;
> + slave_conf.peripheral_size = sizeof(periph_conf);
> + }
> + } else {
> + slave_conf.dst_maxburst = 16;
> + slave_conf.dst_addr = nandc->base_dma + reg_off;
> + if (nandc->cmd_crci) {
> + periph_conf.crci = nandc->cmd_crci;
> + slave_conf.peripheral_config = &periph_conf;
> + slave_conf.peripheral_size = sizeof(periph_conf);
> + }
> + }
> +
> + ret = dmaengine_slave_config(nandc->chan, &slave_conf);
> + if (ret) {
> + dev_err(nandc->dev, "failed to configure dma channel\n");
> + goto err;
> + }
> +
> + dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
> + if (!dma_desc) {
> + dev_err(nandc->dev, "failed to prepare desc\n");
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + list_add_tail(&desc->node, &nandc->desc_list);
> +
> + return 0;
> +err:
> + kfree(desc);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(prep_adm_dma_desc);
> +
> +/* helpers to submit/free our list of dma descriptors */
> +int submit_descs(struct qcom_nand_controller *nandc)
> +{
> + struct desc_info *desc, *n;
> + dma_cookie_t cookie = 0;
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> + int ret = 0;
> +
> + if (nandc->props->is_bam) {
> + if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
> + ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
> + if (ret)
> + goto err_unmap_free_desc;
> + }
> +
> + if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
> + ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> + DMA_PREP_INTERRUPT);
> + if (ret)
> + goto err_unmap_free_desc;
> + }
> +
> + if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
> + ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> + DMA_PREP_CMD);
> + if (ret)
> + goto err_unmap_free_desc;
> + }
> + }
> +
> + list_for_each_entry(desc, &nandc->desc_list, node)
> + cookie = dmaengine_submit(desc->dma_desc);
> +
> + if (nandc->props->is_bam) {
> + bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
> + bam_txn->last_cmd_desc->callback_param = bam_txn;
> + if (bam_txn->last_data_desc) {
> + bam_txn->last_data_desc->callback = qpic_bam_dma_done;
> + bam_txn->last_data_desc->callback_param = bam_txn;
> + bam_txn->wait_second_completion = true;
> + }
> +
> + dma_async_issue_pending(nandc->tx_chan);
> + dma_async_issue_pending(nandc->rx_chan);
> + dma_async_issue_pending(nandc->cmd_chan);
> +
> + if (!wait_for_completion_timeout(&bam_txn->txn_done,
> + QPIC_NAND_COMPLETION_TIMEOUT))
> + ret = -ETIMEDOUT;
> + } else {
> + if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> + ret = -ETIMEDOUT;
> + }
> +
> +err_unmap_free_desc:
> + /*
> + * Unmap the dma sg_list and free the desc allocated by both
> + * prepare_bam_async_desc() and prep_adm_dma_desc() functions.
> + */
> + list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
> + list_del(&desc->node);
> +
> + if (nandc->props->is_bam)
> + dma_unmap_sg(nandc->dev, desc->bam_sgl,
> + desc->sgl_cnt, desc->dir);
> + else
> + dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
> + desc->dir);
> +
> + kfree(desc);
> + }
> +
> + return ret;
> +}
> +EXPORT_SYMBOL(submit_descs);
> +
> +/*
> + * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
> + * for BAM. This descriptor will be added in the NAND DMA descriptor queue
> + * which will be submitted to DMA engine.
> + */
> +int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
> + struct dma_chan *chan,
> + unsigned long flags)
> +{
> + struct desc_info *desc;
> + struct scatterlist *sgl;
> + unsigned int sgl_cnt;
> + int ret;
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> + enum dma_transfer_direction dir_eng;
> + struct dma_async_tx_descriptor *dma_desc;
> +
> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> + if (!desc)
> + return -ENOMEM;
> +
> + if (chan == nandc->cmd_chan) {
> + sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
> + sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
> + bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + } else if (chan == nandc->tx_chan) {
> + sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
> + sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
> + bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
> + dir_eng = DMA_MEM_TO_DEV;
> + desc->dir = DMA_TO_DEVICE;
> + } else {
> + sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
> + sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
> + bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
> + dir_eng = DMA_DEV_TO_MEM;
> + desc->dir = DMA_FROM_DEVICE;
> + }
> +
> + sg_mark_end(sgl + sgl_cnt - 1);
> + ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
> + if (ret == 0) {
> + dev_err(nandc->dev, "failure in mapping desc\n");
> + kfree(desc);
> + return -ENOMEM;
> + }
> +
> + desc->sgl_cnt = sgl_cnt;
> + desc->bam_sgl = sgl;
> +
> + dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
> + flags);
> +
> + if (!dma_desc) {
> + dev_err(nandc->dev, "failure in prep desc\n");
> + dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
> + kfree(desc);
> + return -EINVAL;
> + }
> +
> + desc->dma_desc = dma_desc;
> +
> + /* update last data/command descriptor */
> + if (chan == nandc->cmd_chan)
> + bam_txn->last_cmd_desc = dma_desc;
> + else
> + bam_txn->last_data_desc = dma_desc;
> +
> + list_add_tail(&desc->node, &nandc->desc_list);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(prepare_bam_async_desc);
> +
> +/*
> + * Prepares the command descriptor for BAM DMA which will be used for NAND
> + * register reads and writes. The command descriptor requires the command
> + * to be formed in command element type so this function uses the command
> + * element from bam transaction ce array and fills the same with required
> + * data. A single SGL can contain multiple command elements so
> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
> + * after the current command element.
> + */
> +int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
> + int reg_off, const void *vaddr,
> + int size, unsigned int flags)
> +{
> + int bam_ce_size;
> + int i, ret;
> + struct bam_cmd_element *bam_ce_buffer;
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> + bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
> +
> + /* fill the command desc */
> + for (i = 0; i < size; i++) {
> + if (read)
> + bam_prep_ce(&bam_ce_buffer[i],
> + nandc_reg_phys(nandc, reg_off + 4 * i),
> + BAM_READ_COMMAND,
> + reg_buf_dma_addr(nandc,
> + (__le32 *)vaddr + i));
> + else
> + bam_prep_ce_le32(&bam_ce_buffer[i],
> + nandc_reg_phys(nandc, reg_off + 4 * i),
> + BAM_WRITE_COMMAND,
> + *((__le32 *)vaddr + i));
> + }
> +
> + bam_txn->bam_ce_pos += size;
> +
> + /* use the separate sgl after this command */
> + if (flags & NAND_BAM_NEXT_SGL) {
> + bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
> + bam_ce_size = (bam_txn->bam_ce_pos -
> + bam_txn->bam_ce_start) *
> + sizeof(struct bam_cmd_element);
> + sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
> + bam_ce_buffer, bam_ce_size);
> + bam_txn->cmd_sgl_pos++;
> + bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
> +
> + if (flags & NAND_BAM_NWD) {
> + ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> + DMA_PREP_FENCE |
> + DMA_PREP_CMD);
> + if (ret)
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(prep_bam_dma_desc_cmd);
> +
> +/*
> + * Prepares the data descriptor for BAM DMA which will be used for NAND
> + * data reads and writes.
> + */
> +int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
> + const void *vaddr,
> + int size, unsigned int flags)
> +{
> + int ret;
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> + if (read) {
> + sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
> + vaddr, size);
> + bam_txn->rx_sgl_pos++;
> + } else {
> + sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
> + vaddr, size);
> + bam_txn->tx_sgl_pos++;
> +
> + /*
> + * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
> + * is not set, form the DMA descriptor
> + */
> + if (!(flags & NAND_BAM_NO_EOT)) {
> + ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> + DMA_PREP_INTERRUPT);
> + if (ret)
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(prep_bam_dma_desc_data);
> +
> +/*
> + * read_reg_dma: prepares a descriptor to read a given number of
> + * contiguous registers to the reg_read_buf pointer
> + *
> + * @first: offset of the first register in the contiguous block
> + * @num_regs: number of registers to read
> + * @flags: flags to control DMA descriptor preparation
> + */
> +int read_reg_dma(struct qcom_nand_controller *nandc, int first,
> + int num_regs, unsigned int flags)
> +{
> + bool flow_control = false;
> + void *vaddr;
> +
> + vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
> + nandc->reg_read_pos += num_regs;
> +
> + if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
> + first = dev_cmd_reg_addr(nandc, first);
> +
> + if (nandc->props->is_bam)
> + return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
> + num_regs, flags);
> +
> + if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
> + flow_control = true;
> +
> + return prep_adm_dma_desc(nandc, true, first, vaddr,
> + num_regs * sizeof(u32), flow_control);
> +}
> +EXPORT_SYMBOL(read_reg_dma);
> +
> +/*
> + * write_reg_dma: prepares a descriptor to write a given number of
> + * contiguous registers
> + *
> + * @first: offset of the first register in the contiguous block
> + * @num_regs: number of registers to write
> + * @flags: flags to control DMA descriptor preparation
> + */
> +int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> + int num_regs, unsigned int flags)
> +{
> + bool flow_control = false;
> + struct nandc_regs *regs = nandc->regs;
> + void *vaddr;
> +
> + vaddr = offset_to_nandc_reg(regs, first);
> +
> + if (first == NAND_ERASED_CW_DETECT_CFG) {
> + if (flags & NAND_ERASED_CW_SET)
> + vaddr = ®s->erased_cw_detect_cfg_set;
> + else
> + vaddr = ®s->erased_cw_detect_cfg_clr;
> + }
> +
> + if (first == NAND_EXEC_CMD)
> + flags |= NAND_BAM_NWD;
> +
> + if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
> + first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
> +
> + if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
> + first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
> +
> + if (nandc->props->is_bam)
> + return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
> + num_regs, flags);
> +
> + if (first == NAND_FLASH_CMD)
> + flow_control = true;
> +
> + return prep_adm_dma_desc(nandc, false, first, vaddr,
> + num_regs * sizeof(u32), flow_control);
> +}
> +EXPORT_SYMBOL(write_reg_dma);
> +
> +/*
> + * read_data_dma: prepares a DMA descriptor to transfer data from the
> + * controller's internal buffer to the buffer 'vaddr'
> + *
> + * @reg_off: offset within the controller's data buffer
> + * @vaddr: virtual address of the buffer we want to write to
> + * @size: DMA transaction size in bytes
> + * @flags: flags to control DMA descriptor preparation
> + */
> +int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> + const u8 *vaddr, int size, unsigned int flags)
> +{
> + if (nandc->props->is_bam)
> + return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
> +
> + return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
> +}
> +EXPORT_SYMBOL(read_data_dma);
> +
> +/*
> + * write_data_dma: prepares a DMA descriptor to transfer data from
> + * 'vaddr' to the controller's internal buffer
> + *
> + * @reg_off: offset within the controller's data buffer
> + * @vaddr: virtual address of the buffer we want to read from
> + * @size: DMA transaction size in bytes
> + * @flags: flags to control DMA descriptor preparation
> + */
> +int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> + const u8 *vaddr, int size, unsigned int flags)
> +{
> + if (nandc->props->is_bam)
> + return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
> +
> + return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
> +}
> +EXPORT_SYMBOL(write_data_dma);
> +
> +/* Allocates and Initializes the BAM transaction */
> +struct bam_transaction *
> +alloc_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> + struct bam_transaction *bam_txn;
> + size_t bam_txn_size;
> + unsigned int num_cw = nandc->max_cwperpage;
> + void *bam_txn_buf;
> +
> + bam_txn_size =
> + sizeof(*bam_txn) + num_cw *
> + ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
> + (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
> + (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
> +
> + bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
> + if (!bam_txn_buf)
> + return NULL;
> +
> + bam_txn = bam_txn_buf;
> + bam_txn_buf += sizeof(*bam_txn);
> +
> + bam_txn->bam_ce = bam_txn_buf;
> + bam_txn_buf +=
> + sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
> +
> + bam_txn->cmd_sgl = bam_txn_buf;
> + bam_txn_buf +=
> + sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
> +
> + bam_txn->data_sgl = bam_txn_buf;
> +
> + init_completion(&bam_txn->txn_done);
> +
> + return bam_txn;
> +}
> +EXPORT_SYMBOL(alloc_bam_transaction);
> +
> +/* Clears the BAM transaction indexes */
> +void clear_bam_transaction(struct qcom_nand_controller *nandc)
> +{
> + struct bam_transaction *bam_txn = nandc->bam_txn;
> +
> + if (!nandc->props->is_bam)
> + return;
> +
> + bam_txn->bam_ce_pos = 0;
> + bam_txn->bam_ce_start = 0;
> + bam_txn->cmd_sgl_pos = 0;
> + bam_txn->cmd_sgl_start = 0;
> + bam_txn->tx_sgl_pos = 0;
> + bam_txn->tx_sgl_start = 0;
> + bam_txn->rx_sgl_pos = 0;
> + bam_txn->rx_sgl_start = 0;
> + bam_txn->last_data_desc = NULL;
> + bam_txn->wait_second_completion = false;
> +
> + sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
> + QPIC_PER_CW_CMD_SGL);
> + sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
> + QPIC_PER_CW_DATA_SGL);
> +
> + reinit_completion(&bam_txn->txn_done);
> +}
> +EXPORT_SYMBOL(clear_bam_transaction);
> +
> +void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
> +{
> + if (nandc->props->is_bam) {
> + if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
> + dma_unmap_single(nandc->dev, nandc->reg_read_dma,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> +
> + if (nandc->tx_chan)
> + dma_release_channel(nandc->tx_chan);
> +
> + if (nandc->rx_chan)
> + dma_release_channel(nandc->rx_chan);
> +
> + if (nandc->cmd_chan)
> + dma_release_channel(nandc->cmd_chan);
> + } else {
> + if (nandc->chan)
> + dma_release_channel(nandc->chan);
> + }
> +}
> +EXPORT_SYMBOL(qcom_nandc_unalloc);
> +
> +int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
> +{
> + int ret;
> +
> + ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
> + if (ret) {
> + dev_err(nandc->dev, "failed to set DMA mask\n");
> + return ret;
> + }
> +
> + /*
> + * we use the internal buffer for reading ONFI params, reading small
> + * data like ID and status, and preforming read-copy-write operations
> + * when writing to a codeword partially. 532 is the maximum possible
> + * size of a codeword for our nand controller
> + */
> + nandc->buf_size = 532;
> +
> + nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
> + if (!nandc->data_buffer)
> + return -ENOMEM;
> +
> + nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
> + if (!nandc->regs)
> + return -ENOMEM;
> +
> + nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
> + sizeof(*nandc->reg_read_buf),
> + GFP_KERNEL);
> + if (!nandc->reg_read_buf)
> + return -ENOMEM;
> +
> + if (nandc->props->is_bam) {
> + nandc->reg_read_dma =
> + dma_map_single(nandc->dev, nandc->reg_read_buf,
> + MAX_REG_RD *
> + sizeof(*nandc->reg_read_buf),
> + DMA_FROM_DEVICE);
> + if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
> + dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
> + return -EIO;
> + }
> +
> + nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
> + if (IS_ERR(nandc->tx_chan)) {
> + ret = PTR_ERR(nandc->tx_chan);
> + nandc->tx_chan = NULL;
> + dev_err_probe(nandc->dev, ret,
> + "tx DMA channel request failed\n");
> + goto unalloc;
> + }
> +
> + nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
> + if (IS_ERR(nandc->rx_chan)) {
> + ret = PTR_ERR(nandc->rx_chan);
> + nandc->rx_chan = NULL;
> + dev_err_probe(nandc->dev, ret,
> + "rx DMA channel request failed\n");
> + goto unalloc;
> + }
> +
> + nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
> + if (IS_ERR(nandc->cmd_chan)) {
> + ret = PTR_ERR(nandc->cmd_chan);
> + nandc->cmd_chan = NULL;
> + dev_err_probe(nandc->dev, ret,
> + "cmd DMA channel request failed\n");
> + goto unalloc;
> + }
> +
> + /*
> + * Initially allocate BAM transaction to read ONFI param page.
> + * After detecting all the devices, this BAM transaction will
> + * be freed and the next BAM transaction will be allocated with
> + * maximum codeword size
> + */
> + nandc->max_cwperpage = 1;
> + nandc->bam_txn = alloc_bam_transaction(nandc);
> + if (!nandc->bam_txn) {
> + dev_err(nandc->dev,
> + "failed to allocate bam transaction\n");
> + ret = -ENOMEM;
> + goto unalloc;
> + }
> + } else {
> + nandc->chan = dma_request_chan(nandc->dev, "rxtx");
> + if (IS_ERR(nandc->chan)) {
> + ret = PTR_ERR(nandc->chan);
> + nandc->chan = NULL;
> + dev_err_probe(nandc->dev, ret,
> + "rxtx DMA channel request failed\n");
> + return ret;
> + }
> + }
> +
> + INIT_LIST_HEAD(&nandc->desc_list);
> + INIT_LIST_HEAD(&nandc->host_list);
> +
> + return 0;
> +unalloc:
> + qcom_nandc_unalloc(nandc);
> + return ret;
> +}
> +EXPORT_SYMBOL(qcom_nandc_alloc);
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index b079605c84d3..75c6ca698c85 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -2,186 +2,7 @@
> /*
> * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> */
> -#include <linux/bitops.h>
> -#include <linux/clk.h>
> -#include <linux/delay.h>
> -#include <linux/dmaengine.h>
> -#include <linux/dma-mapping.h>
> -#include <linux/dma/qcom_adm.h>
> -#include <linux/dma/qcom_bam_dma.h>
> -#include <linux/module.h>
> -#include <linux/mtd/partitions.h>
> -#include <linux/mtd/rawnand.h>
> -#include <linux/of.h>
> -#include <linux/platform_device.h>
> -#include <linux/slab.h>
> -
> -/* NANDc reg offsets */
> -#define NAND_FLASH_CMD 0x00
> -#define NAND_ADDR0 0x04
> -#define NAND_ADDR1 0x08
> -#define NAND_FLASH_CHIP_SELECT 0x0c
> -#define NAND_EXEC_CMD 0x10
> -#define NAND_FLASH_STATUS 0x14
> -#define NAND_BUFFER_STATUS 0x18
> -#define NAND_DEV0_CFG0 0x20
> -#define NAND_DEV0_CFG1 0x24
> -#define NAND_DEV0_ECC_CFG 0x28
> -#define NAND_AUTO_STATUS_EN 0x2c
> -#define NAND_DEV1_CFG0 0x30
> -#define NAND_DEV1_CFG1 0x34
> -#define NAND_READ_ID 0x40
> -#define NAND_READ_STATUS 0x44
> -#define NAND_DEV_CMD0 0xa0
> -#define NAND_DEV_CMD1 0xa4
> -#define NAND_DEV_CMD2 0xa8
> -#define NAND_DEV_CMD_VLD 0xac
> -#define SFLASHC_BURST_CFG 0xe0
> -#define NAND_ERASED_CW_DETECT_CFG 0xe8
> -#define NAND_ERASED_CW_DETECT_STATUS 0xec
> -#define NAND_EBI2_ECC_BUF_CFG 0xf0
> -#define FLASH_BUF_ACC 0x100
> -
> -#define NAND_CTRL 0xf00
> -#define NAND_VERSION 0xf08
> -#define NAND_READ_LOCATION_0 0xf20
> -#define NAND_READ_LOCATION_1 0xf24
> -#define NAND_READ_LOCATION_2 0xf28
> -#define NAND_READ_LOCATION_3 0xf2c
> -#define NAND_READ_LOCATION_LAST_CW_0 0xf40
> -#define NAND_READ_LOCATION_LAST_CW_1 0xf44
> -#define NAND_READ_LOCATION_LAST_CW_2 0xf48
> -#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
> -
> -/* dummy register offsets, used by write_reg_dma */
> -#define NAND_DEV_CMD1_RESTORE 0xdead
> -#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
> -
> -/* NAND_FLASH_CMD bits */
> -#define PAGE_ACC BIT(4)
> -#define LAST_PAGE BIT(5)
> -
> -/* NAND_FLASH_CHIP_SELECT bits */
> -#define NAND_DEV_SEL 0
> -#define DM_EN BIT(2)
> -
> -/* NAND_FLASH_STATUS bits */
> -#define FS_OP_ERR BIT(4)
> -#define FS_READY_BSY_N BIT(5)
> -#define FS_MPU_ERR BIT(8)
> -#define FS_DEVICE_STS_ERR BIT(16)
> -#define FS_DEVICE_WP BIT(23)
> -
> -/* NAND_BUFFER_STATUS bits */
> -#define BS_UNCORRECTABLE_BIT BIT(8)
> -#define BS_CORRECTABLE_ERR_MSK 0x1f
> -
> -/* NAND_DEVn_CFG0 bits */
> -#define DISABLE_STATUS_AFTER_WRITE 4
> -#define CW_PER_PAGE 6
> -#define UD_SIZE_BYTES 9
> -#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
> -#define ECC_PARITY_SIZE_BYTES_RS 19
> -#define SPARE_SIZE_BYTES 23
> -#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
> -#define NUM_ADDR_CYCLES 27
> -#define STATUS_BFR_READ 30
> -#define SET_RD_MODE_AFTER_STATUS 31
> -
> -/* NAND_DEVn_CFG0 bits */
> -#define DEV0_CFG1_ECC_DISABLE 0
> -#define WIDE_FLASH 1
> -#define NAND_RECOVERY_CYCLES 2
> -#define CS_ACTIVE_BSY 5
> -#define BAD_BLOCK_BYTE_NUM 6
> -#define BAD_BLOCK_IN_SPARE_AREA 16
> -#define WR_RD_BSY_GAP 17
> -#define ENABLE_BCH_ECC 27
> -
> -/* NAND_DEV0_ECC_CFG bits */
> -#define ECC_CFG_ECC_DISABLE 0
> -#define ECC_SW_RESET 1
> -#define ECC_MODE 4
> -#define ECC_PARITY_SIZE_BYTES_BCH 8
> -#define ECC_NUM_DATA_BYTES 16
> -#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
> -#define ECC_FORCE_CLK_OPEN 30
> -
> -/* NAND_DEV_CMD1 bits */
> -#define READ_ADDR 0
> -
> -/* NAND_DEV_CMD_VLD bits */
> -#define READ_START_VLD BIT(0)
> -#define READ_STOP_VLD BIT(1)
> -#define WRITE_START_VLD BIT(2)
> -#define ERASE_START_VLD BIT(3)
> -#define SEQ_READ_START_VLD BIT(4)
> -
> -/* NAND_EBI2_ECC_BUF_CFG bits */
> -#define NUM_STEPS 0
> -
> -/* NAND_ERASED_CW_DETECT_CFG bits */
> -#define ERASED_CW_ECC_MASK 1
> -#define AUTO_DETECT_RES 0
> -#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
> -#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
> -#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
> -#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
> -#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
> -
> -/* NAND_ERASED_CW_DETECT_STATUS bits */
> -#define PAGE_ALL_ERASED BIT(7)
> -#define CODEWORD_ALL_ERASED BIT(6)
> -#define PAGE_ERASED BIT(5)
> -#define CODEWORD_ERASED BIT(4)
> -#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
> -#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
> -
> -/* NAND_READ_LOCATION_n bits */
> -#define READ_LOCATION_OFFSET 0
> -#define READ_LOCATION_SIZE 16
> -#define READ_LOCATION_LAST 31
> -
> -/* Version Mask */
> -#define NAND_VERSION_MAJOR_MASK 0xf0000000
> -#define NAND_VERSION_MAJOR_SHIFT 28
> -#define NAND_VERSION_MINOR_MASK 0x0fff0000
> -#define NAND_VERSION_MINOR_SHIFT 16
> -
> -/* NAND OP_CMDs */
> -#define OP_PAGE_READ 0x2
> -#define OP_PAGE_READ_WITH_ECC 0x3
> -#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
> -#define OP_PAGE_READ_ONFI_READ 0x5
> -#define OP_PROGRAM_PAGE 0x6
> -#define OP_PAGE_PROGRAM_WITH_ECC 0x7
> -#define OP_PROGRAM_PAGE_SPARE 0x9
> -#define OP_BLOCK_ERASE 0xa
> -#define OP_CHECK_STATUS 0xc
> -#define OP_FETCH_ID 0xb
> -#define OP_RESET_DEVICE 0xd
> -
> -/* Default Value for NAND_DEV_CMD_VLD */
> -#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
> - ERASE_START_VLD | SEQ_READ_START_VLD)
> -
> -/* NAND_CTRL bits */
> -#define BAM_MODE_EN BIT(0)
> -
> -/*
> - * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> - * the driver calls the chunks 'step' or 'codeword' interchangeably
> - */
> -#define NANDC_STEP_SIZE 512
> -
> -/*
> - * the largest page size we support is 8K, this will have 16 steps/codewords
> - * of 512 bytes each
> - */
> -#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
> -
> -/* we read at most 3 registers per codeword scan */
> -#define MAX_REG_RD (3 * MAX_NUM_STEPS)
> +#include <linux/mtd/nand-qpic-common.h>
>
> /* ECC modes supported by the controller */
> #define ECC_NONE BIT(0)
> @@ -200,247 +21,6 @@ nandc_set_reg(chip, reg, \
> ((cw_offset) << READ_LOCATION_OFFSET) | \
> ((read_size) << READ_LOCATION_SIZE) | \
> ((is_last_read_loc) << READ_LOCATION_LAST))
> -/*
> - * Returns the actual register address for all NAND_DEV_ registers
> - * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
> - */
> -#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
> -
> -/* Returns the NAND register physical address */
> -#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
> -
> -/* Returns the dma address for reg read buffer */
> -#define reg_buf_dma_addr(chip, vaddr) \
> - ((chip)->reg_read_dma + \
> - ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
> -
> -#define QPIC_PER_CW_CMD_ELEMENTS 32
> -#define QPIC_PER_CW_CMD_SGL 32
> -#define QPIC_PER_CW_DATA_SGL 8
> -
> -#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
> -
> -/*
> - * Flags used in DMA descriptor preparation helper functions
> - * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
> - */
> -/* Don't set the EOT in current tx BAM sgl */
> -#define NAND_BAM_NO_EOT BIT(0)
> -/* Set the NWD flag in current BAM sgl */
> -#define NAND_BAM_NWD BIT(1)
> -/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
> -#define NAND_BAM_NEXT_SGL BIT(2)
> -/*
> - * Erased codeword status is being used two times in single transfer so this
> - * flag will determine the current value of erased codeword status register
> - */
> -#define NAND_ERASED_CW_SET BIT(4)
> -
> -#define MAX_ADDRESS_CYCLE 5
> -
> -/*
> - * This data type corresponds to the BAM transaction which will be used for all
> - * NAND transfers.
> - * @bam_ce - the array of BAM command elements
> - * @cmd_sgl - sgl for NAND BAM command pipe
> - * @data_sgl - sgl for NAND BAM consumer/producer pipe
> - * @last_data_desc - last DMA desc in data channel (tx/rx).
> - * @last_cmd_desc - last DMA desc in command channel.
> - * @txn_done - completion for NAND transfer.
> - * @bam_ce_pos - the index in bam_ce which is available for next sgl
> - * @bam_ce_start - the index in bam_ce which marks the start position ce
> - * for current sgl. It will be used for size calculation
> - * for current sgl
> - * @cmd_sgl_pos - current index in command sgl.
> - * @cmd_sgl_start - start index in command sgl.
> - * @tx_sgl_pos - current index in data sgl for tx.
> - * @tx_sgl_start - start index in data sgl for tx.
> - * @rx_sgl_pos - current index in data sgl for rx.
> - * @rx_sgl_start - start index in data sgl for rx.
> - * @wait_second_completion - wait for second DMA desc completion before making
> - * the NAND transfer completion.
> - */
> -struct bam_transaction {
> - struct bam_cmd_element *bam_ce;
> - struct scatterlist *cmd_sgl;
> - struct scatterlist *data_sgl;
> - struct dma_async_tx_descriptor *last_data_desc;
> - struct dma_async_tx_descriptor *last_cmd_desc;
> - struct completion txn_done;
> - u32 bam_ce_pos;
> - u32 bam_ce_start;
> - u32 cmd_sgl_pos;
> - u32 cmd_sgl_start;
> - u32 tx_sgl_pos;
> - u32 tx_sgl_start;
> - u32 rx_sgl_pos;
> - u32 rx_sgl_start;
> - bool wait_second_completion;
> -};
> -
> -/*
> - * This data type corresponds to the nand dma descriptor
> - * @dma_desc - low level DMA engine descriptor
> - * @list - list for desc_info
> - *
> - * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
> - * ADM
> - * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
> - * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
> - * @dir - DMA transfer direction
> - */
> -struct desc_info {
> - struct dma_async_tx_descriptor *dma_desc;
> - struct list_head node;
> -
> - union {
> - struct scatterlist adm_sgl;
> - struct {
> - struct scatterlist *bam_sgl;
> - int sgl_cnt;
> - };
> - };
> - enum dma_data_direction dir;
> -};
> -
> -/*
> - * holds the current register values that we want to write. acts as a contiguous
> - * chunk of memory which we use to write the controller registers through DMA.
> - */
> -struct nandc_regs {
> - __le32 cmd;
> - __le32 addr0;
> - __le32 addr1;
> - __le32 chip_sel;
> - __le32 exec;
> -
> - __le32 cfg0;
> - __le32 cfg1;
> - __le32 ecc_bch_cfg;
> -
> - __le32 clrflashstatus;
> - __le32 clrreadstatus;
> -
> - __le32 cmd1;
> - __le32 vld;
> -
> - __le32 orig_cmd1;
> - __le32 orig_vld;
> -
> - __le32 ecc_buf_cfg;
> - __le32 read_location0;
> - __le32 read_location1;
> - __le32 read_location2;
> - __le32 read_location3;
> - __le32 read_location_last0;
> - __le32 read_location_last1;
> - __le32 read_location_last2;
> - __le32 read_location_last3;
> -
> - __le32 erased_cw_detect_cfg_clr;
> - __le32 erased_cw_detect_cfg_set;
> -};
> -
> -/*
> - * NAND controller data struct
> - *
> - * @dev: parent device
> - *
> - * @base: MMIO base
> - *
> - * @core_clk: controller clock
> - * @aon_clk: another controller clock
> - *
> - * @regs: a contiguous chunk of memory for DMA register
> - * writes. contains the register values to be
> - * written to controller
> - *
> - * @props: properties of current NAND controller,
> - * initialized via DT match data
> - *
> - * @controller: base controller structure
> - * @host_list: list containing all the chips attached to the
> - * controller
> - *
> - * @chan: dma channel
> - * @cmd_crci: ADM DMA CRCI for command flow control
> - * @data_crci: ADM DMA CRCI for data flow control
> - *
> - * @desc_list: DMA descriptor list (list of desc_infos)
> - *
> - * @data_buffer: our local DMA buffer for page read/writes,
> - * used when we can't use the buffer provided
> - * by upper layers directly
> - * @reg_read_buf: local buffer for reading back registers via DMA
> - *
> - * @base_phys: physical base address of controller registers
> - * @base_dma: dma base address of controller registers
> - * @reg_read_dma: contains dma address for register read buffer
> - *
> - * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
> - * functions
> - * @max_cwperpage: maximum QPIC codewords required. calculated
> - * from all connected NAND devices pagesize
> - *
> - * @reg_read_pos: marker for data read in reg_read_buf
> - *
> - * @cmd1/vld: some fixed controller register values
> - *
> - * @exec_opwrite: flag to select correct number of code word
> - * while reading status
> - */
> -struct qcom_nand_controller {
> - struct device *dev;
> -
> - void __iomem *base;
> -
> - struct clk *core_clk;
> - struct clk *aon_clk;
> -
> - struct nandc_regs *regs;
> - struct bam_transaction *bam_txn;
> -
> - const struct qcom_nandc_props *props;
> -
> - struct nand_controller controller;
> - struct list_head host_list;
> -
> - union {
> - /* will be used only by QPIC for BAM DMA */
> - struct {
> - struct dma_chan *tx_chan;
> - struct dma_chan *rx_chan;
> - struct dma_chan *cmd_chan;
> - };
> -
> - /* will be used only by EBI2 for ADM DMA */
> - struct {
> - struct dma_chan *chan;
> - unsigned int cmd_crci;
> - unsigned int data_crci;
> - };
> - };
> -
> - struct list_head desc_list;
> -
> - u8 *data_buffer;
> - __le32 *reg_read_buf;
> -
> - phys_addr_t base_phys;
> - dma_addr_t base_dma;
> - dma_addr_t reg_read_dma;
> -
> - int buf_size;
> - int buf_count;
> - int buf_start;
> - unsigned int max_cwperpage;
> -
> - int reg_read_pos;
> -
> - u32 cmd1, vld;
> - bool exec_opwrite;
> -};
> -
> /*
> * NAND special boot partitions
> *
> @@ -544,113 +124,17 @@ struct qcom_nand_host {
> bool bch_enabled;
> };
>
> -/*
> - * This data type corresponds to the NAND controller properties which varies
> - * among different NAND controllers.
> - * @ecc_modes - ecc mode for NAND
> - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
> - * @is_bam - whether NAND controller is using BAM
> - * @is_qpic - whether NAND CTRL is part of qpic IP
> - * @qpic_v2 - flag to indicate QPIC IP version 2
> - * @use_codeword_fixup - whether NAND has different layout for boot partitions
> - */
> -struct qcom_nandc_props {
> - u32 ecc_modes;
> - u32 dev_cmd_reg_start;
> - bool is_bam;
> - bool is_qpic;
> - bool qpic_v2;
> - bool use_codeword_fixup;
> -};
> -
> -/* Frees the BAM transaction memory */
> -static void free_bam_transaction(struct qcom_nand_controller *nandc)
> -{
> - struct bam_transaction *bam_txn = nandc->bam_txn;
> -
> - devm_kfree(nandc->dev, bam_txn);
> -}
> -
> -/* Allocates and Initializes the BAM transaction */
> -static struct bam_transaction *
> -alloc_bam_transaction(struct qcom_nand_controller *nandc)
> -{
> - struct bam_transaction *bam_txn;
> - size_t bam_txn_size;
> - unsigned int num_cw = nandc->max_cwperpage;
> - void *bam_txn_buf;
> -
> - bam_txn_size =
> - sizeof(*bam_txn) + num_cw *
> - ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
> - (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
> - (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
> -
> - bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
> - if (!bam_txn_buf)
> - return NULL;
> -
> - bam_txn = bam_txn_buf;
> - bam_txn_buf += sizeof(*bam_txn);
> -
> - bam_txn->bam_ce = bam_txn_buf;
> - bam_txn_buf +=
> - sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
> -
> - bam_txn->cmd_sgl = bam_txn_buf;
> - bam_txn_buf +=
> - sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
> -
> - bam_txn->data_sgl = bam_txn_buf;
> -
> - init_completion(&bam_txn->txn_done);
> -
> - return bam_txn;
> -}
> -
> -/* Clears the BAM transaction indexes */
> -static void clear_bam_transaction(struct qcom_nand_controller *nandc)
> +static void nandc_set_reg(struct nand_chip *chip, int offset,
> + u32 val)
> {
> - struct bam_transaction *bam_txn = nandc->bam_txn;
> -
> - if (!nandc->props->is_bam)
> - return;
> -
> - bam_txn->bam_ce_pos = 0;
> - bam_txn->bam_ce_start = 0;
> - bam_txn->cmd_sgl_pos = 0;
> - bam_txn->cmd_sgl_start = 0;
> - bam_txn->tx_sgl_pos = 0;
> - bam_txn->tx_sgl_start = 0;
> - bam_txn->rx_sgl_pos = 0;
> - bam_txn->rx_sgl_start = 0;
> - bam_txn->last_data_desc = NULL;
> - bam_txn->wait_second_completion = false;
> -
> - sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
> - QPIC_PER_CW_CMD_SGL);
> - sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
> - QPIC_PER_CW_DATA_SGL);
> -
> - reinit_completion(&bam_txn->txn_done);
> -}
> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> + struct nandc_regs *regs = nandc->regs;
> + __le32 *reg;
>
> -/* Callback for DMA descriptor completion */
> -static void qpic_bam_dma_done(void *data)
> -{
> - struct bam_transaction *bam_txn = data;
> + reg = offset_to_nandc_reg(regs, offset);
>
> - /*
> - * In case of data transfer with NAND, 2 callbacks will be generated.
> - * One for command channel and another one for data channel.
> - * If current transaction has data descriptors
> - * (i.e. wait_second_completion is true), then set this to false
> - * and wait for second DMA descriptor completion.
> - */
> - if (bam_txn->wait_second_completion)
> - bam_txn->wait_second_completion = false;
> - else
> - complete(&bam_txn->txn_done);
> + if (reg)
> + *reg = cpu_to_le32(val);
> }
>
> static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> @@ -658,13 +142,6 @@ static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
> return container_of(chip, struct qcom_nand_host, chip);
> }
>
> -static inline struct qcom_nand_controller *
> -get_qcom_nand_controller(struct nand_chip *chip)
> -{
> - return container_of(chip->controller, struct qcom_nand_controller,
> - controller);
> -}
> -
> static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
> {
> return ioread32(nandc->base + offset);
> @@ -676,91 +153,6 @@ static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
> iowrite32(val, nandc->base + offset);
> }
>
> -static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
> - bool is_cpu)
> -{
> - if (!nandc->props->is_bam)
> - return;
> -
> - if (is_cpu)
> - dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
> - MAX_REG_RD *
> - sizeof(*nandc->reg_read_buf),
> - DMA_FROM_DEVICE);
> - else
> - dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
> - MAX_REG_RD *
> - sizeof(*nandc->reg_read_buf),
> - DMA_FROM_DEVICE);
> -}
> -
> -static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
> -{
> - switch (offset) {
> - case NAND_FLASH_CMD:
> - return ®s->cmd;
> - case NAND_ADDR0:
> - return ®s->addr0;
> - case NAND_ADDR1:
> - return ®s->addr1;
> - case NAND_FLASH_CHIP_SELECT:
> - return ®s->chip_sel;
> - case NAND_EXEC_CMD:
> - return ®s->exec;
> - case NAND_FLASH_STATUS:
> - return ®s->clrflashstatus;
> - case NAND_DEV0_CFG0:
> - return ®s->cfg0;
> - case NAND_DEV0_CFG1:
> - return ®s->cfg1;
> - case NAND_DEV0_ECC_CFG:
> - return ®s->ecc_bch_cfg;
> - case NAND_READ_STATUS:
> - return ®s->clrreadstatus;
> - case NAND_DEV_CMD1:
> - return ®s->cmd1;
> - case NAND_DEV_CMD1_RESTORE:
> - return ®s->orig_cmd1;
> - case NAND_DEV_CMD_VLD:
> - return ®s->vld;
> - case NAND_DEV_CMD_VLD_RESTORE:
> - return ®s->orig_vld;
> - case NAND_EBI2_ECC_BUF_CFG:
> - return ®s->ecc_buf_cfg;
> - case NAND_READ_LOCATION_0:
> - return ®s->read_location0;
> - case NAND_READ_LOCATION_1:
> - return ®s->read_location1;
> - case NAND_READ_LOCATION_2:
> - return ®s->read_location2;
> - case NAND_READ_LOCATION_3:
> - return ®s->read_location3;
> - case NAND_READ_LOCATION_LAST_CW_0:
> - return ®s->read_location_last0;
> - case NAND_READ_LOCATION_LAST_CW_1:
> - return ®s->read_location_last1;
> - case NAND_READ_LOCATION_LAST_CW_2:
> - return ®s->read_location_last2;
> - case NAND_READ_LOCATION_LAST_CW_3:
> - return ®s->read_location_last3;
> - default:
> - return NULL;
> - }
> -}
> -
> -static void nandc_set_reg(struct nand_chip *chip, int offset,
> - u32 val)
> -{
> - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> - struct nandc_regs *regs = nandc->regs;
> - __le32 *reg;
> -
> - reg = offset_to_nandc_reg(regs, offset);
> -
> - if (reg)
> - *reg = cpu_to_le32(val);
> -}
> -
> /* Helper to check the code word, whether it is last cw or not */
> static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
> {
> @@ -852,383 +244,6 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
> host->cw_data : host->cw_size, 1);
> }
>
> -/*
> - * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
> - * for BAM. This descriptor will be added in the NAND DMA descriptor queue
> - * which will be submitted to DMA engine.
> - */
> -static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
> - struct dma_chan *chan,
> - unsigned long flags)
> -{
> - struct desc_info *desc;
> - struct scatterlist *sgl;
> - unsigned int sgl_cnt;
> - int ret;
> - struct bam_transaction *bam_txn = nandc->bam_txn;
> - enum dma_transfer_direction dir_eng;
> - struct dma_async_tx_descriptor *dma_desc;
> -
> - desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> - if (!desc)
> - return -ENOMEM;
> -
> - if (chan == nandc->cmd_chan) {
> - sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
> - sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
> - bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
> - dir_eng = DMA_MEM_TO_DEV;
> - desc->dir = DMA_TO_DEVICE;
> - } else if (chan == nandc->tx_chan) {
> - sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
> - sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
> - bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
> - dir_eng = DMA_MEM_TO_DEV;
> - desc->dir = DMA_TO_DEVICE;
> - } else {
> - sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
> - sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
> - bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
> - dir_eng = DMA_DEV_TO_MEM;
> - desc->dir = DMA_FROM_DEVICE;
> - }
> -
> - sg_mark_end(sgl + sgl_cnt - 1);
> - ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
> - if (ret == 0) {
> - dev_err(nandc->dev, "failure in mapping desc\n");
> - kfree(desc);
> - return -ENOMEM;
> - }
> -
> - desc->sgl_cnt = sgl_cnt;
> - desc->bam_sgl = sgl;
> -
> - dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
> - flags);
> -
> - if (!dma_desc) {
> - dev_err(nandc->dev, "failure in prep desc\n");
> - dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
> - kfree(desc);
> - return -EINVAL;
> - }
> -
> - desc->dma_desc = dma_desc;
> -
> - /* update last data/command descriptor */
> - if (chan == nandc->cmd_chan)
> - bam_txn->last_cmd_desc = dma_desc;
> - else
> - bam_txn->last_data_desc = dma_desc;
> -
> - list_add_tail(&desc->node, &nandc->desc_list);
> -
> - return 0;
> -}
> -
> -/*
> - * Prepares the command descriptor for BAM DMA which will be used for NAND
> - * register reads and writes. The command descriptor requires the command
> - * to be formed in command element type so this function uses the command
> - * element from bam transaction ce array and fills the same with required
> - * data. A single SGL can contain multiple command elements so
> - * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
> - * after the current command element.
> - */
> -static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
> - int reg_off, const void *vaddr,
> - int size, unsigned int flags)
> -{
> - int bam_ce_size;
> - int i, ret;
> - struct bam_cmd_element *bam_ce_buffer;
> - struct bam_transaction *bam_txn = nandc->bam_txn;
> -
> - bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
> -
> - /* fill the command desc */
> - for (i = 0; i < size; i++) {
> - if (read)
> - bam_prep_ce(&bam_ce_buffer[i],
> - nandc_reg_phys(nandc, reg_off + 4 * i),
> - BAM_READ_COMMAND,
> - reg_buf_dma_addr(nandc,
> - (__le32 *)vaddr + i));
> - else
> - bam_prep_ce_le32(&bam_ce_buffer[i],
> - nandc_reg_phys(nandc, reg_off + 4 * i),
> - BAM_WRITE_COMMAND,
> - *((__le32 *)vaddr + i));
> - }
> -
> - bam_txn->bam_ce_pos += size;
> -
> - /* use the separate sgl after this command */
> - if (flags & NAND_BAM_NEXT_SGL) {
> - bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
> - bam_ce_size = (bam_txn->bam_ce_pos -
> - bam_txn->bam_ce_start) *
> - sizeof(struct bam_cmd_element);
> - sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
> - bam_ce_buffer, bam_ce_size);
> - bam_txn->cmd_sgl_pos++;
> - bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
> -
> - if (flags & NAND_BAM_NWD) {
> - ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> - DMA_PREP_FENCE |
> - DMA_PREP_CMD);
> - if (ret)
> - return ret;
> - }
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * Prepares the data descriptor for BAM DMA which will be used for NAND
> - * data reads and writes.
> - */
> -static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
> - const void *vaddr,
> - int size, unsigned int flags)
> -{
> - int ret;
> - struct bam_transaction *bam_txn = nandc->bam_txn;
> -
> - if (read) {
> - sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
> - vaddr, size);
> - bam_txn->rx_sgl_pos++;
> - } else {
> - sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
> - vaddr, size);
> - bam_txn->tx_sgl_pos++;
> -
> - /*
> - * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
> - * is not set, form the DMA descriptor
> - */
> - if (!(flags & NAND_BAM_NO_EOT)) {
> - ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> - DMA_PREP_INTERRUPT);
> - if (ret)
> - return ret;
> - }
> - }
> -
> - return 0;
> -}
> -
> -static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
> - int reg_off, const void *vaddr, int size,
> - bool flow_control)
> -{
> - struct desc_info *desc;
> - struct dma_async_tx_descriptor *dma_desc;
> - struct scatterlist *sgl;
> - struct dma_slave_config slave_conf;
> - struct qcom_adm_peripheral_config periph_conf = {};
> - enum dma_transfer_direction dir_eng;
> - int ret;
> -
> - desc = kzalloc(sizeof(*desc), GFP_KERNEL);
> - if (!desc)
> - return -ENOMEM;
> -
> - sgl = &desc->adm_sgl;
> -
> - sg_init_one(sgl, vaddr, size);
> -
> - if (read) {
> - dir_eng = DMA_DEV_TO_MEM;
> - desc->dir = DMA_FROM_DEVICE;
> - } else {
> - dir_eng = DMA_MEM_TO_DEV;
> - desc->dir = DMA_TO_DEVICE;
> - }
> -
> - ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
> - if (ret == 0) {
> - ret = -ENOMEM;
> - goto err;
> - }
> -
> - memset(&slave_conf, 0x00, sizeof(slave_conf));
> -
> - slave_conf.device_fc = flow_control;
> - if (read) {
> - slave_conf.src_maxburst = 16;
> - slave_conf.src_addr = nandc->base_dma + reg_off;
> - if (nandc->data_crci) {
> - periph_conf.crci = nandc->data_crci;
> - slave_conf.peripheral_config = &periph_conf;
> - slave_conf.peripheral_size = sizeof(periph_conf);
> - }
> - } else {
> - slave_conf.dst_maxburst = 16;
> - slave_conf.dst_addr = nandc->base_dma + reg_off;
> - if (nandc->cmd_crci) {
> - periph_conf.crci = nandc->cmd_crci;
> - slave_conf.peripheral_config = &periph_conf;
> - slave_conf.peripheral_size = sizeof(periph_conf);
> - }
> - }
> -
> - ret = dmaengine_slave_config(nandc->chan, &slave_conf);
> - if (ret) {
> - dev_err(nandc->dev, "failed to configure dma channel\n");
> - goto err;
> - }
> -
> - dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
> - if (!dma_desc) {
> - dev_err(nandc->dev, "failed to prepare desc\n");
> - ret = -EINVAL;
> - goto err;
> - }
> -
> - desc->dma_desc = dma_desc;
> -
> - list_add_tail(&desc->node, &nandc->desc_list);
> -
> - return 0;
> -err:
> - kfree(desc);
> -
> - return ret;
> -}
> -
> -/*
> - * read_reg_dma: prepares a descriptor to read a given number of
> - * contiguous registers to the reg_read_buf pointer
> - *
> - * @first: offset of the first register in the contiguous block
> - * @num_regs: number of registers to read
> - * @flags: flags to control DMA descriptor preparation
> - */
> -static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
> - int num_regs, unsigned int flags)
> -{
> - bool flow_control = false;
> - void *vaddr;
> -
> - vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
> - nandc->reg_read_pos += num_regs;
> -
> - if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
> - first = dev_cmd_reg_addr(nandc, first);
> -
> - if (nandc->props->is_bam)
> - return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
> - num_regs, flags);
> -
> - if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
> - flow_control = true;
> -
> - return prep_adm_dma_desc(nandc, true, first, vaddr,
> - num_regs * sizeof(u32), flow_control);
> -}
> -
> -/*
> - * write_reg_dma: prepares a descriptor to write a given number of
> - * contiguous registers
> - *
> - * @first: offset of the first register in the contiguous block
> - * @num_regs: number of registers to write
> - * @flags: flags to control DMA descriptor preparation
> - */
> -static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> - int num_regs, unsigned int flags)
> -{
> - bool flow_control = false;
> - struct nandc_regs *regs = nandc->regs;
> - void *vaddr;
> -
> - vaddr = offset_to_nandc_reg(regs, first);
> -
> - if (first == NAND_ERASED_CW_DETECT_CFG) {
> - if (flags & NAND_ERASED_CW_SET)
> - vaddr = ®s->erased_cw_detect_cfg_set;
> - else
> - vaddr = ®s->erased_cw_detect_cfg_clr;
> - }
> -
> - if (first == NAND_EXEC_CMD)
> - flags |= NAND_BAM_NWD;
> -
> - if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
> - first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
> -
> - if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
> - first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
> -
> - if (nandc->props->is_bam)
> - return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
> - num_regs, flags);
> -
> - if (first == NAND_FLASH_CMD)
> - flow_control = true;
> -
> - return prep_adm_dma_desc(nandc, false, first, vaddr,
> - num_regs * sizeof(u32), flow_control);
> -}
> -
> -/*
> - * read_data_dma: prepares a DMA descriptor to transfer data from the
> - * controller's internal buffer to the buffer 'vaddr'
> - *
> - * @reg_off: offset within the controller's data buffer
> - * @vaddr: virtual address of the buffer we want to write to
> - * @size: DMA transaction size in bytes
> - * @flags: flags to control DMA descriptor preparation
> - */
> -static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> - const u8 *vaddr, int size, unsigned int flags)
> -{
> - if (nandc->props->is_bam)
> - return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
> -
> - return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
> -}
> -
> -/*
> - * write_data_dma: prepares a DMA descriptor to transfer data from
> - * 'vaddr' to the controller's internal buffer
> - *
> - * @reg_off: offset within the controller's data buffer
> - * @vaddr: virtual address of the buffer we want to read from
> - * @size: DMA transaction size in bytes
> - * @flags: flags to control DMA descriptor preparation
> - */
> -static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> - const u8 *vaddr, int size, unsigned int flags)
> -{
> - if (nandc->props->is_bam)
> - return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
> -
> - return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
> -}
> -
> -/*
> - * Helper to prepare DMA descriptors for configuring registers
> - * before reading a NAND page.
> - */
> -static void config_nand_page_read(struct nand_chip *chip)
> -{
> - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> -
> - write_reg_dma(nandc, NAND_ADDR0, 2, 0);
> - write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
> - if (!nandc->props->qpic_v2)
> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> - write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
> - write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
> - NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
> -}
> -
> /*
> * Helper to prepare DMA descriptors for configuring registers
> * before reading each codeword in NAND page.
> @@ -1303,88 +318,6 @@ static void config_nand_cw_write(struct nand_chip *chip)
> write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
> }
>
> -/* helpers to submit/free our list of dma descriptors */
> -static int submit_descs(struct qcom_nand_controller *nandc)
> -{
> - struct desc_info *desc, *n;
> - dma_cookie_t cookie = 0;
> - struct bam_transaction *bam_txn = nandc->bam_txn;
> - int ret = 0;
> -
> - if (nandc->props->is_bam) {
> - if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
> - ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
> - if (ret)
> - goto err_unmap_free_desc;
> - }
> -
> - if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
> - ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
> - DMA_PREP_INTERRUPT);
> - if (ret)
> - goto err_unmap_free_desc;
> - }
> -
> - if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
> - ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
> - DMA_PREP_CMD);
> - if (ret)
> - goto err_unmap_free_desc;
> - }
> - }
> -
> - list_for_each_entry(desc, &nandc->desc_list, node)
> - cookie = dmaengine_submit(desc->dma_desc);
> -
> - if (nandc->props->is_bam) {
> - bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
> - bam_txn->last_cmd_desc->callback_param = bam_txn;
> - if (bam_txn->last_data_desc) {
> - bam_txn->last_data_desc->callback = qpic_bam_dma_done;
> - bam_txn->last_data_desc->callback_param = bam_txn;
> - bam_txn->wait_second_completion = true;
> - }
> -
> - dma_async_issue_pending(nandc->tx_chan);
> - dma_async_issue_pending(nandc->rx_chan);
> - dma_async_issue_pending(nandc->cmd_chan);
> -
> - if (!wait_for_completion_timeout(&bam_txn->txn_done,
> - QPIC_NAND_COMPLETION_TIMEOUT))
> - ret = -ETIMEDOUT;
> - } else {
> - if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
> - ret = -ETIMEDOUT;
> - }
> -
> -err_unmap_free_desc:
> - /*
> - * Unmap the dma sg_list and free the desc allocated by both
> - * prepare_bam_async_desc() and prep_adm_dma_desc() functions.
> - */
> - list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
> - list_del(&desc->node);
> -
> - if (nandc->props->is_bam)
> - dma_unmap_sg(nandc->dev, desc->bam_sgl,
> - desc->sgl_cnt, desc->dir);
> - else
> - dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
> - desc->dir);
> -
> - kfree(desc);
> - }
> -
> - return ret;
> -}
> -
> -/* reset the register read buffer for next NAND operation */
> -static void clear_read_regs(struct qcom_nand_controller *nandc)
> -{
> - nandc->reg_read_pos = 0;
> - nandc_read_buffer_sync(nandc, false);
> -}
> -
> /*
> * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
> * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
> @@ -3016,136 +1949,6 @@ static const struct nand_controller_ops qcom_nandc_ops = {
> .exec_op = qcom_nand_exec_op,
> };
>
> -static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
> -{
> - if (nandc->props->is_bam) {
> - if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
> - dma_unmap_single(nandc->dev, nandc->reg_read_dma,
> - MAX_REG_RD *
> - sizeof(*nandc->reg_read_buf),
> - DMA_FROM_DEVICE);
> -
> - if (nandc->tx_chan)
> - dma_release_channel(nandc->tx_chan);
> -
> - if (nandc->rx_chan)
> - dma_release_channel(nandc->rx_chan);
> -
> - if (nandc->cmd_chan)
> - dma_release_channel(nandc->cmd_chan);
> - } else {
> - if (nandc->chan)
> - dma_release_channel(nandc->chan);
> - }
> -}
> -
> -static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
> -{
> - int ret;
> -
> - ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
> - if (ret) {
> - dev_err(nandc->dev, "failed to set DMA mask\n");
> - return ret;
> - }
> -
> - /*
> - * we use the internal buffer for reading ONFI params, reading small
> - * data like ID and status, and preforming read-copy-write operations
> - * when writing to a codeword partially. 532 is the maximum possible
> - * size of a codeword for our nand controller
> - */
> - nandc->buf_size = 532;
> -
> - nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
> - if (!nandc->data_buffer)
> - return -ENOMEM;
> -
> - nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
> - if (!nandc->regs)
> - return -ENOMEM;
> -
> - nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
> - sizeof(*nandc->reg_read_buf),
> - GFP_KERNEL);
> - if (!nandc->reg_read_buf)
> - return -ENOMEM;
> -
> - if (nandc->props->is_bam) {
> - nandc->reg_read_dma =
> - dma_map_single(nandc->dev, nandc->reg_read_buf,
> - MAX_REG_RD *
> - sizeof(*nandc->reg_read_buf),
> - DMA_FROM_DEVICE);
> - if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
> - dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
> - return -EIO;
> - }
> -
> - nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
> - if (IS_ERR(nandc->tx_chan)) {
> - ret = PTR_ERR(nandc->tx_chan);
> - nandc->tx_chan = NULL;
> - dev_err_probe(nandc->dev, ret,
> - "tx DMA channel request failed\n");
> - goto unalloc;
> - }
> -
> - nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
> - if (IS_ERR(nandc->rx_chan)) {
> - ret = PTR_ERR(nandc->rx_chan);
> - nandc->rx_chan = NULL;
> - dev_err_probe(nandc->dev, ret,
> - "rx DMA channel request failed\n");
> - goto unalloc;
> - }
> -
> - nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
> - if (IS_ERR(nandc->cmd_chan)) {
> - ret = PTR_ERR(nandc->cmd_chan);
> - nandc->cmd_chan = NULL;
> - dev_err_probe(nandc->dev, ret,
> - "cmd DMA channel request failed\n");
> - goto unalloc;
> - }
> -
> - /*
> - * Initially allocate BAM transaction to read ONFI param page.
> - * After detecting all the devices, this BAM transaction will
> - * be freed and the next BAM transaction will be allocated with
> - * maximum codeword size
> - */
> - nandc->max_cwperpage = 1;
> - nandc->bam_txn = alloc_bam_transaction(nandc);
> - if (!nandc->bam_txn) {
> - dev_err(nandc->dev,
> - "failed to allocate bam transaction\n");
> - ret = -ENOMEM;
> - goto unalloc;
> - }
> - } else {
> - nandc->chan = dma_request_chan(nandc->dev, "rxtx");
> - if (IS_ERR(nandc->chan)) {
> - ret = PTR_ERR(nandc->chan);
> - nandc->chan = NULL;
> - dev_err_probe(nandc->dev, ret,
> - "rxtx DMA channel request failed\n");
> - return ret;
> - }
> - }
> -
> - INIT_LIST_HEAD(&nandc->desc_list);
> - INIT_LIST_HEAD(&nandc->host_list);
> -
> - nand_controller_init(&nandc->controller);
> - nandc->controller.ops = &qcom_nandc_ops;
> -
> - return 0;
> -unalloc:
> - qcom_nandc_unalloc(nandc);
> - return ret;
> -}
> -
> /* one time setup of a few nand controller registers */
> static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> {
> @@ -3427,6 +2230,9 @@ static int qcom_nandc_probe(struct platform_device *pdev)
> if (ret)
> goto err_nandc_alloc;
>
> + nand_controller_init(&nandc->controller);
> + nandc->controller.ops = &qcom_nandc_ops;
> +
> ret = qcom_nandc_setup(nandc);
> if (ret)
> goto err_setup;
> @@ -3473,28 +2279,28 @@ static void qcom_nandc_remove(struct platform_device *pdev)
> DMA_BIDIRECTIONAL, 0);
> }
>
> -static const struct qcom_nandc_props ipq806x_nandc_props = {
> +static struct qcom_nandc_props ipq806x_nandc_props = {
> .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
> .is_bam = false,
> .use_codeword_fixup = true,
> .dev_cmd_reg_start = 0x0,
> };
>
> -static const struct qcom_nandc_props ipq4019_nandc_props = {
> +static struct qcom_nandc_props ipq4019_nandc_props = {
> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> .is_bam = true,
> .is_qpic = true,
> .dev_cmd_reg_start = 0x0,
> };
>
> -static const struct qcom_nandc_props ipq8074_nandc_props = {
> +static struct qcom_nandc_props ipq8074_nandc_props = {
> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> .is_bam = true,
> .is_qpic = true,
> .dev_cmd_reg_start = 0x7000,
> };
>
> -static const struct qcom_nandc_props sdx55_nandc_props = {
> +static struct qcom_nandc_props sdx55_nandc_props = {
> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
> .is_bam = true,
> .is_qpic = true,
> diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
> new file mode 100644
> index 000000000000..891f975ca173
> --- /dev/null
> +++ b/include/linux/mtd/nand-qpic-common.h
> @@ -0,0 +1,488 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * QCOM QPIC common APIs header file
> + *
> + * Copyright (c) 2023 Qualcomm Inc.
> + * Authors: Md sadre Alam <[email protected]>
> + * Sricharan R <[email protected]>
> + * Varadarajan Narayanan <[email protected]>
> + *
> + */
> +#ifndef __MTD_NAND_QPIC_COMMON_H__
> +#define __MTD_NAND_QPIC_COMMON_H__
> +
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dma/qcom_adm.h>
> +#include <linux/dma/qcom_bam_dma.h>
> +#include <linux/module.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/mtd/rawnand.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +/* NANDc reg offsets */
> +#define NAND_FLASH_CMD 0x00
> +#define NAND_ADDR0 0x04
> +#define NAND_ADDR1 0x08
> +#define NAND_FLASH_CHIP_SELECT 0x0c
> +#define NAND_EXEC_CMD 0x10
> +#define NAND_FLASH_STATUS 0x14
> +#define NAND_BUFFER_STATUS 0x18
> +#define NAND_DEV0_CFG0 0x20
> +#define NAND_DEV0_CFG1 0x24
> +#define NAND_DEV0_ECC_CFG 0x28
> +#define NAND_AUTO_STATUS_EN 0x2c
> +#define NAND_DEV1_CFG0 0x30
> +#define NAND_DEV1_CFG1 0x34
> +#define NAND_READ_ID 0x40
> +#define NAND_READ_STATUS 0x44
> +#define NAND_DEV_CMD0 0xa0
> +#define NAND_DEV_CMD1 0xa4
> +#define NAND_DEV_CMD2 0xa8
> +#define NAND_DEV_CMD_VLD 0xac
> +#define SFLASHC_BURST_CFG 0xe0
> +#define NAND_ERASED_CW_DETECT_CFG 0xe8
> +#define NAND_ERASED_CW_DETECT_STATUS 0xec
> +#define NAND_EBI2_ECC_BUF_CFG 0xf0
> +#define FLASH_BUF_ACC 0x100
> +
> +#define NAND_CTRL 0xf00
> +#define NAND_VERSION 0xf08
> +#define NAND_READ_LOCATION_0 0xf20
> +#define NAND_READ_LOCATION_1 0xf24
> +#define NAND_READ_LOCATION_2 0xf28
> +#define NAND_READ_LOCATION_3 0xf2c
> +#define NAND_READ_LOCATION_LAST_CW_0 0xf40
> +#define NAND_READ_LOCATION_LAST_CW_1 0xf44
> +#define NAND_READ_LOCATION_LAST_CW_2 0xf48
> +#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
> +
> +/* dummy register offsets, used by write_reg_dma */
> +#define NAND_DEV_CMD1_RESTORE 0xdead
> +#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
> +
> +/* NAND_FLASH_CMD bits */
> +#define PAGE_ACC BIT(4)
> +#define LAST_PAGE BIT(5)
> +
> +/* NAND_FLASH_CHIP_SELECT bits */
> +#define NAND_DEV_SEL 0
> +#define DM_EN BIT(2)
> +
> +/* NAND_FLASH_STATUS bits */
> +#define FS_OP_ERR BIT(4)
> +#define FS_READY_BSY_N BIT(5)
> +#define FS_MPU_ERR BIT(8)
> +#define FS_DEVICE_STS_ERR BIT(16)
> +#define FS_DEVICE_WP BIT(23)
> +
> +/* NAND_BUFFER_STATUS bits */
> +#define BS_UNCORRECTABLE_BIT BIT(8)
> +#define BS_CORRECTABLE_ERR_MSK 0x1f
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DISABLE_STATUS_AFTER_WRITE 4
> +#define CW_PER_PAGE 6
> +#define UD_SIZE_BYTES 9
> +#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
> +#define ECC_PARITY_SIZE_BYTES_RS 19
> +#define SPARE_SIZE_BYTES 23
> +#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
> +#define NUM_ADDR_CYCLES 27
> +#define STATUS_BFR_READ 30
> +#define SET_RD_MODE_AFTER_STATUS 31
> +
> +/* NAND_DEVn_CFG0 bits */
> +#define DEV0_CFG1_ECC_DISABLE 0
> +#define WIDE_FLASH 1
> +#define NAND_RECOVERY_CYCLES 2
> +#define CS_ACTIVE_BSY 5
> +#define BAD_BLOCK_BYTE_NUM 6
> +#define BAD_BLOCK_IN_SPARE_AREA 16
> +#define WR_RD_BSY_GAP 17
> +#define ENABLE_BCH_ECC 27
> +
> +/* NAND_DEV0_ECC_CFG bits */
> +#define ECC_CFG_ECC_DISABLE 0
> +#define ECC_SW_RESET 1
> +#define ECC_MODE 4
> +#define ECC_PARITY_SIZE_BYTES_BCH 8
> +#define ECC_NUM_DATA_BYTES 16
> +#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
> +#define ECC_FORCE_CLK_OPEN 30
> +
> +/* NAND_DEV_CMD1 bits */
> +#define READ_ADDR 0
> +
> +/* NAND_DEV_CMD_VLD bits */
> +#define READ_START_VLD BIT(0)
> +#define READ_STOP_VLD BIT(1)
> +#define WRITE_START_VLD BIT(2)
> +#define ERASE_START_VLD BIT(3)
> +#define SEQ_READ_START_VLD BIT(4)
> +
> +/* NAND_EBI2_ECC_BUF_CFG bits */
> +#define NUM_STEPS 0
> +
> +/* NAND_ERASED_CW_DETECT_CFG bits */
> +#define ERASED_CW_ECC_MASK 1
> +#define AUTO_DETECT_RES 0
> +#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
> +#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
> +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
> +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
> +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
> +
> +/* NAND_ERASED_CW_DETECT_STATUS bits */
> +#define PAGE_ALL_ERASED BIT(7)
> +#define CODEWORD_ALL_ERASED BIT(6)
> +#define PAGE_ERASED BIT(5)
> +#define CODEWORD_ERASED BIT(4)
> +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
> +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
> +
> +/* NAND_READ_LOCATION_n bits */
> +#define READ_LOCATION_OFFSET 0
> +#define READ_LOCATION_SIZE 16
> +#define READ_LOCATION_LAST 31
> +
> +/* Version Mask */
> +#define NAND_VERSION_MAJOR_MASK 0xf0000000
> +#define NAND_VERSION_MAJOR_SHIFT 28
> +#define NAND_VERSION_MINOR_MASK 0x0fff0000
> +#define NAND_VERSION_MINOR_SHIFT 16
> +
> +/* NAND OP_CMDs */
> +#define OP_PAGE_READ 0x2
> +#define OP_PAGE_READ_WITH_ECC 0x3
> +#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
> +#define OP_PAGE_READ_ONFI_READ 0x5
> +#define OP_PROGRAM_PAGE 0x6
> +#define OP_PAGE_PROGRAM_WITH_ECC 0x7
> +#define OP_PROGRAM_PAGE_SPARE 0x9
> +#define OP_BLOCK_ERASE 0xa
> +#define OP_CHECK_STATUS 0xc
> +#define OP_FETCH_ID 0xb
> +#define OP_RESET_DEVICE 0xd
> +
> +/* Default Value for NAND_DEV_CMD_VLD */
> +#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
> + ERASE_START_VLD | SEQ_READ_START_VLD)
> +
> +/* NAND_CTRL bits */
> +#define BAM_MODE_EN BIT(0)
> +
> +/*
> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> + * the driver calls the chunks 'step' or 'codeword' interchangeably
> + */
> +#define NANDC_STEP_SIZE 512
> +
> +/*
> + * the largest page size we support is 8K, this will have 16 steps/codewords
> + * of 512 bytes each
> + */
> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
> +
> +/* we read at most 3 registers per codeword scan */
> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
> +
> +#define QPIC_PER_CW_CMD_ELEMENTS 32
> +#define QPIC_PER_CW_CMD_SGL 32
> +#define QPIC_PER_CW_DATA_SGL 8
> +
> +#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
> +
> +/*
> + * Flags used in DMA descriptor preparation helper functions
> + * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
> + */
> +/* Don't set the EOT in current tx BAM sgl */
> +#define NAND_BAM_NO_EOT BIT(0)
> +/* Set the NWD flag in current BAM sgl */
> +#define NAND_BAM_NWD BIT(1)
> +/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
> +#define NAND_BAM_NEXT_SGL BIT(2)
> +
> +/*
> + * Returns the actual register address for all NAND_DEV_ registers
> + * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
> + */
> +#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
> +
> +/* Returns the NAND register physical address */
> +#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
> +
> +/* Returns the dma address for reg read buffer */
> +#define reg_buf_dma_addr(chip, vaddr) \
> + ((chip)->reg_read_dma + \
> + ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
> +
> +/*
> + * Erased codeword status is being used two times in single transfer so this
> + * flag will determine the current value of erased codeword status register
> + */
> +#define NAND_ERASED_CW_SET BIT(4)
> +
> +#define MAX_ADDRESS_CYCLE 5
> +
> +/*
> + * This data type corresponds to the BAM transaction which will be used for all
> + * NAND transfers.
> + * @bam_ce - the array of BAM command elements
> + * @cmd_sgl - sgl for NAND BAM command pipe
> + * @data_sgl - sgl for NAND BAM consumer/producer pipe
> + * @last_data_desc - last DMA desc in data channel (tx/rx).
> + * @last_cmd_desc - last DMA desc in command channel.
> + * @txn_done - completion for NAND transfer.
> + * @bam_ce_pos - the index in bam_ce which is available for next sgl
> + * @bam_ce_start - the index in bam_ce which marks the start position ce
> + * for current sgl. It will be used for size calculation
> + * for current sgl
> + * @cmd_sgl_pos - current index in command sgl.
> + * @cmd_sgl_start - start index in command sgl.
> + * @tx_sgl_pos - current index in data sgl for tx.
> + * @tx_sgl_start - start index in data sgl for tx.
> + * @rx_sgl_pos - current index in data sgl for rx.
> + * @rx_sgl_start - start index in data sgl for rx.
> + * @wait_second_completion - wait for second DMA desc completion before making
> + * the NAND transfer completion.
> + */
> +struct bam_transaction {
> + struct bam_cmd_element *bam_ce;
> + struct scatterlist *cmd_sgl;
> + struct scatterlist *data_sgl;
> + struct dma_async_tx_descriptor *last_data_desc;
> + struct dma_async_tx_descriptor *last_cmd_desc;
> + struct completion txn_done;
> + u32 bam_ce_pos;
> + u32 bam_ce_start;
> + u32 cmd_sgl_pos;
> + u32 cmd_sgl_start;
> + u32 tx_sgl_pos;
> + u32 tx_sgl_start;
> + u32 rx_sgl_pos;
> + u32 rx_sgl_start;
> + bool wait_second_completion;
> +};
> +
> +/*
> + * This data type corresponds to the nand dma descriptor
> + * @dma_desc - low level DMA engine descriptor
> + * @list - list for desc_info
> + *
> + * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
> + * ADM
> + * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
> + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
> + * @dir - DMA transfer direction
> + */
> +struct desc_info {
> + struct dma_async_tx_descriptor *dma_desc;
> + struct list_head node;
> +
> + union {
> + struct scatterlist adm_sgl;
> + struct {
> + struct scatterlist *bam_sgl;
> + int sgl_cnt;
> + };
> + };
> + enum dma_data_direction dir;
> +};
> +
> +/*
> + * holds the current register values that we want to write. acts as a contiguous
> + * chunk of memory which we use to write the controller registers through DMA.
> + */
> +struct nandc_regs {
> + __le32 cmd;
> + __le32 addr0;
> + __le32 addr1;
> + __le32 chip_sel;
> + __le32 exec;
> +
> + __le32 cfg0;
> + __le32 cfg1;
> + __le32 ecc_bch_cfg;
> +
> + __le32 clrflashstatus;
> + __le32 clrreadstatus;
> +
> + __le32 cmd1;
> + __le32 vld;
> +
> + __le32 orig_cmd1;
> + __le32 orig_vld;
> +
> + __le32 ecc_buf_cfg;
> + __le32 read_location0;
> + __le32 read_location1;
> + __le32 read_location2;
> + __le32 read_location3;
> + __le32 read_location_last0;
> + __le32 read_location_last1;
> + __le32 read_location_last2;
> + __le32 read_location_last3;
> +
> + __le32 erased_cw_detect_cfg_clr;
> + __le32 erased_cw_detect_cfg_set;
> +};
> +
> +/*
> + * NAND controller data struct
> + *
> + * @dev: parent device
> + *
> + * @base: MMIO base
> + *
> + * @core_clk: controller clock
> + * @aon_clk: another controller clock
> + *
> + * @regs: a contiguous chunk of memory for DMA register
> + * writes. contains the register values to be
> + * written to controller
> + *
> + * @props: properties of current NAND controller,
> + * initialized via DT match data
> + *
> + * @controller: base controller structure
> + * @host_list: list containing all the chips attached to the
> + * controller
> + *
> + * @chan: dma channel
> + * @cmd_crci: ADM DMA CRCI for command flow control
> + * @data_crci: ADM DMA CRCI for data flow control
> + *
> + * @desc_list: DMA descriptor list (list of desc_infos)
> + *
> + * @data_buffer: our local DMA buffer for page read/writes,
> + * used when we can't use the buffer provided
> + * by upper layers directly
> + * @reg_read_buf: local buffer for reading back registers via DMA
> + *
> + * @base_phys: physical base address of controller registers
> + * @base_dma: dma base address of controller registers
> + * @reg_read_dma: contains dma address for register read buffer
> + *
> + * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
> + * functions
> + * @max_cwperpage: maximum QPIC codewords required. calculated
> + * from all connected NAND devices pagesize
> + *
> + * @reg_read_pos: marker for data read in reg_read_buf
> + *
> + * @cmd1/vld: some fixed controller register values
> + *
> + * @exec_opwrite: flag to select correct number of code word
> + * while reading status
> + */
> +struct qcom_nand_controller {
> + struct device *dev;
> +
> + void __iomem *base;
> +
> + struct clk *core_clk;
> + struct clk *aon_clk;
> +
> + struct nandc_regs *regs;
> + struct bam_transaction *bam_txn;
> +
> + const struct qcom_nandc_props *props;
> +
> + struct nand_controller controller;
> + struct list_head host_list;
> +
> + union {
> + /* will be used only by QPIC for BAM DMA */
> + struct {
> + struct dma_chan *tx_chan;
> + struct dma_chan *rx_chan;
> + struct dma_chan *cmd_chan;
> + };
> +
> + /* will be used only by EBI2 for ADM DMA */
> + struct {
> + struct dma_chan *chan;
> + unsigned int cmd_crci;
> + unsigned int data_crci;
> + };
> + };
> +
> + struct list_head desc_list;
> +
> + u8 *data_buffer;
> + __le32 *reg_read_buf;
> +
> + phys_addr_t base_phys;
> + dma_addr_t base_dma;
> + dma_addr_t reg_read_dma;
> +
> + int buf_size;
> + int buf_count;
> + int buf_start;
> + unsigned int max_cwperpage;
> +
> + int reg_read_pos;
> +
> + u32 cmd1, vld;
> + bool exec_opwrite;
> +};
> +
> +/*
> + * This data type corresponds to the NAND controller properties which varies
> + * among different NAND controllers.
> + * @ecc_modes - ecc mode for NAND
> + * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
> + * @is_bam - whether NAND controller is using BAM
> + * @is_qpic - whether NAND CTRL is part of qpic IP
> + * @qpic_v2 - flag to indicate QPIC IP version 2
> + * @use_codeword_fixup - whether NAND has different layout for boot partitions
> + */
> +struct qcom_nandc_props {
> + u32 ecc_modes;
> + u32 dev_cmd_reg_start;
> + bool is_bam;
> + bool is_qpic;
> + bool qpic_v2;
> + bool use_codeword_fixup;
> +};
> +
> +void config_nand_page_read(struct nand_chip *chip);
> +void free_bam_transaction(struct qcom_nand_controller *nandc);
> +void qpic_bam_dma_done(void *data);
> +void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, bool is_cpu);
> +__le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset);
> +void clear_read_regs(struct qcom_nand_controller *nandc);
> +int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
> + int reg_off, const void *vaddr, int size,
> + bool flow_control);
> +int submit_descs(struct qcom_nand_controller *nandc);
> +int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
> + struct dma_chan *chan, unsigned long flags);
> +int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
> + int reg_off, const void *vaddr,
> + int size, unsigned int flags);
> +int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
> + const void *vaddr,
> + int size, unsigned int flags);
> +int read_reg_dma(struct qcom_nand_controller *nandc, int first,
> + int num_regs, unsigned int flags);
> +int write_reg_dma(struct qcom_nand_controller *nandc, int first,
> + int num_regs, unsigned int flags);
> +int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> + const u8 *vaddr, int size, unsigned int flags);
> +int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
> + const u8 *vaddr, int size, unsigned int flags);
> +struct bam_transaction *alloc_bam_transaction(struct qcom_nand_controller *nandc);
> +void clear_bam_transaction(struct qcom_nand_controller *nandc);
> +void qcom_nandc_unalloc(struct qcom_nand_controller *nandc);
> +int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
> +struct qcom_nand_controller *get_qcom_nand_controller(struct nand_chip *chip);
> +
> +#endif
Hi Md,
kernel test robot noticed the following build warnings:
[auto build test WARNING on next-20240215]
[also build test WARNING on linus/master v6.8-rc4]
[cannot apply to mtd/nand/next broonie-spi/for-next robh/for-next v6.8-rc4 v6.8-rc3 v6.8-rc2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Md-Sadre-Alam/spi-dt-bindings-add-binding-doc-for-spi-qpic-snand/20240215-215348
base: next-20240215
patch link: https://lore.kernel.org/r/20240215134856.1313239-4-quic_mdalam%40quicinc.com
patch subject: [PATCH 3/5] spi: spi-qpic: Add qpic spi nand driver support
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20240217/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240217/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
drivers/spi/spi-qpic-snand.c: In function 'qpic_snand_ecc_init_ctx_pipelined':
drivers/spi/spi-qpic-snand.c:161:14: warning: variable 'ecc_user' set but not used [-Wunused-but-set-variable]
161 | bool ecc_user = false;
| ^~~~~~~~
drivers/spi/spi-qpic-snand.c:160:42: warning: variable 'desired_correction' set but not used [-Wunused-but-set-variable]
160 | int step_size = 0, strength = 0, desired_correction = 0, steps;
| ^~~~~~~~~~~~~~~~~~
drivers/spi/spi-qpic-snand.c: In function 'qpic_snand_read_oob':
drivers/spi/spi-qpic-snand.c:399:13: warning: variable 'oob_buf' set but not used [-Wunused-but-set-variable]
399 | u8 *oob_buf;
| ^~~~~~~
drivers/spi/spi-qpic-snand.c: In function 'snandc_check_error':
drivers/spi/spi-qpic-snand.c:452:37: warning: variable 'erased' set but not used [-Wunused-but-set-variable]
452 | bool serial_op_err = false, erased;
| ^~~~~~
drivers/spi/spi-qpic-snand.c: In function 'qpic_snand_write_page_cache':
>> drivers/spi/spi-qpic-snand.c:682:30: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
682 | snandc->wbuf = op->data.buf.out;
| ^
>> drivers/spi/spi-qpic-snand.c:675:30: warning: variable 's_op' set but not used [-Wunused-but-set-variable]
675 | struct qpic_snand_op s_op = {};
| ^~~~
vim +/const +682 drivers/spi/spi-qpic-snand.c
671
672 static int qpic_snand_write_page_cache(struct qcom_nand_controller *snandc,
673 const struct spi_mem_op *op)
674 {
> 675 struct qpic_snand_op s_op = {};
676 u32 cmd;
677
678 cmd = qpic_snand_cmd_mapping(snandc, op->cmd.opcode);
679 s_op.cmd_reg = cmd;
680
681 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) {
> 682 snandc->wbuf = op->data.buf.out;
683 snandc->wlen = op->data.nbytes;
684 }
685
686 return 0;
687 }
688
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Md,
kernel test robot noticed the following build warnings:
[auto build test WARNING on next-20240215]
[also build test WARNING on linus/master v6.8-rc4]
[cannot apply to mtd/nand/next broonie-spi/for-next robh/for-next v6.8-rc4 v6.8-rc3 v6.8-rc2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Md-Sadre-Alam/spi-dt-bindings-add-binding-doc-for-spi-qpic-snand/20240215-215348
base: next-20240215
patch link: https://lore.kernel.org/r/20240215134856.1313239-4-quic_mdalam%40quicinc.com
patch subject: [PATCH 3/5] spi: spi-qpic: Add qpic spi nand driver support
config: arm-defconfig (https://download.01.org/0day-ci/archive/20240218/[email protected]/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project.git f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240218/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
>> drivers/spi/spi-qpic-snand.c:161:7: warning: variable 'ecc_user' set but not used [-Wunused-but-set-variable]
bool ecc_user = false;
^
>> drivers/spi/spi-qpic-snand.c:160:35: warning: variable 'desired_correction' set but not used [-Wunused-but-set-variable]
int step_size = 0, strength = 0, desired_correction = 0, steps;
^
>> drivers/spi/spi-qpic-snand.c:399:6: warning: variable 'oob_buf' set but not used [-Wunused-but-set-variable]
u8 *oob_buf;
^
>> drivers/spi/spi-qpic-snand.c:452:30: warning: variable 'erased' set but not used [-Wunused-but-set-variable]
bool serial_op_err = false, erased;
^
drivers/spi/spi-qpic-snand.c:682:16: error: assigning to 'u8 *' (aka 'unsigned char *') from 'const void *const' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
snandc->wbuf = op->data.buf.out;
^ ~~~~~~~~~~~~~~~~
4 warnings and 1 error generated.
vim +/ecc_user +161 drivers/spi/spi-qpic-snand.c
152
153 static int qpic_snand_ecc_init_ctx_pipelined(struct nand_device *nand)
154 {
155 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
156 struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
157 struct nand_ecc_props *reqs = &nand->ecc.requirements;
158 struct nand_ecc_props *user = &nand->ecc.user_conf;
159 struct mtd_info *mtd = nanddev_to_mtd(nand);
> 160 int step_size = 0, strength = 0, desired_correction = 0, steps;
> 161 bool ecc_user = false;
162 int cwperpage, bad_block_byte;
163 struct qpic_ecc *ecc_cfg;
164
165 cwperpage = mtd->writesize / NANDC_STEP_SIZE;
166
167 ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
168 if (!ecc_cfg)
169 return -ENOMEM;
170
171 nand->ecc.ctx.priv = ecc_cfg;
172
173 if (user->step_size && user->strength) {
174 step_size = user->step_size;
175 strength = user->strength;
176 ecc_user = true;
177 } else if (reqs->step_size && reqs->strength) {
178 step_size = reqs->step_size;
179 strength = reqs->strength;
180 }
181
182 if (step_size && strength) {
183 steps = mtd->writesize / step_size;
184 desired_correction = steps * strength;
185 }
186
187 ecc_cfg->ecc_bytes_hw = 7;
188 ecc_cfg->spare_bytes = 4;
189 ecc_cfg->bbm_size = 1;
190 ecc_cfg->bch_enabled = true;
191 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
192
193 ecc_cfg->steps = 4;
194 ecc_cfg->strength = 4;
195 ecc_cfg->step_size = 512;
196
197 mtd_set_ooblayout(mtd, &qcom_snand_ooblayout);
198
199 ecc_cfg->cw_data = 516;
200 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
201 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
202
203 ecc_cfg->cfg0 = (cwperpage - 1) << CW_PER_PAGE
204 | ecc_cfg->cw_data << UD_SIZE_BYTES
205 | 1 << DISABLE_STATUS_AFTER_WRITE
206 | 3 << NUM_ADDR_CYCLES
207 | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
208 | 0 << STATUS_BFR_READ
209 | 1 << SET_RD_MODE_AFTER_STATUS
210 | ecc_cfg->spare_bytes << SPARE_SIZE_BYTES;
211
212 ecc_cfg->cfg1 = 0 << NAND_RECOVERY_CYCLES
213 | 0 << CS_ACTIVE_BSY
214 | bad_block_byte << BAD_BLOCK_BYTE_NUM
215 | 0 << BAD_BLOCK_IN_SPARE_AREA
216 | 20 << WR_RD_BSY_GAP
217 | 0 << WIDE_FLASH
218 | ecc_cfg->bch_enabled << ENABLE_BCH_ECC;
219
220 ecc_cfg->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
221 | ecc_cfg->cw_size << UD_SIZE_BYTES
222 | 3 << NUM_ADDR_CYCLES
223 | 0 << SPARE_SIZE_BYTES;
224
225 ecc_cfg->cfg1_raw = 0 << NAND_RECOVERY_CYCLES
226 | 0 << CS_ACTIVE_BSY
227 | 17 << BAD_BLOCK_BYTE_NUM
228 | 1 << BAD_BLOCK_IN_SPARE_AREA
229 | 20 << WR_RD_BSY_GAP
230 | 0 << WIDE_FLASH
231 | 1 << DEV0_CFG1_ECC_DISABLE;
232
233 ecc_cfg->ecc_bch_cfg = !ecc_cfg->bch_enabled << ECC_CFG_ECC_DISABLE
234 | 0 << ECC_SW_RESET
235 | ecc_cfg->cw_data << ECC_NUM_DATA_BYTES
236 | 1 << ECC_FORCE_CLK_OPEN
237 | 0 << ECC_MODE
238 | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
239
240 ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
241 ecc_cfg->clrflashstatus = FS_READY_BSY_N;
242 ecc_cfg->clrreadstatus = 0xc0;
243
244 conf->step_size = ecc_cfg->step_size;
245 conf->strength = ecc_cfg->strength;
246
247 if (ecc_cfg->strength < strength)
248 dev_warn(snandc->dev, "Unable to fulfill ECC requirements of %u bits.\n", strength);
249
250 dev_info(snandc->dev, "ECC strength: %u bits per %u bytes\n",
251 ecc_cfg->strength, ecc_cfg->step_size);
252
253 return 0;
254 }
255
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Md,
kernel test robot noticed the following build errors:
[auto build test ERROR on next-20240215]
[also build test ERROR on linus/master v6.8-rc4]
[cannot apply to mtd/nand/next broonie-spi/for-next robh/for-next v6.8-rc4 v6.8-rc3 v6.8-rc2]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Md-Sadre-Alam/spi-dt-bindings-add-binding-doc-for-spi-qpic-snand/20240215-215348
base: next-20240215
patch link: https://lore.kernel.org/r/20240215134856.1313239-4-quic_mdalam%40quicinc.com
patch subject: [PATCH 3/5] spi: spi-qpic: Add qpic spi nand driver support
config: arm-defconfig (https://download.01.org/0day-ci/archive/20240218/[email protected]/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project.git f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240218/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
drivers/spi/spi-qpic-snand.c:161:7: warning: variable 'ecc_user' set but not used [-Wunused-but-set-variable]
bool ecc_user = false;
^
drivers/spi/spi-qpic-snand.c:160:35: warning: variable 'desired_correction' set but not used [-Wunused-but-set-variable]
int step_size = 0, strength = 0, desired_correction = 0, steps;
^
drivers/spi/spi-qpic-snand.c:399:6: warning: variable 'oob_buf' set but not used [-Wunused-but-set-variable]
u8 *oob_buf;
^
drivers/spi/spi-qpic-snand.c:452:30: warning: variable 'erased' set but not used [-Wunused-but-set-variable]
bool serial_op_err = false, erased;
^
>> drivers/spi/spi-qpic-snand.c:682:16: error: assigning to 'u8 *' (aka 'unsigned char *') from 'const void *const' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
snandc->wbuf = op->data.buf.out;
^ ~~~~~~~~~~~~~~~~
4 warnings and 1 error generated.
vim +682 drivers/spi/spi-qpic-snand.c
671
672 static int qpic_snand_write_page_cache(struct qcom_nand_controller *snandc,
673 const struct spi_mem_op *op)
674 {
675 struct qpic_snand_op s_op = {};
676 u32 cmd;
677
678 cmd = qpic_snand_cmd_mapping(snandc, op->cmd.opcode);
679 s_op.cmd_reg = cmd;
680
681 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) {
> 682 snandc->wbuf = op->data.buf.out;
683 snandc->wlen = op->data.nbytes;
684 }
685
686 return 0;
687 }
688
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Thu, Feb 15, 2024 at 07:18:51PM +0530, Md Sadre Alam wrote:
> This series of patches will add initial supports
> for QPIC SPI NAND driver.
>
> Currently this driver support following commands
>
> -- RESET
> -- READ ID
> -- BLOCK ERASE
> -- PAGE READ
> -- PAGE WRITE
> -- GET FEATURE
> -- SET FEATURE
> -- BAD BLOCK CHECK
>
> This driver has been tested with dd command with read/write page
> with multiple file size 1MiB, 10MiB,40MiB etc.
> Also tested with "mtd" command like mtd erase, mtd write, mtd verify etc.
>
This is not the first version isn't it? Where is the changelog describing what
has changed since then?
- Mani
> Need help to test these all patches on SDX65 and SDX75 platform.
>
> Md Sadre Alam (5):
> spi: dt-bindings: add binding doc for spi-qpic-snand
> drivers: mtd: nand: Add qpic_common API file
> spi: spi-qpic: Add qpic spi nand driver support
> arm64: dts: qcom: ipq9574: Add SPI nand support
> arm64: dts: qcom: ipq9574: Disable eMMC node
>
> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 ++
> .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +
> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 2 +-
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/qpic_common.c | 794 +++++++++++
> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +----------------
> drivers/spi/Kconfig | 9 +
> drivers/spi/Makefile | 1 +
> drivers/spi/spi-qpic-snand.c | 1025 ++++++++++++++
> include/linux/mtd/nand-qpic-common.h | 548 ++++++++
> 11 files changed, 2547 insertions(+), 1211 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
> create mode 100644 drivers/mtd/nand/qpic_common.c
> create mode 100644 drivers/spi/spi-qpic-snand.c
> create mode 100644 include/linux/mtd/nand-qpic-common.h
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
On 2/19/2024 6:34 PM, Manivannan Sadhasivam wrote:
> On Thu, Feb 15, 2024 at 07:18:51PM +0530, Md Sadre Alam wrote:
>> This series of patches will add initial supports
>> for QPIC SPI NAND driver.
>>
>> Currently this driver support following commands
>>
>> -- RESET
>> -- READ ID
>> -- BLOCK ERASE
>> -- PAGE READ
>> -- PAGE WRITE
>> -- GET FEATURE
>> -- SET FEATURE
>> -- BAD BLOCK CHECK
>>
>> This driver has been tested with dd command with read/write page
>> with multiple file size 1MiB, 10MiB,40MiB etc.
>> Also tested with "mtd" command like mtd erase, mtd write, mtd verify etc.
>>
>
> This is not the first version isn't it? Where is the changelog describing what
> has changed since then?
The earlier patch was the RFC for design review only.
>
> - Mani
>
>> Need help to test these all patches on SDX65 and SDX75 platform.
>>
>> Md Sadre Alam (5):
>> spi: dt-bindings: add binding doc for spi-qpic-snand
>> drivers: mtd: nand: Add qpic_common API file
>> spi: spi-qpic: Add qpic spi nand driver support
>> arm64: dts: qcom: ipq9574: Add SPI nand support
>> arm64: dts: qcom: ipq9574: Disable eMMC node
>>
>> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 ++
>> .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +
>> arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 2 +-
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 27 +
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/qpic_common.c | 794 +++++++++++
>> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +----------------
>> drivers/spi/Kconfig | 9 +
>> drivers/spi/Makefile | 1 +
>> drivers/spi/spi-qpic-snand.c | 1025 ++++++++++++++
>> include/linux/mtd/nand-qpic-common.h | 548 ++++++++
>> 11 files changed, 2547 insertions(+), 1211 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>> create mode 100644 drivers/mtd/nand/qpic_common.c
>> create mode 100644 drivers/spi/spi-qpic-snand.c
>> create mode 100644 include/linux/mtd/nand-qpic-common.h
>>
>> --
>> 2.34.1
>>
>
On 20/02/2024 12:32, Md Sadre Alam wrote:
>
>
> On 2/19/2024 6:34 PM, Manivannan Sadhasivam wrote:
>> On Thu, Feb 15, 2024 at 07:18:51PM +0530, Md Sadre Alam wrote:
>>> This series of patches will add initial supports
>>> for QPIC SPI NAND driver.
>>>
>>> Currently this driver support following commands
>>>
>>> -- RESET
>>> -- READ ID
>>> -- BLOCK ERASE
>>> -- PAGE READ
>>> -- PAGE WRITE
>>> -- GET FEATURE
>>> -- SET FEATURE
>>> -- BAD BLOCK CHECK
>>>
>>> This driver has been tested with dd command with read/write page
>>> with multiple file size 1MiB, 10MiB,40MiB etc.
>>> Also tested with "mtd" command like mtd erase, mtd write, mtd verify etc.
>>>
>>
>> This is not the first version isn't it? Where is the changelog describing what
>> has changed since then?
>
> The earlier patch was the RFC for design review only.
RFC is state of patch, not version. This is v2 then.
These RFC postings are really becoming mess. Some people make multiple
RFCs and then post v1 hiding entire previous history... And why even
bother with calling it RFC?
Best regards,
Krzysztof
On 2/15/2024 7:44 PM, Mark Brown wrote:
> On Thu, Feb 15, 2024 at 07:18:54PM +0530, Md Sadre Alam wrote:
>
>> +config SPI_QPIC_SNAND
>> + tristate "QPIC SNAND controller"
>> + default y
>
> Why is this driver so special it should be enabled by default?
Sorry by mistake I kept this enabled by default, will change in next
patch.
>
>> + depends on ARCH_QCOM
>
> Please add an || COMPILE_TEST so this gets some build coverage.
Ok
>
>> + help
>> + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
>> + QPIC controller supports both parallel nand and serial nand.
>> + This config will enable serial nand driver for QPIC controller.
>> +
>> config SPI_QUP
>> tristate "Qualcomm SPI controller with QUP interface"
>> depends on ARCH_QCOM || COMPILE_TEST
>> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
>> index 4ff8d725ba5e..1ac3bac35007 100644
>> --- a/drivers/spi/Makefile
>> +++ b/drivers/spi/Makefile
>> @@ -153,6 +153,7 @@ obj-$(CONFIG_SPI_XTENSA_XTFPGA) += spi-xtensa-xtfpga.o
>> obj-$(CONFIG_SPI_ZYNQ_QSPI) += spi-zynq-qspi.o
>> obj-$(CONFIG_SPI_ZYNQMP_GQSPI) += spi-zynqmp-gqspi.o
>> obj-$(CONFIG_SPI_AMD) += spi-amd.o
>> +obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
>
> Please keep this sorted.
Ok
>
>> --- /dev/null
>> +++ b/drivers/spi/spi-qpic-snand.c
>> @@ -0,0 +1,1025 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>
> Please make the entire comment a C++ one so things look more
> intentional.
Ok
>
>> +#define snandc_set_read_loc_first(snandc, reg, cw_offset, read_size, is_last_read_loc) \
>> +snandc_set_reg(snandc, reg, \
>> + ((cw_offset) << READ_LOCATION_OFFSET) | \
>> + ((read_size) << READ_LOCATION_SIZE) | \
>> + ((is_last_read_loc) << READ_LOCATION_LAST))
>> +
>> +#define snandc_set_read_loc_last(snandc, reg, cw_offset, read_size, is_last_read_loc) \
>> +snandc_set_reg(snandc, reg, \
>> + ((cw_offset) << READ_LOCATION_OFFSET) | \
>> + ((read_size) << READ_LOCATION_SIZE) | \
>> + ((is_last_read_loc) << READ_LOCATION_LAST))
>
> For type safety and legibility please write these as functions, mark
> them as static inline if needed.
Ok
>
>> +void snandc_set_reg(struct qcom_nand_controller *snandc, int offset, u32 val)
>> +{
>> + struct nandc_regs *regs = snandc->regs;
>> + __le32 *reg;
>> +
>> + reg = offset_to_nandc_reg(regs, offset);
>> +
>> + if (reg)
>> + *reg = cpu_to_le32(val);
>> +}
>
> This silently ignores writes to invalid registers, that doesn't seem
> great.
Ok
>
>> + return snandc->ecc_stats.failed ? -EBADMSG : snandc->ecc_stats.bitflips;
>
> For legibility please just write normal conditional statements.
Ok
>
>> +static int qpic_snand_program_execute(struct qcom_nand_controller *snandc,
>> + const struct spi_mem_op *op)
>> +{
>
>> + int num_cw = 4;
>
>> + data_buf = (u8 *)snandc->wbuf;
>
> Why the cast? If it's needed that smells like it's masking a bug, it
> looks like it's casting from a u8 * to a u8 *.
Ok Will fix in next patch.
>
>> + for (i = 0; i < num_cw; i++) {
>> + int data_size;
>
> All these functions appear to hard code "num_cw" to 4. What is "num_cw"
> and why are we doing this per function?
QPIC controller internally works on code word size not on page and each
code word size is 512-bytes so if page size is 2K then num_cw = 4, if page
size is 4K then num_cw = 8.
Will not hard code this value to 4 or 8 , will fix this in next patch.
>
>> +static int qpic_snand_program_execute(struct qcom_nand_controller *snandc,
>> + const struct spi_mem_op *op)
>
>> + if (op->cmd.opcode == SPINAND_READID) {
>> + snandc->buf_count = 4;
>> + read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
>> +
>> + ret = submit_descs(snandc);
>> + if (ret)
>> + dev_err(snandc->dev, "failure in submitting descriptor for readid\n");
>> +
>> + nandc_read_buffer_sync(snandc, true);
>> + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
>
> These memcpy()s don't seem great, why aren't we just reading directly
> into the output buffer?
This reg_read_buf is being used in common API so that it will be used by both
serial nand as well raw nand, so I can't directly use the output buffer since
internally CW mechanism I have to maintain in common API.
>
>> + if (op->cmd.opcode == SPINAND_GET_FEATURE) {
>
> This function looks like it should be a switch statement.
Ok
>
>> +static bool qpic_snand_is_page_op(const struct spi_mem_op *op)
>> +{
>
>> + if (op->data.dir == SPI_MEM_DATA_IN) {
>> + if (op->addr.buswidth == 4 && op->data.buswidth == 4)
>> + return true;
>> +
>> + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
>> + return true;
>> +
>> + } else if (op->data.dir == SPI_MEM_DATA_OUT) {
>> + if (op->data.buswidth == 4)
>> + return true;
>> + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
>> + return true;
>> + }
>
> Again looks like a switch statement.
Ok
>
>> + ctlr = devm_spi_alloc_master(dev, sizeof(*snandc));
>> + if (!ctlr)
>> + return -ENOMEM;
>
> Please use _alloc_controller.
Ok
>
>> +static int qcom_snand_remove(struct platform_device *pdev)
>> +{
>> + struct spi_controller *ctlr = platform_get_drvdata(pdev);
>> +
>> + spi_unregister_controller(ctlr);
>> +
>> + return 0;
>> +}
>
> We don't disable any of the clocks in the remove path.
OK will fix in next patch.
Thanks for reviewing, will address all your comments in the next patch.
Regards,
Alam.
On 2/15/2024 7:52 PM, Mark Brown wrote:
> On Thu, Feb 15, 2024 at 07:18:52PM +0530, Md Sadre Alam wrote:
>
>> + clocks:
>> + minItems: 2
>> + maxItems: 3
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 3
>
> The driver requests the clocks by name but this does not document the
> expected set of names. The driver also unconditionally requests all
> three clocks so won't work with only two clocks.
Thanks for reviewing, Will document the clock name in next patch.
By mistake i have given minItems = 2 and maxItems = 3 , will fix
this in next patch.
On 2/15/2024 7:54 PM, Conor Dooley wrote:
> On Thu, Feb 15, 2024 at 07:18:52PM +0530, Md Sadre Alam wrote:
>> Add device-tree binding documentation for QCOM QPIC-SNAND-NAND Flash
>> Interface.
>>
>> Co-developed-by: Sricharan Ramabadhran <[email protected]>
>> Signed-off-by: Sricharan Ramabadhran <[email protected]>
>> Co-developed-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Md Sadre Alam <[email protected]>
>> ---
>> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 +++++++++++++++++++
>> 1 file changed, 82 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>> new file mode 100644
>> index 000000000000..fa7484ce1319
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>> @@ -0,0 +1,82 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QPIC NAND controller
>> +
>> +maintainers:
>> + - Md sadre Alam <[email protected]>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,ipq9574-snand
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 2
>> + maxItems: 3
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 3
>> +
>> +allOf:
>> + - $ref: /schemas/spi/spi-controller.yaml#
>> + - if:
>
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,ipq9574-snand
>> +
>> + then:
>> + properties:
>> + dmas:
>> + items:
>> + - description: tx DMA channel
>> + - description: rx DMA channel
>> + - description: cmd DMA channel
>> +
>> + dma-names:
>> + items:
>> + - const: tx
>> + - const: rx
>> + - const: cmd
>
> None of this complexity here is needed, you have only one device in this
> binding and therefore can define these properties at the top level.
Thanks for reviewing, Will fix this in next patch.
>
> Cheers,
> Conor.
>
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> + qpic_nand: spi@79b0000 {
>> + compatible = "qcom,ipq9574-snand";
>> + reg = <0x1ac00000 0x800>;
>> +
>> + clocks = <&gcc GCC_QPIC_CLK>,
>> + <&gcc GCC_QPIC_AHB_CLK>,
>> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
>> + clock-names = "core", "aon", "iom";
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + flash@0 {
>> + compatible = "spi-nand";
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + nand-ecc-engine = <&qpic_nand>;
>> + nand-ecc-strength = <4>;
>> + nand-ecc-step-size = <512>;
>> + };
>> + };
>> --
>> 2.34.1
>>
On 2/15/2024 11:27 PM, Konrad Dybcio wrote:
> On 15.02.2024 14:48, Md Sadre Alam wrote:
>> Add qpic spi nand driver support. The spi nand
>> driver currently supported the below commands.
>>
>> -- RESET
>> -- READ ID
>> -- SET FEATURE
>> -- GET FEATURE
>> -- READ PAGE
>> -- WRITE PAGE
>> -- ERASE PAGE
>>
>> Co-developed-by: Sricharan Ramabadhran <[email protected]>
>> Signed-off-by: Sricharan Ramabadhran <[email protected]>
>> Co-developed-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Md Sadre Alam <[email protected]>
>> ---
>
> [...]
>
>> +void snandc_set_reg(struct qcom_nand_controller *snandc, int offset, u32 val)
>> +{
>> + struct nandc_regs *regs = snandc->regs;
>> + __le32 *reg;
>> +
>> + reg = offset_to_nandc_reg(regs, offset);
>> +
>> + if (reg)
>> + *reg = cpu_to_le32(val);
>
> if (WARN_ON(!reg))
> return;
>
> instead?
>
> This would be tragic..
will fix this in next patch.
>
> [...]
>
>> +
>> + ecc_cfg->cfg0 = (cwperpage - 1) << CW_PER_PAGE
>> + | ecc_cfg->cw_data << UD_SIZE_BYTES
>> + | 1 << DISABLE_STATUS_AFTER_WRITE
>> + | 3 << NUM_ADDR_CYCLES
>> + | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
>> + | 0 << STATUS_BFR_READ
>> + | 1 << SET_RD_MODE_AFTER_STATUS
>> + | ecc_cfg->spare_bytes << SPARE_SIZE_BYTES;
>
> Let me introduce you to FIELD_PREP/GET and GENMASK().. Many assignments
> in this file could use these.
Ok
>
> Konrad
Thanks for reviewing, will fix all the comments in next patch.
Regards,
Alam.
On 2/15/2024 11:25 PM, Konrad Dybcio wrote:
> On 15.02.2024 14:48, Md Sadre Alam wrote:
>> Add qpic_common.c file which hold all the common
>> qpic APIs which will be used by both qpic raw nand
>> driver and qpic spi nand driver.
>>
>> Co-developed-by: Sricharan Ramabadhran <[email protected]>
>> Signed-off-by: Sricharan Ramabadhran <[email protected]>
>> Co-developed-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Md Sadre Alam <[email protected]>
>> ---
>
> IIUC this is mostly moving code around?
>
> I do however have some suggestions..
Ok
>
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
>> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
>> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
>> 4 files changed, 1291 insertions(+), 1210 deletions(-)
>> create mode 100644 drivers/mtd/nand/qpic_common.c
>> create mode 100644 include/linux/mtd/nand-qpic-common.h
>>
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index 19e1291ac4d5..131707a41293 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
>> +obj-y += qpic_common.o
>> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
>> new file mode 100644
>> index 000000000000..4d74ba888028
>> --- /dev/null
>> +++ b/drivers/mtd/nand/qpic_common.c
>> @@ -0,0 +1,786 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * QPIC Controller common API file.
>> + * Copyright (C) 2023 Qualcomm Inc.
>> + * Authors: Md sadre Alam <[email protected]>
>> + * Sricharan R <[email protected]>
>> + * Varadarajan Narayanan <[email protected]>
>> + *
>> + */
>> +
>> +#include <linux/mtd/nand-qpic-common.h>
>> +
>> +struct qcom_nand_controller *
>> +get_qcom_nand_controller(struct nand_chip *chip)
>> +{
>> + return container_of(chip->controller, struct qcom_nand_controller,
>> + controller);
>> +}
>> +EXPORT_SYMBOL(get_qcom_nand_controller);
>
> #define to_qcom_nand_controller()?
Ok
>
>> +
>> +/*
>> + * Helper to prepare DMA descriptors for configuring registers
>> + * before reading a NAND page.
>> + */
>
> Can you convert these to kerneldoc instead?
Ok
>
>> +void config_nand_page_read(struct nand_chip *chip)
>> +{
>> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +
>> + write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> + write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> + if (!nandc->props->qpic_v2)
>
> This is not going to scale going forward.. please include a version
> enum instead.
Ok
>
> [...]
>
>> +
>> +int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
>> + int reg_off, const void *vaddr, int size,
>> + bool flow_control)
>> +{
>> + struct desc_info *desc;
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct scatterlist *sgl;
>> + struct dma_slave_config slave_conf;
>> + struct qcom_adm_peripheral_config periph_conf = {};
>> + enum dma_transfer_direction dir_eng;
>> + int ret;
>
> Revertse-christmas-tree, please
Ok
>
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + sgl = &desc->adm_sgl;
>> +
>> + sg_init_one(sgl, vaddr, size);
>> +
>> + if (read) {
>> + dir_eng = DMA_DEV_TO_MEM;
>> + desc->dir = DMA_FROM_DEVICE;
>> + } else {
>> + dir_eng = DMA_MEM_TO_DEV;
>> + desc->dir = DMA_TO_DEVICE;
>> + }
>> +
>> + ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
>> + if (ret == 0) {
>
> if (!ret)
Ok
>
>> + ret = -ENOMEM;
>> + goto err;
>> + }
>> +
>> + memset(&slave_conf, 0x00, sizeof(slave_conf));
>
> Just zero-initialize it (= { 0 }) at declaration time
Ok
>
> Konrad
>
Thanks for reviewing , I will fix all the comments in next patch.
Regards,
Alam.
On 2/16/2024 12:32 AM, Krzysztof Kozlowski wrote:
> On 15/02/2024 14:48, Md Sadre Alam wrote:
>> Add device-tree binding documentation for QCOM QPIC-SNAND-NAND Flash
>> Interface.
>>
>
> A nit, subject: drop second/last, redundant "bindings". The
> "dt-bindings" prefix is already stating that these are bindings.
> See also:
> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
Ok
>
>> Co-developed-by: Sricharan Ramabadhran <[email protected]>
>> Signed-off-by: Sricharan Ramabadhran <[email protected]>
>> Co-developed-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Md Sadre Alam <[email protected]>
>> ---
>> .../bindings/spi/qcom,spi-qpic-snand.yaml | 82 +++++++++++++++++++
>> 1 file changed, 82 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>> new file mode 100644
>> index 000000000000..fa7484ce1319
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
>
> Filename like compatible.
Ok
>
>> @@ -0,0 +1,82 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QPIC NAND controller
>> +
>> +maintainers:
>> + - Md sadre Alam <[email protected]>
>> +
>
> Provide description which will describe hardware.
Ok
>
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,ipq9574-snand
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 2
>> + maxItems: 3
>
> You must document the items (could be sufficient in clock-names if the
> names are obvious).
Ok
>
>
> Why the clocks are flexible? This given IPQ9574 has variable clock
> inputs? Please explain.
I have checked Hardware Spec. and clocks are fixed in IPQ9574. Will fix in next
patch.
>
>> +
>> + clock-names:
>> + minItems: 2
>> + maxItems: 3
>> +
>
> required goes here.
Ok
>
>> +allOf:
>> + - $ref: /schemas/spi/spi-controller.yaml#
>
>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,ipq9574-snand
>> +
>> + then:
>> + properties:
>> + dmas:
>> + items:
>> + - description: tx DMA channel
>> + - description: rx DMA channel
>> + - description: cmd DMA channel
>> +
>> + dma-names:
>> + items:
>> + - const: tx
>> + - const: rx
>> + - const: cmd
>
> No clue why it is here, move it to top level.
Ok
>
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
>> + qpic_nand: spi@79b0000 {
>
> Drop unused label
Ok
>
>> + compatible = "qcom,ipq9574-snand";
>> + reg = <0x1ac00000 0x800>;
>> +
>> + clocks = <&gcc GCC_QPIC_CLK>,
>> + <&gcc GCC_QPIC_AHB_CLK>,
>> + <&gcc GCC_QPIC_IO_MACRO_CLK>;
>> + clock-names = "core", "aon", "iom";
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + flash@0 {
>> + compatible = "spi-nand";
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + nand-ecc-engine = <&qpic_nand>;
>> + nand-ecc-strength = <4>;
>> + nand-ecc-step-size = <512>;
>> + };
>
> Fix indentation.
Ok
>
>> + };
>
> Best regards,
> Krzysztof
>
On 2/16/2024 8:59 PM, Kathiravan Thirumoorthy wrote:
>
>
> On 2/15/2024 7:18 PM, Md Sadre Alam wrote:
>> Add qpic_common.c file which hold all the common
>> qpic APIs which will be used by both qpic raw nand
>> driver and qpic spi nand driver.
>>
>> Co-developed-by: Sricharan Ramabadhran <[email protected]>
>> Signed-off-by: Sricharan Ramabadhran <[email protected]>
>> Co-developed-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Md Sadre Alam <[email protected]>
>> ---
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
>> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
>> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
>> 4 files changed, 1291 insertions(+), 1210 deletions(-)
>> create mode 100644 drivers/mtd/nand/qpic_common.c
>> create mode 100644 include/linux/mtd/nand-qpic-common.h
>>
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index 19e1291ac4d5..131707a41293 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
>> +obj-y += qpic_common.o
>> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
>> new file mode 100644
>> index 000000000000..4d74ba888028
>> --- /dev/null
>> +++ b/drivers/mtd/nand/qpic_common.c
>> @@ -0,0 +1,786 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * QPIC Controller common API file.
>> + * Copyright (C) 2023 Qualcomm Inc.
>
>
> Copyright should be repharsed?
Will fix in next patch.
>
>> + * Authors: Md sadre Alam <[email protected]>
>> + * Sricharan R <[email protected]>
>> + * Varadarajan Narayanan <[email protected]>
>> + *
>> + */
>> +
>> +#include <linux/mtd/nand-qpic-common.h>
>> +
>> +struct qcom_nand_controller *
>> +get_qcom_nand_controller(struct nand_chip *chip)
>> +{
>> + return container_of(chip->controller, struct qcom_nand_controller,
>> + controller);
>> +}
>> +EXPORT_SYMBOL(get_qcom_nand_controller);
>> +
>> +/*
>> + * Helper to prepare DMA descriptors for configuring registers
>> + * before reading a NAND page.
>> + */
>> +void config_nand_page_read(struct nand_chip *chip)
>> +{
>> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +
>> + write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> + write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> + if (!nandc->props->qpic_v2)
>> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> +}
>> +EXPORT_SYMBOL(config_nand_page_read);
>> +
>> +/* Frees the BAM transaction memory */
>> +void free_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> + struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> + devm_kfree(nandc->dev, bam_txn);
>> +}
>> +EXPORT_SYMBOL(free_bam_transaction);
>> +
>> +/* Callback for DMA descriptor completion */
>> +void qpic_bam_dma_done(void *data)
>> +{
>> + struct bam_transaction *bam_txn = data;
>> +
>> + /*
>> + * In case of data transfer with NAND, 2 callbacks will be generated.
>> + * One for command channel and another one for data channel.
>> + * If current transaction has data descriptors
>> + * (i.e. wait_second_completion is true), then set this to false
>> + * and wait for second DMA descriptor completion.
>> + */
>> + if (bam_txn->wait_second_completion)
>> + bam_txn->wait_second_completion = false;
>> + else
>> + complete(&bam_txn->txn_done);
>> +}
>> +EXPORT_SYMBOL(qpic_bam_dma_done);
>> +
>> +void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
>> + bool is_cpu)
>> +{
>> + if (!nandc->props->is_bam)
>> + return;
>> +
>> + if (is_cpu)
>> + dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
>> + MAX_REG_RD *
>> + sizeof(*nandc->reg_read_buf),
>> + DMA_FROM_DEVICE);
>> + else
>> + dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
>> + MAX_REG_RD *
>> + sizeof(*nandc->reg_read_buf),
>> + DMA_FROM_DEVICE);
>> +}
>> +EXPORT_SYMBOL(nandc_read_buffer_sync);
>> +
>> +__le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
>> +{
>> + switch (offset) {
>> + case NAND_FLASH_CMD:
>> + return ®s->cmd;
>> + case NAND_ADDR0:
>> + return ®s->addr0;
>> + case NAND_ADDR1:
>> + return ®s->addr1;
>> + case NAND_FLASH_CHIP_SELECT:
>> + return ®s->chip_sel;
>> + case NAND_EXEC_CMD:
>> + return ®s->exec;
>> + case NAND_FLASH_STATUS:
>> + return ®s->clrflashstatus;
>> + case NAND_DEV0_CFG0:
>> + return ®s->cfg0;
>> + case NAND_DEV0_CFG1:
>> + return ®s->cfg1;
>> + case NAND_DEV0_ECC_CFG:
>> + return ®s->ecc_bch_cfg;
>> + case NAND_READ_STATUS:
>> + return ®s->clrreadstatus;
>> + case NAND_DEV_CMD1:
>> + return ®s->cmd1;
>> + case NAND_DEV_CMD1_RESTORE:
>> + return ®s->orig_cmd1;
>> + case NAND_DEV_CMD_VLD:
>> + return ®s->vld;
>> + case NAND_DEV_CMD_VLD_RESTORE:
>> + return ®s->orig_vld;
>> + case NAND_EBI2_ECC_BUF_CFG:
>> + return ®s->ecc_buf_cfg;
>> + case NAND_READ_LOCATION_0:
>> + return ®s->read_location0;
>> + case NAND_READ_LOCATION_1:
>> + return ®s->read_location1;
>> + case NAND_READ_LOCATION_2:
>> + return ®s->read_location2;
>> + case NAND_READ_LOCATION_3:
>> + return ®s->read_location3;
>> + case NAND_READ_LOCATION_LAST_CW_0:
>> + return ®s->read_location_last0;
>> + case NAND_READ_LOCATION_LAST_CW_1:
>> + return ®s->read_location_last1;
>> + case NAND_READ_LOCATION_LAST_CW_2:
>> + return ®s->read_location_last2;
>> + case NAND_READ_LOCATION_LAST_CW_3:
>> + return ®s->read_location_last3;
>> + default:
>> + return NULL;
>> + }
>> +}
>> +EXPORT_SYMBOL(offset_to_nandc_reg);
>> +
>> +/* reset the register read buffer for next NAND operation */
>> +void clear_read_regs(struct qcom_nand_controller *nandc)
>> +{
>> + nandc->reg_read_pos = 0;
>> + nandc_read_buffer_sync(nandc, false);
>> +}
>> +EXPORT_SYMBOL(clear_read_regs);
>> +
>> +int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
>> + int reg_off, const void *vaddr, int size,
>> + bool flow_control)
>> +{
>> + struct desc_info *desc;
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct scatterlist *sgl;
>> + struct dma_slave_config slave_conf;
>> + struct qcom_adm_peripheral_config periph_conf = {};
>> + enum dma_transfer_direction dir_eng;
>> + int ret;
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + sgl = &desc->adm_sgl;
>> +
>> + sg_init_one(sgl, vaddr, size);
>> +
>> + if (read) {
>> + dir_eng = DMA_DEV_TO_MEM;
>> + desc->dir = DMA_FROM_DEVICE;
>> + } else {
>> + dir_eng = DMA_MEM_TO_DEV;
>> + desc->dir = DMA_TO_DEVICE;
>> + }
>> +
>> + ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
>> + if (ret == 0) {
>> + ret = -ENOMEM;
>> + goto err;
>> + }
>> +
>> + memset(&slave_conf, 0x00, sizeof(slave_conf));
>> +
>> + slave_conf.device_fc = flow_control;
>> + if (read) {
>> + slave_conf.src_maxburst = 16;
>> + slave_conf.src_addr = nandc->base_dma + reg_off;
>> + if (nandc->data_crci) {
>> + periph_conf.crci = nandc->data_crci;
>> + slave_conf.peripheral_config = &periph_conf;
>> + slave_conf.peripheral_size = sizeof(periph_conf);
>> + }
>> + } else {
>> + slave_conf.dst_maxburst = 16;
>> + slave_conf.dst_addr = nandc->base_dma + reg_off;
>> + if (nandc->cmd_crci) {
>> + periph_conf.crci = nandc->cmd_crci;
>> + slave_conf.peripheral_config = &periph_conf;
>> + slave_conf.peripheral_size = sizeof(periph_conf);
>> + }
>> + }
>> +
>> + ret = dmaengine_slave_config(nandc->chan, &slave_conf);
>> + if (ret) {
>> + dev_err(nandc->dev, "failed to configure dma channel\n");
>> + goto err;
>> + }
>> +
>> + dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
>> + if (!dma_desc) {
>> + dev_err(nandc->dev, "failed to prepare desc\n");
>> + ret = -EINVAL;
>> + goto err;
>> + }
>> +
>> + desc->dma_desc = dma_desc;
>> +
>> + list_add_tail(&desc->node, &nandc->desc_list);
>> +
>> + return 0;
>> +err:
>> + kfree(desc);
>> +
>> + return ret;
>> +}
>> +EXPORT_SYMBOL(prep_adm_dma_desc);
>> +
>> +/* helpers to submit/free our list of dma descriptors */
>> +int submit_descs(struct qcom_nand_controller *nandc)
>> +{
>> + struct desc_info *desc, *n;
>> + dma_cookie_t cookie = 0;
>> + struct bam_transaction *bam_txn = nandc->bam_txn;
>> + int ret = 0;
>> +
>> + if (nandc->props->is_bam) {
>> + if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
>> + ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
>> + if (ret)
>> + goto err_unmap_free_desc;
>> + }
>> +
>> + if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
>> + ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> + DMA_PREP_INTERRUPT);
>> + if (ret)
>> + goto err_unmap_free_desc;
>> + }
>> +
>> + if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
>> + ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> + DMA_PREP_CMD);
>> + if (ret)
>> + goto err_unmap_free_desc;
>> + }
>> + }
>> +
>> + list_for_each_entry(desc, &nandc->desc_list, node)
>> + cookie = dmaengine_submit(desc->dma_desc);
>> +
>> + if (nandc->props->is_bam) {
>> + bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
>> + bam_txn->last_cmd_desc->callback_param = bam_txn;
>> + if (bam_txn->last_data_desc) {
>> + bam_txn->last_data_desc->callback = qpic_bam_dma_done;
>> + bam_txn->last_data_desc->callback_param = bam_txn;
>> + bam_txn->wait_second_completion = true;
>> + }
>> +
>> + dma_async_issue_pending(nandc->tx_chan);
>> + dma_async_issue_pending(nandc->rx_chan);
>> + dma_async_issue_pending(nandc->cmd_chan);
>> +
>> + if (!wait_for_completion_timeout(&bam_txn->txn_done,
>> + QPIC_NAND_COMPLETION_TIMEOUT))
>> + ret = -ETIMEDOUT;
>> + } else {
>> + if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
>> + ret = -ETIMEDOUT;
>> + }
>> +
>> +err_unmap_free_desc:
>> + /*
>> + * Unmap the dma sg_list and free the desc allocated by both
>> + * prepare_bam_async_desc() and prep_adm_dma_desc() functions.
>> + */
>> + list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
>> + list_del(&desc->node);
>> +
>> + if (nandc->props->is_bam)
>> + dma_unmap_sg(nandc->dev, desc->bam_sgl,
>> + desc->sgl_cnt, desc->dir);
>> + else
>> + dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
>> + desc->dir);
>> +
>> + kfree(desc);
>> + }
>> +
>> + return ret;
>> +}
>> +EXPORT_SYMBOL(submit_descs);
>> +
>> +/*
>> + * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
>> + * for BAM. This descriptor will be added in the NAND DMA descriptor queue
>> + * which will be submitted to DMA engine.
>> + */
>> +int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>> + struct dma_chan *chan,
>> + unsigned long flags)
>> +{
>> + struct desc_info *desc;
>> + struct scatterlist *sgl;
>> + unsigned int sgl_cnt;
>> + int ret;
>> + struct bam_transaction *bam_txn = nandc->bam_txn;
>> + enum dma_transfer_direction dir_eng;
>> + struct dma_async_tx_descriptor *dma_desc;
>> +
>> + desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> + if (!desc)
>> + return -ENOMEM;
>> +
>> + if (chan == nandc->cmd_chan) {
>> + sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
>> + sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
>> + bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
>> + dir_eng = DMA_MEM_TO_DEV;
>> + desc->dir = DMA_TO_DEVICE;
>> + } else if (chan == nandc->tx_chan) {
>> + sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
>> + sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
>> + bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
>> + dir_eng = DMA_MEM_TO_DEV;
>> + desc->dir = DMA_TO_DEVICE;
>> + } else {
>> + sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
>> + sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
>> + bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
>> + dir_eng = DMA_DEV_TO_MEM;
>> + desc->dir = DMA_FROM_DEVICE;
>> + }
>> +
>> + sg_mark_end(sgl + sgl_cnt - 1);
>> + ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
>> + if (ret == 0) {
>> + dev_err(nandc->dev, "failure in mapping desc\n");
>> + kfree(desc);
>> + return -ENOMEM;
>> + }
>> +
>> + desc->sgl_cnt = sgl_cnt;
>> + desc->bam_sgl = sgl;
>> +
>> + dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
>> + flags);
>> +
>> + if (!dma_desc) {
>> + dev_err(nandc->dev, "failure in prep desc\n");
>> + dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
>> + kfree(desc);
>> + return -EINVAL;
>> + }
>> +
>> + desc->dma_desc = dma_desc;
>> +
>> + /* update last data/command descriptor */
>> + if (chan == nandc->cmd_chan)
>> + bam_txn->last_cmd_desc = dma_desc;
>> + else
>> + bam_txn->last_data_desc = dma_desc;
>> +
>> + list_add_tail(&desc->node, &nandc->desc_list);
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(prepare_bam_async_desc);
>> +
>> +/*
>> + * Prepares the command descriptor for BAM DMA which will be used for NAND
>> + * register reads and writes. The command descriptor requires the command
>> + * to be formed in command element type so this function uses the command
>> + * element from bam transaction ce array and fills the same with required
>> + * data. A single SGL can contain multiple command elements so
>> + * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
>> + * after the current command element.
>> + */
>> +int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
>> + int reg_off, const void *vaddr,
>> + int size, unsigned int flags)
>> +{
>> + int bam_ce_size;
>> + int i, ret;
>> + struct bam_cmd_element *bam_ce_buffer;
>> + struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> + bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
>> +
>> + /* fill the command desc */
>> + for (i = 0; i < size; i++) {
>> + if (read)
>> + bam_prep_ce(&bam_ce_buffer[i],
>> + nandc_reg_phys(nandc, reg_off + 4 * i),
>> + BAM_READ_COMMAND,
>> + reg_buf_dma_addr(nandc,
>> + (__le32 *)vaddr + i));
>> + else
>> + bam_prep_ce_le32(&bam_ce_buffer[i],
>> + nandc_reg_phys(nandc, reg_off + 4 * i),
>> + BAM_WRITE_COMMAND,
>> + *((__le32 *)vaddr + i));
>> + }
>> +
>> + bam_txn->bam_ce_pos += size;
>> +
>> + /* use the separate sgl after this command */
>> + if (flags & NAND_BAM_NEXT_SGL) {
>> + bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
>> + bam_ce_size = (bam_txn->bam_ce_pos -
>> + bam_txn->bam_ce_start) *
>> + sizeof(struct bam_cmd_element);
>> + sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
>> + bam_ce_buffer, bam_ce_size);
>> + bam_txn->cmd_sgl_pos++;
>> + bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
>> +
>> + if (flags & NAND_BAM_NWD) {
>> + ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> + DMA_PREP_FENCE |
>> + DMA_PREP_CMD);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(prep_bam_dma_desc_cmd);
>> +
>> +/*
>> + * Prepares the data descriptor for BAM DMA which will be used for NAND
>> + * data reads and writes.
>> + */
>> +int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
>> + const void *vaddr,
>> + int size, unsigned int flags)
>> +{
>> + int ret;
>> + struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> + if (read) {
>> + sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
>> + vaddr, size);
>> + bam_txn->rx_sgl_pos++;
>> + } else {
>> + sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
>> + vaddr, size);
>> + bam_txn->tx_sgl_pos++;
>> +
>> + /*
>> + * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
>> + * is not set, form the DMA descriptor
>> + */
>> + if (!(flags & NAND_BAM_NO_EOT)) {
>> + ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> + DMA_PREP_INTERRUPT);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(prep_bam_dma_desc_data);
>> +
>> +/*
>> + * read_reg_dma: prepares a descriptor to read a given number of
>> + * contiguous registers to the reg_read_buf pointer
>> + *
>> + * @first: offset of the first register in the contiguous block
>> + * @num_regs: number of registers to read
>> + * @flags: flags to control DMA descriptor preparation
>> + */
>> +int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>> + int num_regs, unsigned int flags)
>> +{
>> + bool flow_control = false;
>> + void *vaddr;
>> +
>> + vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>> + nandc->reg_read_pos += num_regs;
>> +
>> + if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
>> + first = dev_cmd_reg_addr(nandc, first);
>> +
>> + if (nandc->props->is_bam)
>> + return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
>> + num_regs, flags);
>> +
>> + if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>> + flow_control = true;
>> +
>> + return prep_adm_dma_desc(nandc, true, first, vaddr,
>> + num_regs * sizeof(u32), flow_control);
>> +}
>> +EXPORT_SYMBOL(read_reg_dma);
>> +
>> +/*
>> + * write_reg_dma: prepares a descriptor to write a given number of
>> + * contiguous registers
>> + *
>> + * @first: offset of the first register in the contiguous block
>> + * @num_regs: number of registers to write
>> + * @flags: flags to control DMA descriptor preparation
>> + */
>> +int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>> + int num_regs, unsigned int flags)
>> +{
>> + bool flow_control = false;
>> + struct nandc_regs *regs = nandc->regs;
>> + void *vaddr;
>> +
>> + vaddr = offset_to_nandc_reg(regs, first);
>> +
>> + if (first == NAND_ERASED_CW_DETECT_CFG) {
>> + if (flags & NAND_ERASED_CW_SET)
>> + vaddr = ®s->erased_cw_detect_cfg_set;
>> + else
>> + vaddr = ®s->erased_cw_detect_cfg_clr;
>> + }
>> +
>> + if (first == NAND_EXEC_CMD)
>> + flags |= NAND_BAM_NWD;
>> +
>> + if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
>> + first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
>> +
>> + if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
>> + first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
>> +
>> + if (nandc->props->is_bam)
>> + return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
>> + num_regs, flags);
>> +
>> + if (first == NAND_FLASH_CMD)
>> + flow_control = true;
>> +
>> + return prep_adm_dma_desc(nandc, false, first, vaddr,
>> + num_regs * sizeof(u32), flow_control);
>> +}
>> +EXPORT_SYMBOL(write_reg_dma);
>> +
>> +/*
>> + * read_data_dma: prepares a DMA descriptor to transfer data from the
>> + * controller's internal buffer to the buffer 'vaddr'
>> + *
>> + * @reg_off: offset within the controller's data buffer
>> + * @vaddr: virtual address of the buffer we want to write to
>> + * @size: DMA transaction size in bytes
>> + * @flags: flags to control DMA descriptor preparation
>> + */
>> +int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>> + const u8 *vaddr, int size, unsigned int flags)
>> +{
>> + if (nandc->props->is_bam)
>> + return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
>> +
>> + return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
>> +}
>> +EXPORT_SYMBOL(read_data_dma);
>> +
>> +/*
>> + * write_data_dma: prepares a DMA descriptor to transfer data from
>> + * 'vaddr' to the controller's internal buffer
>> + *
>> + * @reg_off: offset within the controller's data buffer
>> + * @vaddr: virtual address of the buffer we want to read from
>> + * @size: DMA transaction size in bytes
>> + * @flags: flags to control DMA descriptor preparation
>> + */
>> +int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>> + const u8 *vaddr, int size, unsigned int flags)
>> +{
>> + if (nandc->props->is_bam)
>> + return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
>> +
>> + return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
>> +}
>> +EXPORT_SYMBOL(write_data_dma);
>> +
>> +/* Allocates and Initializes the BAM transaction */
>> +struct bam_transaction *
>> +alloc_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> + struct bam_transaction *bam_txn;
>> + size_t bam_txn_size;
>> + unsigned int num_cw = nandc->max_cwperpage;
>> + void *bam_txn_buf;
>> +
>> + bam_txn_size =
>> + sizeof(*bam_txn) + num_cw *
>> + ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
>> + (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
>> + (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
>> +
>> + bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
>> + if (!bam_txn_buf)
>> + return NULL;
>> +
>> + bam_txn = bam_txn_buf;
>> + bam_txn_buf += sizeof(*bam_txn);
>> +
>> + bam_txn->bam_ce = bam_txn_buf;
>> + bam_txn_buf +=
>> + sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
>> +
>> + bam_txn->cmd_sgl = bam_txn_buf;
>> + bam_txn_buf +=
>> + sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
>> +
>> + bam_txn->data_sgl = bam_txn_buf;
>> +
>> + init_completion(&bam_txn->txn_done);
>> +
>> + return bam_txn;
>> +}
>> +EXPORT_SYMBOL(alloc_bam_transaction);
>> +
>> +/* Clears the BAM transaction indexes */
>> +void clear_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> + struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> + if (!nandc->props->is_bam)
>> + return;
>> +
>> + bam_txn->bam_ce_pos = 0;
>> + bam_txn->bam_ce_start = 0;
>> + bam_txn->cmd_sgl_pos = 0;
>> + bam_txn->cmd_sgl_start = 0;
>> + bam_txn->tx_sgl_pos = 0;
>> + bam_txn->tx_sgl_start = 0;
>> + bam_txn->rx_sgl_pos = 0;
>> + bam_txn->rx_sgl_start = 0;
>> + bam_txn->last_data_desc = NULL;
>> + bam_txn->wait_second_completion = false;
>> +
>> + sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
>> + QPIC_PER_CW_CMD_SGL);
>> + sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
>> + QPIC_PER_CW_DATA_SGL);
>> +
>> + reinit_completion(&bam_txn->txn_done);
>> +}
>> +EXPORT_SYMBOL(clear_bam_transaction);
>> +
>> +void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>> +{
>> + if (nandc->props->is_bam) {
>> + if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
>> + dma_unmap_single(nandc->dev, nandc->reg_read_dma,
>> + MAX_REG_RD *
>> + sizeof(*nandc->reg_read_buf),
>> + DMA_FROM_DEVICE);
>> +
>> + if (nandc->tx_chan)
>> + dma_release_channel(nandc->tx_chan);
>> +
>> + if (nandc->rx_chan)
>> + dma_release_channel(nandc->rx_chan);
>> +
>> + if (nandc->cmd_chan)
>> + dma_release_channel(nandc->cmd_chan);
>> + } else {
>> + if (nandc->chan)
>> + dma_release_channel(nandc->chan);
>> + }
>> +}
>> +EXPORT_SYMBOL(qcom_nandc_unalloc);
>> +
>> +int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>> +{
>> + int ret;
>> +
>> + ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
>> + if (ret) {
>> + dev_err(nandc->dev, "failed to set DMA mask\n");
>> + return ret;
>> + }
>> +
>> + /*
>> + * we use the internal buffer for reading ONFI params, reading small
>> + * data like ID and status, and preforming read-copy-write operations
>> + * when writing to a codeword partially. 532 is the maximum possible
>> + * size of a codeword for our nand controller
>> + */
>> + nandc->buf_size = 532;
>> +
>> + nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
>> + if (!nandc->data_buffer)
>> + return -ENOMEM;
>> +
>> + nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
>> + if (!nandc->regs)
>> + return -ENOMEM;
>> +
>> + nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
>> + sizeof(*nandc->reg_read_buf),
>> + GFP_KERNEL);
>> + if (!nandc->reg_read_buf)
>> + return -ENOMEM;
>> +
>> + if (nandc->props->is_bam) {
>> + nandc->reg_read_dma =
>> + dma_map_single(nandc->dev, nandc->reg_read_buf,
>> + MAX_REG_RD *
>> + sizeof(*nandc->reg_read_buf),
>> + DMA_FROM_DEVICE);
>> + if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
>> + dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
>> + return -EIO;
>> + }
>> +
>> + nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
>> + if (IS_ERR(nandc->tx_chan)) {
>> + ret = PTR_ERR(nandc->tx_chan);
>> + nandc->tx_chan = NULL;
>> + dev_err_probe(nandc->dev, ret,
>> + "tx DMA channel request failed\n");
>> + goto unalloc;
>> + }
>> +
>> + nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
>> + if (IS_ERR(nandc->rx_chan)) {
>> + ret = PTR_ERR(nandc->rx_chan);
>> + nandc->rx_chan = NULL;
>> + dev_err_probe(nandc->dev, ret,
>> + "rx DMA channel request failed\n");
>> + goto unalloc;
>> + }
>> +
>> + nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
>> + if (IS_ERR(nandc->cmd_chan)) {
>> + ret = PTR_ERR(nandc->cmd_chan);
>> + nandc->cmd_chan = NULL;
>> + dev_err_probe(nandc->dev, ret,
>> + "cmd DMA channel request failed\n");
>> + goto unalloc;
>> + }
>> +
>> + /*
>> + * Initially allocate BAM transaction to read ONFI param page.
>> + * After detecting all the devices, this BAM transaction will
>> + * be freed and the next BAM transaction will be allocated with
>> + * maximum codeword size
>> + */
>> + nandc->max_cwperpage = 1;
>> + nandc->bam_txn = alloc_bam_transaction(nandc);
>> + if (!nandc->bam_txn) {
>> + dev_err(nandc->dev,
>> + "failed to allocate bam transaction\n");
>> + ret = -ENOMEM;
>> + goto unalloc;
>> + }
>> + } else {
>> + nandc->chan = dma_request_chan(nandc->dev, "rxtx");
>> + if (IS_ERR(nandc->chan)) {
>> + ret = PTR_ERR(nandc->chan);
>> + nandc->chan = NULL;
>> + dev_err_probe(nandc->dev, ret,
>> + "rxtx DMA channel request failed\n");
>> + return ret;
>> + }
>> + }
>> +
>> + INIT_LIST_HEAD(&nandc->desc_list);
>> + INIT_LIST_HEAD(&nandc->host_list);
>> +
>> + return 0;
>> +unalloc:
>> + qcom_nandc_unalloc(nandc);
>> + return ret;
>> +}
>> +EXPORT_SYMBOL(qcom_nandc_alloc);
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
>> index b079605c84d3..75c6ca698c85 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -2,186 +2,7 @@
>> /*
>> * Copyright (c) 2016, The Linux Foundation. All rights reserved.
>> */
>> -#include <linux/bitops.h>
>> -#include <linux/clk.h>
>> -#include <linux/delay.h>
>> -#include <linux/dmaengine.h>
>> -#include <linux/dma-mapping.h>
>> -#include <linux/dma/qcom_adm.h>
>> -#include <linux/dma/qcom_bam_dma.h>
>> -#include <linux/module.h>
>> -#include <linux/mtd/partitions.h>
>> -#include <linux/mtd/rawnand.h>
>> -#include <linux/of.h>
>> -#include <linux/platform_device.h>
>> -#include <linux/slab.h>
>> -
>> -/* NANDc reg offsets */
>> -#define NAND_FLASH_CMD 0x00
>> -#define NAND_ADDR0 0x04
>> -#define NAND_ADDR1 0x08
>> -#define NAND_FLASH_CHIP_SELECT 0x0c
>> -#define NAND_EXEC_CMD 0x10
>> -#define NAND_FLASH_STATUS 0x14
>> -#define NAND_BUFFER_STATUS 0x18
>> -#define NAND_DEV0_CFG0 0x20
>> -#define NAND_DEV0_CFG1 0x24
>> -#define NAND_DEV0_ECC_CFG 0x28
>> -#define NAND_AUTO_STATUS_EN 0x2c
>> -#define NAND_DEV1_CFG0 0x30
>> -#define NAND_DEV1_CFG1 0x34
>> -#define NAND_READ_ID 0x40
>> -#define NAND_READ_STATUS 0x44
>> -#define NAND_DEV_CMD0 0xa0
>> -#define NAND_DEV_CMD1 0xa4
>> -#define NAND_DEV_CMD2 0xa8
>> -#define NAND_DEV_CMD_VLD 0xac
>> -#define SFLASHC_BURST_CFG 0xe0
>> -#define NAND_ERASED_CW_DETECT_CFG 0xe8
>> -#define NAND_ERASED_CW_DETECT_STATUS 0xec
>> -#define NAND_EBI2_ECC_BUF_CFG 0xf0
>> -#define FLASH_BUF_ACC 0x100
>> -
>> -#define NAND_CTRL 0xf00
>> -#define NAND_VERSION 0xf08
>> -#define NAND_READ_LOCATION_0 0xf20
>> -#define NAND_READ_LOCATION_1 0xf24
>> -#define NAND_READ_LOCATION_2 0xf28
>> -#define NAND_READ_LOCATION_3 0xf2c
>> -#define NAND_READ_LOCATION_LAST_CW_0 0xf40
>> -#define NAND_READ_LOCATION_LAST_CW_1 0xf44
>> -#define NAND_READ_LOCATION_LAST_CW_2 0xf48
>> -#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
>> -
>> -/* dummy register offsets, used by write_reg_dma */
>> -#define NAND_DEV_CMD1_RESTORE 0xdead
>> -#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
>> -
>> -/* NAND_FLASH_CMD bits */
>> -#define PAGE_ACC BIT(4)
>> -#define LAST_PAGE BIT(5)
>> -
>> -/* NAND_FLASH_CHIP_SELECT bits */
>> -#define NAND_DEV_SEL 0
>> -#define DM_EN BIT(2)
>> -
>> -/* NAND_FLASH_STATUS bits */
>> -#define FS_OP_ERR BIT(4)
>> -#define FS_READY_BSY_N BIT(5)
>> -#define FS_MPU_ERR BIT(8)
>> -#define FS_DEVICE_STS_ERR BIT(16)
>> -#define FS_DEVICE_WP BIT(23)
>> -
>> -/* NAND_BUFFER_STATUS bits */
>> -#define BS_UNCORRECTABLE_BIT BIT(8)
>> -#define BS_CORRECTABLE_ERR_MSK 0x1f
>> -
>> -/* NAND_DEVn_CFG0 bits */
>> -#define DISABLE_STATUS_AFTER_WRITE 4
>> -#define CW_PER_PAGE 6
>> -#define UD_SIZE_BYTES 9
>> -#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
>> -#define ECC_PARITY_SIZE_BYTES_RS 19
>> -#define SPARE_SIZE_BYTES 23
>> -#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
>> -#define NUM_ADDR_CYCLES 27
>> -#define STATUS_BFR_READ 30
>> -#define SET_RD_MODE_AFTER_STATUS 31
>> -
>> -/* NAND_DEVn_CFG0 bits */
>> -#define DEV0_CFG1_ECC_DISABLE 0
>> -#define WIDE_FLASH 1
>> -#define NAND_RECOVERY_CYCLES 2
>> -#define CS_ACTIVE_BSY 5
>> -#define BAD_BLOCK_BYTE_NUM 6
>> -#define BAD_BLOCK_IN_SPARE_AREA 16
>> -#define WR_RD_BSY_GAP 17
>> -#define ENABLE_BCH_ECC 27
>> -
>> -/* NAND_DEV0_ECC_CFG bits */
>> -#define ECC_CFG_ECC_DISABLE 0
>> -#define ECC_SW_RESET 1
>> -#define ECC_MODE 4
>> -#define ECC_PARITY_SIZE_BYTES_BCH 8
>> -#define ECC_NUM_DATA_BYTES 16
>> -#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
>> -#define ECC_FORCE_CLK_OPEN 30
>> -
>> -/* NAND_DEV_CMD1 bits */
>> -#define READ_ADDR 0
>> -
>> -/* NAND_DEV_CMD_VLD bits */
>> -#define READ_START_VLD BIT(0)
>> -#define READ_STOP_VLD BIT(1)
>> -#define WRITE_START_VLD BIT(2)
>> -#define ERASE_START_VLD BIT(3)
>> -#define SEQ_READ_START_VLD BIT(4)
>> -
>> -/* NAND_EBI2_ECC_BUF_CFG bits */
>> -#define NUM_STEPS 0
>> -
>> -/* NAND_ERASED_CW_DETECT_CFG bits */
>> -#define ERASED_CW_ECC_MASK 1
>> -#define AUTO_DETECT_RES 0
>> -#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
>> -#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
>> -#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
>> -#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
>> -#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
>> -
>> -/* NAND_ERASED_CW_DETECT_STATUS bits */
>> -#define PAGE_ALL_ERASED BIT(7)
>> -#define CODEWORD_ALL_ERASED BIT(6)
>> -#define PAGE_ERASED BIT(5)
>> -#define CODEWORD_ERASED BIT(4)
>> -#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
>> -#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
>> -
>> -/* NAND_READ_LOCATION_n bits */
>> -#define READ_LOCATION_OFFSET 0
>> -#define READ_LOCATION_SIZE 16
>> -#define READ_LOCATION_LAST 31
>> -
>> -/* Version Mask */
>> -#define NAND_VERSION_MAJOR_MASK 0xf0000000
>> -#define NAND_VERSION_MAJOR_SHIFT 28
>> -#define NAND_VERSION_MINOR_MASK 0x0fff0000
>> -#define NAND_VERSION_MINOR_SHIFT 16
>> -
>> -/* NAND OP_CMDs */
>> -#define OP_PAGE_READ 0x2
>> -#define OP_PAGE_READ_WITH_ECC 0x3
>> -#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
>> -#define OP_PAGE_READ_ONFI_READ 0x5
>> -#define OP_PROGRAM_PAGE 0x6
>> -#define OP_PAGE_PROGRAM_WITH_ECC 0x7
>> -#define OP_PROGRAM_PAGE_SPARE 0x9
>> -#define OP_BLOCK_ERASE 0xa
>> -#define OP_CHECK_STATUS 0xc
>> -#define OP_FETCH_ID 0xb
>> -#define OP_RESET_DEVICE 0xd
>> -
>> -/* Default Value for NAND_DEV_CMD_VLD */
>> -#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
>> - ERASE_START_VLD | SEQ_READ_START_VLD)
>> -
>> -/* NAND_CTRL bits */
>> -#define BAM_MODE_EN BIT(0)
>> -
>> -/*
>> - * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>> - * the driver calls the chunks 'step' or 'codeword' interchangeably
>> - */
>> -#define NANDC_STEP_SIZE 512
>> -
>> -/*
>> - * the largest page size we support is 8K, this will have 16 steps/codewords
>> - * of 512 bytes each
>> - */
>> -#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
>> -
>> -/* we read at most 3 registers per codeword scan */
>> -#define MAX_REG_RD (3 * MAX_NUM_STEPS)
>> +#include <linux/mtd/nand-qpic-common.h>
>> /* ECC modes supported by the controller */
>> #define ECC_NONE BIT(0)
>> @@ -200,247 +21,6 @@ nandc_set_reg(chip, reg, \
>> ((cw_offset) << READ_LOCATION_OFFSET) | \
>> ((read_size) << READ_LOCATION_SIZE) | \
>> ((is_last_read_loc) << READ_LOCATION_LAST))
>> -/*
>> - * Returns the actual register address for all NAND_DEV_ registers
>> - * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
>> - */
>> -#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
>> -
>> -/* Returns the NAND register physical address */
>> -#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
>> -
>> -/* Returns the dma address for reg read buffer */
>> -#define reg_buf_dma_addr(chip, vaddr) \
>> - ((chip)->reg_read_dma + \
>> - ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
>> -
>> -#define QPIC_PER_CW_CMD_ELEMENTS 32
>> -#define QPIC_PER_CW_CMD_SGL 32
>> -#define QPIC_PER_CW_DATA_SGL 8
>> -
>> -#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
>> -
>> -/*
>> - * Flags used in DMA descriptor preparation helper functions
>> - * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
>> - */
>> -/* Don't set the EOT in current tx BAM sgl */
>> -#define NAND_BAM_NO_EOT BIT(0)
>> -/* Set the NWD flag in current BAM sgl */
>> -#define NAND_BAM_NWD BIT(1)
>> -/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
>> -#define NAND_BAM_NEXT_SGL BIT(2)
>> -/*
>> - * Erased codeword status is being used two times in single transfer so this
>> - * flag will determine the current value of erased codeword status register
>> - */
>> -#define NAND_ERASED_CW_SET BIT(4)
>> -
>> -#define MAX_ADDRESS_CYCLE 5
>> -
>> -/*
>> - * This data type corresponds to the BAM transaction which will be used for all
>> - * NAND transfers.
>> - * @bam_ce - the array of BAM command elements
>> - * @cmd_sgl - sgl for NAND BAM command pipe
>> - * @data_sgl - sgl for NAND BAM consumer/producer pipe
>> - * @last_data_desc - last DMA desc in data channel (tx/rx).
>> - * @last_cmd_desc - last DMA desc in command channel.
>> - * @txn_done - completion for NAND transfer.
>> - * @bam_ce_pos - the index in bam_ce which is available for next sgl
>> - * @bam_ce_start - the index in bam_ce which marks the start position ce
>> - * for current sgl. It will be used for size calculation
>> - * for current sgl
>> - * @cmd_sgl_pos - current index in command sgl.
>> - * @cmd_sgl_start - start index in command sgl.
>> - * @tx_sgl_pos - current index in data sgl for tx.
>> - * @tx_sgl_start - start index in data sgl for tx.
>> - * @rx_sgl_pos - current index in data sgl for rx.
>> - * @rx_sgl_start - start index in data sgl for rx.
>> - * @wait_second_completion - wait for second DMA desc completion before making
>> - * the NAND transfer completion.
>> - */
>> -struct bam_transaction {
>> - struct bam_cmd_element *bam_ce;
>> - struct scatterlist *cmd_sgl;
>> - struct scatterlist *data_sgl;
>> - struct dma_async_tx_descriptor *last_data_desc;
>> - struct dma_async_tx_descriptor *last_cmd_desc;
>> - struct completion txn_done;
>> - u32 bam_ce_pos;
>> - u32 bam_ce_start;
>> - u32 cmd_sgl_pos;
>> - u32 cmd_sgl_start;
>> - u32 tx_sgl_pos;
>> - u32 tx_sgl_start;
>> - u32 rx_sgl_pos;
>> - u32 rx_sgl_start;
>> - bool wait_second_completion;
>> -};
>> -
>> -/*
>> - * This data type corresponds to the nand dma descriptor
>> - * @dma_desc - low level DMA engine descriptor
>> - * @list - list for desc_info
>> - *
>> - * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
>> - * ADM
>> - * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
>> - * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
>> - * @dir - DMA transfer direction
>> - */
>> -struct desc_info {
>> - struct dma_async_tx_descriptor *dma_desc;
>> - struct list_head node;
>> -
>> - union {
>> - struct scatterlist adm_sgl;
>> - struct {
>> - struct scatterlist *bam_sgl;
>> - int sgl_cnt;
>> - };
>> - };
>> - enum dma_data_direction dir;
>> -};
>> -
>> -/*
>> - * holds the current register values that we want to write. acts as a contiguous
>> - * chunk of memory which we use to write the controller registers through DMA.
>> - */
>> -struct nandc_regs {
>> - __le32 cmd;
>> - __le32 addr0;
>> - __le32 addr1;
>> - __le32 chip_sel;
>> - __le32 exec;
>> -
>> - __le32 cfg0;
>> - __le32 cfg1;
>> - __le32 ecc_bch_cfg;
>> -
>> - __le32 clrflashstatus;
>> - __le32 clrreadstatus;
>> -
>> - __le32 cmd1;
>> - __le32 vld;
>> -
>> - __le32 orig_cmd1;
>> - __le32 orig_vld;
>> -
>> - __le32 ecc_buf_cfg;
>> - __le32 read_location0;
>> - __le32 read_location1;
>> - __le32 read_location2;
>> - __le32 read_location3;
>> - __le32 read_location_last0;
>> - __le32 read_location_last1;
>> - __le32 read_location_last2;
>> - __le32 read_location_last3;
>> -
>> - __le32 erased_cw_detect_cfg_clr;
>> - __le32 erased_cw_detect_cfg_set;
>> -};
>> -
>> -/*
>> - * NAND controller data struct
>> - *
>> - * @dev: parent device
>> - *
>> - * @base: MMIO base
>> - *
>> - * @core_clk: controller clock
>> - * @aon_clk: another controller clock
>> - *
>> - * @regs: a contiguous chunk of memory for DMA register
>> - * writes. contains the register values to be
>> - * written to controller
>> - *
>> - * @props: properties of current NAND controller,
>> - * initialized via DT match data
>> - *
>> - * @controller: base controller structure
>> - * @host_list: list containing all the chips attached to the
>> - * controller
>> - *
>> - * @chan: dma channel
>> - * @cmd_crci: ADM DMA CRCI for command flow control
>> - * @data_crci: ADM DMA CRCI for data flow control
>> - *
>> - * @desc_list: DMA descriptor list (list of desc_infos)
>> - *
>> - * @data_buffer: our local DMA buffer for page read/writes,
>> - * used when we can't use the buffer provided
>> - * by upper layers directly
>> - * @reg_read_buf: local buffer for reading back registers via DMA
>> - *
>> - * @base_phys: physical base address of controller registers
>> - * @base_dma: dma base address of controller registers
>> - * @reg_read_dma: contains dma address for register read buffer
>> - *
>> - * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
>> - * functions
>> - * @max_cwperpage: maximum QPIC codewords required. calculated
>> - * from all connected NAND devices pagesize
>> - *
>> - * @reg_read_pos: marker for data read in reg_read_buf
>> - *
>> - * @cmd1/vld: some fixed controller register values
>> - *
>> - * @exec_opwrite: flag to select correct number of code word
>> - * while reading status
>> - */
>> -struct qcom_nand_controller {
>> - struct device *dev;
>> -
>> - void __iomem *base;
>> -
>> - struct clk *core_clk;
>> - struct clk *aon_clk;
>> -
>> - struct nandc_regs *regs;
>> - struct bam_transaction *bam_txn;
>> -
>> - const struct qcom_nandc_props *props;
>> -
>> - struct nand_controller controller;
>> - struct list_head host_list;
>> -
>> - union {
>> - /* will be used only by QPIC for BAM DMA */
>> - struct {
>> - struct dma_chan *tx_chan;
>> - struct dma_chan *rx_chan;
>> - struct dma_chan *cmd_chan;
>> - };
>> -
>> - /* will be used only by EBI2 for ADM DMA */
>> - struct {
>> - struct dma_chan *chan;
>> - unsigned int cmd_crci;
>> - unsigned int data_crci;
>> - };
>> - };
>> -
>> - struct list_head desc_list;
>> -
>> - u8 *data_buffer;
>> - __le32 *reg_read_buf;
>> -
>> - phys_addr_t base_phys;
>> - dma_addr_t base_dma;
>> - dma_addr_t reg_read_dma;
>> -
>> - int buf_size;
>> - int buf_count;
>> - int buf_start;
>> - unsigned int max_cwperpage;
>> -
>> - int reg_read_pos;
>> -
>> - u32 cmd1, vld;
>> - bool exec_opwrite;
>> -};
>> -
>> /*
>> * NAND special boot partitions
>> *
>> @@ -544,113 +124,17 @@ struct qcom_nand_host {
>> bool bch_enabled;
>> };
>> -/*
>> - * This data type corresponds to the NAND controller properties which varies
>> - * among different NAND controllers.
>> - * @ecc_modes - ecc mode for NAND
>> - * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
>> - * @is_bam - whether NAND controller is using BAM
>> - * @is_qpic - whether NAND CTRL is part of qpic IP
>> - * @qpic_v2 - flag to indicate QPIC IP version 2
>> - * @use_codeword_fixup - whether NAND has different layout for boot partitions
>> - */
>> -struct qcom_nandc_props {
>> - u32 ecc_modes;
>> - u32 dev_cmd_reg_start;
>> - bool is_bam;
>> - bool is_qpic;
>> - bool qpic_v2;
>> - bool use_codeword_fixup;
>> -};
>> -
>> -/* Frees the BAM transaction memory */
>> -static void free_bam_transaction(struct qcom_nand_controller *nandc)
>> -{
>> - struct bam_transaction *bam_txn = nandc->bam_txn;
>> -
>> - devm_kfree(nandc->dev, bam_txn);
>> -}
>> -
>> -/* Allocates and Initializes the BAM transaction */
>> -static struct bam_transaction *
>> -alloc_bam_transaction(struct qcom_nand_controller *nandc)
>> -{
>> - struct bam_transaction *bam_txn;
>> - size_t bam_txn_size;
>> - unsigned int num_cw = nandc->max_cwperpage;
>> - void *bam_txn_buf;
>> -
>> - bam_txn_size =
>> - sizeof(*bam_txn) + num_cw *
>> - ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
>> - (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
>> - (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
>> -
>> - bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
>> - if (!bam_txn_buf)
>> - return NULL;
>> -
>> - bam_txn = bam_txn_buf;
>> - bam_txn_buf += sizeof(*bam_txn);
>> -
>> - bam_txn->bam_ce = bam_txn_buf;
>> - bam_txn_buf +=
>> - sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
>> -
>> - bam_txn->cmd_sgl = bam_txn_buf;
>> - bam_txn_buf +=
>> - sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
>> -
>> - bam_txn->data_sgl = bam_txn_buf;
>> -
>> - init_completion(&bam_txn->txn_done);
>> -
>> - return bam_txn;
>> -}
>> -
>> -/* Clears the BAM transaction indexes */
>> -static void clear_bam_transaction(struct qcom_nand_controller *nandc)
>> +static void nandc_set_reg(struct nand_chip *chip, int offset,
>> + u32 val)
>> {
>> - struct bam_transaction *bam_txn = nandc->bam_txn;
>> -
>> - if (!nandc->props->is_bam)
>> - return;
>> -
>> - bam_txn->bam_ce_pos = 0;
>> - bam_txn->bam_ce_start = 0;
>> - bam_txn->cmd_sgl_pos = 0;
>> - bam_txn->cmd_sgl_start = 0;
>> - bam_txn->tx_sgl_pos = 0;
>> - bam_txn->tx_sgl_start = 0;
>> - bam_txn->rx_sgl_pos = 0;
>> - bam_txn->rx_sgl_start = 0;
>> - bam_txn->last_data_desc = NULL;
>> - bam_txn->wait_second_completion = false;
>> -
>> - sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage *
>> - QPIC_PER_CW_CMD_SGL);
>> - sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage *
>> - QPIC_PER_CW_DATA_SGL);
>> -
>> - reinit_completion(&bam_txn->txn_done);
>> -}
>> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> + struct nandc_regs *regs = nandc->regs;
>> + __le32 *reg;
>> -/* Callback for DMA descriptor completion */
>> -static void qpic_bam_dma_done(void *data)
>> -{
>> - struct bam_transaction *bam_txn = data;
>> + reg = offset_to_nandc_reg(regs, offset);
>> - /*
>> - * In case of data transfer with NAND, 2 callbacks will be generated.
>> - * One for command channel and another one for data channel.
>> - * If current transaction has data descriptors
>> - * (i.e. wait_second_completion is true), then set this to false
>> - * and wait for second DMA descriptor completion.
>> - */
>> - if (bam_txn->wait_second_completion)
>> - bam_txn->wait_second_completion = false;
>> - else
>> - complete(&bam_txn->txn_done);
>> + if (reg)
>> + *reg = cpu_to_le32(val);
>> }
>> static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>> @@ -658,13 +142,6 @@ static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
>> return container_of(chip, struct qcom_nand_host, chip);
>> }
>> -static inline struct qcom_nand_controller *
>> -get_qcom_nand_controller(struct nand_chip *chip)
>> -{
>> - return container_of(chip->controller, struct qcom_nand_controller,
>> - controller);
>> -}
>> -
>> static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset)
>> {
>> return ioread32(nandc->base + offset);
>> @@ -676,91 +153,6 @@ static inline void nandc_write(struct qcom_nand_controller *nandc, int offset,
>> iowrite32(val, nandc->base + offset);
>> }
>> -static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc,
>> - bool is_cpu)
>> -{
>> - if (!nandc->props->is_bam)
>> - return;
>> -
>> - if (is_cpu)
>> - dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma,
>> - MAX_REG_RD *
>> - sizeof(*nandc->reg_read_buf),
>> - DMA_FROM_DEVICE);
>> - else
>> - dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma,
>> - MAX_REG_RD *
>> - sizeof(*nandc->reg_read_buf),
>> - DMA_FROM_DEVICE);
>> -}
>> -
>> -static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
>> -{
>> - switch (offset) {
>> - case NAND_FLASH_CMD:
>> - return ®s->cmd;
>> - case NAND_ADDR0:
>> - return ®s->addr0;
>> - case NAND_ADDR1:
>> - return ®s->addr1;
>> - case NAND_FLASH_CHIP_SELECT:
>> - return ®s->chip_sel;
>> - case NAND_EXEC_CMD:
>> - return ®s->exec;
>> - case NAND_FLASH_STATUS:
>> - return ®s->clrflashstatus;
>> - case NAND_DEV0_CFG0:
>> - return ®s->cfg0;
>> - case NAND_DEV0_CFG1:
>> - return ®s->cfg1;
>> - case NAND_DEV0_ECC_CFG:
>> - return ®s->ecc_bch_cfg;
>> - case NAND_READ_STATUS:
>> - return ®s->clrreadstatus;
>> - case NAND_DEV_CMD1:
>> - return ®s->cmd1;
>> - case NAND_DEV_CMD1_RESTORE:
>> - return ®s->orig_cmd1;
>> - case NAND_DEV_CMD_VLD:
>> - return ®s->vld;
>> - case NAND_DEV_CMD_VLD_RESTORE:
>> - return ®s->orig_vld;
>> - case NAND_EBI2_ECC_BUF_CFG:
>> - return ®s->ecc_buf_cfg;
>> - case NAND_READ_LOCATION_0:
>> - return ®s->read_location0;
>> - case NAND_READ_LOCATION_1:
>> - return ®s->read_location1;
>> - case NAND_READ_LOCATION_2:
>> - return ®s->read_location2;
>> - case NAND_READ_LOCATION_3:
>> - return ®s->read_location3;
>> - case NAND_READ_LOCATION_LAST_CW_0:
>> - return ®s->read_location_last0;
>> - case NAND_READ_LOCATION_LAST_CW_1:
>> - return ®s->read_location_last1;
>> - case NAND_READ_LOCATION_LAST_CW_2:
>> - return ®s->read_location_last2;
>> - case NAND_READ_LOCATION_LAST_CW_3:
>> - return ®s->read_location_last3;
>> - default:
>> - return NULL;
>> - }
>> -}
>> -
>> -static void nandc_set_reg(struct nand_chip *chip, int offset,
>> - u32 val)
>> -{
>> - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> - struct nandc_regs *regs = nandc->regs;
>> - __le32 *reg;
>> -
>> - reg = offset_to_nandc_reg(regs, offset);
>> -
>> - if (reg)
>> - *reg = cpu_to_le32(val);
>> -}
>> -
>> /* Helper to check the code word, whether it is last cw or not */
>> static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
>> {
>> @@ -852,383 +244,6 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
>> host->cw_data : host->cw_size, 1);
>> }
>> -/*
>> - * Maps the scatter gather list for DMA transfer and forms the DMA descriptor
>> - * for BAM. This descriptor will be added in the NAND DMA descriptor queue
>> - * which will be submitted to DMA engine.
>> - */
>> -static int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>> - struct dma_chan *chan,
>> - unsigned long flags)
>> -{
>> - struct desc_info *desc;
>> - struct scatterlist *sgl;
>> - unsigned int sgl_cnt;
>> - int ret;
>> - struct bam_transaction *bam_txn = nandc->bam_txn;
>> - enum dma_transfer_direction dir_eng;
>> - struct dma_async_tx_descriptor *dma_desc;
>> -
>> - desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> - if (!desc)
>> - return -ENOMEM;
>> -
>> - if (chan == nandc->cmd_chan) {
>> - sgl = &bam_txn->cmd_sgl[bam_txn->cmd_sgl_start];
>> - sgl_cnt = bam_txn->cmd_sgl_pos - bam_txn->cmd_sgl_start;
>> - bam_txn->cmd_sgl_start = bam_txn->cmd_sgl_pos;
>> - dir_eng = DMA_MEM_TO_DEV;
>> - desc->dir = DMA_TO_DEVICE;
>> - } else if (chan == nandc->tx_chan) {
>> - sgl = &bam_txn->data_sgl[bam_txn->tx_sgl_start];
>> - sgl_cnt = bam_txn->tx_sgl_pos - bam_txn->tx_sgl_start;
>> - bam_txn->tx_sgl_start = bam_txn->tx_sgl_pos;
>> - dir_eng = DMA_MEM_TO_DEV;
>> - desc->dir = DMA_TO_DEVICE;
>> - } else {
>> - sgl = &bam_txn->data_sgl[bam_txn->rx_sgl_start];
>> - sgl_cnt = bam_txn->rx_sgl_pos - bam_txn->rx_sgl_start;
>> - bam_txn->rx_sgl_start = bam_txn->rx_sgl_pos;
>> - dir_eng = DMA_DEV_TO_MEM;
>> - desc->dir = DMA_FROM_DEVICE;
>> - }
>> -
>> - sg_mark_end(sgl + sgl_cnt - 1);
>> - ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
>> - if (ret == 0) {
>> - dev_err(nandc->dev, "failure in mapping desc\n");
>> - kfree(desc);
>> - return -ENOMEM;
>> - }
>> -
>> - desc->sgl_cnt = sgl_cnt;
>> - desc->bam_sgl = sgl;
>> -
>> - dma_desc = dmaengine_prep_slave_sg(chan, sgl, sgl_cnt, dir_eng,
>> - flags);
>> -
>> - if (!dma_desc) {
>> - dev_err(nandc->dev, "failure in prep desc\n");
>> - dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir);
>> - kfree(desc);
>> - return -EINVAL;
>> - }
>> -
>> - desc->dma_desc = dma_desc;
>> -
>> - /* update last data/command descriptor */
>> - if (chan == nandc->cmd_chan)
>> - bam_txn->last_cmd_desc = dma_desc;
>> - else
>> - bam_txn->last_data_desc = dma_desc;
>> -
>> - list_add_tail(&desc->node, &nandc->desc_list);
>> -
>> - return 0;
>> -}
>> -
>> -/*
>> - * Prepares the command descriptor for BAM DMA which will be used for NAND
>> - * register reads and writes. The command descriptor requires the command
>> - * to be formed in command element type so this function uses the command
>> - * element from bam transaction ce array and fills the same with required
>> - * data. A single SGL can contain multiple command elements so
>> - * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
>> - * after the current command element.
>> - */
>> -static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
>> - int reg_off, const void *vaddr,
>> - int size, unsigned int flags)
>> -{
>> - int bam_ce_size;
>> - int i, ret;
>> - struct bam_cmd_element *bam_ce_buffer;
>> - struct bam_transaction *bam_txn = nandc->bam_txn;
>> -
>> - bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
>> -
>> - /* fill the command desc */
>> - for (i = 0; i < size; i++) {
>> - if (read)
>> - bam_prep_ce(&bam_ce_buffer[i],
>> - nandc_reg_phys(nandc, reg_off + 4 * i),
>> - BAM_READ_COMMAND,
>> - reg_buf_dma_addr(nandc,
>> - (__le32 *)vaddr + i));
>> - else
>> - bam_prep_ce_le32(&bam_ce_buffer[i],
>> - nandc_reg_phys(nandc, reg_off + 4 * i),
>> - BAM_WRITE_COMMAND,
>> - *((__le32 *)vaddr + i));
>> - }
>> -
>> - bam_txn->bam_ce_pos += size;
>> -
>> - /* use the separate sgl after this command */
>> - if (flags & NAND_BAM_NEXT_SGL) {
>> - bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
>> - bam_ce_size = (bam_txn->bam_ce_pos -
>> - bam_txn->bam_ce_start) *
>> - sizeof(struct bam_cmd_element);
>> - sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
>> - bam_ce_buffer, bam_ce_size);
>> - bam_txn->cmd_sgl_pos++;
>> - bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
>> -
>> - if (flags & NAND_BAM_NWD) {
>> - ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> - DMA_PREP_FENCE |
>> - DMA_PREP_CMD);
>> - if (ret)
>> - return ret;
>> - }
>> - }
>> -
>> - return 0;
>> -}
>> -
>> -/*
>> - * Prepares the data descriptor for BAM DMA which will be used for NAND
>> - * data reads and writes.
>> - */
>> -static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
>> - const void *vaddr,
>> - int size, unsigned int flags)
>> -{
>> - int ret;
>> - struct bam_transaction *bam_txn = nandc->bam_txn;
>> -
>> - if (read) {
>> - sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
>> - vaddr, size);
>> - bam_txn->rx_sgl_pos++;
>> - } else {
>> - sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
>> - vaddr, size);
>> - bam_txn->tx_sgl_pos++;
>> -
>> - /*
>> - * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
>> - * is not set, form the DMA descriptor
>> - */
>> - if (!(flags & NAND_BAM_NO_EOT)) {
>> - ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> - DMA_PREP_INTERRUPT);
>> - if (ret)
>> - return ret;
>> - }
>> - }
>> -
>> - return 0;
>> -}
>> -
>> -static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
>> - int reg_off, const void *vaddr, int size,
>> - bool flow_control)
>> -{
>> - struct desc_info *desc;
>> - struct dma_async_tx_descriptor *dma_desc;
>> - struct scatterlist *sgl;
>> - struct dma_slave_config slave_conf;
>> - struct qcom_adm_peripheral_config periph_conf = {};
>> - enum dma_transfer_direction dir_eng;
>> - int ret;
>> -
>> - desc = kzalloc(sizeof(*desc), GFP_KERNEL);
>> - if (!desc)
>> - return -ENOMEM;
>> -
>> - sgl = &desc->adm_sgl;
>> -
>> - sg_init_one(sgl, vaddr, size);
>> -
>> - if (read) {
>> - dir_eng = DMA_DEV_TO_MEM;
>> - desc->dir = DMA_FROM_DEVICE;
>> - } else {
>> - dir_eng = DMA_MEM_TO_DEV;
>> - desc->dir = DMA_TO_DEVICE;
>> - }
>> -
>> - ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir);
>> - if (ret == 0) {
>> - ret = -ENOMEM;
>> - goto err;
>> - }
>> -
>> - memset(&slave_conf, 0x00, sizeof(slave_conf));
>> -
>> - slave_conf.device_fc = flow_control;
>> - if (read) {
>> - slave_conf.src_maxburst = 16;
>> - slave_conf.src_addr = nandc->base_dma + reg_off;
>> - if (nandc->data_crci) {
>> - periph_conf.crci = nandc->data_crci;
>> - slave_conf.peripheral_config = &periph_conf;
>> - slave_conf.peripheral_size = sizeof(periph_conf);
>> - }
>> - } else {
>> - slave_conf.dst_maxburst = 16;
>> - slave_conf.dst_addr = nandc->base_dma + reg_off;
>> - if (nandc->cmd_crci) {
>> - periph_conf.crci = nandc->cmd_crci;
>> - slave_conf.peripheral_config = &periph_conf;
>> - slave_conf.peripheral_size = sizeof(periph_conf);
>> - }
>> - }
>> -
>> - ret = dmaengine_slave_config(nandc->chan, &slave_conf);
>> - if (ret) {
>> - dev_err(nandc->dev, "failed to configure dma channel\n");
>> - goto err;
>> - }
>> -
>> - dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0);
>> - if (!dma_desc) {
>> - dev_err(nandc->dev, "failed to prepare desc\n");
>> - ret = -EINVAL;
>> - goto err;
>> - }
>> -
>> - desc->dma_desc = dma_desc;
>> -
>> - list_add_tail(&desc->node, &nandc->desc_list);
>> -
>> - return 0;
>> -err:
>> - kfree(desc);
>> -
>> - return ret;
>> -}
>> -
>> -/*
>> - * read_reg_dma: prepares a descriptor to read a given number of
>> - * contiguous registers to the reg_read_buf pointer
>> - *
>> - * @first: offset of the first register in the contiguous block
>> - * @num_regs: number of registers to read
>> - * @flags: flags to control DMA descriptor preparation
>> - */
>> -static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>> - int num_regs, unsigned int flags)
>> -{
>> - bool flow_control = false;
>> - void *vaddr;
>> -
>> - vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
>> - nandc->reg_read_pos += num_regs;
>> -
>> - if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
>> - first = dev_cmd_reg_addr(nandc, first);
>> -
>> - if (nandc->props->is_bam)
>> - return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
>> - num_regs, flags);
>> -
>> - if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
>> - flow_control = true;
>> -
>> - return prep_adm_dma_desc(nandc, true, first, vaddr,
>> - num_regs * sizeof(u32), flow_control);
>> -}
>> -
>> -/*
>> - * write_reg_dma: prepares a descriptor to write a given number of
>> - * contiguous registers
>> - *
>> - * @first: offset of the first register in the contiguous block
>> - * @num_regs: number of registers to write
>> - * @flags: flags to control DMA descriptor preparation
>> - */
>> -static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>> - int num_regs, unsigned int flags)
>> -{
>> - bool flow_control = false;
>> - struct nandc_regs *regs = nandc->regs;
>> - void *vaddr;
>> -
>> - vaddr = offset_to_nandc_reg(regs, first);
>> -
>> - if (first == NAND_ERASED_CW_DETECT_CFG) {
>> - if (flags & NAND_ERASED_CW_SET)
>> - vaddr = ®s->erased_cw_detect_cfg_set;
>> - else
>> - vaddr = ®s->erased_cw_detect_cfg_clr;
>> - }
>> -
>> - if (first == NAND_EXEC_CMD)
>> - flags |= NAND_BAM_NWD;
>> -
>> - if (first == NAND_DEV_CMD1_RESTORE || first == NAND_DEV_CMD1)
>> - first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1);
>> -
>> - if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
>> - first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
>> -
>> - if (nandc->props->is_bam)
>> - return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
>> - num_regs, flags);
>> -
>> - if (first == NAND_FLASH_CMD)
>> - flow_control = true;
>> -
>> - return prep_adm_dma_desc(nandc, false, first, vaddr,
>> - num_regs * sizeof(u32), flow_control);
>> -}
>> -
>> -/*
>> - * read_data_dma: prepares a DMA descriptor to transfer data from the
>> - * controller's internal buffer to the buffer 'vaddr'
>> - *
>> - * @reg_off: offset within the controller's data buffer
>> - * @vaddr: virtual address of the buffer we want to write to
>> - * @size: DMA transaction size in bytes
>> - * @flags: flags to control DMA descriptor preparation
>> - */
>> -static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>> - const u8 *vaddr, int size, unsigned int flags)
>> -{
>> - if (nandc->props->is_bam)
>> - return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags);
>> -
>> - return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false);
>> -}
>> -
>> -/*
>> - * write_data_dma: prepares a DMA descriptor to transfer data from
>> - * 'vaddr' to the controller's internal buffer
>> - *
>> - * @reg_off: offset within the controller's data buffer
>> - * @vaddr: virtual address of the buffer we want to read from
>> - * @size: DMA transaction size in bytes
>> - * @flags: flags to control DMA descriptor preparation
>> - */
>> -static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>> - const u8 *vaddr, int size, unsigned int flags)
>> -{
>> - if (nandc->props->is_bam)
>> - return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags);
>> -
>> - return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false);
>> -}
>> -
>> -/*
>> - * Helper to prepare DMA descriptors for configuring registers
>> - * before reading a NAND page.
>> - */
>> -static void config_nand_page_read(struct nand_chip *chip)
>> -{
>> - struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> -
>> - write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> - write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> - if (!nandc->props->qpic_v2)
>> - write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> - write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> - write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> - NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> -}
>> -
>> /*
>> * Helper to prepare DMA descriptors for configuring registers
>> * before reading each codeword in NAND page.
>> @@ -1303,88 +318,6 @@ static void config_nand_cw_write(struct nand_chip *chip)
>> write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL);
>> }
>> -/* helpers to submit/free our list of dma descriptors */
>> -static int submit_descs(struct qcom_nand_controller *nandc)
>> -{
>> - struct desc_info *desc, *n;
>> - dma_cookie_t cookie = 0;
>> - struct bam_transaction *bam_txn = nandc->bam_txn;
>> - int ret = 0;
>> -
>> - if (nandc->props->is_bam) {
>> - if (bam_txn->rx_sgl_pos > bam_txn->rx_sgl_start) {
>> - ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0);
>> - if (ret)
>> - goto err_unmap_free_desc;
>> - }
>> -
>> - if (bam_txn->tx_sgl_pos > bam_txn->tx_sgl_start) {
>> - ret = prepare_bam_async_desc(nandc, nandc->tx_chan,
>> - DMA_PREP_INTERRUPT);
>> - if (ret)
>> - goto err_unmap_free_desc;
>> - }
>> -
>> - if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
>> - ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
>> - DMA_PREP_CMD);
>> - if (ret)
>> - goto err_unmap_free_desc;
>> - }
>> - }
>> -
>> - list_for_each_entry(desc, &nandc->desc_list, node)
>> - cookie = dmaengine_submit(desc->dma_desc);
>> -
>> - if (nandc->props->is_bam) {
>> - bam_txn->last_cmd_desc->callback = qpic_bam_dma_done;
>> - bam_txn->last_cmd_desc->callback_param = bam_txn;
>> - if (bam_txn->last_data_desc) {
>> - bam_txn->last_data_desc->callback = qpic_bam_dma_done;
>> - bam_txn->last_data_desc->callback_param = bam_txn;
>> - bam_txn->wait_second_completion = true;
>> - }
>> -
>> - dma_async_issue_pending(nandc->tx_chan);
>> - dma_async_issue_pending(nandc->rx_chan);
>> - dma_async_issue_pending(nandc->cmd_chan);
>> -
>> - if (!wait_for_completion_timeout(&bam_txn->txn_done,
>> - QPIC_NAND_COMPLETION_TIMEOUT))
>> - ret = -ETIMEDOUT;
>> - } else {
>> - if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE)
>> - ret = -ETIMEDOUT;
>> - }
>> -
>> -err_unmap_free_desc:
>> - /*
>> - * Unmap the dma sg_list and free the desc allocated by both
>> - * prepare_bam_async_desc() and prep_adm_dma_desc() functions.
>> - */
>> - list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
>> - list_del(&desc->node);
>> -
>> - if (nandc->props->is_bam)
>> - dma_unmap_sg(nandc->dev, desc->bam_sgl,
>> - desc->sgl_cnt, desc->dir);
>> - else
>> - dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1,
>> - desc->dir);
>> -
>> - kfree(desc);
>> - }
>> -
>> - return ret;
>> -}
>> -
>> -/* reset the register read buffer for next NAND operation */
>> -static void clear_read_regs(struct qcom_nand_controller *nandc)
>> -{
>> - nandc->reg_read_pos = 0;
>> - nandc_read_buffer_sync(nandc, false);
>> -}
>> -
>> /*
>> * when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
>> * an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
>> @@ -3016,136 +1949,6 @@ static const struct nand_controller_ops qcom_nandc_ops = {
>> .exec_op = qcom_nand_exec_op,
>> };
>> -static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
>> -{
>> - if (nandc->props->is_bam) {
>> - if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma))
>> - dma_unmap_single(nandc->dev, nandc->reg_read_dma,
>> - MAX_REG_RD *
>> - sizeof(*nandc->reg_read_buf),
>> - DMA_FROM_DEVICE);
>> -
>> - if (nandc->tx_chan)
>> - dma_release_channel(nandc->tx_chan);
>> -
>> - if (nandc->rx_chan)
>> - dma_release_channel(nandc->rx_chan);
>> -
>> - if (nandc->cmd_chan)
>> - dma_release_channel(nandc->cmd_chan);
>> - } else {
>> - if (nandc->chan)
>> - dma_release_channel(nandc->chan);
>> - }
>> -}
>> -
>> -static int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
>> -{
>> - int ret;
>> -
>> - ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32));
>> - if (ret) {
>> - dev_err(nandc->dev, "failed to set DMA mask\n");
>> - return ret;
>> - }
>> -
>> - /*
>> - * we use the internal buffer for reading ONFI params, reading small
>> - * data like ID and status, and preforming read-copy-write operations
>> - * when writing to a codeword partially. 532 is the maximum possible
>> - * size of a codeword for our nand controller
>> - */
>> - nandc->buf_size = 532;
>> -
>> - nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL);
>> - if (!nandc->data_buffer)
>> - return -ENOMEM;
>> -
>> - nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL);
>> - if (!nandc->regs)
>> - return -ENOMEM;
>> -
>> - nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD,
>> - sizeof(*nandc->reg_read_buf),
>> - GFP_KERNEL);
>> - if (!nandc->reg_read_buf)
>> - return -ENOMEM;
>> -
>> - if (nandc->props->is_bam) {
>> - nandc->reg_read_dma =
>> - dma_map_single(nandc->dev, nandc->reg_read_buf,
>> - MAX_REG_RD *
>> - sizeof(*nandc->reg_read_buf),
>> - DMA_FROM_DEVICE);
>> - if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) {
>> - dev_err(nandc->dev, "failed to DMA MAP reg buffer\n");
>> - return -EIO;
>> - }
>> -
>> - nandc->tx_chan = dma_request_chan(nandc->dev, "tx");
>> - if (IS_ERR(nandc->tx_chan)) {
>> - ret = PTR_ERR(nandc->tx_chan);
>> - nandc->tx_chan = NULL;
>> - dev_err_probe(nandc->dev, ret,
>> - "tx DMA channel request failed\n");
>> - goto unalloc;
>> - }
>> -
>> - nandc->rx_chan = dma_request_chan(nandc->dev, "rx");
>> - if (IS_ERR(nandc->rx_chan)) {
>> - ret = PTR_ERR(nandc->rx_chan);
>> - nandc->rx_chan = NULL;
>> - dev_err_probe(nandc->dev, ret,
>> - "rx DMA channel request failed\n");
>> - goto unalloc;
>> - }
>> -
>> - nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd");
>> - if (IS_ERR(nandc->cmd_chan)) {
>> - ret = PTR_ERR(nandc->cmd_chan);
>> - nandc->cmd_chan = NULL;
>> - dev_err_probe(nandc->dev, ret,
>> - "cmd DMA channel request failed\n");
>> - goto unalloc;
>> - }
>> -
>> - /*
>> - * Initially allocate BAM transaction to read ONFI param page.
>> - * After detecting all the devices, this BAM transaction will
>> - * be freed and the next BAM transaction will be allocated with
>> - * maximum codeword size
>> - */
>> - nandc->max_cwperpage = 1;
>> - nandc->bam_txn = alloc_bam_transaction(nandc);
>> - if (!nandc->bam_txn) {
>> - dev_err(nandc->dev,
>> - "failed to allocate bam transaction\n");
>> - ret = -ENOMEM;
>> - goto unalloc;
>> - }
>> - } else {
>> - nandc->chan = dma_request_chan(nandc->dev, "rxtx");
>> - if (IS_ERR(nandc->chan)) {
>> - ret = PTR_ERR(nandc->chan);
>> - nandc->chan = NULL;
>> - dev_err_probe(nandc->dev, ret,
>> - "rxtx DMA channel request failed\n");
>> - return ret;
>> - }
>> - }
>> -
>> - INIT_LIST_HEAD(&nandc->desc_list);
>> - INIT_LIST_HEAD(&nandc->host_list);
>> -
>> - nand_controller_init(&nandc->controller);
>> - nandc->controller.ops = &qcom_nandc_ops;
>> -
>> - return 0;
>> -unalloc:
>> - qcom_nandc_unalloc(nandc);
>> - return ret;
>> -}
>> -
>> /* one time setup of a few nand controller registers */
>> static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>> {
>> @@ -3427,6 +2230,9 @@ static int qcom_nandc_probe(struct platform_device *pdev)
>> if (ret)
>> goto err_nandc_alloc;
>> + nand_controller_init(&nandc->controller);
>> + nandc->controller.ops = &qcom_nandc_ops;
>> +
>> ret = qcom_nandc_setup(nandc);
>> if (ret)
>> goto err_setup;
>> @@ -3473,28 +2279,28 @@ static void qcom_nandc_remove(struct platform_device *pdev)
>> DMA_BIDIRECTIONAL, 0);
>> }
>> -static const struct qcom_nandc_props ipq806x_nandc_props = {
>> +static struct qcom_nandc_props ipq806x_nandc_props = {
>> .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
>> .is_bam = false,
>> .use_codeword_fixup = true,
>> .dev_cmd_reg_start = 0x0,
>> };
>> -static const struct qcom_nandc_props ipq4019_nandc_props = {
>> +static struct qcom_nandc_props ipq4019_nandc_props = {
>> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>> .is_bam = true,
>> .is_qpic = true,
>> .dev_cmd_reg_start = 0x0,
>> };
>> -static const struct qcom_nandc_props ipq8074_nandc_props = {
>> +static struct qcom_nandc_props ipq8074_nandc_props = {
>> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>> .is_bam = true,
>> .is_qpic = true,
>> .dev_cmd_reg_start = 0x7000,
>> };
>> -static const struct qcom_nandc_props sdx55_nandc_props = {
>> +static struct qcom_nandc_props sdx55_nandc_props = {
>> .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
>> .is_bam = true,
>> .is_qpic = true,
>> diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
>> new file mode 100644
>> index 000000000000..891f975ca173
>> --- /dev/null
>> +++ b/include/linux/mtd/nand-qpic-common.h
>> @@ -0,0 +1,488 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * QCOM QPIC common APIs header file
>> + *
>> + * Copyright (c) 2023 Qualcomm Inc.
>> + * Authors: Md sadre Alam <[email protected]>
>> + * Sricharan R <[email protected]>
>> + * Varadarajan Narayanan <[email protected]>
>> + *
>> + */
>> +#ifndef __MTD_NAND_QPIC_COMMON_H__
>> +#define __MTD_NAND_QPIC_COMMON_H__
>> +
>> +#include <linux/bitops.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/dmaengine.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/dma/qcom_adm.h>
>> +#include <linux/dma/qcom_bam_dma.h>
>> +#include <linux/module.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/mtd/rawnand.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +
>> +/* NANDc reg offsets */
>> +#define NAND_FLASH_CMD 0x00
>> +#define NAND_ADDR0 0x04
>> +#define NAND_ADDR1 0x08
>> +#define NAND_FLASH_CHIP_SELECT 0x0c
>> +#define NAND_EXEC_CMD 0x10
>> +#define NAND_FLASH_STATUS 0x14
>> +#define NAND_BUFFER_STATUS 0x18
>> +#define NAND_DEV0_CFG0 0x20
>> +#define NAND_DEV0_CFG1 0x24
>> +#define NAND_DEV0_ECC_CFG 0x28
>> +#define NAND_AUTO_STATUS_EN 0x2c
>> +#define NAND_DEV1_CFG0 0x30
>> +#define NAND_DEV1_CFG1 0x34
>> +#define NAND_READ_ID 0x40
>> +#define NAND_READ_STATUS 0x44
>> +#define NAND_DEV_CMD0 0xa0
>> +#define NAND_DEV_CMD1 0xa4
>> +#define NAND_DEV_CMD2 0xa8
>> +#define NAND_DEV_CMD_VLD 0xac
>> +#define SFLASHC_BURST_CFG 0xe0
>> +#define NAND_ERASED_CW_DETECT_CFG 0xe8
>> +#define NAND_ERASED_CW_DETECT_STATUS 0xec
>> +#define NAND_EBI2_ECC_BUF_CFG 0xf0
>> +#define FLASH_BUF_ACC 0x100
>> +
>> +#define NAND_CTRL 0xf00
>> +#define NAND_VERSION 0xf08
>> +#define NAND_READ_LOCATION_0 0xf20
>> +#define NAND_READ_LOCATION_1 0xf24
>> +#define NAND_READ_LOCATION_2 0xf28
>> +#define NAND_READ_LOCATION_3 0xf2c
>> +#define NAND_READ_LOCATION_LAST_CW_0 0xf40
>> +#define NAND_READ_LOCATION_LAST_CW_1 0xf44
>> +#define NAND_READ_LOCATION_LAST_CW_2 0xf48
>> +#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
>> +
>> +/* dummy register offsets, used by write_reg_dma */
>> +#define NAND_DEV_CMD1_RESTORE 0xdead
>> +#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
>> +
>> +/* NAND_FLASH_CMD bits */
>> +#define PAGE_ACC BIT(4)
>> +#define LAST_PAGE BIT(5)
>> +
>> +/* NAND_FLASH_CHIP_SELECT bits */
>> +#define NAND_DEV_SEL 0
>> +#define DM_EN BIT(2)
>> +
>> +/* NAND_FLASH_STATUS bits */
>> +#define FS_OP_ERR BIT(4)
>> +#define FS_READY_BSY_N BIT(5)
>> +#define FS_MPU_ERR BIT(8)
>> +#define FS_DEVICE_STS_ERR BIT(16)
>> +#define FS_DEVICE_WP BIT(23)
>> +
>> +/* NAND_BUFFER_STATUS bits */
>> +#define BS_UNCORRECTABLE_BIT BIT(8)
>> +#define BS_CORRECTABLE_ERR_MSK 0x1f
>> +
>> +/* NAND_DEVn_CFG0 bits */
>> +#define DISABLE_STATUS_AFTER_WRITE 4
>> +#define CW_PER_PAGE 6
>> +#define UD_SIZE_BYTES 9
>> +#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
>> +#define ECC_PARITY_SIZE_BYTES_RS 19
>> +#define SPARE_SIZE_BYTES 23
>> +#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
>> +#define NUM_ADDR_CYCLES 27
>> +#define STATUS_BFR_READ 30
>> +#define SET_RD_MODE_AFTER_STATUS 31
>> +
>> +/* NAND_DEVn_CFG0 bits */
>> +#define DEV0_CFG1_ECC_DISABLE 0
>> +#define WIDE_FLASH 1
>> +#define NAND_RECOVERY_CYCLES 2
>> +#define CS_ACTIVE_BSY 5
>> +#define BAD_BLOCK_BYTE_NUM 6
>> +#define BAD_BLOCK_IN_SPARE_AREA 16
>> +#define WR_RD_BSY_GAP 17
>> +#define ENABLE_BCH_ECC 27
>> +
>> +/* NAND_DEV0_ECC_CFG bits */
>> +#define ECC_CFG_ECC_DISABLE 0
>> +#define ECC_SW_RESET 1
>> +#define ECC_MODE 4
>> +#define ECC_PARITY_SIZE_BYTES_BCH 8
>> +#define ECC_NUM_DATA_BYTES 16
>> +#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
>> +#define ECC_FORCE_CLK_OPEN 30
>> +
>> +/* NAND_DEV_CMD1 bits */
>> +#define READ_ADDR 0
>> +
>> +/* NAND_DEV_CMD_VLD bits */
>> +#define READ_START_VLD BIT(0)
>> +#define READ_STOP_VLD BIT(1)
>> +#define WRITE_START_VLD BIT(2)
>> +#define ERASE_START_VLD BIT(3)
>> +#define SEQ_READ_START_VLD BIT(4)
>> +
>> +/* NAND_EBI2_ECC_BUF_CFG bits */
>> +#define NUM_STEPS 0
>> +
>> +/* NAND_ERASED_CW_DETECT_CFG bits */
>> +#define ERASED_CW_ECC_MASK 1
>> +#define AUTO_DETECT_RES 0
>> +#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
>> +#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
>> +#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
>> +#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
>> +#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
>> +
>> +/* NAND_ERASED_CW_DETECT_STATUS bits */
>> +#define PAGE_ALL_ERASED BIT(7)
>> +#define CODEWORD_ALL_ERASED BIT(6)
>> +#define PAGE_ERASED BIT(5)
>> +#define CODEWORD_ERASED BIT(4)
>> +#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
>> +#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
>> +
>> +/* NAND_READ_LOCATION_n bits */
>> +#define READ_LOCATION_OFFSET 0
>> +#define READ_LOCATION_SIZE 16
>> +#define READ_LOCATION_LAST 31
>> +
>> +/* Version Mask */
>> +#define NAND_VERSION_MAJOR_MASK 0xf0000000
>> +#define NAND_VERSION_MAJOR_SHIFT 28
>> +#define NAND_VERSION_MINOR_MASK 0x0fff0000
>> +#define NAND_VERSION_MINOR_SHIFT 16
>> +
>> +/* NAND OP_CMDs */
>> +#define OP_PAGE_READ 0x2
>> +#define OP_PAGE_READ_WITH_ECC 0x3
>> +#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
>> +#define OP_PAGE_READ_ONFI_READ 0x5
>> +#define OP_PROGRAM_PAGE 0x6
>> +#define OP_PAGE_PROGRAM_WITH_ECC 0x7
>> +#define OP_PROGRAM_PAGE_SPARE 0x9
>> +#define OP_BLOCK_ERASE 0xa
>> +#define OP_CHECK_STATUS 0xc
>> +#define OP_FETCH_ID 0xb
>> +#define OP_RESET_DEVICE 0xd
>> +
>> +/* Default Value for NAND_DEV_CMD_VLD */
>> +#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
>> + ERASE_START_VLD | SEQ_READ_START_VLD)
>> +
>> +/* NAND_CTRL bits */
>> +#define BAM_MODE_EN BIT(0)
>> +
>> +/*
>> + * the NAND controller performs reads/writes with ECC in 516 byte chunks.
>> + * the driver calls the chunks 'step' or 'codeword' interchangeably
>> + */
>> +#define NANDC_STEP_SIZE 512
>> +
>> +/*
>> + * the largest page size we support is 8K, this will have 16 steps/codewords
>> + * of 512 bytes each
>> + */
>> +#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
>> +
>> +/* we read at most 3 registers per codeword scan */
>> +#define MAX_REG_RD (3 * MAX_NUM_STEPS)
>> +
>> +#define QPIC_PER_CW_CMD_ELEMENTS 32
>> +#define QPIC_PER_CW_CMD_SGL 32
>> +#define QPIC_PER_CW_DATA_SGL 8
>> +
>> +#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
>> +
>> +/*
>> + * Flags used in DMA descriptor preparation helper functions
>> + * (i.e. read_reg_dma/write_reg_dma/read_data_dma/write_data_dma)
>> + */
>> +/* Don't set the EOT in current tx BAM sgl */
>> +#define NAND_BAM_NO_EOT BIT(0)
>> +/* Set the NWD flag in current BAM sgl */
>> +#define NAND_BAM_NWD BIT(1)
>> +/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
>> +#define NAND_BAM_NEXT_SGL BIT(2)
>> +
>> +/*
>> + * Returns the actual register address for all NAND_DEV_ registers
>> + * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
>> + */
>> +#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
>> +
>> +/* Returns the NAND register physical address */
>> +#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
>> +
>> +/* Returns the dma address for reg read buffer */
>> +#define reg_buf_dma_addr(chip, vaddr) \
>> + ((chip)->reg_read_dma + \
>> + ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
>> +
>> +/*
>> + * Erased codeword status is being used two times in single transfer so this
>> + * flag will determine the current value of erased codeword status register
>> + */
>> +#define NAND_ERASED_CW_SET BIT(4)
>> +
>> +#define MAX_ADDRESS_CYCLE 5
>> +
>> +/*
>> + * This data type corresponds to the BAM transaction which will be used for all
>> + * NAND transfers.
>> + * @bam_ce - the array of BAM command elements
>> + * @cmd_sgl - sgl for NAND BAM command pipe
>> + * @data_sgl - sgl for NAND BAM consumer/producer pipe
>> + * @last_data_desc - last DMA desc in data channel (tx/rx).
>> + * @last_cmd_desc - last DMA desc in command channel.
>> + * @txn_done - completion for NAND transfer.
>> + * @bam_ce_pos - the index in bam_ce which is available for next sgl
>> + * @bam_ce_start - the index in bam_ce which marks the start position ce
>> + * for current sgl. It will be used for size calculation
>> + * for current sgl
>> + * @cmd_sgl_pos - current index in command sgl.
>> + * @cmd_sgl_start - start index in command sgl.
>> + * @tx_sgl_pos - current index in data sgl for tx.
>> + * @tx_sgl_start - start index in data sgl for tx.
>> + * @rx_sgl_pos - current index in data sgl for rx.
>> + * @rx_sgl_start - start index in data sgl for rx.
>> + * @wait_second_completion - wait for second DMA desc completion before making
>> + * the NAND transfer completion.
>> + */
>> +struct bam_transaction {
>> + struct bam_cmd_element *bam_ce;
>> + struct scatterlist *cmd_sgl;
>> + struct scatterlist *data_sgl;
>> + struct dma_async_tx_descriptor *last_data_desc;
>> + struct dma_async_tx_descriptor *last_cmd_desc;
>> + struct completion txn_done;
>> + u32 bam_ce_pos;
>> + u32 bam_ce_start;
>> + u32 cmd_sgl_pos;
>> + u32 cmd_sgl_start;
>> + u32 tx_sgl_pos;
>> + u32 tx_sgl_start;
>> + u32 rx_sgl_pos;
>> + u32 rx_sgl_start;
>> + bool wait_second_completion;
>> +};
>> +
>> +/*
>> + * This data type corresponds to the nand dma descriptor
>> + * @dma_desc - low level DMA engine descriptor
>> + * @list - list for desc_info
>> + *
>> + * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
>> + * ADM
>> + * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
>> + * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
>> + * @dir - DMA transfer direction
>> + */
>> +struct desc_info {
>> + struct dma_async_tx_descriptor *dma_desc;
>> + struct list_head node;
>> +
>> + union {
>> + struct scatterlist adm_sgl;
>> + struct {
>> + struct scatterlist *bam_sgl;
>> + int sgl_cnt;
>> + };
>> + };
>> + enum dma_data_direction dir;
>> +};
>> +
>> +/*
>> + * holds the current register values that we want to write. acts as a contiguous
>> + * chunk of memory which we use to write the controller registers through DMA.
>> + */
>> +struct nandc_regs {
>> + __le32 cmd;
>> + __le32 addr0;
>> + __le32 addr1;
>> + __le32 chip_sel;
>> + __le32 exec;
>> +
>> + __le32 cfg0;
>> + __le32 cfg1;
>> + __le32 ecc_bch_cfg;
>> +
>> + __le32 clrflashstatus;
>> + __le32 clrreadstatus;
>> +
>> + __le32 cmd1;
>> + __le32 vld;
>> +
>> + __le32 orig_cmd1;
>> + __le32 orig_vld;
>> +
>> + __le32 ecc_buf_cfg;
>> + __le32 read_location0;
>> + __le32 read_location1;
>> + __le32 read_location2;
>> + __le32 read_location3;
>> + __le32 read_location_last0;
>> + __le32 read_location_last1;
>> + __le32 read_location_last2;
>> + __le32 read_location_last3;
>> +
>> + __le32 erased_cw_detect_cfg_clr;
>> + __le32 erased_cw_detect_cfg_set;
>> +};
>> +
>> +/*
>> + * NAND controller data struct
>> + *
>> + * @dev: parent device
>> + *
>> + * @base: MMIO base
>> + *
>> + * @core_clk: controller clock
>> + * @aon_clk: another controller clock
>> + *
>> + * @regs: a contiguous chunk of memory for DMA register
>> + * writes. contains the register values to be
>> + * written to controller
>> + *
>> + * @props: properties of current NAND controller,
>> + * initialized via DT match data
>> + *
>> + * @controller: base controller structure
>> + * @host_list: list containing all the chips attached to the
>> + * controller
>> + *
>> + * @chan: dma channel
>> + * @cmd_crci: ADM DMA CRCI for command flow control
>> + * @data_crci: ADM DMA CRCI for data flow control
>> + *
>> + * @desc_list: DMA descriptor list (list of desc_infos)
>> + *
>> + * @data_buffer: our local DMA buffer for page read/writes,
>> + * used when we can't use the buffer provided
>> + * by upper layers directly
>> + * @reg_read_buf: local buffer for reading back registers via DMA
>> + *
>> + * @base_phys: physical base address of controller registers
>> + * @base_dma: dma base address of controller registers
>> + * @reg_read_dma: contains dma address for register read buffer
>> + *
>> + * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
>> + * functions
>> + * @max_cwperpage: maximum QPIC codewords required. calculated
>> + * from all connected NAND devices pagesize
>> + *
>> + * @reg_read_pos: marker for data read in reg_read_buf
>> + *
>> + * @cmd1/vld: some fixed controller register values
>> + *
>> + * @exec_opwrite: flag to select correct number of code word
>> + * while reading status
>> + */
>> +struct qcom_nand_controller {
>> + struct device *dev;
>> +
>> + void __iomem *base;
>> +
>> + struct clk *core_clk;
>> + struct clk *aon_clk;
>> +
>> + struct nandc_regs *regs;
>> + struct bam_transaction *bam_txn;
>> +
>> + const struct qcom_nandc_props *props;
>> +
>> + struct nand_controller controller;
>> + struct list_head host_list;
>> +
>> + union {
>> + /* will be used only by QPIC for BAM DMA */
>> + struct {
>> + struct dma_chan *tx_chan;
>> + struct dma_chan *rx_chan;
>> + struct dma_chan *cmd_chan;
>> + };
>> +
>> + /* will be used only by EBI2 for ADM DMA */
>> + struct {
>> + struct dma_chan *chan;
>> + unsigned int cmd_crci;
>> + unsigned int data_crci;
>> + };
>> + };
>> +
>> + struct list_head desc_list;
>> +
>> + u8 *data_buffer;
>> + __le32 *reg_read_buf;
>> +
>> + phys_addr_t base_phys;
>> + dma_addr_t base_dma;
>> + dma_addr_t reg_read_dma;
>> +
>> + int buf_size;
>> + int buf_count;
>> + int buf_start;
>> + unsigned int max_cwperpage;
>> +
>> + int reg_read_pos;
>> +
>> + u32 cmd1, vld;
>> + bool exec_opwrite;
>> +};
>> +
>> +/*
>> + * This data type corresponds to the NAND controller properties which varies
>> + * among different NAND controllers.
>> + * @ecc_modes - ecc mode for NAND
>> + * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
>> + * @is_bam - whether NAND controller is using BAM
>> + * @is_qpic - whether NAND CTRL is part of qpic IP
>> + * @qpic_v2 - flag to indicate QPIC IP version 2
>> + * @use_codeword_fixup - whether NAND has different layout for boot partitions
>> + */
>> +struct qcom_nandc_props {
>> + u32 ecc_modes;
>> + u32 dev_cmd_reg_start;
>> + bool is_bam;
>> + bool is_qpic;
>> + bool qpic_v2;
>> + bool use_codeword_fixup;
>> +};
>> +
>> +void config_nand_page_read(struct nand_chip *chip);
>> +void free_bam_transaction(struct qcom_nand_controller *nandc);
>> +void qpic_bam_dma_done(void *data);
>> +void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, bool is_cpu);
>> +__le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset);
>> +void clear_read_regs(struct qcom_nand_controller *nandc);
>> +int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read,
>> + int reg_off, const void *vaddr, int size,
>> + bool flow_control);
>> +int submit_descs(struct qcom_nand_controller *nandc);
>> +int prepare_bam_async_desc(struct qcom_nand_controller *nandc,
>> + struct dma_chan *chan, unsigned long flags);
>> +int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
>> + int reg_off, const void *vaddr,
>> + int size, unsigned int flags);
>> +int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
>> + const void *vaddr,
>> + int size, unsigned int flags);
>> +int read_reg_dma(struct qcom_nand_controller *nandc, int first,
>> + int num_regs, unsigned int flags);
>> +int write_reg_dma(struct qcom_nand_controller *nandc, int first,
>> + int num_regs, unsigned int flags);
>> +int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>> + const u8 *vaddr, int size, unsigned int flags);
>> +int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>> + const u8 *vaddr, int size, unsigned int flags);
>> +struct bam_transaction *alloc_bam_transaction(struct qcom_nand_controller *nandc);
>> +void clear_bam_transaction(struct qcom_nand_controller *nandc);
>> +void qcom_nandc_unalloc(struct qcom_nand_controller *nandc);
>> +int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
>> +struct qcom_nand_controller *get_qcom_nand_controller(struct nand_chip *chip);
>> +
>> +#endif
On 2/15/2024 8:30 PM, Dmitry Baryshkov wrote:
> On Thu, 15 Feb 2024 at 15:53, Md Sadre Alam <[email protected]> wrote:
>>
>> Add qpic_common.c file which hold all the common
>> qpic APIs which will be used by both qpic raw nand
>> driver and qpic spi nand driver.
>>
>> Co-developed-by: Sricharan Ramabadhran <[email protected]>
>> Signed-off-by: Sricharan Ramabadhran <[email protected]>
>> Co-developed-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> Signed-off-by: Md Sadre Alam <[email protected]>
>> ---
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
>> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
>> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
>> 4 files changed, 1291 insertions(+), 1210 deletions(-)
>> create mode 100644 drivers/mtd/nand/qpic_common.c
>> create mode 100644 include/linux/mtd/nand-qpic-common.h
>>
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index 19e1291ac4d5..131707a41293 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
>> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
>> +obj-y += qpic_common.o
>> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
>> new file mode 100644
>> index 000000000000..4d74ba888028
>> --- /dev/null
>> +++ b/drivers/mtd/nand/qpic_common.c
>> @@ -0,0 +1,786 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * QPIC Controller common API file.
>> + * Copyright (C) 2023 Qualcomm Inc.
>> + * Authors: Md sadre Alam <[email protected]>
>> + * Sricharan R <[email protected]>
>> + * Varadarajan Narayanan <[email protected]>
>
> This is a bit of an exaggeration. You are moving code, not writing new
> code. Please retain the existing copyrights for the moved code.
Ok
>
>> + *
>> + */
>> +
>> +#include <linux/mtd/nand-qpic-common.h>
>> +
>> +struct qcom_nand_controller *
>> +get_qcom_nand_controller(struct nand_chip *chip)
>> +{
>> + return container_of(chip->controller, struct qcom_nand_controller,
>> + controller);
>> +}
>> +EXPORT_SYMBOL(get_qcom_nand_controller);
>
> NAK for adding functions to the global export namespace without a
> proper driver-specific prefix.
Ok, will fix in next patch
>
> Also, a bunch of the code here seems not so well thought. It was fine
> for an internal interface, but it doesn't look so good as a common
> wrapper. Please consider defining a sensible common code module
> interface instead.
QPIC controller will support both raw NAND as well Serial nand interface.
This common API file was the part of raw NAND driver , since for serial
nand most of the APIs from raw nand driver will be re-used that's why i
have created this common API file, so that QPIC serial nand driver
drivers/spi/spi-qpic-snand.c and QPIC raw NAND driver
drivers/mtd/nand/raw/qcom_nandc.c can used these common APIs.
Could you please suggest how I should handle this in batter way.
>
> At least each function that is being exported should get a kerneldoc.
Ok
>
> Last, but not least, please use EXPORT_SYMBOL_GPL.
Ok
>
>> +
>> +/*
>> + * Helper to prepare DMA descriptors for configuring registers
>> + * before reading a NAND page.
>> + */
>> +void config_nand_page_read(struct nand_chip *chip)
>> +{
>> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +
>> + write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>> + write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> + if (!nandc->props->qpic_v2)
>> + write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>> + write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>> + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> +}
>> +EXPORT_SYMBOL(config_nand_page_read);
>> +
>> +/* Frees the BAM transaction memory */
>> +void free_bam_transaction(struct qcom_nand_controller *nandc)
>> +{
>> + struct bam_transaction *bam_txn = nandc->bam_txn;
>> +
>> + devm_kfree(nandc->dev, bam_txn);
>
> devm_kfree is usually a bad sign. Either the devm_kfree should be
> dropped (because the memory area is allocated only during probe / init
> and doesn't need to be freed manually) or use kalloc/kfree directly
> without devres wrapping.
Ok
>
>> +}
>> +EXPORT_SYMBOL(free_bam_transaction);
>> +
>
> [skipped the rest]
>
>> --
>> 2.34.1
>>
>>
>
>
> --
> With best wishes
> Dmitry
Thanks for reviewing, Will fix all the comments in next patch.
Regards,
Alam.
On Tue, 20 Feb 2024 at 17:59, Md Sadre Alam <[email protected]> wrote:
>
>
>
> On 2/15/2024 8:30 PM, Dmitry Baryshkov wrote:
> > On Thu, 15 Feb 2024 at 15:53, Md Sadre Alam <[email protected]> wrote:
> >>
> >> Add qpic_common.c file which hold all the common
> >> qpic APIs which will be used by both qpic raw nand
> >> driver and qpic spi nand driver.
> >>
> >> Co-developed-by: Sricharan Ramabadhran <[email protected]>
> >> Signed-off-by: Sricharan Ramabadhran <[email protected]>
> >> Co-developed-by: Varadarajan Narayanan <[email protected]>
> >> Signed-off-by: Varadarajan Narayanan <[email protected]>
> >> Signed-off-by: Md Sadre Alam <[email protected]>
> >> ---
> >> drivers/mtd/nand/Makefile | 1 +
> >> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
> >> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
> >> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
> >> 4 files changed, 1291 insertions(+), 1210 deletions(-)
> >> create mode 100644 drivers/mtd/nand/qpic_common.c
> >> create mode 100644 include/linux/mtd/nand-qpic-common.h
> >>
> >> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> >> index 19e1291ac4d5..131707a41293 100644
> >> --- a/drivers/mtd/nand/Makefile
> >> +++ b/drivers/mtd/nand/Makefile
> >> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
> >> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
> >> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
> >> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
> >> +obj-y += qpic_common.o
> >> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
> >> new file mode 100644
> >> index 000000000000..4d74ba888028
> >> --- /dev/null
> >> +++ b/drivers/mtd/nand/qpic_common.c
> >> @@ -0,0 +1,786 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * QPIC Controller common API file.
> >> + * Copyright (C) 2023 Qualcomm Inc.
> >> + * Authors: Md sadre Alam <[email protected]>
> >> + * Sricharan R <[email protected]>
> >> + * Varadarajan Narayanan <[email protected]>
> >
> > This is a bit of an exaggeration. You are moving code, not writing new
> > code. Please retain the existing copyrights for the moved code.
> Ok
> >
> >> + *
> >> + */
> >> +
> >> +#include <linux/mtd/nand-qpic-common.h>
> >> +
> >> +struct qcom_nand_controller *
> >> +get_qcom_nand_controller(struct nand_chip *chip)
> >> +{
> >> + return container_of(chip->controller, struct qcom_nand_controller,
> >> + controller);
> >> +}
> >> +EXPORT_SYMBOL(get_qcom_nand_controller);
> >
> > NAK for adding functions to the global export namespace without a
> > proper driver-specific prefix.
> Ok, will fix in next patch
> >
> > Also, a bunch of the code here seems not so well thought. It was fine
> > for an internal interface, but it doesn't look so good as a common
> > wrapper. Please consider defining a sensible common code module
> > interface instead.
>
> QPIC controller will support both raw NAND as well Serial nand interface.
> This common API file was the part of raw NAND driver , since for serial
> nand most of the APIs from raw nand driver will be re-used that's why i
> have created this common API file, so that QPIC serial nand driver
> drivers/spi/spi-qpic-snand.c and QPIC raw NAND driver
> drivers/mtd/nand/raw/qcom_nandc.c can used these common APIs.
>
> Could you please suggest how I should handle this in batter way.
Yes. Start by designing common accessor functions that form a
sufficient and complete API to access the hardware functionality. A
set of functions blindly moved from the existing driver usually do not
make such an API, because usually nobody cares enough about the driver
internals. It should be something that external user (NAND, SPI, etc)
can use without looking into the actual implementation of these
functions.
--
With best wishes
Dmitry
On Tue, Feb 20, 2024 at 05:24:43PM +0530, Md Sadre Alam wrote:
> On 2/15/2024 7:44 PM, Mark Brown wrote:
> > On Thu, Feb 15, 2024 at 07:18:54PM +0530, Md Sadre Alam wrote:
> > > + if (op->cmd.opcode == SPINAND_READID) {
> > > + snandc->buf_count = 4;
> > > + read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
> > > +
> > > + ret = submit_descs(snandc);
> > > + if (ret)
> > > + dev_err(snandc->dev, "failure in submitting descriptor for readid\n");
> > > +
> > > + nandc_read_buffer_sync(snandc, true);
> > > + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
> > These memcpy()s don't seem great, why aren't we just reading directly
> > into the output buffer?
> This reg_read_buf is being used in common API so that it will be used by both
> serial nand as well raw nand, so I can't directly use the output buffer since
> internally CW mechanism I have to maintain in common API.
We have control over all the source code in the kernel so if there's
problems with the internal interfaces we can improve them.
On 2/20/2024 5:06 PM, Krzysztof Kozlowski wrote:
> On 20/02/2024 12:32, Md Sadre Alam wrote:
>>
>>
>> On 2/19/2024 6:34 PM, Manivannan Sadhasivam wrote:
>>> On Thu, Feb 15, 2024 at 07:18:51PM +0530, Md Sadre Alam wrote:
>>>> This series of patches will add initial supports
>>>> for QPIC SPI NAND driver.
>>>>
>>>> Currently this driver support following commands
>>>>
>>>> -- RESET
>>>> -- READ ID
>>>> -- BLOCK ERASE
>>>> -- PAGE READ
>>>> -- PAGE WRITE
>>>> -- GET FEATURE
>>>> -- SET FEATURE
>>>> -- BAD BLOCK CHECK
>>>>
>>>> This driver has been tested with dd command with read/write page
>>>> with multiple file size 1MiB, 10MiB,40MiB etc.
>>>> Also tested with "mtd" command like mtd erase, mtd write, mtd verify etc.
>>>>
>>>
>>> This is not the first version isn't it? Where is the changelog describing what
>>> has changed since then?
>>
>> The earlier patch was the RFC for design review only.
>
> RFC is state of patch, not version. This is v2 then.
>
> These RFC postings are really becoming mess. Some people make multiple
> RFCs and then post v1 hiding entire previous history... And why even
> bother with calling it RFC?
Sorry, I was not aware of this. Shall I post the next one as V3
and add references to the RFC patch and this patch in the cover
letter of V3?
>
> Best regards,
> Krzysztof
>
On 2/20/2024 9:34 PM, Mark Brown wrote:
> On Tue, Feb 20, 2024 at 05:24:43PM +0530, Md Sadre Alam wrote:
>> On 2/15/2024 7:44 PM, Mark Brown wrote:
>>> On Thu, Feb 15, 2024 at 07:18:54PM +0530, Md Sadre Alam wrote:
>
>>>> + if (op->cmd.opcode == SPINAND_READID) {
>>>> + snandc->buf_count = 4;
>>>> + read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
>>>> +
>>>> + ret = submit_descs(snandc);
>>>> + if (ret)
>>>> + dev_err(snandc->dev, "failure in submitting descriptor for readid\n");
>>>> +
>>>> + nandc_read_buffer_sync(snandc, true);
>>>> + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
>
>>> These memcpy()s don't seem great, why aren't we just reading directly
>>> into the output buffer?
>
>> This reg_read_buf is being used in common API so that it will be used by both
>> serial nand as well raw nand, so I can't directly use the output buffer since
>> internally CW mechanism I have to maintain in common API.
>
> We have control over all the source code in the kernel so if there's
> problems with the internal interfaces we can improve them.
Ok , will try to maintain CW mechanism uniform and remove from common API
and move to corresponding driver. Will try to fix in next patch.
On 2/20/2024 9:37 PM, Dmitry Baryshkov wrote:
> On Tue, 20 Feb 2024 at 17:59, Md Sadre Alam <[email protected]> wrote:
>>
>>
>>
>> On 2/15/2024 8:30 PM, Dmitry Baryshkov wrote:
>>> On Thu, 15 Feb 2024 at 15:53, Md Sadre Alam <[email protected]> wrote:
>>>>
>>>> Add qpic_common.c file which hold all the common
>>>> qpic APIs which will be used by both qpic raw nand
>>>> driver and qpic spi nand driver.
>>>>
>>>> Co-developed-by: Sricharan Ramabadhran <[email protected]>
>>>> Signed-off-by: Sricharan Ramabadhran <[email protected]>
>>>> Co-developed-by: Varadarajan Narayanan <[email protected]>
>>>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>>>> Signed-off-by: Md Sadre Alam <[email protected]>
>>>> ---
>>>> drivers/mtd/nand/Makefile | 1 +
>>>> drivers/mtd/nand/qpic_common.c | 786 +++++++++++++++++
>>>> drivers/mtd/nand/raw/qcom_nandc.c | 1226 +-------------------------
>>>> include/linux/mtd/nand-qpic-common.h | 488 ++++++++++
>>>> 4 files changed, 1291 insertions(+), 1210 deletions(-)
>>>> create mode 100644 drivers/mtd/nand/qpic_common.c
>>>> create mode 100644 include/linux/mtd/nand-qpic-common.h
>>>>
>>>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>>>> index 19e1291ac4d5..131707a41293 100644
>>>> --- a/drivers/mtd/nand/Makefile
>>>> +++ b/drivers/mtd/nand/Makefile
>>>> @@ -12,3 +12,4 @@ nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
>>>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
>>>> nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
>>>> nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
>>>> +obj-y += qpic_common.o
>>>> diff --git a/drivers/mtd/nand/qpic_common.c b/drivers/mtd/nand/qpic_common.c
>>>> new file mode 100644
>>>> index 000000000000..4d74ba888028
>>>> --- /dev/null
>>>> +++ b/drivers/mtd/nand/qpic_common.c
>>>> @@ -0,0 +1,786 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * QPIC Controller common API file.
>>>> + * Copyright (C) 2023 Qualcomm Inc.
>>>> + * Authors: Md sadre Alam <[email protected]>
>>>> + * Sricharan R <[email protected]>
>>>> + * Varadarajan Narayanan <[email protected]>
>>>
>>> This is a bit of an exaggeration. You are moving code, not writing new
>>> code. Please retain the existing copyrights for the moved code.
>> Ok
>>>
>>>> + *
>>>> + */
>>>> +
>>>> +#include <linux/mtd/nand-qpic-common.h>
>>>> +
>>>> +struct qcom_nand_controller *
>>>> +get_qcom_nand_controller(struct nand_chip *chip)
>>>> +{
>>>> + return container_of(chip->controller, struct qcom_nand_controller,
>>>> + controller);
>>>> +}
>>>> +EXPORT_SYMBOL(get_qcom_nand_controller);
>>>
>>> NAK for adding functions to the global export namespace without a
>>> proper driver-specific prefix.
>> Ok, will fix in next patch
>>>
>>> Also, a bunch of the code here seems not so well thought. It was fine
>>> for an internal interface, but it doesn't look so good as a common
>>> wrapper. Please consider defining a sensible common code module
>>> interface instead.
>>
>> QPIC controller will support both raw NAND as well Serial nand interface.
>> This common API file was the part of raw NAND driver , since for serial
>> nand most of the APIs from raw nand driver will be re-used that's why i
>> have created this common API file, so that QPIC serial nand driver
>> drivers/spi/spi-qpic-snand.c and QPIC raw NAND driver
>> drivers/mtd/nand/raw/qcom_nandc.c can used these common APIs.
>>
>> Could you please suggest how I should handle this in batter way.
>
> Yes. Start by designing common accessor functions that form a
> sufficient and complete API to access the hardware functionality. A
> set of functions blindly moved from the existing driver usually do not
> make such an API, because usually nobody cares enough about the driver
> internals. It should be something that external user (NAND, SPI, etc)
> can use without looking into the actual implementation of these
> functions.
Thanks for suggestion. Will make the Common API more generic and
post in next patch.
>
On 21/02/2024 11:34, Md Sadre Alam wrote:
>
>
> On 2/20/2024 5:06 PM, Krzysztof Kozlowski wrote:
>> On 20/02/2024 12:32, Md Sadre Alam wrote:
>>>
>>>
>>> On 2/19/2024 6:34 PM, Manivannan Sadhasivam wrote:
>>>> On Thu, Feb 15, 2024 at 07:18:51PM +0530, Md Sadre Alam wrote:
>>>>> This series of patches will add initial supports
>>>>> for QPIC SPI NAND driver.
>>>>>
>>>>> Currently this driver support following commands
>>>>>
>>>>> -- RESET
>>>>> -- READ ID
>>>>> -- BLOCK ERASE
>>>>> -- PAGE READ
>>>>> -- PAGE WRITE
>>>>> -- GET FEATURE
>>>>> -- SET FEATURE
>>>>> -- BAD BLOCK CHECK
>>>>>
>>>>> This driver has been tested with dd command with read/write page
>>>>> with multiple file size 1MiB, 10MiB,40MiB etc.
>>>>> Also tested with "mtd" command like mtd erase, mtd write, mtd verify etc.
>>>>>
>>>>
>>>> This is not the first version isn't it? Where is the changelog describing what
>>>> has changed since then?
>>>
>>> The earlier patch was the RFC for design review only.
>>
>> RFC is state of patch, not version. This is v2 then.
>>
>> These RFC postings are really becoming mess. Some people make multiple
>> RFCs and then post v1 hiding entire previous history... And why even
>> bother with calling it RFC?
>
> Sorry, I was not aware of this. Shall I post the next one as V3
> and add references to the RFC patch and this patch in the cover
> letter of V3?
Yes, like with every posting.
Best regards,
Krzysztof
On 2/21/2024 4:31 PM, Krzysztof Kozlowski wrote:
> On 21/02/2024 11:34, Md Sadre Alam wrote:
>>
>>
>> On 2/20/2024 5:06 PM, Krzysztof Kozlowski wrote:
>>> On 20/02/2024 12:32, Md Sadre Alam wrote:
>>>>
>>>>
>>>> On 2/19/2024 6:34 PM, Manivannan Sadhasivam wrote:
>>>>> On Thu, Feb 15, 2024 at 07:18:51PM +0530, Md Sadre Alam wrote:
>>>>>> This series of patches will add initial supports
>>>>>> for QPIC SPI NAND driver.
>>>>>>
>>>>>> Currently this driver support following commands
>>>>>>
>>>>>> -- RESET
>>>>>> -- READ ID
>>>>>> -- BLOCK ERASE
>>>>>> -- PAGE READ
>>>>>> -- PAGE WRITE
>>>>>> -- GET FEATURE
>>>>>> -- SET FEATURE
>>>>>> -- BAD BLOCK CHECK
>>>>>>
>>>>>> This driver has been tested with dd command with read/write page
>>>>>> with multiple file size 1MiB, 10MiB,40MiB etc.
>>>>>> Also tested with "mtd" command like mtd erase, mtd write, mtd verify etc.
>>>>>>
>>>>>
>>>>> This is not the first version isn't it? Where is the changelog describing what
>>>>> has changed since then?
>>>>
>>>> The earlier patch was the RFC for design review only.
>>>
>>> RFC is state of patch, not version. This is v2 then.
>>>
>>> These RFC postings are really becoming mess. Some people make multiple
>>> RFCs and then post v1 hiding entire previous history... And why even
>>> bother with calling it RFC?
>>
>> Sorry, I was not aware of this. Shall I post the next one as V3
>> and add references to the RFC patch and this patch in the cover
>> letter of V3?
>
> Yes, like with every posting.
Thank you.
>
> Best regards,
> Krzysztof
>
Konrad,
On 2/20/2024 5:44 PM, Md Sadre Alam wrote:
>>> + ecc_cfg->cfg0 = (cwperpage - 1) << CW_PER_PAGE
>>> + | ecc_cfg->cw_data << UD_SIZE_BYTES
>>> + | 1 << DISABLE_STATUS_AFTER_WRITE
>>> + | 3 << NUM_ADDR_CYCLES
>>> + | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
>>> + | 0 << STATUS_BFR_READ
>>> + | 1 << SET_RD_MODE_AFTER_STATUS
>>> + | ecc_cfg->spare_bytes << SPARE_SIZE_BYTES;
>>
>> Let me introduce you to FIELD_PREP/GET and GENMASK().. Many assignments
>> in this file could use these.
>
> Ok
While doing the change i realized that it will impact raw nand driver as well.
Shall I post this change as separate patch. Is this ok? Please let me know.
Regards,
Alam.
>>
>> Konrad
>
> Thanks for reviewing, will fix all the comments in next patch.
>
> Regards,
> Alam.
>
On 3/6/24 07:01, Md Sadre Alam wrote:
> Konrad,
>
> On 2/20/2024 5:44 PM, Md Sadre Alam wrote:
>>>> + ecc_cfg->cfg0 = (cwperpage - 1) << CW_PER_PAGE
>>>> + | ecc_cfg->cw_data << UD_SIZE_BYTES
>>>> + | 1 << DISABLE_STATUS_AFTER_WRITE
>>>> + | 3 << NUM_ADDR_CYCLES
>>>> + | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
>>>> + | 0 << STATUS_BFR_READ
>>>> + | 1 << SET_RD_MODE_AFTER_STATUS
>>>> + | ecc_cfg->spare_bytes << SPARE_SIZE_BYTES;
>>>
>>> Let me introduce you to FIELD_PREP/GET and GENMASK().. Many assignments
>>> in this file could use these.
>>
>> Ok
>
> While doing the change i realized that it will impact raw nand driver as well.
> Shall I post this change as separate patch. Is this ok? Please let me know.
One patch per file/topic, yes, please
Konrad
On 3/6/2024 9:57 PM, Konrad Dybcio wrote:
>
>
> On 3/6/24 07:01, Md Sadre Alam wrote:
>> Konrad,
>>
>> On 2/20/2024 5:44 PM, Md Sadre Alam wrote:
>>>>> + ecc_cfg->cfg0 = (cwperpage - 1) << CW_PER_PAGE
>>>>> + | ecc_cfg->cw_data << UD_SIZE_BYTES
>>>>> + | 1 << DISABLE_STATUS_AFTER_WRITE
>>>>> + | 3 << NUM_ADDR_CYCLES
>>>>> + | ecc_cfg->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
>>>>> + | 0 << STATUS_BFR_READ
>>>>> + | 1 << SET_RD_MODE_AFTER_STATUS
>>>>> + | ecc_cfg->spare_bytes << SPARE_SIZE_BYTES;
>>>>
>>>> Let me introduce you to FIELD_PREP/GET and GENMASK().. Many assignments
>>>> in this file could use these.
>>>
>>> Ok
>>
>> While doing the change i realized that it will impact raw nand driver as well.
>> Shall I post this change as separate patch. Is this ok? Please let me know.
>
> One patch per file/topic, yes, please
Thank you
>
> Konrad