Added geometry description for Microchip 25LC256 memory.
Signed-off-by: Radu Pirea <[email protected]>
---
drivers/mtd/devices/m25p80.c | 3 +++
drivers/mtd/spi-nor/spi-nor.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index a4e18f6aaa33..1e359d811261 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] = {
{ "mr25h10" }, /* 1 Mib, 40 MHz */
{ "mr25h40" }, /* 4 Mib, 40 MHz */
+ /* Microchip */
+ { "25lc256" },
+
{ },
};
MODULE_DEVICE_TABLE(spi, m25p_ids);
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index d445a4d3b770..6341c86be647 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
+ /* Microchip */
+ { "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+
/* Micron */
{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
--
2.16.2
On 05/04/2018 05:54 PM, Radu Pirea wrote:
> Added geometry description for Microchip 25LC256 memory.
Are you sure this is a SPI NOR ? I don't see any RDID instruction in the
datasheet, only some 6 instructions to read/write the array and lock it.
Isn't the AT25 driver a better fit for this EEPROM ?
> Signed-off-by: Radu Pirea <[email protected]>
> ---
> drivers/mtd/devices/m25p80.c | 3 +++
> drivers/mtd/spi-nor/spi-nor.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index a4e18f6aaa33..1e359d811261 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] = {
> { "mr25h10" }, /* 1 Mib, 40 MHz */
> { "mr25h40" }, /* 4 Mib, 40 MHz */
>
> + /* Microchip */
> + { "25lc256" },
> +
> { },
> };
> MODULE_DEVICE_TABLE(spi, m25p_ids);
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index d445a4d3b770..6341c86be647 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[] = {
> { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
>
> + /* Microchip */
> + { "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> +
> /* Micron */
> { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
>
--
Best regards,
Marek Vasut
On Fri, 4 May 2018 18:54:04 +0300
Radu Pirea <[email protected]> wrote:
> Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't
think this device belongs in the SPI NOR framework.
>
> Signed-off-by: Radu Pirea <[email protected]>
> ---
> drivers/mtd/devices/m25p80.c | 3 +++
> drivers/mtd/spi-nor/spi-nor.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index a4e18f6aaa33..1e359d811261 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] = {
> { "mr25h10" }, /* 1 Mib, 40 MHz */
> { "mr25h40" }, /* 4 Mib, 40 MHz */
>
> + /* Microchip */
> + { "25lc256" },
> +
> { },
> };
> MODULE_DEVICE_TABLE(spi, m25p_ids);
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index d445a4d3b770..6341c86be647 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[] = {
> { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
>
> + /* Microchip */
> + { "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> +
> /* Micron */
> { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
> On Fri, 4 May 2018 18:54:04 +0300
> Radu Pirea <[email protected]> wrote:
>
> > Added geometry description for Microchip 25LC256 memory.
>
> Same as for the dataflash stuff you posted a few weeks ago: I don't
> think this device belongs in the SPI NOR framework.
Hi Boris,
25lc256 memory is similar with mr25h256, the only difference is the
page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
I added here 25lc256.
> >
> > Signed-off-by: Radu Pirea <[email protected]>
> > ---
> > drivers/mtd/devices/m25p80.c | 3 +++
> > drivers/mtd/spi-nor/spi-nor.c | 3 +++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/mtd/devices/m25p80.c
> > b/drivers/mtd/devices/m25p80.c
> > index a4e18f6aaa33..1e359d811261 100644
> > --- a/drivers/mtd/devices/m25p80.c
> > +++ b/drivers/mtd/devices/m25p80.c
> > @@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] =
> > {
> > { "mr25h10" }, /* 1 Mib, 40 MHz */
> > { "mr25h40" }, /* 4 Mib, 40 MHz */
> >
> > + /* Microchip */
> > + { "25lc256" },
> > +
> > { },
> > };
> > MODULE_DEVICE_TABLE(spi, m25p_ids);
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-
> > nor/spi-nor.c
> > index d445a4d3b770..6341c86be647 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[]
> > = {
> > { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048,
> > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048,
> > SPI_NOR_QUAD_READ) },
> >
> > + /* Microchip */
> > + { "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2,
> > SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> > +
> > /* Micron */
> > { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32,
> > SECT_4K | SPI_NOR_QUAD_READ) },
> > { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64,
> > SPI_NOR_QUAD_READ) },
>
>
On 05/15/2018 06:22 PM, Radu Pirea wrote:
> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
>> On Fri, 4 May 2018 18:54:04 +0300
>> Radu Pirea <[email protected]> wrote:
>>
>>> Added geometry description for Microchip 25LC256 memory.
>>
>> Same as for the dataflash stuff you posted a few weeks ago: I don't
>> think this device belongs in the SPI NOR framework.
> Hi Boris,
>
> 25lc256 memory is similar with mr25h256, the only difference is the
> page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
> I added here 25lc256.
I think I must be reading the wrong datasheet, but can you show me how
does it support things like READID opcode ?
--
Best regards,
Marek Vasut
On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote:
> On 05/15/2018 06:22 PM, Radu Pirea wrote:
> > On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
> > > On Fri, 4 May 2018 18:54:04 +0300
> > > Radu Pirea <[email protected]> wrote:
> > >
> > > > Added geometry description for Microchip 25LC256 memory.
> > >
> > > Same as for the dataflash stuff you posted a few weeks ago: I
> > > don't
> > > think this device belongs in the SPI NOR framework.
> >
> > Hi Boris,
> >
> > 25lc256 memory is similar with mr25h256, the only difference is the
> > page size(64 vs 256). Because mr25h256 is already in SPI NOR
> > framework
> > I added here 25lc256.
>
> I think I must be reading the wrong datasheet, but can you show me
> how
> does it support things like READID opcode ?
>
Hi Marek,
I read the datasheet for 25lc256 and for mr25h256 and none of them
supports READID. Is this required for a chip to be included in spi-nor
framework? I just followed the mr25h256 as an example.
On 05/16/2018 12:05 PM, Radu Pirea wrote:
> On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote:
>> On 05/15/2018 06:22 PM, Radu Pirea wrote:
>>> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
>>>> On Fri, 4 May 2018 18:54:04 +0300
>>>> Radu Pirea <[email protected]> wrote:
>>>>
>>>>> Added geometry description for Microchip 25LC256 memory.
>>>>
>>>> Same as for the dataflash stuff you posted a few weeks ago: I
>>>> don't
>>>> think this device belongs in the SPI NOR framework.
>>>
>>> Hi Boris,
>>>
>>> 25lc256 memory is similar with mr25h256, the only difference is the
>>> page size(64 vs 256). Because mr25h256 is already in SPI NOR
>>> framework
>>> I added here 25lc256.
>>
>> I think I must be reading the wrong datasheet, but can you show me
>> how
>> does it support things like READID opcode ?
>>
> Hi Marek,
>
> I read the datasheet for 25lc256 and for mr25h256 and none of them
> supports READID. Is this required for a chip to be included in spi-nor
> framework? I just followed the mr25h256 as an example.
So I thought until you pointed out the MR25 devices.
Does the 25LC device need erase or not ? I think the MR25s didn't, but I
might be wrong.
Maybe the framework could support the 25LC afterall.
--
Best regards,
Marek Vasut
On 05/16/2018 04:47 PM, Marek Vasut wrote:
> On 05/16/2018 12:05 PM, Radu Pirea wrote:
>> On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote:
>>> On 05/15/2018 06:22 PM, Radu Pirea wrote:
>>>> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
>>>>> On Fri, 4 May 2018 18:54:04 +0300
>>>>> Radu Pirea <[email protected]> wrote:
>>>>>
>>>>>> Added geometry description for Microchip 25LC256 memory.
>>>>>
>>>>> Same as for the dataflash stuff you posted a few weeks ago: I
>>>>> don't
>>>>> think this device belongs in the SPI NOR framework.
>>>>
>>>> Hi Boris,
>>>>
>>>> 25lc256 memory is similar with mr25h256, the only difference is the
>>>> page size(64 vs 256). Because mr25h256 is already in SPI NOR
>>>> framework
>>>> I added here 25lc256.
>>>
>>> I think I must be reading the wrong datasheet, but can you show me
>>> how
>>> does it support things like READID opcode ?
>>>
>> Hi Marek,
>>
>> I read the datasheet for 25lc256 and for mr25h256 and none of them
>> supports READID. Is this required for a chip to be included in spi-nor
>> framework? I just followed the mr25h256 as an example.
>
> So I thought until you pointed out the MR25 devices.
>
> Does the 25LC device need erase or not ? I think the MR25s didn't, but I
> might be wrong.
You are right. MR25s does not need erase and the same thing is true for
25LC.
>
> Maybe the framework could support the 25LC afterall.
>
Yes, this was my impression too.
Thanks.
On 05/18/2018 11:50 AM, Radu Pirea wrote:
>
>
> On 05/16/2018 04:47 PM, Marek Vasut wrote:
>> On 05/16/2018 12:05 PM, Radu Pirea wrote:
>>> On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote:
>>>> On 05/15/2018 06:22 PM, Radu Pirea wrote:
>>>>> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
>>>>>> On Fri, 4 May 2018 18:54:04 +0300
>>>>>> Radu Pirea <[email protected]> wrote:
>>>>>>
>>>>>>> Added geometry description for Microchip 25LC256 memory.
>>>>>>
>>>>>> Same as for the dataflash stuff you posted a few weeks ago: I
>>>>>> don't
>>>>>> think this device belongs in the SPI NOR framework.
>>>>>
>>>>> Hi Boris,
>>>>>
>>>>> 25lc256 memory is similar with mr25h256, the only difference is the
>>>>> page size(64 vs 256). Because mr25h256 is already in SPI NOR
>>>>> framework
>>>>> I added here 25lc256.
>>>>
>>>> I think I must be reading the wrong datasheet, but can you show me
>>>> how
>>>> does it support things like READID opcode ?
>>>>
>>> Hi Marek,
>>>
>>> I read the datasheet for 25lc256 and for mr25h256 and none of them
>>> supports READID. Is this required for a chip to be included in spi-nor
>>> framework? I just followed the mr25h256 as an example.
>>
>> So I thought until you pointed out the MR25 devices.
>>
>> Does the 25LC device need erase or not ? I think the MR25s didn't, but I
>> might be wrong.
>
> You are right. MR25s does not need erase and the same thing is true for
> 25LC.
Oh. And the command set is (except for readid) comparable to SPI NOR ?
>> Maybe the framework could support the 25LC afterall.
>>
> Yes, this was my impression too.
I am still thinking that the AT25 driver might be a better fit for such
devices. Can you take a look ?
--
Best regards,
Marek Vasut
On 05/18/2018 01:03 PM, Marek Vasut wrote:
> On 05/18/2018 11:50 AM, Radu Pirea wrote:
>>
>>
>> On 05/16/2018 04:47 PM, Marek Vasut wrote:
>>> On 05/16/2018 12:05 PM, Radu Pirea wrote:
>>>> On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote:
>>>>> On 05/15/2018 06:22 PM, Radu Pirea wrote:
>>>>>> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
>>>>>>> On Fri, 4 May 2018 18:54:04 +0300
>>>>>>> Radu Pirea <[email protected]> wrote:
>>>>>>>
>>>>>>>> Added geometry description for Microchip 25LC256 memory.
>>>>>>>
>>>>>>> Same as for the dataflash stuff you posted a few weeks ago: I
>>>>>>> don't
>>>>>>> think this device belongs in the SPI NOR framework.
>>>>>>
>>>>>> Hi Boris,
>>>>>>
>>>>>> 25lc256 memory is similar with mr25h256, the only difference is the
>>>>>> page size(64 vs 256). Because mr25h256 is already in SPI NOR
>>>>>> framework
>>>>>> I added here 25lc256.
>>>>>
>>>>> I think I must be reading the wrong datasheet, but can you show me
>>>>> how
>>>>> does it support things like READID opcode ?
>>>>>
>>>> Hi Marek,
>>>>
>>>> I read the datasheet for 25lc256 and for mr25h256 and none of them
>>>> supports READID. Is this required for a chip to be included in spi-nor
>>>> framework? I just followed the mr25h256 as an example.
>>>
>>> So I thought until you pointed out the MR25 devices.
>>>
>>> Does the 25LC device need erase or not ? I think the MR25s didn't, but I
>>> might be wrong.
>>
>> You are right. MR25s does not need erase and the same thing is true for
>> 25LC.
>
> Oh. And the command set is (except for readid) comparable to SPI NOR ?
>
>>> Maybe the framework could support the 25LC afterall.
>>>
>> Yes, this was my impression too.
>
> I am still thinking that the AT25 driver might be a better fit for such
> devices. Can you take a look ?
I tested the memory with at25 driver and it works with no line changed
in driver. :)
>
On 05/18/2018 03:00 PM, Radu Pirea wrote:
>
>
> On 05/18/2018 01:03 PM, Marek Vasut wrote:
>> On 05/18/2018 11:50 AM, Radu Pirea wrote:
>>>
>>>
>>> On 05/16/2018 04:47 PM, Marek Vasut wrote:
>>>> On 05/16/2018 12:05 PM, Radu Pirea wrote:
>>>>> On Wed, 2018-05-16 at 00:17 +0200, Marek Vasut wrote:
>>>>>> On 05/15/2018 06:22 PM, Radu Pirea wrote:
>>>>>>> On Fri, 2018-05-04 at 20:40 +0200, Boris Brezillon wrote:
>>>>>>>> On Fri, 4 May 2018 18:54:04 +0300
>>>>>>>> Radu Pirea <[email protected]> wrote:
>>>>>>>>
>>>>>>>>> Added geometry description for Microchip 25LC256 memory.
>>>>>>>>
>>>>>>>> Same as for the dataflash stuff you posted a few weeks ago: I
>>>>>>>> don't
>>>>>>>> think this device belongs in the SPI NOR framework.
>>>>>>>
>>>>>>> Hi Boris,
>>>>>>>
>>>>>>> 25lc256 memory is similar with mr25h256, the only difference is the
>>>>>>> page size(64 vs 256). Because mr25h256 is already in SPI NOR
>>>>>>> framework
>>>>>>> I added here 25lc256.
>>>>>>
>>>>>> I think I must be reading the wrong datasheet, but can you show me
>>>>>> how
>>>>>> does it support things like READID opcode ?
>>>>>>
>>>>> Hi Marek,
>>>>>
>>>>> I read the datasheet for 25lc256 and for mr25h256 and none of them
>>>>> supports READID. Is this required for a chip to be included in spi-nor
>>>>> framework? I just followed the mr25h256 as an example.
>>>>
>>>> So I thought until you pointed out the MR25 devices.
>>>>
>>>> Does the 25LC device need erase or not ? I think the MR25s didn't,
>>>> but I
>>>> might be wrong.
>>>
>>> You are right. MR25s does not need erase and the same thing is true for
>>> 25LC.
>>
>> Oh. And the command set is (except for readid) comparable to SPI NOR ?
>>
>>>> Maybe the framework could support the 25LC afterall.
>>>>
>>> Yes, this was my impression too.
>>
>> I am still thinking that the AT25 driver might be a better fit for such
>> devices. Can you take a look ?
>
> I tested the memory with at25 driver and it works with no line changed
> in driver. :)
So AT25 it is then ?
--
Best regards,
Marek Vasut