This patch just cleans up some files of Intel Processor Trace, does not
change its behavior. Removing unused definition, replace a constant
value with macro, etc.
Signed-off-by: Takao Indoh <[email protected]>
---
arch/x86/kernel/cpu/intel_pt.h | 33 +++++-----------------------
arch/x86/kernel/cpu/perf_event_intel_pt.c | 14 ++++++------
2 files changed, 13 insertions(+), 34 deletions(-)
diff --git a/arch/x86/kernel/cpu/intel_pt.h b/arch/x86/kernel/cpu/intel_pt.h
index 1c338b0..6b48ba8 100644
--- a/arch/x86/kernel/cpu/intel_pt.h
+++ b/arch/x86/kernel/cpu/intel_pt.h
@@ -25,32 +25,11 @@
*/
#define TOPA_PMI_MARGIN 512
-/*
- * Table of Physical Addresses bits
- */
-enum topa_sz {
- TOPA_4K = 0,
- TOPA_8K,
- TOPA_16K,
- TOPA_32K,
- TOPA_64K,
- TOPA_128K,
- TOPA_256K,
- TOPA_512K,
- TOPA_1MB,
- TOPA_2MB,
- TOPA_4MB,
- TOPA_8MB,
- TOPA_16MB,
- TOPA_32MB,
- TOPA_64MB,
- TOPA_128MB,
- TOPA_SZ_END,
-};
+#define TOPA_SHIFT PAGE_SHIFT
-static inline unsigned int sizes(enum topa_sz tsz)
+static inline unsigned int sizes(unsigned int tsz)
{
- return 1 << (tsz + 12);
+ return 1 << (tsz + TOPA_SHIFT);
};
struct topa_entry {
@@ -66,8 +45,8 @@ struct topa_entry {
u64 rsvd4 : 16;
};
-#define TOPA_SHIFT 12
-#define PT_CPUID_LEAVES 2
+#define PT_CPUID_LEAVES 2
+#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
enum pt_capabilities {
PT_CAP_max_subleaf = 0,
@@ -79,7 +58,7 @@ enum pt_capabilities {
struct pt_pmu {
struct pmu pmu;
- u32 caps[4 * PT_CPUID_LEAVES];
+ u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
};
/**
diff --git a/arch/x86/kernel/cpu/perf_event_intel_pt.c b/arch/x86/kernel/cpu/perf_event_intel_pt.c
index 183de71..1e7d89e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_pt.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_pt.c
@@ -37,9 +37,9 @@ static struct pt_pmu pt_pmu;
enum cpuid_regs {
CR_EAX = 0,
+ CR_EBX,
CR_ECX,
- CR_EDX,
- CR_EBX
+ CR_EDX
};
/*
@@ -73,7 +73,7 @@ static struct pt_cap_desc {
static u32 pt_cap_get(enum pt_capabilities cap)
{
struct pt_cap_desc *cd = &pt_caps[cap];
- u32 c = pt_pmu.caps[cd->leaf * 4 + cd->reg];
+ u32 c = pt_pmu.caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg];
unsigned int shift = __ffs(cd->mask);
return (c & cd->mask) >> shift;
@@ -129,10 +129,10 @@ static int __init pt_pmu_hw_init(void)
for (i = 0; i < PT_CPUID_LEAVES; i++) {
cpuid_count(20, i,
- &pt_pmu.caps[CR_EAX + i*4],
- &pt_pmu.caps[CR_EBX + i*4],
- &pt_pmu.caps[CR_ECX + i*4],
- &pt_pmu.caps[CR_EDX + i*4]);
+ &pt_pmu.caps[CR_EAX + i*PT_CPUID_REGS_NUM],
+ &pt_pmu.caps[CR_EBX + i*PT_CPUID_REGS_NUM],
+ &pt_pmu.caps[CR_ECX + i*PT_CPUID_REGS_NUM],
+ &pt_pmu.caps[CR_EDX + i*PT_CPUID_REGS_NUM]);
}
ret = -ENOMEM;
--
1.7.1
Takao Indoh <[email protected]> writes:
> This patch just cleans up some files of Intel Processor Trace, does not
> change its behavior. Removing unused definition, replace a constant
> value with macro, etc.
>
> Signed-off-by: Takao Indoh <[email protected]>
> ---
> arch/x86/kernel/cpu/intel_pt.h | 33 +++++-----------------------
> arch/x86/kernel/cpu/perf_event_intel_pt.c | 14 ++++++------
> 2 files changed, 13 insertions(+), 34 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/intel_pt.h b/arch/x86/kernel/cpu/intel_pt.h
> index 1c338b0..6b48ba8 100644
> --- a/arch/x86/kernel/cpu/intel_pt.h
> +++ b/arch/x86/kernel/cpu/intel_pt.h
> @@ -25,32 +25,11 @@
> */
> #define TOPA_PMI_MARGIN 512
>
> -/*
> - * Table of Physical Addresses bits
> - */
> -enum topa_sz {
> - TOPA_4K = 0,
> - TOPA_8K,
> - TOPA_16K,
> - TOPA_32K,
> - TOPA_64K,
> - TOPA_128K,
> - TOPA_256K,
> - TOPA_512K,
> - TOPA_1MB,
> - TOPA_2MB,
> - TOPA_4MB,
> - TOPA_8MB,
> - TOPA_16MB,
> - TOPA_32MB,
> - TOPA_64MB,
> - TOPA_128MB,
> - TOPA_SZ_END,
> -};
> +#define TOPA_SHIFT PAGE_SHIFT
Even though TOPA_SHIFT happens to be the same as PAGE_SHIFT, it is a
property of a separate hardware block, not mmu. PAGE_SHIFT is 12, but
12 is not always PAGE_SHIFT.
> -static inline unsigned int sizes(enum topa_sz tsz)
> +static inline unsigned int sizes(unsigned int tsz)
> {
> - return 1 << (tsz + 12);
> + return 1 << (tsz + TOPA_SHIFT);
> };
>
> struct topa_entry {
> @@ -66,8 +45,8 @@ struct topa_entry {
> u64 rsvd4 : 16;
> };
>
> -#define TOPA_SHIFT 12
> -#define PT_CPUID_LEAVES 2
> +#define PT_CPUID_LEAVES 2
> +#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
>
> enum pt_capabilities {
> PT_CAP_max_subleaf = 0,
> @@ -79,7 +58,7 @@ enum pt_capabilities {
>
> struct pt_pmu {
> struct pmu pmu;
> - u32 caps[4 * PT_CPUID_LEAVES];
> + u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
> };
>
> /**
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_pt.c b/arch/x86/kernel/cpu/perf_event_intel_pt.c
> index 183de71..1e7d89e 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_pt.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_pt.c
> @@ -37,9 +37,9 @@ static struct pt_pmu pt_pmu;
>
> enum cpuid_regs {
> CR_EAX = 0,
> + CR_EBX,
> CR_ECX,
> - CR_EDX,
> - CR_EBX
> + CR_EDX
> };
This doesn't seem necessary.
Thanks,
--
Alex
On Mon, Aug 03, 2015 at 12:03:13PM +0300, Alexander Shishkin wrote:
> Takao Indoh <[email protected]> writes:
> Even though TOPA_SHIFT happens to be the same as PAGE_SHIFT, it is a
> property of a separate hardware block, not mmu. PAGE_SHIFT is 12, but
> 12 is not always PAGE_SHIFT.
PAGE_SHIFT is _always_ 12 on x86. Changing that will require changing
the page table format, a rather unlikely thing to go happen.
> > diff --git a/arch/x86/kernel/cpu/perf_event_intel_pt.c b/arch/x86/kernel/cpu/perf_event_intel_pt.c
> > index 183de71..1e7d89e 100644
> > --- a/arch/x86/kernel/cpu/perf_event_intel_pt.c
> > +++ b/arch/x86/kernel/cpu/perf_event_intel_pt.c
> > @@ -37,9 +37,9 @@ static struct pt_pmu pt_pmu;
> >
> > enum cpuid_regs {
> > CR_EAX = 0,
> > + CR_EBX,
> > CR_ECX,
> > - CR_EDX,
> > - CR_EBX
> > + CR_EDX
> > };
>
> This doesn't seem necessary.
For those of us suffering OCDs and all, its a good change though. The
alfabet song does go: A, B, C, D etc.. after all. Not: A, C, D, B ...
On 3 August 2015 at 12:08, Peter Zijlstra <[email protected]> wrote:
> On Mon, Aug 03, 2015 at 12:03:13PM +0300, Alexander Shishkin wrote:
>> Takao Indoh <[email protected]> writes:
>
>> Even though TOPA_SHIFT happens to be the same as PAGE_SHIFT, it is a
>> property of a separate hardware block, not mmu. PAGE_SHIFT is 12, but
>> 12 is not always PAGE_SHIFT.
>
> PAGE_SHIFT is _always_ 12 on x86. Changing that will require changing
> the page table format, a rather unlikely thing to go happen.
Of course. Yet that doesn't justify turning every 12 into PAGE_SHIFT
is what I'm saying.
Oh, look, it's PAGE_SHIFT o'clock on x86, time for lunch. :)
Regards,
--
Alex
On Mon, Aug 03, 2015 at 11:08:07AM +0200, Peter Zijlstra wrote:
> For those of us suffering OCDs and all, its a good change though. The
> alfabet song does go: A, B, C, D etc.. after all. Not: A, C, D, B ...
... except that x86 encoding orders regs like it was originally: AX,
CX, DX, BX, ... Don't ask me why - looks like someone thought that the
C (count) and D (double precision - AX extension) registers were more
important than B (base).
Or someone was simply illiterate.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
On 2015/08/03 18:44, Alexander Shishkin wrote:
> On 3 August 2015 at 12:08, Peter Zijlstra <[email protected]> wrote:
>> On Mon, Aug 03, 2015 at 12:03:13PM +0300, Alexander Shishkin wrote:
>>> Takao Indoh <[email protected]> writes:
>>
>>> Even though TOPA_SHIFT happens to be the same as PAGE_SHIFT, it is a
>>> property of a separate hardware block, not mmu. PAGE_SHIFT is 12, but
>>> 12 is not always PAGE_SHIFT.
>>
>> PAGE_SHIFT is _always_ 12 on x86. Changing that will require changing
>> the page table format, a rather unlikely thing to go happen.
>
> Of course. Yet that doesn't justify turning every 12 into PAGE_SHIFT
> is what I'm saying.
>
> Oh, look, it's PAGE_SHIFT o'clock on x86, time for lunch. :)
I thought the base address of output region is page aligned. I took a
look at Intel SDM again, it just says the base address is 4K-aligned
physical address, does not mention page size. So, logically TOPA_SHIFT
and PAGE_SHIFT are different things and I'll remove this change in next
version.
Thanks,
Takao Indoh
>
> Regards,
> --
> Alex
>
On 2015/08/03 20:03, Borislav Petkov wrote:
> On Mon, Aug 03, 2015 at 11:08:07AM +0200, Peter Zijlstra wrote:
>> For those of us suffering OCDs and all, its a good change though. The
>> alfabet song does go: A, B, C, D etc.. after all. Not: A, C, D, B ...
>
> ... except that x86 encoding orders regs like it was originally: AX,
> CX, DX, BX, ... Don't ask me why - looks like someone thought that the
> C (count) and D (double precision - AX extension) registers were more
> important than B (base).
>
> Or someone was simply illiterate.
>
I thought this was typo. If it is intentional, I'll keep it intact.
Thanks,
Takao Indoh