This patch set aims to add the necessary DTS nodes to complete the
MAC/PCS/PHY representation on DPAA2 devices. The external MDIO bus nodes
and the PHYs found on them are added, along with the PCS MDIO internal
buses and their PCS PHYs. Also, links to these PHYs are added from the
DPMAC node.
Ioana Ciornei (9):
arm64: dts: ls1088a: add external MDIO device nodes
arm64: dts: ls1088ardb: add QSGMII PHY nodes
arm64: dts: ls1088ardb: add necessary DTS nodes for DPMAC2
arm64: dts: ls208xa: add the external MDIO nodes
arm64: dts: ls2088ardb: add PHY nodes for the CS4340 PHYs
arm64: dts: ls2088ardb: add PHY nodes for the AQR405 PHYs
arm64: dts: ls208xa: add PCS MDIO and PCS PHY nodes
arm64: dts: lx2160a: add PCS MDIO and PCS PHY nodes
arm64: dts: lx2160ardb: add nodes for the AQR107 PHYs
.../boot/dts/freescale/fsl-ls1088a-rdb.dts | 119 +++++++++
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 81 ++++++
.../boot/dts/freescale/fsl-ls2088a-rdb.dts | 118 ++++++++
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 242 +++++++++++++++++
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 32 +++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 252 ++++++++++++++++++
6 files changed, 844 insertions(+)
--
2.25.1
Annotate the EMDIO1 node and describe the 2 AQR107 PHYs found on the
LX2160ARDB board. Also, add the necessary phy-handles for DPMACs 3 and 4
to their associated PHY.
Signed-off-by: Ioana Ciornei <[email protected]>
---
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 54fe8cd3a711..7723ad5efd37 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -35,6 +35,18 @@ &crypto {
status = "okay";
};
+&dpmac3 {
+ phy-handle = <&aquantia_phy1>;
+ phy-connection-type = "usxgmii";
+ managed = "in-band-status";
+};
+
+&dpmac4 {
+ phy-handle = <&aquantia_phy2>;
+ phy-connection-type = "usxgmii";
+ managed = "in-band-status";
+};
+
&dpmac17 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
@@ -61,6 +73,18 @@ rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
eee-broken-1000t;
};
+
+ aquantia_phy1: ethernet-phy@4 {
+ /* AQR107 PHY */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x4>;
+ };
+
+ aquantia_phy2: ethernet-phy@5 {
+ /* AQR107 PHY */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x5>;
+ };
};
&esdhc0 {
@@ -156,6 +180,14 @@ rtc@51 {
};
};
+&pcs_mdio3 {
+ status = "okay";
+};
+
+&pcs_mdio4 {
+ status = "okay";
+};
+
&sata0 {
status = "okay";
};
--
2.25.1
Add PCS MDIO nodes for the internal MDIO buses on the LX2160A, along
with their internal PCS PHYs, which will be used when the DPMAC is
in TYPE_PHY mode.
Signed-off-by: Ioana Ciornei <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 252 ++++++++++++++++++
1 file changed, 252 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index d247e4228d60..a7f808a96dc4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1305,6 +1305,240 @@ emdio2: mdio@8b97000 {
status = "disabled";
};
+ pcs_mdio1: mdio@8c07000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c07000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs1: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio2: mdio@8c0b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs2: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio3: mdio@8c0f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs3: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio4: mdio@8c13000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c13000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs4: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio5: mdio@8c17000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c17000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs5: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio6: mdio@8c1b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs6: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio7: mdio@8c1f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs7: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio8: mdio@8c23000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c23000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs8: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio9: mdio@8c27000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c27000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs9: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio10: mdio@8c2b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c2b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs10: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio11: mdio@8c2f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c2f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs11: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio12: mdio@8c33000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c33000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs12: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio13: mdio@8c37000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c37000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs13: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio14: mdio@8c3b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c3b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs14: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio15: mdio@8c3f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c3f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs15: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio16: mdio@8c43000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c43000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs16: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio17: mdio@8c47000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c47000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs17: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio18: mdio@8c4b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c4b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs18: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
@@ -1333,91 +1567,109 @@ dpmacs {
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x1>;
+ pcs-handle = <&pcs1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x2>;
+ pcs-handle = <&pcs2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
+ pcs-handle = <&pcs3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x4>;
+ pcs-handle = <&pcs4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x5>;
+ pcs-handle = <&pcs5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x6>;
+ pcs-handle = <&pcs6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x7>;
+ pcs-handle = <&pcs7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x8>;
+ pcs-handle = <&pcs8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x9>;
+ pcs-handle = <&pcs9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
+ pcs-handle = <&pcs10>;
};
dpmac11: dpmac@b {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xb>;
+ pcs-handle = <&pcs11>;
};
dpmac12: dpmac@c {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xc>;
+ pcs-handle = <&pcs12>;
};
dpmac13: dpmac@d {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xd>;
+ pcs-handle = <&pcs13>;
};
dpmac14: dpmac@e {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xe>;
+ pcs-handle = <&pcs14>;
};
dpmac15: dpmac@f {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xf>;
+ pcs-handle = <&pcs15>;
};
dpmac16: dpmac@10 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x10>;
+ pcs-handle = <&pcs16>;
};
dpmac17: dpmac@11 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x11>;
+ pcs-handle = <&pcs17>;
};
dpmac18: dpmac@12 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x12>;
+ pcs-handle = <&pcs18>;
};
};
};
--
2.25.1
Add the external MDIO device nodes found in the WRIOP global memory
region. This is needed for management of external PHYs.
Signed-off-by: Ioana Ciornei <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e1..d906d05e6a51 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -335,6 +335,24 @@ ptp-timer@8b95000 {
fsl,extts-fifo;
};
+ emdio1: mdio@0x8B96000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B96000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ emdio2: mdio@0x8B97000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8B97000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
--
2.25.1
Add PCS MDIO nodes for the internal MDIO buses on the LS208x SoCs, along
with their internal PCS PHYs which will be used when the DPMAC object is
in TYPE_PHY mode.
Signed-off-by: Ioana Ciornei <[email protected]>
---
.../boot/dts/freescale/fsl-ls2088a-rdb.dts | 32 +++
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 224 ++++++++++++++++++
2 files changed, 256 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
index 0492c9f76490..20e14d1a3caa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
@@ -108,3 +108,35 @@ mdio2_phy4: emdio2_phy@4 {
phy-connection-type = "10gbase-r";
};
};
+
+&pcs_mdio1 {
+ status = "okay";
+};
+
+&pcs_mdio2 {
+ status = "okay";
+};
+
+&pcs_mdio3 {
+ status = "okay";
+};
+
+&pcs_mdio4 {
+ status = "okay";
+};
+
+&pcs_mdio5 {
+ status = "okay";
+};
+
+&pcs_mdio6 {
+ status = "okay";
+};
+
+&pcs_mdio7 {
+ status = "okay";
+};
+
+&pcs_mdio8 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index d906d05e6a51..80ec981526d1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -353,6 +353,214 @@ emdio2: mdio@0x8B97000 {
status = "disabled";
};
+ pcs_mdio1: mdio@8c07000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c07000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs1: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio2: mdio@8c0b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs2: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio3: mdio@8c0f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs3: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio4: mdio@8c13000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c13000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs4: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio5: mdio@8c17000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c17000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs5: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio6: mdio@8c1b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs6: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio7: mdio@8c1f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs7: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio8: mdio@8c23000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c23000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs8: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio9: mdio@8c27000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c27000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs9: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio10: mdio@8c2b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c2b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs10: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio11: mdio@8c2f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c2f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs11: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio12: mdio@8c33000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c33000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs12: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio13: mdio@8c37000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c37000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs13: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio14: mdio@8c3b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c3b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs14: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio15: mdio@8c3f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c3f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs15: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
+ pcs_mdio16: mdio@8c43000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c43000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs16: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
@@ -380,81 +588,97 @@ dpmacs {
dpmac1: dpmac@1 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x1>;
+ pcs-handle = <&pcs1>;
};
dpmac2: dpmac@2 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x2>;
+ pcs-handle = <&pcs2>;
};
dpmac3: dpmac@3 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x3>;
+ pcs-handle = <&pcs3>;
};
dpmac4: dpmac@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x4>;
+ pcs-handle = <&pcs4>;
};
dpmac5: dpmac@5 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x5>;
+ pcs-handle = <&pcs5>;
};
dpmac6: dpmac@6 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x6>;
+ pcs-handle = <&pcs6>;
};
dpmac7: dpmac@7 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x7>;
+ pcs-handle = <&pcs7>;
};
dpmac8: dpmac@8 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x8>;
+ pcs-handle = <&pcs8>;
};
dpmac9: dpmac@9 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x9>;
+ pcs-handle = <&pcs9>;
};
dpmac10: dpmac@a {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xa>;
+ pcs-handle = <&pcs10>;
};
dpmac11: dpmac@b {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xb>;
+ pcs-handle = <&pcs11>;
};
dpmac12: dpmac@c {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xc>;
+ pcs-handle = <&pcs12>;
};
dpmac13: dpmac@d {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xd>;
+ pcs-handle = <&pcs13>;
};
dpmac14: dpmac@e {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xe>;
+ pcs-handle = <&pcs14>;
};
dpmac15: dpmac@f {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0xf>;
+ pcs-handle = <&pcs15>;
};
dpmac16: dpmac@10 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x10>;
+ pcs-handle = <&pcs16>;
};
};
};
--
2.25.1
Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found on
the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its
associated PHY. Also, add the internal PCS MDIO nodes for the internal
MDIO buses found on the LS1088A SoC along with their internal PCS PHY
and link the corresponding DPMAC to the PCS through the pcs-handle.
Signed-off-by: Ioana Ciornei <[email protected]>
---
.../boot/dts/freescale/fsl-ls1088a-rdb.dts | 100 ++++++++++++++++++
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 50 +++++++++
2 files changed, 150 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 5633e59febc3..d7886b084f7f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -17,6 +17,98 @@ / {
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
};
+&dpmac3 {
+ phy-handle = <&mdio1_phy5>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs3_0>;
+};
+
+&dpmac4 {
+ phy-handle = <&mdio1_phy6>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs3_1>;
+};
+
+&dpmac5 {
+ phy-handle = <&mdio1_phy7>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs3_2>;
+};
+
+&dpmac6 {
+ phy-handle = <&mdio1_phy8>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs3_3>;
+};
+
+&dpmac7 {
+ phy-handle = <&mdio1_phy1>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs7_0>;
+};
+
+&dpmac8 {
+ phy-handle = <&mdio1_phy2>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs7_1>;
+};
+
+&dpmac9 {
+ phy-handle = <&mdio1_phy3>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs7_2>;
+};
+
+&dpmac10 {
+ phy-handle = <&mdio1_phy4>;
+ phy-connection-type = "qsgmii";
+ managed = "in-band-status";
+ pcs-handle = <&pcs7_3>;
+};
+
+&emdio1 {
+ status = "okay";
+
+ mdio1_phy1: emdio1_phy@1 {
+ reg = <0x1c>;
+ };
+
+ mdio1_phy2: emdio1_phy@2 {
+ reg = <0x1d>;
+ };
+
+ mdio1_phy3: emdio1_phy@3 {
+ reg = <0x1e>;
+ };
+
+ mdio1_phy4: emdio1_phy@4 {
+ reg = <0x1f>;
+ };
+
+ mdio1_phy5: emdio1_phy@5 {
+ reg = <0x0c>;
+ };
+
+ mdio1_phy6: emdio1_phy@6 {
+ reg = <0x0d>;
+ };
+
+ mdio1_phy7: emdio1_phy@7 {
+ reg = <0x0e>;
+ };
+
+ mdio1_phy8: emdio1_phy@8 {
+ reg = <0x0f>;
+ };
+};
+
&i2c0 {
status = "okay";
@@ -87,6 +179,14 @@ &esdhc {
status = "okay";
};
+&pcs_mdio3 {
+ status = "okay";
+};
+
+&pcs_mdio7 {
+ status = "okay";
+};
+
&qspi {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 22544e3b7737..ad8679e58f9a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -672,6 +672,56 @@ emdio2: mdio@0x8B97000 {
status = "disabled";
};
+ pcs_mdio3: mdio@8c0f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs3_0: pcs-phy@0 {
+ reg = <0>;
+ };
+
+ pcs3_1: pcs-phy@1 {
+ reg = <1>;
+ };
+
+ pcs3_2: pcs-phy@2 {
+ reg = <2>;
+ };
+
+ pcs3_3: pcs-phy@3 {
+ reg = <3>;
+ };
+ };
+
+ pcs_mdio7: mdio@8c1f000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c1f000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs7_0: pcs-phy@0 {
+ reg = <0>;
+ };
+
+ pcs7_1: pcs-phy@1 {
+ reg = <1>;
+ };
+
+ pcs7_2: pcs-phy@2 {
+ reg = <2>;
+ };
+
+ pcs7_3: pcs-phy@3 {
+ reg = <3>;
+ };
+ };
+
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
--
2.25.1
Annotate the external MDIO2 node and describe the 10GBASER PHY found on
the LS1088ARDB board and add a phy-handle for DPMAC2 to link it.
Also, add the internal PCS MDIO node for the internal MDIO buses found
on the LS1088A SoC along with its internal PCS PHY and link the
corresponding DPMAC to the PCS through the pcs-handle.
Signed-off-by: Ioana Ciornei <[email protected]>
---
.../boot/dts/freescale/fsl-ls1088a-rdb.dts | 19 +++++++++++++++++++
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 13 +++++++++++++
2 files changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index d7886b084f7f..661898064f0c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -17,6 +17,12 @@ / {
compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
};
+&dpmac2 {
+ phy-handle = <&mdio2_aquantia_phy>;
+ phy-connection-type = "10gbase-r";
+ pcs-handle = <&pcs2>;
+};
+
&dpmac3 {
phy-handle = <&mdio1_phy5>;
phy-connection-type = "qsgmii";
@@ -109,6 +115,15 @@ mdio1_phy8: emdio1_phy@8 {
};
};
+&emdio2 {
+ status = "okay";
+
+ mdio2_aquantia_phy: emdio2_aquantia@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+ };
+};
+
&i2c0 {
status = "okay";
@@ -179,6 +194,10 @@ &esdhc {
status = "okay";
};
+&pcs_mdio2 {
+ status = "okay";
+};
+
&pcs_mdio3 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index ad8679e58f9a..837d53472000 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -672,6 +672,19 @@ emdio2: mdio@0x8B97000 {
status = "disabled";
};
+ pcs_mdio2: mdio@8c0b000 {
+ compatible = "fsl,fman-memac-mdio";
+ reg = <0x0 0x8c0b000 0x0 0x1000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pcs2: pcs-phy@0 {
+ reg = <0>;
+ };
+ };
+
pcs_mdio3: mdio@8c0f000 {
compatible = "fsl,fman-memac-mdio";
reg = <0x0 0x8c0f000 0x0 0x1000>;
--
2.25.1
Annotate the EMDIO2 node and describe the other 4 10GBASER PHYs found on
the LS2088ARDB board. Also, add phy-handles for DPMACs 5-8 to their
associated PHY.
Signed-off-by: Ioana Ciornei <[email protected]>
---
.../boot/dts/freescale/fsl-ls2088a-rdb.dts | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
index 0d1935fcd201..0492c9f76490 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
@@ -39,6 +39,22 @@ &dpmac4 {
phy-handle = <&mdio1_phy4>;
};
+&dpmac5 {
+ phy-handle = <&mdio2_phy1>;
+};
+
+&dpmac6 {
+ phy-handle = <&mdio2_phy2>;
+};
+
+&dpmac7 {
+ phy-handle = <&mdio2_phy3>;
+};
+
+&dpmac8 {
+ phy-handle = <&mdio2_phy4>;
+};
+
&emdio1 {
status = "okay";
@@ -63,3 +79,32 @@ mdio1_phy4: emdio1_phy@4 {
phy-connection-type = "10gbase-r";
};
};
+
+&emdio2 {
+ status = "okay";
+
+ mdio2_phy1: emdio2_phy@1 {
+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 1 0x4>;
+ reg = <0x0>;
+ phy-connection-type = "10gbase-r";
+ };
+ mdio2_phy2: emdio2_phy@2 {
+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>;
+ reg = <0x1>;
+ phy-connection-type = "10gbase-r";
+ };
+ mdio2_phy3: emdio2_phy@3 {
+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 4 0x4>;
+ reg = <0x2>;
+ phy-connection-type = "10gbase-r";
+ };
+ mdio2_phy4: emdio2_phy@4 {
+ compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 5 0x4>;
+ reg = <0x3>;
+ phy-connection-type = "10gbase-r";
+ };
+};
--
2.25.1
On Fri, Sep 25, 2020 at 04:24:56PM +0300, Ioana Ciornei wrote:
> Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found on
> the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its
> associated PHY. Also, add the internal PCS MDIO nodes for the internal
> MDIO buses found on the LS1088A SoC along with their internal PCS PHY
> and link the corresponding DPMAC to the PCS through the pcs-handle.
>
> Signed-off-by: Ioana Ciornei <[email protected]>
> ---
> .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 100 ++++++++++++++++++
> .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 50 +++++++++
> 2 files changed, 150 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> index 5633e59febc3..d7886b084f7f 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> @@ -17,6 +17,98 @@ / {
> compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
> };
>
> +&dpmac3 {
> + phy-handle = <&mdio1_phy5>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs3_0>;
> +};
> +
> +&dpmac4 {
> + phy-handle = <&mdio1_phy6>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs3_1>;
> +};
> +
> +&dpmac5 {
> + phy-handle = <&mdio1_phy7>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs3_2>;
> +};
> +
> +&dpmac6 {
> + phy-handle = <&mdio1_phy8>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs3_3>;
> +};
> +
> +&dpmac7 {
> + phy-handle = <&mdio1_phy1>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs7_0>;
> +};
> +
> +&dpmac8 {
> + phy-handle = <&mdio1_phy2>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs7_1>;
> +};
> +
> +&dpmac9 {
> + phy-handle = <&mdio1_phy3>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs7_2>;
> +};
> +
> +&dpmac10 {
> + phy-handle = <&mdio1_phy4>;
> + phy-connection-type = "qsgmii";
> + managed = "in-band-status";
> + pcs-handle = <&pcs7_3>;
> +};
> +
> +&emdio1 {
> + status = "okay";
> +
> + mdio1_phy1: emdio1_phy@1 {
If this is an Ethernet PHY device, please use generic node name like
'ethernet-phy'. Also the unit-address in node name should match 'reg'
property.
> + reg = <0x1c>;
> + };
> +
> + mdio1_phy2: emdio1_phy@2 {
> + reg = <0x1d>;
> + };
> +
> + mdio1_phy3: emdio1_phy@3 {
> + reg = <0x1e>;
> + };
> +
> + mdio1_phy4: emdio1_phy@4 {
> + reg = <0x1f>;
> + };
> +
> + mdio1_phy5: emdio1_phy@5 {
> + reg = <0x0c>;
> + };
> +
> + mdio1_phy6: emdio1_phy@6 {
> + reg = <0x0d>;
> + };
> +
> + mdio1_phy7: emdio1_phy@7 {
> + reg = <0x0e>;
> + };
> +
> + mdio1_phy8: emdio1_phy@8 {
> + reg = <0x0f>;
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> @@ -87,6 +179,14 @@ &esdhc {
> status = "okay";
> };
>
> +&pcs_mdio3 {
> + status = "okay";
> +};
> +
> +&pcs_mdio7 {
> + status = "okay";
> +};
> +
> &qspi {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index 22544e3b7737..ad8679e58f9a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -672,6 +672,56 @@ emdio2: mdio@0x8B97000 {
> status = "disabled";
> };
>
> + pcs_mdio3: mdio@8c0f000 {
> + compatible = "fsl,fman-memac-mdio";
> + reg = <0x0 0x8c0f000 0x0 0x1000>;
> + little-endian;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + pcs3_0: pcs-phy@0 {
ethernet-phy@0?
Shawn
> + reg = <0>;
> + };
> +
> + pcs3_1: pcs-phy@1 {
> + reg = <1>;
> + };
> +
> + pcs3_2: pcs-phy@2 {
> + reg = <2>;
> + };
> +
> + pcs3_3: pcs-phy@3 {
> + reg = <3>;
> + };
> + };
> +
> + pcs_mdio7: mdio@8c1f000 {
> + compatible = "fsl,fman-memac-mdio";
> + reg = <0x0 0x8c1f000 0x0 0x1000>;
> + little-endian;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + pcs7_0: pcs-phy@0 {
> + reg = <0>;
> + };
> +
> + pcs7_1: pcs-phy@1 {
> + reg = <1>;
> + };
> +
> + pcs7_2: pcs-phy@2 {
> + reg = <2>;
> + };
> +
> + pcs7_3: pcs-phy@3 {
> + reg = <3>;
> + };
> + };
> +
> cluster1_core0_watchdog: wdt@c000000 {
> compatible = "arm,sp805-wdt", "arm,primecell";
> reg = <0x0 0xc000000 0x0 0x1000>;
> --
> 2.25.1
>
On Fri, Oct 30, 2020 at 08:07:26AM +0800, Shawn Guo wrote:
> On Fri, Sep 25, 2020 at 04:24:56PM +0300, Ioana Ciornei wrote:
> > Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found on
> > the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its
> > associated PHY. Also, add the internal PCS MDIO nodes for the internal
> > MDIO buses found on the LS1088A SoC along with their internal PCS PHY
> > and link the corresponding DPMAC to the PCS through the pcs-handle.
> >
> > Signed-off-by: Ioana Ciornei <[email protected]>
> > ---
> > .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 100 ++++++++++++++++++
> > .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 50 +++++++++
> > 2 files changed, 150 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> > index 5633e59febc3..d7886b084f7f 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> > @@ -17,6 +17,98 @@ / {
> > compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
> > };
(...)
> > +&emdio1 {
> > + status = "okay";
> > +
> > + mdio1_phy1: emdio1_phy@1 {
>
> If this is an Ethernet PHY device, please use generic node name like
> 'ethernet-phy'. Also the unit-address in node name should match 'reg'
> property.
Yes, it is. I'll rename them and use the reg as the unit-address.
(...)
> > + pcs_mdio3: mdio@8c0f000 {
> > + compatible = "fsl,fman-memac-mdio";
> > + reg = <0x0 0x8c0f000 0x0 0x1000>;
> > + little-endian;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > +
> > + pcs3_0: pcs-phy@0 {
>
> ethernet-phy@0?
>
Will change.
Ioana