Add DT Binding doc for the Unique ID of i.MX 8M series.
Signed-off-by: Alice Guo <[email protected]>
---
.../devicetree/bindings/arm/fsl.yaml | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index e4db0f9ed664..0419f078502b 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -901,6 +901,39 @@ properties:
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
- const: fsl,s32v234
+ soc:
+ description:
+ i.MX8M Family SoC must provide a soc node in the root of the device tree,
+ representing the System-on-Chip since these test chips are rather complex.
+ type: object
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,imx8mm-soc
+ - const: simple-bus
+ - items:
+ - const: fsl,imx8mn-soc
+ - const: simple-bus
+ - items:
+ - const: fsl,imx8mp-soc
+ - const: simple-bus
+ - items:
+ - const: fsl,imx8mq-soc
+ - const: simple-bus
+
+ nvmem-cells:
+ maxItems: 1
+ description: Phandle to the SOC Unique ID provided by a nvmem node
+
+ nvmem-cells-names:
+ const: soc_unique_id
+
+ required:
+ - compatible
+ - nvmem-cells
+ - nvmem-cell-names
+
additionalProperties: true
...
--
2.17.1
Add compatible string to .dtsi file for binding of imx8_soc_init_driver
and device.
Signed-off-by: Alice Guo <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 033fee525982..cd9a77d763eb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -257,7 +257,7 @@
};
soc@0 {
- compatible = "simple-bus";
+ compatible = "fsl,imx8mm-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index a06d2a6268e6..6d3a809a00fd 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -241,7 +241,7 @@
};
soc@0 {
- compatible = "simple-bus";
+ compatible = "fsl,imx8mn-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 479312293036..9cd218f5f004 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -218,7 +218,7 @@
};
soc@0 {
- compatible = "simple-bus";
+ compatible = "fsl,imx8mp-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index a841a023e8e0..9b6d9307e5d7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -286,7 +286,7 @@
};
soc@0 {
- compatible = "simple-bus";
+ compatible = "fsl,imx8mq-soc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
--
2.17.1
Add nvmem-cell related stuff for the soc unique ID.
Signed-off-by: Alice Guo <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 6 ++++++
4 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index cd9a77d763eb..d4aec3eae147 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -261,6 +261,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ nvmem-cells = <&imx8mm_uid>;
+ nvmem-cell-names = "soc_unique_id";
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
@@ -518,6 +520,10 @@
#address-cells = <1>;
#size-cells = <1>;
+ imx8mm_uid: unique_id@410 {
+ reg = <0x4 0x8>;
+ };
+
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 6d3a809a00fd..ff12194b60a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -245,6 +245,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ nvmem-cells = <&imx8mn_uid>;
+ nvmem-cell-names = "soc_unique_id";
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
@@ -388,6 +390,10 @@
#address-cells = <1>;
#size-cells = <1>;
+ imx8mn_uid: unique_id@410 {
+ reg = <0x4 0x8>;
+ };
+
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9cd218f5f004..3db59f61e871 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -222,6 +222,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ nvmem-cells = <&imx8mp_uid>;
+ nvmem-cell-names = "soc_unique_id";
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
@@ -328,6 +330,10 @@
#address-cells = <1>;
#size-cells = <1>;
+ imx8mp_uid: unique_id@420 {
+ reg = <0x8 0x8>;
+ };
+
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9b6d9307e5d7..6db5cba9c07d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -291,6 +291,8 @@
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
+ nvmem-cells = <&imx8mq_uid>;
+ nvmem-cell-names = "soc_unique_id";
bus@30000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
@@ -555,6 +557,10 @@
#address-cells = <1>;
#size-cells = <1>;
+ imx8mq_uid: soc_uid@410 {
+ reg = <0x4 0x8>;
+ };
+
cpu_speed_grade: speed-grade@10 {
reg = <0x10 4>;
};
--
2.17.1
Directly reading ocotp register depends on that bootloader enables ocotp
clk, which is not always effective, so change to use nvmem API. Using
nvmem API requires to support driver defer probe and thus change
soc-imx8m.c to use platform driver.
The other reason is that directly reading ocotp register causes kexec
kernel hang because the 1st kernel running will disable unused clks
after kernel boots up, and then ocotp clk will be disabled even if
bootloader enables it. When kexec kernel, ocotp clk needs to be enabled
before reading ocotp registers, and nvmem API with platform driver
supported can accomplish this.
Signed-off-by: Alice Guo <[email protected]>
---
drivers/soc/imx/soc-imx8m.c | 75 +++++++++++++++++++++----------------
1 file changed, 42 insertions(+), 33 deletions(-)
diff --git a/drivers/soc/imx/soc-imx8m.c b/drivers/soc/imx/soc-imx8m.c
index cc57a384d74d..83f3297509be 100644
--- a/drivers/soc/imx/soc-imx8m.c
+++ b/drivers/soc/imx/soc-imx8m.c
@@ -5,6 +5,8 @@
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
@@ -29,7 +31,7 @@
struct imx8_soc_data {
char *name;
- u32 (*soc_revision)(void);
+ u32 (*soc_revision)(struct device *dev);
};
static u64 soc_uid;
@@ -50,12 +52,15 @@ static u32 imx8mq_soc_revision_from_atf(void)
static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
#endif
-static u32 __init imx8mq_soc_revision(void)
+static u32 __init imx8mm_soc_uid(struct device *dev);
+
+static u32 __init imx8mq_soc_revision(struct device *dev)
{
struct device_node *np;
void __iomem *ocotp_base;
u32 magic;
u32 rev;
+ int ret = 0;
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
if (!np)
@@ -75,9 +80,9 @@ static u32 __init imx8mq_soc_revision(void)
rev = REV_B1;
}
- soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
- soc_uid <<= 32;
- soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
+ ret = imx8mm_soc_uid(dev);
+ if (ret)
+ return ret;
iounmap(ocotp_base);
of_node_put(np);
@@ -85,33 +90,20 @@ static u32 __init imx8mq_soc_revision(void)
return rev;
}
-static void __init imx8mm_soc_uid(void)
+static u32 __init imx8mm_soc_uid(struct device *dev)
{
- void __iomem *ocotp_base;
- struct device_node *np;
- u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
- IMX8MP_OCOTP_UID_OFFSET : 0;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
- if (!np)
- return;
-
- ocotp_base = of_iomap(np, 0);
- WARN_ON(!ocotp_base);
-
- soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
- soc_uid <<= 32;
- soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
+ int ret = 0;
- iounmap(ocotp_base);
- of_node_put(np);
+ ret = nvmem_cell_read_u64(dev, "soc_unique_id", &soc_uid);
+ return ret;
}
-static u32 __init imx8mm_soc_revision(void)
+static u32 __init imx8mm_soc_revision(struct device *dev)
{
struct device_node *np;
void __iomem *anatop_base;
u32 rev;
+ int ret;
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
if (!np)
@@ -125,7 +117,9 @@ static u32 __init imx8mm_soc_revision(void)
iounmap(anatop_base);
of_node_put(np);
- imx8mm_soc_uid();
+ ret = imx8mm_soc_uid(dev);
+ if (ret)
+ return ret;
return rev;
}
@@ -151,19 +145,20 @@ static const struct imx8_soc_data imx8mp_soc_data = {
};
static __maybe_unused const struct of_device_id imx8_soc_match[] = {
- { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
- { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
- { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
- { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
+ { .compatible = "fsl,imx8mq-soc", .data = &imx8mq_soc_data, },
+ { .compatible = "fsl,imx8mm-soc", .data = &imx8mm_soc_data, },
+ { .compatible = "fsl,imx8mn-soc", .data = &imx8mn_soc_data, },
+ { .compatible = "fsl,imx8mp-soc", .data = &imx8mp_soc_data, },
{ }
};
+MODULE_DEVICE_TABLE(of, imx8_soc_match);
#define imx8_revision(soc_rev) \
soc_rev ? \
kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \
"unknown"
-static int __init imx8_soc_init(void)
+static int imx8_soc_init_probe(struct platform_device *pdev)
{
struct soc_device_attribute *soc_dev_attr;
struct soc_device *soc_dev;
@@ -182,7 +177,7 @@ static int __init imx8_soc_init(void)
if (ret)
goto free_soc;
- id = of_match_node(imx8_soc_match, of_root);
+ id = of_match_node(imx8_soc_match, pdev->dev.of_node);
if (!id) {
ret = -ENODEV;
goto free_soc;
@@ -192,7 +187,11 @@ static int __init imx8_soc_init(void)
if (data) {
soc_dev_attr->soc_id = data->name;
if (data->soc_revision)
- soc_rev = data->soc_revision();
+ soc_rev = data->soc_revision(&pdev->dev);
+
+ ret = soc_rev;
+ if (ret < 0)
+ goto free_soc;
}
soc_dev_attr->revision = imx8_revision(soc_rev);
@@ -230,4 +229,14 @@ static int __init imx8_soc_init(void)
kfree(soc_dev_attr);
return ret;
}
-device_initcall(imx8_soc_init);
+
+static struct platform_driver imx8_soc_init_driver = {
+ .probe = imx8_soc_init_probe,
+ .driver = {
+ .name = "imx8_soc_init",
+ .of_match_table = of_match_ptr(imx8_soc_match),
+ },
+};
+
+module_platform_driver(imx8_soc_init_driver);
+MODULE_LICENSE("GPL v2");
--
2.17.1
On Thu, Nov 05, 2020 at 03:26:26PM +0800, Alice Guo wrote:
> Add DT Binding doc for the Unique ID of i.MX 8M series.
>
> Signed-off-by: Alice Guo <[email protected]>
> ---
> .../devicetree/bindings/arm/fsl.yaml | 33 +++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index e4db0f9ed664..0419f078502b 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -901,6 +901,39 @@ properties:
> - fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
> - const: fsl,s32v234
>
> + soc:
> + description:
> + i.MX8M Family SoC must provide a soc node in the root of the device tree,
> + representing the System-on-Chip since these test chips are rather complex.
> + type: object
> + properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: fsl,imx8mm-soc
> + - const: simple-bus
> + - items:
> + - const: fsl,imx8mn-soc
> + - const: simple-bus
> + - items:
> + - const: fsl,imx8mp-soc
> + - const: simple-bus
> + - items:
> + - const: fsl,imx8mq-soc
> + - const: simple-bus
> +
> + nvmem-cells:
> + maxItems: 1
> + description: Phandle to the SOC Unique ID provided by a nvmem node
> +
> + nvmem-cells-names:
> + const: soc_unique_id
> +
> + required:
> + - compatible
> + - nvmem-cells
> + - nvmem-cell-names
> +
Did you actually test it? I see multiple errors with this patch.
fsl-ls1012a-frdm.dt.yaml: /: soc:compatible: ['simple-bus'] is not valid under any of the given schemas
Best regards,
Krzysztof
On Thu, Nov 05, 2020 at 03:26:29PM +0800, Alice Guo wrote:
> Directly reading ocotp register depends on that bootloader enables ocotp
> clk, which is not always effective, so change to use nvmem API. Using
> nvmem API requires to support driver defer probe and thus change
> soc-imx8m.c to use platform driver.
>
> The other reason is that directly reading ocotp register causes kexec
> kernel hang because the 1st kernel running will disable unused clks
> after kernel boots up, and then ocotp clk will be disabled even if
> bootloader enables it. When kexec kernel, ocotp clk needs to be enabled
> before reading ocotp registers, and nvmem API with platform driver
> supported can accomplish this.
>
> Signed-off-by: Alice Guo <[email protected]>
> ---
> drivers/soc/imx/soc-imx8m.c | 75 +++++++++++++++++++++----------------
> 1 file changed, 42 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/soc/imx/soc-imx8m.c b/drivers/soc/imx/soc-imx8m.c
> index cc57a384d74d..83f3297509be 100644
> --- a/drivers/soc/imx/soc-imx8m.c
> +++ b/drivers/soc/imx/soc-imx8m.c
> @@ -5,6 +5,8 @@
>
> #include <linux/init.h>
> #include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> #include <linux/of_address.h>
> #include <linux/slab.h>
> #include <linux/sys_soc.h>
> @@ -29,7 +31,7 @@
>
> struct imx8_soc_data {
> char *name;
> - u32 (*soc_revision)(void);
> + u32 (*soc_revision)(struct device *dev);
> };
>
> static u64 soc_uid;
> @@ -50,12 +52,15 @@ static u32 imx8mq_soc_revision_from_atf(void)
> static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
> #endif
>
> -static u32 __init imx8mq_soc_revision(void)
> +static u32 __init imx8mm_soc_uid(struct device *dev);
> +
> +static u32 __init imx8mq_soc_revision(struct device *dev)
> {
> struct device_node *np;
> void __iomem *ocotp_base;
> u32 magic;
> u32 rev;
> + int ret = 0;
>
> np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
> if (!np)
> @@ -75,9 +80,9 @@ static u32 __init imx8mq_soc_revision(void)
> rev = REV_B1;
> }
>
> - soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
> - soc_uid <<= 32;
> - soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
> + ret = imx8mm_soc_uid(dev);
> + if (ret)
> + return ret;
>
> iounmap(ocotp_base);
> of_node_put(np);
> @@ -85,33 +90,20 @@ static u32 __init imx8mq_soc_revision(void)
> return rev;
> }
>
> -static void __init imx8mm_soc_uid(void)
> +static u32 __init imx8mm_soc_uid(struct device *dev)
> {
> - void __iomem *ocotp_base;
> - struct device_node *np;
> - u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
> - IMX8MP_OCOTP_UID_OFFSET : 0;
> -
> - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
> - if (!np)
> - return;
> -
> - ocotp_base = of_iomap(np, 0);
> - WARN_ON(!ocotp_base);
> -
> - soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
> - soc_uid <<= 32;
> - soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
> + int ret = 0;
>
> - iounmap(ocotp_base);
> - of_node_put(np);
> + ret = nvmem_cell_read_u64(dev, "soc_unique_id", &soc_uid);
> + return ret;
> }
>
> -static u32 __init imx8mm_soc_revision(void)
> +static u32 __init imx8mm_soc_revision(struct device *dev)
> {
> struct device_node *np;
> void __iomem *anatop_base;
> u32 rev;
> + int ret;
>
> np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
> if (!np)
> @@ -125,7 +117,9 @@ static u32 __init imx8mm_soc_revision(void)
> iounmap(anatop_base);
> of_node_put(np);
>
> - imx8mm_soc_uid();
> + ret = imx8mm_soc_uid(dev);
> + if (ret)
> + return ret;
I think this breaks old existing DTBs. If applied on separate branch
than DTS patches, it will cause bisect regressions. Regardless of it,
all out-of-tree (customer DTBs) will start failing here as well.
Best regards,
Krzysztof
>
> return rev;
> }
> @@ -151,19 +145,20 @@ static const struct imx8_soc_data imx8mp_soc_data = {
> };
>
> static __maybe_unused const struct of_device_id imx8_soc_match[] = {
> - { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
> - { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
> - { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
> - { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
> + { .compatible = "fsl,imx8mq-soc", .data = &imx8mq_soc_data, },
> + { .compatible = "fsl,imx8mm-soc", .data = &imx8mm_soc_data, },
> + { .compatible = "fsl,imx8mn-soc", .data = &imx8mn_soc_data, },
> + { .compatible = "fsl,imx8mp-soc", .data = &imx8mp_soc_data, },
> { }
> };
> +MODULE_DEVICE_TABLE(of, imx8_soc_match);
>
> #define imx8_revision(soc_rev) \
> soc_rev ? \
> kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev & 0xf) : \
> "unknown"
>
> -static int __init imx8_soc_init(void)
> +static int imx8_soc_init_probe(struct platform_device *pdev)
> {
> struct soc_device_attribute *soc_dev_attr;
> struct soc_device *soc_dev;
> @@ -182,7 +177,7 @@ static int __init imx8_soc_init(void)
> if (ret)
> goto free_soc;
>
> - id = of_match_node(imx8_soc_match, of_root);
> + id = of_match_node(imx8_soc_match, pdev->dev.of_node);
> if (!id) {
> ret = -ENODEV;
> goto free_soc;
> @@ -192,7 +187,11 @@ static int __init imx8_soc_init(void)
> if (data) {
> soc_dev_attr->soc_id = data->name;
> if (data->soc_revision)
> - soc_rev = data->soc_revision();
> + soc_rev = data->soc_revision(&pdev->dev);
> +
> + ret = soc_rev;
> + if (ret < 0)
> + goto free_soc;
> }
>
> soc_dev_attr->revision = imx8_revision(soc_rev);
> @@ -230,4 +229,14 @@ static int __init imx8_soc_init(void)
> kfree(soc_dev_attr);
> return ret;
> }
> -device_initcall(imx8_soc_init);
> +
> +static struct platform_driver imx8_soc_init_driver = {
> + .probe = imx8_soc_init_probe,
> + .driver = {
> + .name = "imx8_soc_init",
> + .of_match_table = of_match_ptr(imx8_soc_match),
> + },
> +};
> +
> +module_platform_driver(imx8_soc_init_driver);
> +MODULE_LICENSE("GPL v2");
> --
> 2.17.1
>
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: 2020年11月5日 16:26
> To: Alice Guo <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> dl-linux-imx <[email protected]>; Peng Fan <[email protected]>;
> [email protected]; [email protected];
> [email protected]
> Subject: [EXT] Re: [PATCH v2 1/4] dt-bindings: soc: imx8m: add DT Binding doc
> for soc unique ID
>
> Caution: EXT Email
>
> On Thu, Nov 05, 2020 at 03:26:26PM +0800, Alice Guo wrote:
> > Add DT Binding doc for the Unique ID of i.MX 8M series.
> >
> > Signed-off-by: Alice Guo <[email protected]>
> > ---
> > .../devicetree/bindings/arm/fsl.yaml | 33
> +++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
> b/Documentation/devicetree/bindings/arm/fsl.yaml
> > index e4db0f9ed664..0419f078502b 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > @@ -901,6 +901,39 @@ properties:
> > - fsl,s32v234-evb # S32V234-EVB2 Customer
> Evaluation Board
> > - const: fsl,s32v234
> >
> > + soc:
> > + description:
> > + i.MX8M Family SoC must provide a soc node in the root of the device
> tree,
> > + representing the System-on-Chip since these test chips are rather
> complex.
> > + type: object
> > + properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: fsl,imx8mm-soc
> > + - const: simple-bus
> > + - items:
> > + - const: fsl,imx8mn-soc
> > + - const: simple-bus
> > + - items:
> > + - const: fsl,imx8mp-soc
> > + - const: simple-bus
> > + - items:
> > + - const: fsl,imx8mq-soc
> > + - const: simple-bus
> > +
> > + nvmem-cells:
> > + maxItems: 1
> > + description: Phandle to the SOC Unique ID provided by a nvmem
> node
> > +
> > + nvmem-cells-names:
> > + const: soc_unique_id
> > +
> > + required:
> > + - compatible
> > + - nvmem-cells
> > + - nvmem-cell-names
> > +
>
> Did you actually test it? I see multiple errors with this patch.
> fsl-ls1012a-frdm.dt.yaml: /: soc:compatible: ['simple-bus'] is not valid under any
> of the given schemas
>
> Best regards,
> Krzysztof
[Alice Guo] Sorry. I did not see errors what you said. Can you tell me how did you test it?
Best regards,
Alice Guo
On Thu, 5 Nov 2020 at 13:19, Alice Guo <[email protected]> wrote:
>
>
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <[email protected]>
> > Sent: 2020年11月5日 16:26
> > To: Alice Guo <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected];
> > dl-linux-imx <[email protected]>; Peng Fan <[email protected]>;
> > [email protected]; [email protected];
> > [email protected]
> > Subject: [EXT] Re: [PATCH v2 1/4] dt-bindings: soc: imx8m: add DT Binding doc
> > for soc unique ID
> >
> > Caution: EXT Email
> >
> > On Thu, Nov 05, 2020 at 03:26:26PM +0800, Alice Guo wrote:
> > > Add DT Binding doc for the Unique ID of i.MX 8M series.
> > >
> > > Signed-off-by: Alice Guo <[email protected]>
> > > ---
> > > .../devicetree/bindings/arm/fsl.yaml | 33
> > +++++++++++++++++++
> > > 1 file changed, 33 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
> > b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > index e4db0f9ed664..0419f078502b 100644
> > > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > > @@ -901,6 +901,39 @@ properties:
> > > - fsl,s32v234-evb # S32V234-EVB2 Customer
> > Evaluation Board
> > > - const: fsl,s32v234
> > >
> > > + soc:
> > > + description:
> > > + i.MX8M Family SoC must provide a soc node in the root of the device
> > tree,
> > > + representing the System-on-Chip since these test chips are rather
> > complex.
> > > + type: object
> > > + properties:
> > > + compatible:
> > > + oneOf:
> > > + - items:
> > > + - const: fsl,imx8mm-soc
> > > + - const: simple-bus
> > > + - items:
> > > + - const: fsl,imx8mn-soc
> > > + - const: simple-bus
> > > + - items:
> > > + - const: fsl,imx8mp-soc
> > > + - const: simple-bus
> > > + - items:
> > > + - const: fsl,imx8mq-soc
> > > + - const: simple-bus
> > > +
> > > + nvmem-cells:
> > > + maxItems: 1
> > > + description: Phandle to the SOC Unique ID provided by a nvmem
> > node
> > > +
> > > + nvmem-cells-names:
> > > + const: soc_unique_id
> > > +
> > > + required:
> > > + - compatible
> > > + - nvmem-cells
> > > + - nvmem-cell-names
> > > +
> >
> > Did you actually test it? I see multiple errors with this patch.
> > fsl-ls1012a-frdm.dt.yaml: /: soc:compatible: ['simple-bus'] is not valid under any
> > of the given schemas
> >
> > Best regards,
> > Krzysztof
>
>
> [Alice Guo] Sorry. I did not see errors what you said. Can you tell me how did you test it?
It was a regular DT check, nothing unusual (make dtbs_check).
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: 2020年11月5日 17:06
> To: Alice Guo <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> dl-linux-imx <[email protected]>; Peng Fan <[email protected]>;
> [email protected]; [email protected];
> [email protected]
> Subject: [EXT] Re: [PATCH v2 4/4] soc: imx8m: change to use platform driver
>
> Caution: EXT Email
>
> On Thu, Nov 05, 2020 at 03:26:29PM +0800, Alice Guo wrote:
> > Directly reading ocotp register depends on that bootloader enables
> > ocotp clk, which is not always effective, so change to use nvmem API.
> > Using nvmem API requires to support driver defer probe and thus change
> > soc-imx8m.c to use platform driver.
> >
> > The other reason is that directly reading ocotp register causes kexec
> > kernel hang because the 1st kernel running will disable unused clks
> > after kernel boots up, and then ocotp clk will be disabled even if
> > bootloader enables it. When kexec kernel, ocotp clk needs to be
> > enabled before reading ocotp registers, and nvmem API with platform
> > driver supported can accomplish this.
> >
> > Signed-off-by: Alice Guo <[email protected]>
> > ---
> > drivers/soc/imx/soc-imx8m.c | 75
> > +++++++++++++++++++++----------------
> > 1 file changed, 42 insertions(+), 33 deletions(-)
> >
> > diff --git a/drivers/soc/imx/soc-imx8m.c b/drivers/soc/imx/soc-imx8m.c
> > index cc57a384d74d..83f3297509be 100644
> > --- a/drivers/soc/imx/soc-imx8m.c
> > +++ b/drivers/soc/imx/soc-imx8m.c
> > @@ -5,6 +5,8 @@
> >
> > #include <linux/init.h>
> > #include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-consumer.h>
> > #include <linux/of_address.h>
> > #include <linux/slab.h>
> > #include <linux/sys_soc.h>
> > @@ -29,7 +31,7 @@
> >
> > struct imx8_soc_data {
> > char *name;
> > - u32 (*soc_revision)(void);
> > + u32 (*soc_revision)(struct device *dev);
> > };
> >
> > static u64 soc_uid;
> > @@ -50,12 +52,15 @@ static u32 imx8mq_soc_revision_from_atf(void)
> > static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
> > #endif
> >
> > -static u32 __init imx8mq_soc_revision(void)
> > +static u32 __init imx8mm_soc_uid(struct device *dev);
> > +
> > +static u32 __init imx8mq_soc_revision(struct device *dev)
> > {
> > struct device_node *np;
> > void __iomem *ocotp_base;
> > u32 magic;
> > u32 rev;
> > + int ret = 0;
> >
> > np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
> > if (!np)
> > @@ -75,9 +80,9 @@ static u32 __init imx8mq_soc_revision(void)
> > rev = REV_B1;
> > }
> >
> > - soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
> > - soc_uid <<= 32;
> > - soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
> > + ret = imx8mm_soc_uid(dev);
> > + if (ret)
> > + return ret;
> >
> > iounmap(ocotp_base);
> > of_node_put(np);
> > @@ -85,33 +90,20 @@ static u32 __init imx8mq_soc_revision(void)
> > return rev;
> > }
> >
> > -static void __init imx8mm_soc_uid(void)
> > +static u32 __init imx8mm_soc_uid(struct device *dev)
> > {
> > - void __iomem *ocotp_base;
> > - struct device_node *np;
> > - u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
> > - IMX8MP_OCOTP_UID_OFFSET : 0;
> > -
> > - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
> > - if (!np)
> > - return;
> > -
> > - ocotp_base = of_iomap(np, 0);
> > - WARN_ON(!ocotp_base);
> > -
> > - soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
> > - soc_uid <<= 32;
> > - soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
> > + int ret = 0;
> >
> > - iounmap(ocotp_base);
> > - of_node_put(np);
> > + ret = nvmem_cell_read_u64(dev, "soc_unique_id", &soc_uid);
> > + return ret;
> > }
> >
> > -static u32 __init imx8mm_soc_revision(void)
> > +static u32 __init imx8mm_soc_revision(struct device *dev)
> > {
> > struct device_node *np;
> > void __iomem *anatop_base;
> > u32 rev;
> > + int ret;
> >
> > np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
> > if (!np)
> > @@ -125,7 +117,9 @@ static u32 __init imx8mm_soc_revision(void)
> > iounmap(anatop_base);
> > of_node_put(np);
> >
> > - imx8mm_soc_uid();
> > + ret = imx8mm_soc_uid(dev);
> > + if (ret)
> > + return ret;
>
> I think this breaks old existing DTBs. If applied on separate branch than DTS
> patches, it will cause bisect regressions. Regardless of it, all out-of-tree
> (customer DTBs) will start failing here as well.
>
> Best regards,
> Krzysztof
>
>
[Alice Guo] Compatible with old existing DTBs, I did not find a good solution. I want to use soc device to match this driver. Do you have some suggestions? Thank you.
Best regards,
Alice
> >
> > return rev;
> > }
> > @@ -151,19 +145,20 @@ static const struct imx8_soc_data
> > imx8mp_soc_data = { };
> >
> > static __maybe_unused const struct of_device_id imx8_soc_match[] = {
> > - { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
> > - { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
> > - { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
> > - { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
> > + { .compatible = "fsl,imx8mq-soc", .data = &imx8mq_soc_data, },
> > + { .compatible = "fsl,imx8mm-soc", .data = &imx8mm_soc_data, },
> > + { .compatible = "fsl,imx8mn-soc", .data = &imx8mn_soc_data, },
> > + { .compatible = "fsl,imx8mp-soc", .data = &imx8mp_soc_data, },
> > { }
> > };
> > +MODULE_DEVICE_TABLE(of, imx8_soc_match);
> >
> > #define imx8_revision(soc_rev) \
> > soc_rev ? \
> > kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf, soc_rev &
> 0xf) : \
> > "unknown"
> >
> > -static int __init imx8_soc_init(void)
> > +static int imx8_soc_init_probe(struct platform_device *pdev)
> > {
> > struct soc_device_attribute *soc_dev_attr;
> > struct soc_device *soc_dev;
> > @@ -182,7 +177,7 @@ static int __init imx8_soc_init(void)
> > if (ret)
> > goto free_soc;
> >
> > - id = of_match_node(imx8_soc_match, of_root);
> > + id = of_match_node(imx8_soc_match, pdev->dev.of_node);
> > if (!id) {
> > ret = -ENODEV;
> > goto free_soc;
> > @@ -192,7 +187,11 @@ static int __init imx8_soc_init(void)
> > if (data) {
> > soc_dev_attr->soc_id = data->name;
> > if (data->soc_revision)
> > - soc_rev = data->soc_revision();
> > + soc_rev = data->soc_revision(&pdev->dev);
> > +
> > + ret = soc_rev;
> > + if (ret < 0)
> > + goto free_soc;
> > }
> >
> > soc_dev_attr->revision = imx8_revision(soc_rev); @@ -230,4
> > +229,14 @@ static int __init imx8_soc_init(void)
> > kfree(soc_dev_attr);
> > return ret;
> > }
> > -device_initcall(imx8_soc_init);
> > +
> > +static struct platform_driver imx8_soc_init_driver = {
> > + .probe = imx8_soc_init_probe,
> > + .driver = {
> > + .name = "imx8_soc_init",
> > + .of_match_table = of_match_ptr(imx8_soc_match),
> > + },
> > +};
> > +
> > +module_platform_driver(imx8_soc_init_driver);
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.17.1
> >
On Fri, Nov 06, 2020 at 10:35:35AM +0000, Alice Guo wrote:
>
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <[email protected]>
> > Sent: 2020年11月5日 17:06
> > To: Alice Guo <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected];
> > dl-linux-imx <[email protected]>; Peng Fan <[email protected]>;
> > [email protected]; [email protected];
> > [email protected]
> > Subject: [EXT] Re: [PATCH v2 4/4] soc: imx8m: change to use platform driver
> >
> > Caution: EXT Email
> >
> > On Thu, Nov 05, 2020 at 03:26:29PM +0800, Alice Guo wrote:
> > > Directly reading ocotp register depends on that bootloader enables
> > > ocotp clk, which is not always effective, so change to use nvmem API.
> > > Using nvmem API requires to support driver defer probe and thus change
> > > soc-imx8m.c to use platform driver.
> > >
> > > The other reason is that directly reading ocotp register causes kexec
> > > kernel hang because the 1st kernel running will disable unused clks
> > > after kernel boots up, and then ocotp clk will be disabled even if
> > > bootloader enables it. When kexec kernel, ocotp clk needs to be
> > > enabled before reading ocotp registers, and nvmem API with platform
> > > driver supported can accomplish this.
> > >
> > > Signed-off-by: Alice Guo <[email protected]>
> > > ---
> > > drivers/soc/imx/soc-imx8m.c | 75
> > > +++++++++++++++++++++----------------
> > > 1 file changed, 42 insertions(+), 33 deletions(-)
> > >
> > > diff --git a/drivers/soc/imx/soc-imx8m.c b/drivers/soc/imx/soc-imx8m.c
> > > index cc57a384d74d..83f3297509be 100644
> > > --- a/drivers/soc/imx/soc-imx8m.c
> > > +++ b/drivers/soc/imx/soc-imx8m.c
> > > @@ -5,6 +5,8 @@
> > >
> > > #include <linux/init.h>
> > > #include <linux/io.h>
> > > +#include <linux/module.h>
> > > +#include <linux/nvmem-consumer.h>
> > > #include <linux/of_address.h>
> > > #include <linux/slab.h>
> > > #include <linux/sys_soc.h>
> > > @@ -29,7 +31,7 @@
> > >
> > > struct imx8_soc_data {
> > > char *name;
> > > - u32 (*soc_revision)(void);
> > > + u32 (*soc_revision)(struct device *dev);
> > > };
> > >
> > > static u64 soc_uid;
> > > @@ -50,12 +52,15 @@ static u32 imx8mq_soc_revision_from_atf(void)
> > > static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
> > > #endif
> > >
> > > -static u32 __init imx8mq_soc_revision(void)
> > > +static u32 __init imx8mm_soc_uid(struct device *dev);
> > > +
> > > +static u32 __init imx8mq_soc_revision(struct device *dev)
> > > {
> > > struct device_node *np;
> > > void __iomem *ocotp_base;
> > > u32 magic;
> > > u32 rev;
> > > + int ret = 0;
> > >
> > > np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
> > > if (!np)
> > > @@ -75,9 +80,9 @@ static u32 __init imx8mq_soc_revision(void)
> > > rev = REV_B1;
> > > }
> > >
> > > - soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
> > > - soc_uid <<= 32;
> > > - soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
> > > + ret = imx8mm_soc_uid(dev);
> > > + if (ret)
> > > + return ret;
> > >
> > > iounmap(ocotp_base);
> > > of_node_put(np);
> > > @@ -85,33 +90,20 @@ static u32 __init imx8mq_soc_revision(void)
> > > return rev;
> > > }
> > >
> > > -static void __init imx8mm_soc_uid(void)
> > > +static u32 __init imx8mm_soc_uid(struct device *dev)
> > > {
> > > - void __iomem *ocotp_base;
> > > - struct device_node *np;
> > > - u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
> > > - IMX8MP_OCOTP_UID_OFFSET : 0;
> > > -
> > > - np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
> > > - if (!np)
> > > - return;
> > > -
> > > - ocotp_base = of_iomap(np, 0);
> > > - WARN_ON(!ocotp_base);
> > > -
> > > - soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
> > > - soc_uid <<= 32;
> > > - soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
> > > + int ret = 0;
> > >
> > > - iounmap(ocotp_base);
> > > - of_node_put(np);
> > > + ret = nvmem_cell_read_u64(dev, "soc_unique_id", &soc_uid);
> > > + return ret;
> > > }
> > >
> > > -static u32 __init imx8mm_soc_revision(void)
> > > +static u32 __init imx8mm_soc_revision(struct device *dev)
> > > {
> > > struct device_node *np;
> > > void __iomem *anatop_base;
> > > u32 rev;
> > > + int ret;
> > >
> > > np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
> > > if (!np)
> > > @@ -125,7 +117,9 @@ static u32 __init imx8mm_soc_revision(void)
> > > iounmap(anatop_base);
> > > of_node_put(np);
> > >
> > > - imx8mm_soc_uid();
> > > + ret = imx8mm_soc_uid(dev);
> > > + if (ret)
> > > + return ret;
> >
> > I think this breaks old existing DTBs. If applied on separate branch than DTS
> > patches, it will cause bisect regressions. Regardless of it, all out-of-tree
> > (customer DTBs) will start failing here as well.
> >
> > Best regards,
> > Krzysztof
> >
> >
> [Alice Guo] Compatible with old existing DTBs, I did not find a good solution. I want to use soc device to match this driver. Do you have some suggestions? Thank you.
How the change above (returning imx8mm_soc_uid error value) and few
others similar are related to topic mentioned in commit msg?
The patch should implement only one thing (one feature or fix one bug)
and then it is easier to manage ABI breakage.
For the ABI breakage, the usual solution is to support old DTBs.
Best regards,
Krzysztof
On Thu, Nov 05, 2020 at 03:26:26PM +0800, Alice Guo wrote:
> Add DT Binding doc for the Unique ID of i.MX 8M series.
>
> Signed-off-by: Alice Guo <[email protected]>
> ---
> .../devicetree/bindings/arm/fsl.yaml | 33 +++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index e4db0f9ed664..0419f078502b 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -901,6 +901,39 @@ properties:
> - fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
> - const: fsl,s32v234
>
> + soc:
> + description:
> + i.MX8M Family SoC must provide a soc node in the root of the device tree,
> + representing the System-on-Chip since these test chips are rather complex.
> + type: object
> + properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: fsl,imx8mm-soc
> + - const: simple-bus
> + - items:
> + - const: fsl,imx8mn-soc
> + - const: simple-bus
> + - items:
> + - const: fsl,imx8mp-soc
> + - const: simple-bus
> + - items:
> + - const: fsl,imx8mq-soc
> + - const: simple-bus
items:
- enum:
- fsl,imx8mm-soc
- fsl,imx8mn-soc
- fsl,imx8mp-soc
- fsl,imx8mq-soc
- const: simple-bus
> +
> + nvmem-cells:
> + maxItems: 1
> + description: Phandle to the SOC Unique ID provided by a nvmem node
> +
> + nvmem-cells-names:
> + const: soc_unique_id
> +
> + required:
> + - compatible
> + - nvmem-cells
> + - nvmem-cell-names
> +
'soc' should be required?
> additionalProperties: true
>
> ...
> --
> 2.17.1
>
> Subject: Re: [PATCH v2 1/4] dt-bindings: soc: imx8m: add DT Binding doc for
> soc unique ID
>
> On Thu, Nov 05, 2020 at 03:26:26PM +0800, Alice Guo wrote:
> > Add DT Binding doc for the Unique ID of i.MX 8M series.
> >
> > Signed-off-by: Alice Guo <[email protected]>
> > ---
> > .../devicetree/bindings/arm/fsl.yaml | 33
> +++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
> b/Documentation/devicetree/bindings/arm/fsl.yaml
> > index e4db0f9ed664..0419f078502b 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > @@ -901,6 +901,39 @@ properties:
> > - fsl,s32v234-evb # S32V234-EVB2
> Customer Evaluation Board
> > - const: fsl,s32v234
> >
> > + soc:
> > + description:
> > + i.MX8M Family SoC must provide a soc node in the root of the
> device tree,
> > + representing the System-on-Chip since these test chips are rather
> complex.
> > + type: object
> > + properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - const: fsl,imx8mm-soc
> > + - const: simple-bus
> > + - items:
> > + - const: fsl,imx8mn-soc
> > + - const: simple-bus
> > + - items:
> > + - const: fsl,imx8mp-soc
> > + - const: simple-bus
> > + - items:
> > + - const: fsl,imx8mq-soc
> > + - const: simple-bus
>
> items:
> - enum:
> - fsl,imx8mm-soc
> - fsl,imx8mn-soc
> - fsl,imx8mp-soc
> - fsl,imx8mq-soc
> - const: simple-bus
>
> > +
> > + nvmem-cells:
> > + maxItems: 1
> > + description: Phandle to the SOC Unique ID provided by a nvmem
> node
> > +
> > + nvmem-cells-names:
> > + const: soc_unique_id
> > +
> > + required:
> > + - compatible
> > + - nvmem-cells
> > + - nvmem-cell-names
> > +
>
> 'soc' should be required?
The fsl,imx8m[m,n,p,q] already used by root node compatible.
So here could reuse the same compatible string? Or
We add an extra 'soc' here?
Thanks,
Peng.
>
> > additionalProperties: true
> >
> > ...
> > --
> > 2.17.1
> >