The IMX8M Mini PCI controller shares much in common with the existing
SoC's supported by the pci-imx6 driver.
This series adds support for it. Driver changes came from the NXP
downstream vendor kernel [1]
This series depends on Lucas Stach's i.MX8MM GPC improvements and
BLK_CTRL driver and is based on top of his v2 submission [2]
The final patch adds PCIe support to the
Tim
[1] https://source.codeaurora.org/external/imx/linux-imx/
[2]
https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=519251
Tim Harvey (6):
dt-bindings: imx6q-pcie: add compatible for IMX8MM support
dt-bindings: reset: imx8mq: add pcie reset
PCI: imx6: add IMX8MM support
reset: imx7: add resets for PCIe
arm64: dts: imx8mm: add PCIe support
arm64: dts: imx8mm: add gpc iomux compatible
.../bindings/pci/fsl,imx6q-pcie.txt | 4 +-
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 38 ++++++-
drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++-
drivers/reset/reset-imx7.c | 3 +
include/dt-bindings/reset/imx8mq-reset.h | 3 +-
5 files changed, 147 insertions(+), 4 deletions(-)
--
2.17.1
Add PCIe node for PCIe support.
Signed-off-by: Tim Harvey <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 36 +++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 3bec6b8d52a0..45017f50a11b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1134,6 +1134,10 @@
reg = <0x32e50200 0x200>;
};
+ pcie_phy: pcie-phy@32f00000 {
+ compatible = "fsl,imx7d-pcie-phy";
+ reg = <0x32f00000 0x10000>;
+ };
};
dma_apbh: dma-controller@33000000 {
@@ -1233,5 +1237,37 @@
reg = <0x3d800000 0x400000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ pcie0: pcie@33800000 {
+ compatible = "fsl,imx8mm-pcie";
+ reg = <0x33800000 0x400000>,
+ <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ num-viewport = <4>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "clkreq", "turnoff";
+ fsl,imx7d-pcie-phy = <&pcie_phy>;
+ status = "disabled";
+ };
};
};
--
2.17.1
Add gpc iomux compatible needed for IMX8MM PCIe.
Signed-off-by: Tim Harvey <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 45017f50a11b..a2de42dc5f61 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -519,7 +519,7 @@
};
gpr: iomuxc-gpr@30340000 {
- compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
--
2.17.1
Add the reset used by the pcie driver
Signed-off-by: Tim Harvey <[email protected]>
---
include/dt-bindings/reset/imx8mq-reset.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
index 705870693ec2..20a25ee4a271 100644
--- a/include/dt-bindings/reset/imx8mq-reset.h
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -61,7 +61,8 @@
#define IMX8MQ_RESET_SW_M4C_RST 50
#define IMX8MQ_RESET_SW_M4P_RST 51
#define IMX8MQ_RESET_M4_ENABLE 52
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ 53
-#define IMX8MQ_RESET_NUM 53
+#define IMX8MQ_RESET_NUM 54
#endif
--
2.17.1
Add reset for PCIe clock and PHY.
Signed-off-by: Tim Harvey <[email protected]>
---
drivers/reset/reset-imx7.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 185a333df66c..423707e1fd59 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -191,6 +191,7 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
[IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
BIT(2) | BIT(1) },
[IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ] = { SRC_PCIEPHY_RCR, BIT(4) },
[IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
[IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
@@ -234,7 +235,9 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
udelay(10);
break;
+ case IMX8MQ_RESET_PCIEPHY_PERST:
case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ:
case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
--
2.17.1
On Fri, Jul 23, 2021 at 2:50 PM Tim Harvey <[email protected]> wrote:
>
> Add PCIe node for PCIe support.
>
> Signed-off-by: Tim Harvey <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 36 +++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 3bec6b8d52a0..45017f50a11b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1134,6 +1134,10 @@
> reg = <0x32e50200 0x200>;
> };
>
> + pcie_phy: pcie-phy@32f00000 {
> + compatible = "fsl,imx7d-pcie-phy";
> + reg = <0x32f00000 0x10000>;
The phy really has 64KB worth of registers? This wastes virtual space
too, but I guess that's 'free' on 64-bit.
> + };
> };
>
> dma_apbh: dma-controller@33000000 {
> @@ -1233,5 +1237,37 @@
> reg = <0x3d800000 0x400000>;
> interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + pcie0: pcie@33800000 {
> + compatible = "fsl,imx8mm-pcie";
> + reg = <0x33800000 0x400000>,
> + <0x1ff00000 0x80000>;
> + reg-names = "dbi", "config";
I don't think the DBI space ever has 4MB of registers. And IIRC, only
4KB is used for config space unless ECAM is used.
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + bus-range = <0x00 0xff>;
> + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
> + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
> + num-lanes = <1>;
> + num-viewport = <4>;
This is deprecated and ignored. The driver has gotten smarter and detects this.
> + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> + fsl,max-link-speed = <2>;
There's a standard property for this.
> + power-domains = <&pgc_pcie>;
> + resets = <&src IMX8MQ_RESET_PCIEPHY>,
> + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
> + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
> + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
> + reset-names = "pciephy", "apps", "clkreq", "turnoff";
The phy reset belongs in the phy node.
> + fsl,imx7d-pcie-phy = <&pcie_phy>;
Didn't we deprecate this? Either way, use the phy binding.
> + status = "disabled";
> + };
> };
> };
> --
> 2.17.1
>
Hello Tim,
On 23.07.21 22:49, Tim Harvey wrote:
> The IMX8M Mini PCI controller shares much in common with the existing
> SoC's supported by the pci-imx6 driver.
>
> This series adds support for it. Driver changes came from the NXP
> downstream vendor kernel [1]
>
> This series depends on Lucas Stach's i.MX8MM GPC improvements and
> BLK_CTRL driver and is based on top of his v2 submission [2]
Are you aware of Lucas' patch series and Rob's remarks there?
https://lore.kernel.org/linux-pci/[email protected]/
Cheers,
Ahmad
>
> The final patch adds PCIe support to the
> Tim
> [1] https://source.codeaurora.org/external/imx/linux-imx/
> [2]
> https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=519251
>
> Tim Harvey (6):
> dt-bindings: imx6q-pcie: add compatible for IMX8MM support
> dt-bindings: reset: imx8mq: add pcie reset
> PCI: imx6: add IMX8MM support
> reset: imx7: add resets for PCIe
> arm64: dts: imx8mm: add PCIe support
> arm64: dts: imx8mm: add gpc iomux compatible
>
> .../bindings/pci/fsl,imx6q-pcie.txt | 4 +-
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 38 ++++++-
> drivers/pci/controller/dwc/pci-imx6.c | 103 +++++++++++++++++-
> drivers/reset/reset-imx7.c | 3 +
> include/dt-bindings/reset/imx8mq-reset.h | 3 +-
> 5 files changed, 147 insertions(+), 4 deletions(-)
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Tim:
Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
Some comments in the review cycle.
- One separate PHY driver should be used for i.MX8MM PCIe driver.
- Schema file should be used I think, otherwise the .txt file in the dt-binding.
I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
Best Regards
Richard Zhu
> -----Original Message-----
> From: Ahmad Fatoum <[email protected]>
> Sent: Thursday, July 29, 2021 10:40 PM
> To: [email protected]; Richard Zhu <[email protected]>; Lucas
> Stach <[email protected]>; Bjorn Helgaas <[email protected]>;
> Rob Herring <[email protected]>; Shawn Guo <[email protected]>;
> Sascha Hauer <[email protected]>; Pengutronix Kernel Team
> <[email protected]>; Fabio Estevam <[email protected]>;
> dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; Krzysztof Wilczy?ski <[email protected]>; Lorenzo
> Pieralisi <[email protected]>
> Subject: Re: [PATCH 0/6] Add IMX8M Mini PCI support
>
> Hello Tim,
>
> On 23.07.21 22:49, Tim Harvey wrote:
> > The IMX8M Mini PCI controller shares much in common with the existing
> > SoC's supported by the pci-imx6 driver.
> >
> > This series adds support for it. Driver changes came from the NXP
> > downstream vendor kernel [1]
> >
> > This series depends on Lucas Stach's i.MX8MM GPC improvements and
> > BLK_CTRL driver and is based on top of his v2 submission [2]
>
> Are you aware of Lucas' patch series and Rob's remarks there?
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> rnel.org%2Flinux-pci%2F20210510141509.929120-7-l.stach%40pengutronix.
> de%2F&data=04%7C01%7Chongxing.zhu%40nxp.com%7C21a3e2ba936
> c443581ea08d9529ebf65%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7
> C0%7C637631664036013517%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> mp;sdata=blnp2JkmGAZ2w5JHZHJQoZJSuY1646KAT8cccaI5n%2Fw%3D&
> reserved=0
>
> Cheers,
> Ahmad
>
> >
> > The final patch adds PCIe support to the Tim [1]
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsour
> >
> ce.codeaurora.org%2Fexternal%2Fimx%2Flinux-imx%2F&data=04%7C0
> 1%7Ch
> >
> ongxing.zhu%40nxp.com%7C21a3e2ba936c443581ea08d9529ebf65%7C686e
> a1d3bc2
> >
> b4c6fa92cd99c5c301635%7C0%7C0%7C637631664036013517%7CUnknown
> %7CTWFpbGZ
> >
> sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6M
> n0%3
> >
> D%7C1000&sdata=5IiG4fnzWkcsV2JPnQJ8gAgMhZSuZypTOixD4lV%2BTf
> g%3D&am
> > p;reserved=0
> > [2]
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> >
> hwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Flist%2F%3Fseries%3D51
> 9
> >
> 251&data=04%7C01%7Chongxing.zhu%40nxp.com%7C21a3e2ba936c44
> 3581ea08
> >
> d9529ebf65%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63763
> 166403601
> >
> 3517%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2lu
> MzIiLCJBT
> >
> iI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=M6%2FzPsxRPv%2Fv7a
> ad7uqjDQY
> > 8LhHOX%2B%2FLzxnuW1UrVgE%3D&reserved=0
> >
> > Tim Harvey (6):
> > dt-bindings: imx6q-pcie: add compatible for IMX8MM support
> > dt-bindings: reset: imx8mq: add pcie reset
> > PCI: imx6: add IMX8MM support
> > reset: imx7: add resets for PCIe
> > arm64: dts: imx8mm: add PCIe support
> > arm64: dts: imx8mm: add gpc iomux compatible
> >
> > .../bindings/pci/fsl,imx6q-pcie.txt | 4 +-
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 38 ++++++-
> > drivers/pci/controller/dwc/pci-imx6.c | 103
> +++++++++++++++++-
> > drivers/reset/reset-imx7.c | 3 +
> > include/dt-bindings/reset/imx8mq-reset.h | 3 +-
> > 5 files changed, 147 insertions(+), 4 deletions(-)
> >
>
>
> --
> Pengutronix e.K. |
> |
> Steuerwalder Str. 21 |
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.p
> engutronix.de%2F&data=04%7C01%7Chongxing.zhu%40nxp.com%7C21
> a3e2ba936c443581ea08d9529ebf65%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C637631664036013517%7CUnknown%7CTWFpbGZsb3d8ey
> JWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> %7C1000&sdata=jynjjRJZyvooJFXwvz45OU9YB0xr5wA2y%2FkoweEtUq
> U%3D&reserved=0 |
> 31137 Hildesheim, Germany | Phone:
> +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax:
> +49-5121-206917-5555 |
On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <[email protected]> wrote:
>
> Hi Tim:
> Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> Some comments in the review cycle.
> - One separate PHY driver should be used for i.MX8MM PCIe driver.
> - Schema file should be used I think, otherwise the .txt file in the dt-binding.
>
> I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
>
> Best Regards
> Richard Zhu
Richard / Ahmad,
Thanks for your response - I did not see the series from Lucas. I will
drop this and wait for him to complete his work.
Thanks,
Tim
On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <[email protected]> wrote:
>
> On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <[email protected]> wrote:
> >
> > Hi Tim:
> > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > Some comments in the review cycle.
> > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> >
> > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> >
> > Best Regards
> > Richard Zhu
>
> Richard / Ahmad,
>
> Thanks for your response - I did not see the series from Lucas. I will
> drop this and wait for him to complete his work.
>
Tim,
It appears that the power domain changes have been applied to Shawn's
for-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next
Is there any chance you could rebase and resend this series?
thanks,
adam
> Thanks,
>
> Tim
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, Oct 11, 2021 at 7:30 AM Lucas Stach <[email protected]> wrote:
>
> Hi Adam,
>
> Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> > On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <[email protected]> wrote:
> > >
> > > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <[email protected]> wrote:
> > > >
> > > > Hi Tim:
> > > > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > > > Some comments in the review cycle.
> > > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> > > >
> > > > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > > > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> > > >
> > > > Best Regards
> > > > Richard Zhu
> > >
> > > Richard / Ahmad,
> > >
> > > Thanks for your response - I did not see the series from Lucas. I will
> > > drop this and wait for him to complete his work.
> > >
> >
> > Tim,
> >
> > It appears that the power domain changes have been applied to Shawn's
> > for-next branch:
> > https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next
> >
> > Is there any chance you could rebase and resend this series?
>
> This wasn't about the power domain series. I also tried to get i.MX8M
> PCIe upstream, but the feedback was that we need to split out the PHY
> functionality, Richard is currently working on this. There is no point
> in resending this series.
Sorry. I missed that part.
adam
>
> Regards,
> Lucas
>
Hi Adam,
Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <[email protected]> wrote:
> >
> > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <[email protected]> wrote:
> > >
> > > Hi Tim:
> > > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > > Some comments in the review cycle.
> > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> > >
> > > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> > >
> > > Best Regards
> > > Richard Zhu
> >
> > Richard / Ahmad,
> >
> > Thanks for your response - I did not see the series from Lucas. I will
> > drop this and wait for him to complete his work.
> >
>
> Tim,
>
> It appears that the power domain changes have been applied to Shawn's
> for-next branch:
> https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next
>
> Is there any chance you could rebase and resend this series?
This wasn't about the power domain series. I also tried to get i.MX8M
PCIe upstream, but the feedback was that we need to split out the PHY
functionality, Richard is currently working on this. There is no point
in resending this series.
Regards,
Lucas
On Mon, Oct 11, 2021 at 5:30 AM Lucas Stach <[email protected]> wrote:
>
> Hi Adam,
>
> Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> > On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <[email protected]> wrote:
> > >
> > > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <[email protected]> wrote:
> > > >
> > > > Hi Tim:
> > > > Just as Ahmad mentioned, Lucas had issue one patch-set to support i.MX8MM PCIe.
> > > > Some comments in the review cycle.
> > > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > > - Schema file should be used I think, otherwise the .txt file in the dt-binding.
> > > >
> > > > I'm preparing one patch-set, but it's relied on the yaml file exchanges and power-domain changes(block control and so on).
> > > > Up to now, I only walking on the first step, trying to exchange the dt-binding files to schema yaml file.
> > > >
> > > > Best Regards
> > > > Richard Zhu
> > >
> > > Richard / Ahmad,
> > >
> > > Thanks for your response - I did not see the series from Lucas. I will
> > > drop this and wait for him to complete his work.
> > >
> >
> > Tim,
> >
> > It appears that the power domain changes have been applied to Shawn's
> > for-next branch:
> > https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/log/?h=for-next
> >
> > Is there any chance you could rebase and resend this series?
>
> This wasn't about the power domain series. I also tried to get i.MX8M
> PCIe upstream, but the feedback was that we need to split out the PHY
> functionality, Richard is currently working on this. There is no point
> in resending this series.
>
Lucas,
Thanks for the update.
Richard - please Cc me when you submit as I have several boards to
test IMX8MM PCI with, some with PCI bridges and some without.
Best regards,
Tim
> -----Original Message-----
> From: Tim Harvey <[email protected]>
> Sent: Monday, October 11, 2021 11:29 PM
> To: Lucas Stach <[email protected]>; Richard Zhu
> <[email protected]>
> Cc: Adam Ford <[email protected]>; Ahmad Fatoum
> <[email protected]>; Bjorn Helgaas <[email protected]>; Rob
> Herring <[email protected]>; Shawn Guo <[email protected]>; Sascha
> Hauer <[email protected]>; Pengutronix Kernel Team
> <[email protected]>; Fabio Estevam <[email protected]>;
> dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; Krzysztof Wilczy?ski <[email protected]>; Lorenzo
> Pieralisi <[email protected]>
> Subject: Re: [PATCH 0/6] Add IMX8M Mini PCI support
>
> On Mon, Oct 11, 2021 at 5:30 AM Lucas Stach <[email protected]>
> wrote:
> >
> > Hi Adam,
> >
> > Am Montag, dem 11.10.2021 um 07:25 -0500 schrieb Adam Ford:
> > > On Mon, Aug 16, 2021 at 10:45 AM Tim Harvey <[email protected]>
> wrote:
> > > >
> > > > On Thu, Jul 29, 2021 at 6:28 PM Richard Zhu <[email protected]>
> wrote:
> > > > >
> > > > > Hi Tim:
> > > > > Just as Ahmad mentioned, Lucas had issue one patch-set to support
> i.MX8MM PCIe.
> > > > > Some comments in the review cycle.
> > > > > - One separate PHY driver should be used for i.MX8MM PCIe driver.
> > > > > - Schema file should be used I think, otherwise the .txt file in the
> dt-binding.
> > > > >
> > > > > I'm preparing one patch-set, but it's relied on the yaml file exchanges
> and power-domain changes(block control and so on).
> > > > > Up to now, I only walking on the first step, trying to exchange the
> dt-binding files to schema yaml file.
> > > > >
> > > > > Best Regards
> > > > > Richard Zhu
> > > >
> > > > Richard / Ahmad,
> > > >
> > > > Thanks for your response - I did not see the series from Lucas. I
> > > > will drop this and wait for him to complete his work.
> > > >
> > >
> > > Tim,
> > >
> > > It appears that the power domain changes have been applied to
> > > Shawn's for-next branch:
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgi
> > >
> t.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fshawnguo%2Flinux.
> g
> > >
> it%2Flog%2F%3Fh%3Dfor-next&data=04%7C01%7Chongxing.zhu%40nx
> p.com
> > > %7C1e298d5c31594e5a09df08d98ccbef7a%7C686ea1d3bc2b4c6fa92cd9
> 9c5c3016
> > >
> 35%7C0%7C0%7C637695629794787625%7CUnknown%7CTWFpbGZsb3d8ey
> JWIjoiMC4w
> > >
> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&a
> mp;sd
> > >
> ata=PY2%2Bvr3s6K5O18lQ9SLY5YCqZHR7Fa%2F2RrbJ%2B041CBU%3D&
> reserve
> > > d=0
> > >
> > > Is there any chance you could rebase and resend this series?
> >
> > This wasn't about the power domain series. I also tried to get i.MX8M
> > PCIe upstream, but the feedback was that we need to split out the PHY
> > functionality, Richard is currently working on this. There is no point
> > in resending this series.
> >
>
> Lucas,
>
> Thanks for the update.
>
> Richard - please Cc me when you submit as I have several boards to test
> IMX8MM PCI with, some with PCI bridges and some without.
[Richard Zhu] Ok, no problem. I would CC you when I issued the v3 patch-set later.
Thanks.
Best Regards
Richard Zhu>
> Best regards,
>
> Tim