LinuxLists.cc - [PATCH v4 0/7] Initial Samsung Galaxy A8 (2018) support

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Subject: [PATCH v4 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU

Just like on Exynos850, the clock controller driver is designed to have
separate instances for each particular CMU, so clock IDs start from 1
for each CMU in this bindings header too.

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: David Virag <[email protected]>
---
Changes in v2:
- Added R-b tag by Krzysztof Kozlowski

Changes in v3:
- Nothing

Changes in v4:
- Nothing

include/dt-bindings/clock/exynos7885.h | 115 +++++++++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 include/dt-bindings/clock/exynos7885.h

diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
new file mode 100644
index 000000000000..1f8701691d62
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7885.h
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 Dávid Virág
+ *
+ * Device Tree binding constants for Exynos7885 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
+
+/* CMU_TOP */
+#define CLK_FOUT_SHARED0_PLL 1
+#define CLK_FOUT_SHARED1_PLL 2
+#define CLK_DOUT_SHARED0_DIV2 3
+#define CLK_DOUT_SHARED0_DIV3 4
+#define CLK_DOUT_SHARED0_DIV4 5
+#define CLK_DOUT_SHARED0_DIV5 6
+#define CLK_DOUT_SHARED1_DIV2 7
+#define CLK_DOUT_SHARED1_DIV3 8
+#define CLK_DOUT_SHARED1_DIV4 9
+#define CLK_MOUT_CORE_BUS 10
+#define CLK_MOUT_CORE_CCI 11
+#define CLK_MOUT_CORE_G3D 12
+#define CLK_DOUT_CORE_BUS 13
+#define CLK_DOUT_CORE_CCI 14
+#define CLK_DOUT_CORE_G3D 15
+#define CLK_GOUT_CORE_BUS 16
+#define CLK_GOUT_CORE_CCI 17
+#define CLK_GOUT_CORE_G3D 18
+#define CLK_MOUT_PERI_BUS 19
+#define CLK_MOUT_PERI_SPI0 20
+#define CLK_MOUT_PERI_SPI1 21
+#define CLK_MOUT_PERI_UART0 22
+#define CLK_MOUT_PERI_UART1 23
+#define CLK_MOUT_PERI_UART2 24
+#define CLK_MOUT_PERI_USI0 25
+#define CLK_MOUT_PERI_USI1 26
+#define CLK_MOUT_PERI_USI2 27
+#define CLK_DOUT_PERI_BUS 28
+#define CLK_DOUT_PERI_SPI0 29
+#define CLK_DOUT_PERI_SPI1 30
+#define CLK_DOUT_PERI_UART0 31
+#define CLK_DOUT_PERI_UART1 32
+#define CLK_DOUT_PERI_UART2 33
+#define CLK_DOUT_PERI_USI0 34
+#define CLK_DOUT_PERI_USI1 35
+#define CLK_DOUT_PERI_USI2 36
+#define CLK_GOUT_PERI_BUS 37
+#define CLK_GOUT_PERI_SPI0 38
+#define CLK_GOUT_PERI_SPI1 39
+#define CLK_GOUT_PERI_UART0 40
+#define CLK_GOUT_PERI_UART1 41
+#define CLK_GOUT_PERI_UART2 42
+#define CLK_GOUT_PERI_USI0 43
+#define CLK_GOUT_PERI_USI1 44
+#define CLK_GOUT_PERI_USI2 45
+#define TOP_NR_CLK 46
+
+/* CMU_CORE */
+#define CLK_MOUT_CORE_BUS_USER 1
+#define CLK_MOUT_CORE_CCI_USER 2
+#define CLK_MOUT_CORE_G3D_USER 3
+#define CLK_MOUT_CORE_GIC 4
+#define CLK_DOUT_CORE_BUSP 5
+#define CLK_GOUT_CCI_ACLK 6
+#define CLK_GOUT_GIC400_CLK 7
+#define CORE_NR_CLK 8
+
+/* CMU_PERI */
+#define CLK_MOUT_PERI_BUS_USER 1
+#define CLK_MOUT_PERI_SPI0_USER 2
+#define CLK_MOUT_PERI_SPI1_USER 3
+#define CLK_MOUT_PERI_UART0_USER 4
+#define CLK_MOUT_PERI_UART1_USER 5
+#define CLK_MOUT_PERI_UART2_USER 6
+#define CLK_MOUT_PERI_USI0_USER 7
+#define CLK_MOUT_PERI_USI1_USER 8
+#define CLK_MOUT_PERI_USI2_USER 9
+#define CLK_GOUT_GPIO_TOP_PCLK 10
+#define CLK_GOUT_HSI2C0_PCLK 11
+#define CLK_GOUT_HSI2C1_PCLK 12
+#define CLK_GOUT_HSI2C2_PCLK 13
+#define CLK_GOUT_HSI2C3_PCLK 14
+#define CLK_GOUT_I2C0_PCLK 15
+#define CLK_GOUT_I2C1_PCLK 16
+#define CLK_GOUT_I2C2_PCLK 17
+#define CLK_GOUT_I2C3_PCLK 18
+#define CLK_GOUT_I2C4_PCLK 19
+#define CLK_GOUT_I2C5_PCLK 20
+#define CLK_GOUT_I2C6_PCLK 21
+#define CLK_GOUT_I2C7_PCLK 22
+#define CLK_GOUT_PWM_MOTOR_PCLK 23
+#define CLK_GOUT_SPI0_PCLK 24
+#define CLK_GOUT_SPI0_EXT_CLK 25
+#define CLK_GOUT_SPI1_PCLK 26
+#define CLK_GOUT_SPI1_EXT_CLK 27
+#define CLK_GOUT_UART0_EXT_UCLK 28
+#define CLK_GOUT_UART0_PCLK 29
+#define CLK_GOUT_UART1_EXT_UCLK 30
+#define CLK_GOUT_UART1_PCLK 31
+#define CLK_GOUT_UART2_EXT_UCLK 32
+#define CLK_GOUT_UART2_PCLK 33
+#define CLK_GOUT_USI0_PCLK 34
+#define CLK_GOUT_USI0_SCLK 35
+#define CLK_GOUT_USI1_PCLK 36
+#define CLK_GOUT_USI1_SCLK 37
+#define CLK_GOUT_USI2_PCLK 38
+#define CLK_GOUT_USI2_SCLK 39
+#define CLK_GOUT_MCT_PCLK 40
+#define CLK_GOUT_SYSREG_PERI_PCLK 41
+#define CLK_GOUT_WDT0_PCLK 42
+#define CLK_GOUT_WDT1_PCLK 43
+#define PERI_NR_CLK 44
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
--
2.34.1

2021-12-06 15:53:21

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Subject: [PATCH v4 2/7] dt-bindings: clock: Document Exynos7885 CMU bindings

Provide dt-schema documentation for Exynos7885 SoC clock controller.
Description is modified from Exynos850 clock controller documentation as
I couldn't describe it any better, that was written by Sam Protsenko.

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: David Virag <[email protected]>
---
Changes in v2:
- Fixed double : in description
- Added R-b tag by Krzysztof Kozlowski

Changes in v3:
- Nothing

Changes in v4:
- Fix leading 0x in example.

.../clock/samsung,exynos7885-clock.yaml | 166 ++++++++++++++++++
1 file changed, 166 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
new file mode 100644
index 000000000000..7e5a9cac2fd2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos7885 SoC clock controller
+
+maintainers:
+ - Dávid Virág <[email protected]>
+ - Chanwoo Choi <[email protected]>
+ - Krzysztof Kozlowski <[email protected]>
+ - Sylwester Nawrocki <[email protected]>
+ - Tomasz Figa <[email protected]>
+
+description: |
+ Exynos7885 clock controller is comprised of several CMU units, generating
+ clocks for different domains. Those CMU units are modeled as separate device
+ tree nodes, and might depend on each other. The root clock in that root tree
+ is an external clock: OSCCLK (26 MHz). This external clock must be defined
+ as a fixed-rate clock in dts.
+
+ CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+ dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+ Each clock is assigned an identifier and client nodes can use this identifier
+ to specify the clock which they consume. All clocks available for usage
+ in clock consumer nodes are defined as preprocessor macros in
+ 'dt-bindings/clock/exynos7885.h' header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos7885-cmu-top
+ - samsung,exynos7885-cmu-core
+ - samsung,exynos7885-cmu-peri
+
+ clocks:
+ minItems: 1
+ maxItems: 10
+
+ clock-names:
+ minItems: 1
+ maxItems: 10
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7885-cmu-top
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+
+ clock-names:
+ items:
+ - const: oscclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7885-cmu-core
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_CORE bus clock (from CMU_TOP)
+ - description: CCI clock (from CMU_TOP)
+ - description: G3D clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_core_bus
+ - const: dout_core_cci
+ - const: dout_core_g3d
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos7885-cmu-peri
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_PERI bus clock (from CMU_TOP)
+ - description: SPI0 clock (from CMU_TOP)
+ - description: SPI1 clock (from CMU_TOP)
+ - description: UART0 clock (from CMU_TOP)
+ - description: UART1 clock (from CMU_TOP)
+ - description: UART2 clock (from CMU_TOP)
+ - description: USI0 clock (from CMU_TOP)
+ - description: USI1 clock (from CMU_TOP)
+ - description: USI2 clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_peri_bus
+ - const: dout_peri_spi0
+ - const: dout_peri_spi1
+ - const: dout_peri_uart0
+ - const: dout_peri_uart1
+ - const: dout_peri_uart2
+ - const: dout_peri_usi0
+ - const: dout_peri_usi1
+ - const: dout_peri_usi2
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_PERI
+ - |
+ #include <dt-bindings/clock/exynos7885.h>
+
+ cmu_peri: clock-controller@10010000 {
+ compatible = "samsung,exynos7885-cmu-peri";
+ reg = <0x10010000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_PERI_BUS>,
+ <&cmu_top CLK_DOUT_PERI_SPI0>,
+ <&cmu_top CLK_DOUT_PERI_SPI1>,
+ <&cmu_top CLK_DOUT_PERI_UART0>,
+ <&cmu_top CLK_DOUT_PERI_UART1>,
+ <&cmu_top CLK_DOUT_PERI_UART2>,
+ <&cmu_top CLK_DOUT_PERI_USI0>,
+ <&cmu_top CLK_DOUT_PERI_USI1>,
+ <&cmu_top CLK_DOUT_PERI_USI2>;
+ clock-names = "oscclk",
+ "dout_peri_bus",
+ "dout_peri_spi0",
+ "dout_peri_spi1",
+ "dout_peri_uart0",
+ "dout_peri_uart1",
+ "dout_peri_uart2",
+ "dout_peri_usi0",
+ "dout_peri_usi1",
+ "dout_peri_usi2";
+ };
+
+...
--
2.34.1

2021-12-06 15:53:47

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Subject: [PATCH v4 3/7] dt-bindings: arm: samsung: document jackpotlte board binding

Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)).

Signed-off-by: David Virag <[email protected]>
---
Changes in v2:
- Nothing

Changes in v3:
- Nothing

Changes in v4:
- Nothing

.../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
index ef6dc14be4b5..d88571202713 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
@@ -199,6 +199,12 @@ properties:
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
- const: samsung,exynos7

+ - description: Exynos7885 based boards
+ items:
+ - enum:
+ - samsung,jackpotlte # Samsung Galaxy A8 (2018)
+ - const: samsung,exynos7885
+
- description: Exynos Auto v9 based boards
items:
- enum:
--
2.34.1

2021-12-06 15:53:46

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Subject: [PATCH v4 4/7] clk: samsung: Make exynos850_register_cmu shared

Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it
to a new file called "clk-exynos-arm64.c".

This should have no functional changes, but it will allow this code to
be shared between other arm64 Exynos SoCs, like the Exynos7885 and
possibly ExynosAuto V9.

Signed-off-by: David Virag <[email protected]>
---
Changes in v2:
- New patch

Changes in v3:
- Fix SPDX comment style in clk-exynos-arm64.h

Changes in v4:
- Fix missing headers but still remove of_address.h
- "__SAMSUNG_CLK_ARM64_H" -> "__CLK_EXYNOS_ARM64_H" in
clk-exynos-arm64.h everywhere (only the comment at the end had the
latter by accident)

drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos-arm64.c | 94 ++++++++++++++++++++++++++
drivers/clk/samsung/clk-exynos-arm64.h | 20 ++++++
drivers/clk/samsung/clk-exynos850.c | 88 ++----------------------
4 files changed, 119 insertions(+), 84 deletions(-)
create mode 100644 drivers/clk/samsung/clk-exynos-arm64.c
create mode 100644 drivers/clk/samsung/clk-exynos-arm64.h

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index c46cf11e4d0b..901e6333c5f0 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/clk-exynos-arm64.c
new file mode 100644
index 000000000000..b921b9a1134a
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-arm64.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Linaro Ltd.
+ * Copyright (C) 2021 Dávid Virág <[email protected]>
+ * Author: Sam Protsenko <[email protected]>
+ * Author: Dávid Virág <[email protected]>
+ *
+ * This file contains shared functions used by some arm64 Exynos SoCs,
+ * such as Exynos7885 or Exynos850 to register and init CMUs.
+ */
+#include <linux/clk.h>
+#include <linux/of_address.h>
+
+#include "clk-exynos-arm64.h"
+
+/* Gate register bits */
+#define GATE_MANUAL BIT(20)
+#define GATE_ENABLE_HWACG BIT(28)
+
+/* Gate register offsets range */
+#define GATE_OFF_START 0x2000
+#define GATE_OFF_END 0x2fff
+
+/**
+ * exynos_arm64_init_clocks - Set clocks initial configuration
+ * @np: CMU device tree node with "reg" property (CMU addr)
+ * @reg_offs: Register offsets array for clocks to init
+ * @reg_offs_len: Number of register offsets in reg_offs array
+ *
+ * Set manual control mode for all gate clocks.
+ */
+static void __init exynos_arm64_init_clocks(struct device_node *np,
+ const unsigned long *reg_offs, size_t reg_offs_len)
+{
+ void __iomem *reg_base;
+ size_t i;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ for (i = 0; i < reg_offs_len; ++i) {
+ void __iomem *reg = reg_base + reg_offs[i];
+ u32 val;
+
+ /* Modify only gate clock registers */
+ if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
+ continue;
+
+ val = readl(reg);
+ val |= GATE_MANUAL;
+ val &= ~GATE_ENABLE_HWACG;
+ writel(val, reg);
+ }
+
+ iounmap(reg_base);
+}
+
+/**
+ * exynos_arm64_register_cmu - Register specified Exynos CMU domain
+ * @dev: Device object; may be NULL if this function is not being
+ * called from platform driver probe function
+ * @np: CMU device tree node
+ * @cmu: CMU data
+ *
+ * Register specified CMU domain, which includes next steps:
+ *
+ * 1. Enable parent clock of @cmu CMU
+ * 2. Set initial registers configuration for @cmu CMU clocks
+ * 3. Register @cmu CMU clocks using Samsung clock framework API
+ */
+void __init exynos_arm64_register_cmu(struct device *dev,
+ struct device_node *np, const struct samsung_cmu_info *cmu)
+{
+ /* Keep CMU parent clock running (needed for CMU registers access) */
+ if (cmu->clk_name) {
+ struct clk *parent_clk;
+
+ if (dev)
+ parent_clk = clk_get(dev, cmu->clk_name);
+ else
+ parent_clk = of_clk_get_by_name(np, cmu->clk_name);
+
+ if (IS_ERR(parent_clk)) {
+ pr_err("%s: could not find bus clock %s; err = %ld\n",
+ __func__, cmu->clk_name, PTR_ERR(parent_clk));
+ } else {
+ clk_prepare_enable(parent_clk);
+ }
+ }
+
+ exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
+ samsung_cmu_register_one(np, cmu);
+}
diff --git a/drivers/clk/samsung/clk-exynos-arm64.h b/drivers/clk/samsung/clk-exynos-arm64.h
new file mode 100644
index 000000000000..0dd174693935
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-arm64.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2021 Linaro Ltd.
+ * Copyright (C) 2021 Dávid Virág <[email protected]>
+ * Author: Sam Protsenko <[email protected]>
+ * Author: Dávid Virág <[email protected]>
+ *
+ * This file contains shared functions used by some arm64 Exynos SoCs,
+ * such as Exynos7885 or Exynos850 to register and init CMUs.
+ */
+
+#ifndef __CLK_EXYNOS_ARM64_H
+#define __CLK_EXYNOS_ARM64_H
+
+#include "clk.h"
+
+void exynos_arm64_register_cmu(struct device *dev,
+ struct device_node *np, const struct samsung_cmu_info *cmu);
+
+#endif /* __CLK_EXYNOS_ARM64_H */
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index 568ac97c8120..17413135196d 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -9,93 +9,13 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
-#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include <dt-bindings/clock/exynos850.h>

#include "clk.h"
-
-/* Gate register bits */
-#define GATE_MANUAL BIT(20)
-#define GATE_ENABLE_HWACG BIT(28)
-
-/* Gate register offsets range */
-#define GATE_OFF_START 0x2000
-#define GATE_OFF_END 0x2fff
-
-/**
- * exynos850_init_clocks - Set clocks initial configuration
- * @np: CMU device tree node with "reg" property (CMU addr)
- * @reg_offs: Register offsets array for clocks to init
- * @reg_offs_len: Number of register offsets in reg_offs array
- *
- * Set manual control mode for all gate clocks.
- */
-static void __init exynos850_init_clocks(struct device_node *np,
- const unsigned long *reg_offs, size_t reg_offs_len)
-{
- void __iomem *reg_base;
- size_t i;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic("%s: failed to map registers\n", __func__);
-
- for (i = 0; i < reg_offs_len; ++i) {
- void __iomem *reg = reg_base + reg_offs[i];
- u32 val;
-
- /* Modify only gate clock registers */
- if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
- continue;
-
- val = readl(reg);
- val |= GATE_MANUAL;
- val &= ~GATE_ENABLE_HWACG;
- writel(val, reg);
- }
-
- iounmap(reg_base);
-}
-
-/**
- * exynos850_register_cmu - Register specified Exynos850 CMU domain
- * @dev: Device object; may be NULL if this function is not being
- * called from platform driver probe function
- * @np: CMU device tree node
- * @cmu: CMU data
- *
- * Register specified CMU domain, which includes next steps:
- *
- * 1. Enable parent clock of @cmu CMU
- * 2. Set initial registers configuration for @cmu CMU clocks
- * 3. Register @cmu CMU clocks using Samsung clock framework API
- */
-static void __init exynos850_register_cmu(struct device *dev,
- struct device_node *np, const struct samsung_cmu_info *cmu)
-{
- /* Keep CMU parent clock running (needed for CMU registers access) */
- if (cmu->clk_name) {
- struct clk *parent_clk;
-
- if (dev)
- parent_clk = clk_get(dev, cmu->clk_name);
- else
- parent_clk = of_clk_get_by_name(np, cmu->clk_name);
-
- if (IS_ERR(parent_clk)) {
- pr_err("%s: could not find bus clock %s; err = %ld\n",
- __func__, cmu->clk_name, PTR_ERR(parent_clk));
- } else {
- clk_prepare_enable(parent_clk);
- }
- }
-
- exynos850_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
- samsung_cmu_register_one(np, cmu);
-}
+#include "clk-exynos-arm64.h"

/* ---- CMU_TOP ------------------------------------------------------------- */

@@ -404,7 +324,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {

static void __init exynos850_cmu_top_init(struct device_node *np)
{
- exynos850_register_cmu(NULL, np, &top_cmu_info);
+ exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
}

/* Register CMU_TOP early, as it's a dependency for other early domains */
@@ -892,7 +812,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {

static void __init exynos850_cmu_peri_init(struct device_node *np)
{
- exynos850_register_cmu(NULL, np, &peri_cmu_info);
+ exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
}

/* Register CMU_PERI early, as it's needed for MCT timer */
@@ -1069,7 +989,7 @@ static int __init exynos850_cmu_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;

info = of_device_get_match_data(dev);
- exynos850_register_cmu(dev, dev->of_node, info);
+ exynos_arm64_register_cmu(dev, dev->of_node, info);

return 0;
}
--
2.34.1

2021-12-06 15:53:47

[permalink] [raw]

Subject: [PATCH v4 6/7] clk: samsung: Add initial Exynos7885 clock driver

This is an initial implementation adding basic clocks, such as UART,
USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the
Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which
was made by Sam Protsenko, thus the copyright and author lines were
kept.

Bus clocks are enabled by default as well to avoid hangs while trying to
access CMU registers.

Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of
CMU_CORE, and most of CMU_PERI is implemented as of now.

Signed-off-by: David Virag <[email protected]>
---
Changes in v2:
- Use shared code between Exynos850 and 7885 clock drivers
- As the code that was from the Exynos850 clock driver was moved to
clk-exynos-arm64.c and what remains is mostly SoC specific data,
move the Linaro copyright and Sam Protsenko author lines there.

Changes in v3:
- Nothing

Changes in v4:
- Fixed missing headers

drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos7885.c | 597 +++++++++++++++++++++++++++
2 files changed, 598 insertions(+)
create mode 100644 drivers/clk/samsung/clk-exynos7885.c

diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 901e6333c5f0..0df74916a895 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
+obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
new file mode 100644
index 000000000000..a7b106302706
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7885.c
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 Dávid Virág <[email protected]>
+ * Author: Dávid Virág <[email protected]>
+ *
+ * Common Clock Framework support for Exynos7885 SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/exynos7885.h>
+
+#include "clk.h"
+#include "clk-exynos-arm64.h"
+
+/* ---- CMU_TOP ------------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_TOP (0x12060000) */
+#define PLL_LOCKTIME_PLL_SHARED0 0x0000
+#define PLL_LOCKTIME_PLL_SHARED1 0x0004
+#define PLL_CON0_PLL_SHARED0 0x0100
+#define PLL_CON0_PLL_SHARED1 0x0120
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
+#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074
+#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078
+#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
+#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
+#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
+#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
+#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
+#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
+#define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880
+#define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884
+#define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888
+#define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c
+#define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890
+#define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894
+#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c
+#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0
+#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4
+#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8
+#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac
+#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0
+#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4
+#define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
+#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094
+#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098
+
+static const unsigned long top_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_SHARED0,
+ PLL_LOCKTIME_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART0,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART1,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART2,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI0,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI1,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI2,
+ CLK_CON_DIV_CLKCMU_CORE_BUS,
+ CLK_CON_DIV_CLKCMU_CORE_CCI,
+ CLK_CON_DIV_CLKCMU_CORE_G3D,
+ CLK_CON_DIV_CLKCMU_PERI_BUS,
+ CLK_CON_DIV_CLKCMU_PERI_SPI0,
+ CLK_CON_DIV_CLKCMU_PERI_SPI1,
+ CLK_CON_DIV_CLKCMU_PERI_UART0,
+ CLK_CON_DIV_CLKCMU_PERI_UART1,
+ CLK_CON_DIV_CLKCMU_PERI_UART2,
+ CLK_CON_DIV_CLKCMU_PERI_USI0,
+ CLK_CON_DIV_CLKCMU_PERI_USI1,
+ CLK_CON_DIV_CLKCMU_PERI_USI2,
+ CLK_CON_DIV_PLL_SHARED0_DIV2,
+ CLK_CON_DIV_PLL_SHARED0_DIV3,
+ CLK_CON_DIV_PLL_SHARED0_DIV4,
+ CLK_CON_DIV_PLL_SHARED0_DIV5,
+ CLK_CON_DIV_PLL_SHARED1_DIV2,
+ CLK_CON_DIV_PLL_SHARED1_DIV3,
+ CLK_CON_DIV_PLL_SHARED1_DIV4,
+ CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1,
+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
+ CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART0,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART2,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI0,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI1,
+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI2,
+};
+
+static const struct samsung_pll_clock top_pll_clks[] __initconst = {
+ PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
+ NULL),
+ PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
+ PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
+ NULL),
+};
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
+PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared0_div3" };
+PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared0_div3" };
+PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared0_div3" };
+
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
+PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
+PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
+PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
+PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
+PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
+PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
+PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
+PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
+PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
+
+static const struct samsung_mux_clock top_mux_clks[] __initconst = {
+ /* CORE */
+ MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
+ MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
+ MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
+ CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
+
+ /* PERI */
+ MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
+ MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
+ MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
+ MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
+ MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
+ MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
+ MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
+ MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
+ MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
+ CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
+};
+
+static const struct samsung_div_clock top_div_clks[] __initconst = {
+ /* TOP */
+ DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
+ DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
+ CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
+ DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
+ DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
+ DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
+ CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
+
+ /* CORE */
+ DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
+ CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
+ DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
+ CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
+ DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d",
+ CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
+
+ /* PERI */
+ DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
+ CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
+ DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0",
+ CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
+ DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1",
+ CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
+ DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0",
+ CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
+ DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1",
+ CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
+ DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2",
+ CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
+ DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0",
+ CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
+ DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1",
+ CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
+ DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
+ CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
+};
+
+static const struct samsung_gate_clock top_gate_clks[] __initconst = {
+ /* CORE */
+ GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
+ GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d",
+ CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
+
+ /* PERI */
+ GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1",
+ CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
+ GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
+ CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info top_cmu_info __initconst = {
+ .pll_clks = top_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
+ .mux_clks = top_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
+ .div_clks = top_div_clks,
+ .nr_div_clks = ARRAY_SIZE(top_div_clks),
+ .gate_clks = top_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
+ .nr_clk_ids = TOP_NR_CLK,
+ .clk_regs = top_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
+};
+
+static void __init exynos7885_cmu_top_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
+}
+
+/* Register CMU_TOP early, as it's a dependency for other early domains */
+CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
+ exynos7885_cmu_top_init);
+
+/* ---- CMU_PERI ------------------------------------------------------------ */
+
+/* Register Offset definitions for CMU_PERI (0x10010000) */
+#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100
+#define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120
+#define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140
+#define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160
+#define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180
+#define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0
+#define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0
+#define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0
+#define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200
+#define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024
+#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
+#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c
+#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030
+#define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034
+#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038
+#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c
+#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040
+#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044
+#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048
+#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c
+#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050
+#define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054
+#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058
+#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c
+#define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060
+#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064
+#define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068
+#define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c
+#define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070
+#define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074
+#define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078
+#define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c
+#define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080
+#define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084
+#define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088
+#define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090
+#define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094
+#define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098
+#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0
+#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0
+#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4
+#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8
+
+static const unsigned long peri_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_UART0_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_UART1_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_UART2_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_USI0_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_USI1_USER,
+ PLL_CON0_MUX_CLKCMU_PERI_USI2_USER,
+ CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK,
+ CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
+ CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
+ CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
+ CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
+ CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK,
+ CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
+ CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
+ CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK,
+ CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
+ CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK,
+ CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK,
+ CLK_CON_GAT_GOUT_PERI_UART_0_PCLK,
+ CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK,
+ CLK_CON_GAT_GOUT_PERI_UART_1_PCLK,
+ CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK,
+ CLK_CON_GAT_GOUT_PERI_UART_2_PCLK,
+ CLK_CON_GAT_GOUT_PERI_USI0_PCLK,
+ CLK_CON_GAT_GOUT_PERI_USI0_SCLK,
+ CLK_CON_GAT_GOUT_PERI_USI1_PCLK,
+ CLK_CON_GAT_GOUT_PERI_USI1_SCLK,
+ CLK_CON_GAT_GOUT_PERI_USI2_PCLK,
+ CLK_CON_GAT_GOUT_PERI_USI2_SCLK,
+ CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
+ CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_PERI */
+PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
+PNAME(mout_peri_spi0_user_p) = { "oscclk", "dout_peri_spi0" };
+PNAME(mout_peri_spi1_user_p) = { "oscclk", "dout_peri_spi1" };
+PNAME(mout_peri_uart0_user_p) = { "oscclk", "dout_peri_uart0" };
+PNAME(mout_peri_uart1_user_p) = { "oscclk", "dout_peri_uart1" };
+PNAME(mout_peri_uart2_user_p) = { "oscclk", "dout_peri_uart2" };
+PNAME(mout_peri_usi0_user_p) = { "oscclk", "dout_peri_usi0" };
+PNAME(mout_peri_usi1_user_p) = { "oscclk", "dout_peri_usi1" };
+PNAME(mout_peri_usi2_user_p) = { "oscclk", "dout_peri_usi2" };
+
+static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p,
+ PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p,
+ PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
+ mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
+ mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
+ mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
+ mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
+ mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1),
+ MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user",
+ mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1),
+};
+
+static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
+ GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk",
+ "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
+ "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user",
+ CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
+ GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user",
+ CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
+ GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user",
+ CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
+ GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user",
+ CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
+ GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user",
+ CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
+ GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user",
+ CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
+ GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user",
+ CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
+ GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user",
+ CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
+ GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
+ "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
+ CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info peri_cmu_info __initconst = {
+ .mux_clks = peri_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
+ .gate_clks = peri_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
+ .nr_clk_ids = PERI_NR_CLK,
+ .clk_regs = peri_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
+ .clk_name = "dout_peri_bus",
+};
+
+static void __init exynos7885_cmu_peri_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
+}
+
+/* Register CMU_PERI early, as it's needed for MCT timer */
+CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
+ exynos7885_cmu_peri_init);
+
+/* ---- CMU_CORE ------------------------------------------------------------ */
+
+/* Register Offset definitions for CMU_CORE (0x12000000) */
+#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
+#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
+#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
+#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
+#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
+#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
+#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
+
+static const unsigned long core_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
+ PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
+ CLK_CON_MUX_MUX_CLK_CORE_GIC,
+ CLK_CON_DIV_DIV_CLK_CORE_BUSP,
+ CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
+ CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
+};
+
+/* List of parent clocks for Muxes in CMU_CORE */
+PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
+PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
+PNAME(mout_core_g3d_user_p) = { "oscclk", "dout_core_g3d" };
+PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
+
+static const struct samsung_mux_clock core_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
+ PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
+ MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p,
+ PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
+ MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
+ CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
+};
+
+static const struct samsung_div_clock core_div_clks[] __initconst = {
+ DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
+ CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
+};
+
+static const struct samsung_gate_clock core_gate_clks[] __initconst = {
+ /* CCI (interconnect) clock must be always running */
+ GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
+ CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
+ /* GIC (interrupt controller) clock must be always running */
+ GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
+ CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info core_cmu_info __initconst = {
+ .mux_clks = core_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
+ .div_clks = core_div_clks,
+ .nr_div_clks = ARRAY_SIZE(core_div_clks),
+ .gate_clks = core_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
+ .nr_clk_ids = CORE_NR_CLK,
+ .clk_regs = core_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
+ .clk_name = "dout_core_bus",
+};
+
+/* ---- platform_driver ----------------------------------------------------- */
+
+static int __init exynos7885_cmu_probe(struct platform_device *pdev)
+{
+ const struct samsung_cmu_info *info;
+ struct device *dev = &pdev->dev;
+
+ info = of_device_get_match_data(dev);
+ exynos_arm64_register_cmu(dev, dev->of_node, info);
+
+ return 0;
+}
+
+static const struct of_device_id exynos7885_cmu_of_match[] = {
+ {
+ .compatible = "samsung,exynos7885-cmu-core",
+ .data = &core_cmu_info,
+ }, {
+ },
+};
+
+static struct platform_driver exynos7885_cmu_driver __refdata = {
+ .driver = {
+ .name = "exynos7885-cmu",
+ .of_match_table = exynos7885_cmu_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = exynos7885_cmu_probe,
+};
+
+static int __init exynos7885_cmu_init(void)
+{
+ return platform_driver_register(&exynos7885_cmu_driver);
+}
+core_initcall(exynos7885_cmu_init);
--
2.34.1

2021-12-06 16:00:03

[permalink] [raw]

Subject: [PATCH v4 5/7] clk: samsung: clk-pll: Add support for pll1417x

pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
It is similar enough to pll0822x that practically the same code can
handle both. The difference that's to be noted is that when defining a
pl1417x PLL, the "con" parameter of the PLL macro should be set to the
CON1 register instead of CON3, like this:

PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
NULL),

Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: David Virag <[email protected]>
---
Changes in v2:
- Nothing

Changes in v3:
- Nothing

Changes in v4:
- Added R-b tag by Krzysztof Kozlowski

drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
2 files changed, 2 insertions(+)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 83d1b03647db..70cdc87f714e 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
else
init.ops = &samsung_pll35xx_clk_ops;
break;
+ case pll_1417x:
case pll_0822x:
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a739f2b7ae80..c83a20195f6d 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -32,6 +32,7 @@ enum samsung_pll_type {
pll_2550xx,
pll_2650x,
pll_2650xx,
+ pll_1417x,
pll_1450x,
pll_1451x,
pll_1452x,
--
2.34.1

2021-12-06 16:00:03

[permalink] [raw]

Subject: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy
A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
Currently this includes some clock support, UART support, and I2C nodes.

Signed-off-by: David Virag <[email protected]>
---
Changes in v2:
- Remove address-cells, and size-cells from dts, since they are
already in the dtsi.
- Lower case hex in memory node
- Fix node names with underscore instead of hyphen
- Fix line breaks
- Fix "-key" missing from gpio keys node names
- Use the form without "key" in gpio key labels on all keys
- Suffix pin configuration node names with "-pins"
- Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
- Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
- Add comment about Arm PMU
- Rename "clock-oscclk" to "osc-clock"
- Include exynos-syscon-restart.dtsi instead of rewriting its contents

Changes in v3:
- Fix typo (seperate -> separate)

Changes in v4:
- Fixed leading 0x in clock-controller nodes
- Actually suffixed pin configuration node names with "-pins"
- Seperated Cortex-A53 and Cortex-A73 PMU

arch/arm64/boot/dts/exynos/Makefile | 7 +-
.../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
.../boot/dts/exynos/exynos7885-pinctrl.dtsi | 865 ++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos7885.dtsi | 438 +++++++++
4 files changed, 1402 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi

diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index b41e86df0a84..c68c4ad577ac 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_EXYNOS) += \
- exynos5433-tm2.dtb \
- exynos5433-tm2e.dtb \
- exynos7-espresso.dtb \
+ exynos5433-tm2.dtb \
+ exynos5433-tm2e.dtb \
+ exynos7-espresso.dtb \
+ exynos7885-jackpotlte.dtb \
exynosautov9-sadk.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
new file mode 100644
index 000000000000..f5941dc4c374
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
+ *
+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2021 Dávid Virág
+ *
+ */
+
+/dts-v1/;
+#include "exynos7885.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Samsung Galaxy A8 (2018)";
+ compatible = "samsung,jackpotlte", "samsung,exynos7885";
+ chassis-type = "handset";
+
+ aliases {
+ serial0 = &serial_0;
+ serial1 = &serial_1;
+ serial2 = &serial_2;
+ };
+
+ chosen {
+ stdout-path = &serial_2;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x3da00000>,
+ <0x0 0xc0000000 0x40000000>,
+ <0x8 0x80000000 0x40000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_volup &key_voldown &key_power>;
+
+ volup-key {
+ label = "Volume Up";
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-parent = <&gpa1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
+ };
+
+ voldown-key {
+ label = "Volume Down";
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-parent = <&gpa1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
+ };
+
+ power-key {
+ label = "Power";
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-parent = <&gpa1>;
+ linux,code = <KEY_POWER>;
+ gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+ };
+};
+
+&serial_2 {
+ status = "okay";
+};
+
+&pinctrl_alive {
+ key_volup: key-volup-pins {
+ samsung,pins = "gpa1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ key_voldown: key-voldown-pins {
+ samsung,pins = "gpa1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ key_power: key-power-pins {
+ samsung,pins = "gpa1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
new file mode 100644
index 000000000000..8336b2e48858
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
@@ -0,0 +1,865 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2021 Dávid Virág
+ *
+ * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ */
+
+#include <dt-bindings/pinctrl/samsung.h>
+
+&pinctrl_alive {
+ etc0: etc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ etc1: etc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpq0: gpq0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sim1_det_gpio: sim1-det-gpio-pins {
+ samsung,pins = "gpa2-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ sim0_det_gpio: sim0-det-gpio-pins {
+ samsung,pins = "gpa2-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ speedy_bus: speedy-bus-pins {
+ samsung,pins = "gpq0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ /* UART_DEBUG */
+ uart2_bus: uart2-bus-pins {
+ samsung,pins = "gpq0-4", "gpq0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+};
+
+&pinctrl_dispaud {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb2: gpb2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ aud_codec_mclk: aud-codec-mclk-pins {
+ samsung,pins = "gpb0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_codec_mclk_idle: aud-codec-mclk-idle-pins {
+ samsung,pins = "gpb0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_codec_bus: aud-codec-bus-pins {
+ samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_codec_bus_idle: aud-codec-bus-idle-pins {
+ samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_loopback_bus: aud-loopback-bus-pins {
+ samsung,pins = "gpb1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_loopback_bus_idle: aud-loopback-bus-idle-pins {
+ samsung,pins = "gpb1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_fm_bus: aud-fm-bus-pins {
+ samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_fm_bus_idle: aud-fm-bus-idle-pins {
+ samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_spk_bus: aud-spk-bus-pins {
+ samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+
+ aud_spk_bus_idle: aud-spk-bus-idle-pins {
+ samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ };
+};
+
+&pinctrl_fsys {
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sd0_clk: sd0-clk-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <1>;
+ };
+
+ sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_cmd: sd0-cmd-pins {
+ samsung,pins = "gpf0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_rdqs: sd0-rdqs-pins {
+ samsung,pins = "gpf0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus1: sd0-bus-width1-pins {
+ samsung,pins = "gpf2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus4: sd0-bus-width4-pins {
+ samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd0_bus8: sd0-bus-width8-pins {
+ samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_clk: sd1-clk-pins {
+ samsung,pins = "gpf3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins {
+ samsung,pins = "gpf3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins {
+ samsung,pins = "gpf3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <1>;
+ };
+
+ sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins {
+ samsung,pins = "gpf3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins {
+ samsung,pins = "gpf3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd1_cmd: sd1-cmd-pins {
+ samsung,pins = "gpf3-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus1: sd1-bus-width1-pins {
+ samsung,pins = "gpf3-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd1_bus4: sd1-bus-width4-pins {
+ samsung,pins = "gpf3-3", "gpf3-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_clk: sd2-clk-pins {
+ samsung,pins = "gpf4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
+ samsung,pins = "gpf4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
+ samsung,pins = "gpf4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <1>;
+ };
+
+ sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
+ samsung,pins = "gpf4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
+ samsung,pins = "gpf4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd-pins {
+ samsung,pins = "gpf4-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_bus1: sd2-bus-width1-pins {
+ samsung,pins = "gpf4-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>;
+ };
+
+ sd2_bus4: sd2-bus-width4-pins {
+ samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <2>;
+ };
+};
+
+&pinctrl_top {
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg4: gpg4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp0: gpp0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp1: gpp1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp2: gpp2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp3: gpp3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp4: gpp4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp5: gpp5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp6: gpp6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp7: gpp7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpp8: gpp8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ /* DECON TE */
+ decon_f_te_on: decon_f_te_on-pins {
+ samsung,pins = "gpc0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
+ };
+
+ decon_f_te_off: decon_f_te_off-pins {
+ samsung,pins = "gpc0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
+ };
+
+ hs_i2c0_bus: hs-i2c0-bus-pins {
+ samsung,pins = "gpc1-1", "gpc1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ };
+
+ hs_i2c1_bus: hs-i2c1-bus-pins {
+ samsung,pins = "gpc1-3", "gpc1-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ hs_i2c2_bus: hs-i2c2-bus-pins {
+ samsung,pins = "gpc1-5", "gpc1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ hs_i2c3_bus: hs-i2c3-bus-pins {
+ samsung,pins = "gpc1-7", "gpc1-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ /* USI0 UART */
+ uart3_bus_single: uart3-bus-single-pins {
+ samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI0 UART_HSI2C1 */
+ uart3_bus_dual: uart3-bus-dual-pins {
+ samsung,pins = "gpc2-1", "gpc2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI0 HSI2C0 */
+ hs_i2c4_bus: hs-i2c4-bus-pins {
+ samsung,pins = "gpc2-1", "gpc2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ /* USI0 HSI2C1 */
+ hs_i2c5_bus: hs-i2c5-bus-pins {
+ samsung,pins = "gpc2-3", "gpc2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ /* USI0 SPI */
+ spi2_bus: spi2-bus-pins {
+ samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi2_cs: spi2-cs-pins {
+ samsung,pins = "gpc2-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ /* USI1 UART */
+ uart4_bus_single: uart4-bus-single-pins {
+ samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI1 UART_HSI2C1*/
+ uart4_bus_dual: uart4-bus-dual-pins {
+ samsung,pins = "gpc2-5", "gpc2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI1 HSI2C0 */
+ hs_i2c6_bus: hs-i2c6-bus-pins {
+ samsung,pins = "gpc2-5", "gpc2-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ /* USI1 HSI2C1 */
+ hs_i2c7_bus: hs-i2c7-bus-pins {
+ samsung,pins = "gpc2-7", "gpc2-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ /* USI1 SPI */
+ spi3_bus: spi3-bus-pins {
+ samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi3_cs: spi3-cs-pins {
+ samsung,pins = "gpc2-6";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ fm_lna_en: fm-lna-en-pins {
+ samsung,pins = "gpg0-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-val = <1>;
+ };
+
+ uart1_bus: uart1-bus-pins {
+ samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i2c7_bus: i2c7-bus-pins {
+ samsung,pins = "gpg1-5", "gpg1-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ aud_dmic_on: aud-dmic-on-pins {
+ samsung,pins = "gpg2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-val = <1>;
+ };
+
+ aud_dmic_off: aud-dmic-off-pins {
+ samsung,pins = "gpg2-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-val = <0>;
+ };
+
+ /* UART_HEALTH */
+ uart0_bus: uart0-bus-pins {
+ samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ i2c0_bus: i2c0-bus-pins {
+ samsung,pins = "gpp1-1", "gpp1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c1_bus: i2c1-bus-pins {
+ samsung,pins = "gpp1-3", "gpp1-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c2_bus: i2c2-bus-pins {
+ samsung,pins = "gpp2-1", "gpp2-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c3_bus: i2c3-bus-pins {
+ samsung,pins = "gpp3-1", "gpp3-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c4_bus: i2c4-bus-pins {
+ samsung,pins = "gpp4-1", "gpp4-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c5_bus: i2c5-bus-pins {
+ samsung,pins = "gpp4-3", "gpp4-2";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ i2c6_bus: i2c6-bus-pins {
+ samsung,pins = "gpp4-5", "gpp4-4";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ /* SPI_ESE */
+ spi0_bus: spi0-bus-pins {
+ samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi0_cs: spi0-cs-pins {
+ samsung,pins = "gpp5-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ /* SPI_FP */
+ spi1_bus: spi1-bus-pins {
+ samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi1_cs: spi1-cs-pins {
+ samsung,pins = "gpp6-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ /* USI2 UART */
+ uart5_bus_single: uart5-bus-single-pins {
+ samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI2 UART_HSI2C1 */
+ uart5_bus_dual: uart5-bus-dual-pins {
+ samsung,pins = "gpp7-1", "gpp7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ };
+
+ /* USI2 HSI2C0 */
+ hs_i2c8_bus: hs-i2c8-bus-pins {
+ samsung,pins = "gpp7-1", "gpp7-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ /* USI2 HSI2C1 */
+ hs_i2c9_bus: hs-i2c9-bus-pins {
+ samsung,pins = "gpp8-1", "gpp8-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <0>;
+ samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
+ samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
+ };
+
+ /* USI2 SPI */
+ spi4_bus: spi4-bus-pins {
+ samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+
+ spi4_cs: spi4-cs-pins {
+ samsung,pins = "gpp8-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
new file mode 100644
index 000000000000..cc7a5ce0c103
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos7885 SoC device tree source
+ *
+ * Copyright (c) 2021 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2021 Dávid Virág
+ *
+ */
+
+#include <dt-bindings/clock/exynos7885.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "samsung,exynos7885";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ pinctrl0 = &pinctrl_alive;
+ pinctrl1 = &pinctrl_dispaud;
+ pinctrl2 = &pinctrl_fsys;
+ pinctrl3 = &pinctrl_top;
+ };
+
+ arm-a53-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>,
+ <&cpu4>,
+ <&cpu5>;
+ };
+
+ arm-a73-pmu {
+ compatible = "arm,cortex-a73-pmu";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu6>,
+ <&cpu7>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ core4 {
+ cpu = <&cpu4>;
+ };
+ core5 {
+ cpu = <&cpu5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu6>;
+ };
+ core1 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ };
+
+ cpu4: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+
+ cpu5: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x201>;
+ enable-method = "psci";
+ };
+
+ cpu6: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x0>;
+ enable-method = "psci";
+ };
+
+ cpu7: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x1>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_suspend = <0xc4000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0xc4000003>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ /* Hypervisor Virtual Timer interrupt is not wired to GIC */
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ fixed-rate-clocks {
+ oscclk: osc-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "oscclk";
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x20000000>;
+
+ chipid@10000000 {
+ compatible = "samsung,exynos850-chipid";
+ reg = <0x10000000 0x24>;
+ };
+
+ gic: interrupt-controller@12301000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x12301000 0x1000>,
+ <0x12302000 0x2000>,
+ <0x12304000 0x2000>,
+ <0x12306000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ cmu_peri: clock-controller@10010000 {
+ compatible = "samsung,exynos7885-cmu-peri";
+ reg = <0x10010000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_PERI_BUS>,
+ <&cmu_top CLK_DOUT_PERI_SPI0>,
+ <&cmu_top CLK_DOUT_PERI_SPI1>,
+ <&cmu_top CLK_DOUT_PERI_UART0>,
+ <&cmu_top CLK_DOUT_PERI_UART1>,
+ <&cmu_top CLK_DOUT_PERI_UART2>,
+ <&cmu_top CLK_DOUT_PERI_USI0>,
+ <&cmu_top CLK_DOUT_PERI_USI1>,
+ <&cmu_top CLK_DOUT_PERI_USI2>;
+ clock-names = "oscclk",
+ "dout_peri_bus",
+ "dout_peri_spi0",
+ "dout_peri_spi1",
+ "dout_peri_uart0",
+ "dout_peri_uart1",
+ "dout_peri_uart2",
+ "dout_peri_usi0",
+ "dout_peri_usi1",
+ "dout_peri_usi2";
+ };
+
+ cmu_core: clock-controller@12000000 {
+ compatible = "samsung,exynos7885-cmu-core";
+ reg = <0x12000000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CORE_BUS>,
+ <&cmu_top CLK_DOUT_CORE_CCI>,
+ <&cmu_top CLK_DOUT_CORE_G3D>;
+ clock-names = "oscclk", "dout_core_bus", "dout_core_cci", "dout_core_g3d";
+ };
+
+ cmu_top: clock-controller@12060000 {
+ compatible = "samsung,exynos7885-cmu-top";
+ reg = <0x12060000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>;
+ clock-names = "oscclk";
+ };
+
+ pinctrl_alive: pinctrl@11cb0000 {
+ compatible = "samsung,exynos7885-pinctrl";
+ reg = <0x11cb0000 0x1000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+
+ wakeup-interrupt-controller {
+ compatible = "samsung,exynos7-wakeup-eint";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ pinctrl_dispaud: pinctrl@148f0000 {
+ compatible = "samsung,exynos7885-pinctrl";
+ reg = <0x148f0000 0x1000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_fsys: pinctrl@13430000 {
+ compatible = "samsung,exynos7885-pinctrl";
+ reg = <0x13430000 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_top: pinctrl@139b0000 {
+ compatible = "samsung,exynos7885-pinctrl";
+ reg = <0x139b0000 0x1000>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu_system_controller: system-controller@11c80000 {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x11c80000 0x10000>;
+ };
+
+ serial_0: serial@13800000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x13800000 0x100>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_bus>;
+ clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
+ <&cmu_peri CLK_GOUT_UART0_PCLK>;
+ clock-names = "uart", "clk_uart_baud0";
+ samsung,uart-fifosize = <64>;
+ status = "disabled";
+ };
+
+ serial_1: serial@13810000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x13810000 0x100>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_bus>;
+ clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
+ <&cmu_peri CLK_GOUT_UART1_PCLK>;
+ clock-names = "uart", "clk_uart_baud0";
+ samsung,uart-fifosize = <256>;
+ status = "disabled";
+ };
+
+ serial_2: serial@13820000 {
+ compatible = "samsung,exynos5433-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_bus>;
+ clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
+ <&cmu_peri CLK_GOUT_UART2_PCLK>;
+ clock-names = "uart", "clk_uart_baud0";
+ samsung,uart-fifosize = <256>;
+ status = "disabled";
+ };
+
+ i2c_0: i2c@13830000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13830000 0x100>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_1: i2c@13840000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13840000 0x100>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_2: i2c@13850000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13850000 0x100>;
+ interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_3: i2c@13860000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13860000 0x100>;
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_4: i2c@13870000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13870000 0x100>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_5: i2c@13880000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13880000 0x100>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_6: i2c@13890000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x13890000 0x100>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+
+ i2c_7: i2c@11cd0000 {
+ compatible = "samsung,s3c2440-i2c";
+ reg = <0x11cd0000 0x100>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_bus>;
+ clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
+ clock-names = "i2c";
+ status = "disabled";
+ };
+ };
+};
+
+#include "exynos7885-pinctrl.dtsi"
+#include "arm/exynos-syscon-restart.dtsi"
--
2.34.1

2021-12-07 09:32:46

[permalink] [raw]

Subject: Re: [PATCH v4 4/7] clk: samsung: Make exynos850_register_cmu shared

On 06/12/2021 16:31, David Virag wrote:
> Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it
> to a new file called "clk-exynos-arm64.c".
>
> This should have no functional changes, but it will allow this code to
> be shared between other arm64 Exynos SoCs, like the Exynos7885 and
> possibly ExynosAuto V9.
>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - New patch
>
> Changes in v3:
> - Fix SPDX comment style in clk-exynos-arm64.h
>
> Changes in v4:
> - Fix missing headers but still remove of_address.h
> - "__SAMSUNG_CLK_ARM64_H" -> "__CLK_EXYNOS_ARM64_H" in
> clk-exynos-arm64.h everywhere (only the comment at the end had the
> latter by accident)
>
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos-arm64.c | 94 ++++++++++++++++++++++++++
> drivers/clk/samsung/clk-exynos-arm64.h | 20 ++++++
> drivers/clk/samsung/clk-exynos850.c | 88 ++----------------------
> 4 files changed, 119 insertions(+), 84 deletions(-)
> create mode 100644 drivers/clk/samsung/clk-exynos-arm64.c
> create mode 100644 drivers/clk/samsung/clk-exynos-arm64.h
>

Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2021-12-07 09:33:08

[permalink] [raw]

Subject: Re: [PATCH v4 6/7] clk: samsung: Add initial Exynos7885 clock driver

On 06/12/2021 16:31, David Virag wrote:
> This is an initial implementation adding basic clocks, such as UART,
> USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the
> Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which
> was made by Sam Protsenko, thus the copyright and author lines were
> kept.
>
> Bus clocks are enabled by default as well to avoid hangs while trying to
> access CMU registers.
>
> Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of
> CMU_CORE, and most of CMU_PERI is implemented as of now.
>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Use shared code between Exynos850 and 7885 clock drivers
> - As the code that was from the Exynos850 clock driver was moved to
> clk-exynos-arm64.c and what remains is mostly SoC specific data,
> move the Linaro copyright and Sam Protsenko author lines there.
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Fixed missing headers
>
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos7885.c | 597 +++++++++++++++++++++++++++
> 2 files changed, 598 insertions(+)
> create mode 100644 drivers/clk/samsung/clk-exynos7885.c
>

Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2021-12-07 09:39:21

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On 06/12/2021 16:31, David Virag wrote:
> Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy
> A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> Currently this includes some clock support, UART support, and I2C nodes.
>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Remove address-cells, and size-cells from dts, since they are
> already in the dtsi.
> - Lower case hex in memory node
> - Fix node names with underscore instead of hyphen
> - Fix line breaks
> - Fix "-key" missing from gpio keys node names
> - Use the form without "key" in gpio key labels on all keys
> - Suffix pin configuration node names with "-pins"
> - Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
> - Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
> - Add comment about Arm PMU
> - Rename "clock-oscclk" to "osc-clock"
> - Include exynos-syscon-restart.dtsi instead of rewriting its contents
>
> Changes in v3:
> - Fix typo (seperate -> separate)
>
> Changes in v4:
> - Fixed leading 0x in clock-controller nodes
> - Actually suffixed pin configuration node names with "-pins"
> - Seperated Cortex-A53 and Cortex-A73 PMU
>
> arch/arm64/boot/dts/exynos/Makefile | 7 +-
> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
> .../boot/dts/exynos/exynos7885-pinctrl.dtsi | 865 ++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 438 +++++++++
> 4 files changed, 1402 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi
>

(...)

> +
> + gpp8: gpp8 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + /* DECON TE */
> + decon_f_te_on: decon_f_te_on-pins {
> + samsung,pins = "gpc0-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> + };
> +
> + decon_f_te_off: decon_f_te_off-pins {

Drop these, similarly to FIMC. Only one pin configuration will be used
when you add DECON support, not two. If you wish to keep one, the proper
for DECON operating state, this also needs fixing of underscores->hyphens.

> + samsung,pins = "gpc0-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + };
> +

(...)

> diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> new file mode 100644
> index 000000000000..cc7a5ce0c103
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> @@ -0,0 +1,438 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Exynos7885 SoC device tree source
> + *
> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2021 Dávid Virág
> + *
> + */
> +
> +#include <dt-bindings/clock/exynos7885.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "samsung,exynos7885";
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_alive;
> + pinctrl1 = &pinctrl_dispaud;
> + pinctrl2 = &pinctrl_fsys;
> + pinctrl3 = &pinctrl_top;
> + };
> +
> + arm-a53-pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>,
> + <&cpu1>,
> + <&cpu2>,
> + <&cpu3>,
> + <&cpu4>,
> + <&cpu5>;
> + };
> +
> + arm-a73-pmu {
> + compatible = "arm,cortex-a73-pmu";
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu6>,
> + <&cpu7>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + core4 {
> + cpu = <&cpu4>;
> + };
> + core5 {
> + cpu = <&cpu5>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x100>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x101>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x102>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x103>;
> + enable-method = "psci";
> + };
> +
> + cpu4: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x200>;
> + enable-method = "psci";
> + };
> +
> + cpu5: cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x201>;
> + enable-method = "psci";
> + };
> +
> + cpu6: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x0>;
> + enable-method = "psci";
> + };
> +
> + cpu7: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x1>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci";
> + method = "smc";
> + cpu_suspend = <0xc4000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + /* Hypervisor Virtual Timer interrupt is not wired to GIC */
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + fixed-rate-clocks {
> + oscclk: osc-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "oscclk";
> + };
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x20000000>;
> +
> + chipid@10000000 {
> + compatible = "samsung,exynos850-chipid";
> + reg = <0x10000000 0x24>;
> + };
> +
> + gic: interrupt-controller@12301000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x12301000 0x1000>,
> + <0x12302000 0x2000>,
> + <0x12304000 0x2000>,
> + <0x12306000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + cmu_peri: clock-controller@10010000 {
> + compatible = "samsung,exynos7885-cmu-peri";
> + reg = <0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>,
> + <&cmu_top CLK_DOUT_PERI_BUS>,
> + <&cmu_top CLK_DOUT_PERI_SPI0>,
> + <&cmu_top CLK_DOUT_PERI_SPI1>,
> + <&cmu_top CLK_DOUT_PERI_UART0>,
> + <&cmu_top CLK_DOUT_PERI_UART1>,
> + <&cmu_top CLK_DOUT_PERI_UART2>,
> + <&cmu_top CLK_DOUT_PERI_USI0>,
> + <&cmu_top CLK_DOUT_PERI_USI1>,
> + <&cmu_top CLK_DOUT_PERI_USI2>;
> + clock-names = "oscclk",
> + "dout_peri_bus",
> + "dout_peri_spi0",
> + "dout_peri_spi1",
> + "dout_peri_uart0",
> + "dout_peri_uart1",
> + "dout_peri_uart2",
> + "dout_peri_usi0",
> + "dout_peri_usi1",
> + "dout_peri_usi2";
> + };
> +
> + cmu_core: clock-controller@12000000 {
> + compatible = "samsung,exynos7885-cmu-core";
> + reg = <0x12000000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>,
> + <&cmu_top CLK_DOUT_CORE_BUS>,
> + <&cmu_top CLK_DOUT_CORE_CCI>,
> + <&cmu_top CLK_DOUT_CORE_G3D>;
> + clock-names = "oscclk", "dout_core_bus", "dout_core_cci", "dout_core_g3d";
> + };
> +
> + cmu_top: clock-controller@12060000 {
> + compatible = "samsung,exynos7885-cmu-top";
> + reg = <0x12060000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>;
> + clock-names = "oscclk";
> + };
> +
> + pinctrl_alive: pinctrl@11cb0000 {
> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x11cb0000 0x1000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "samsung,exynos7-wakeup-eint";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + pinctrl_dispaud: pinctrl@148f0000 {

Let's bring some order - put pinctrl nodes within each other ordered by
unit address. The ordering of other nodes is okay, we never actually
enforced any logic here.

> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x148f0000 0x1000>;
> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_fsys: pinctrl@13430000 {
> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x13430000 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_top: pinctrl@139b0000 {
> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x139b0000 0x1000>;
> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +

Best regards,
Krzysztof

2021-12-07 18:15:42

[permalink] [raw]

Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU

On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>
> Just like on Exynos850, the clock controller driver is designed to have
> separate instances for each particular CMU, so clock IDs start from 1
> for each CMU in this bindings header too.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: David Virag <[email protected]>
> ---

Reviewed-by: Sam Protsenko <[email protected]>

> Changes in v2:
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Nothing
>
> include/dt-bindings/clock/exynos7885.h | 115 +++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 include/dt-bindings/clock/exynos7885.h
>
> diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
> new file mode 100644
> index 000000000000..1f8701691d62
> --- /dev/null
> +++ b/include/dt-bindings/clock/exynos7885.h
> @@ -0,0 +1,115 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2021 Dávid Virág
> + *
> + * Device Tree binding constants for Exynos7885 clock controller.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
> +#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H
> +
> +/* CMU_TOP */
> +#define CLK_FOUT_SHARED0_PLL 1
> +#define CLK_FOUT_SHARED1_PLL 2
> +#define CLK_DOUT_SHARED0_DIV2 3
> +#define CLK_DOUT_SHARED0_DIV3 4
> +#define CLK_DOUT_SHARED0_DIV4 5
> +#define CLK_DOUT_SHARED0_DIV5 6
> +#define CLK_DOUT_SHARED1_DIV2 7
> +#define CLK_DOUT_SHARED1_DIV3 8
> +#define CLK_DOUT_SHARED1_DIV4 9
> +#define CLK_MOUT_CORE_BUS 10
> +#define CLK_MOUT_CORE_CCI 11
> +#define CLK_MOUT_CORE_G3D 12
> +#define CLK_DOUT_CORE_BUS 13
> +#define CLK_DOUT_CORE_CCI 14
> +#define CLK_DOUT_CORE_G3D 15
> +#define CLK_GOUT_CORE_BUS 16
> +#define CLK_GOUT_CORE_CCI 17
> +#define CLK_GOUT_CORE_G3D 18
> +#define CLK_MOUT_PERI_BUS 19
> +#define CLK_MOUT_PERI_SPI0 20
> +#define CLK_MOUT_PERI_SPI1 21
> +#define CLK_MOUT_PERI_UART0 22
> +#define CLK_MOUT_PERI_UART1 23
> +#define CLK_MOUT_PERI_UART2 24
> +#define CLK_MOUT_PERI_USI0 25
> +#define CLK_MOUT_PERI_USI1 26
> +#define CLK_MOUT_PERI_USI2 27
> +#define CLK_DOUT_PERI_BUS 28
> +#define CLK_DOUT_PERI_SPI0 29
> +#define CLK_DOUT_PERI_SPI1 30
> +#define CLK_DOUT_PERI_UART0 31
> +#define CLK_DOUT_PERI_UART1 32
> +#define CLK_DOUT_PERI_UART2 33
> +#define CLK_DOUT_PERI_USI0 34
> +#define CLK_DOUT_PERI_USI1 35
> +#define CLK_DOUT_PERI_USI2 36
> +#define CLK_GOUT_PERI_BUS 37
> +#define CLK_GOUT_PERI_SPI0 38
> +#define CLK_GOUT_PERI_SPI1 39
> +#define CLK_GOUT_PERI_UART0 40
> +#define CLK_GOUT_PERI_UART1 41
> +#define CLK_GOUT_PERI_UART2 42
> +#define CLK_GOUT_PERI_USI0 43
> +#define CLK_GOUT_PERI_USI1 44
> +#define CLK_GOUT_PERI_USI2 45
> +#define TOP_NR_CLK 46
> +
> +/* CMU_CORE */
> +#define CLK_MOUT_CORE_BUS_USER 1
> +#define CLK_MOUT_CORE_CCI_USER 2
> +#define CLK_MOUT_CORE_G3D_USER 3
> +#define CLK_MOUT_CORE_GIC 4
> +#define CLK_DOUT_CORE_BUSP 5
> +#define CLK_GOUT_CCI_ACLK 6
> +#define CLK_GOUT_GIC400_CLK 7
> +#define CORE_NR_CLK 8
> +
> +/* CMU_PERI */
> +#define CLK_MOUT_PERI_BUS_USER 1
> +#define CLK_MOUT_PERI_SPI0_USER 2
> +#define CLK_MOUT_PERI_SPI1_USER 3
> +#define CLK_MOUT_PERI_UART0_USER 4
> +#define CLK_MOUT_PERI_UART1_USER 5
> +#define CLK_MOUT_PERI_UART2_USER 6
> +#define CLK_MOUT_PERI_USI0_USER 7
> +#define CLK_MOUT_PERI_USI1_USER 8
> +#define CLK_MOUT_PERI_USI2_USER 9
> +#define CLK_GOUT_GPIO_TOP_PCLK 10
> +#define CLK_GOUT_HSI2C0_PCLK 11
> +#define CLK_GOUT_HSI2C1_PCLK 12
> +#define CLK_GOUT_HSI2C2_PCLK 13
> +#define CLK_GOUT_HSI2C3_PCLK 14
> +#define CLK_GOUT_I2C0_PCLK 15
> +#define CLK_GOUT_I2C1_PCLK 16
> +#define CLK_GOUT_I2C2_PCLK 17
> +#define CLK_GOUT_I2C3_PCLK 18
> +#define CLK_GOUT_I2C4_PCLK 19
> +#define CLK_GOUT_I2C5_PCLK 20
> +#define CLK_GOUT_I2C6_PCLK 21
> +#define CLK_GOUT_I2C7_PCLK 22
> +#define CLK_GOUT_PWM_MOTOR_PCLK 23
> +#define CLK_GOUT_SPI0_PCLK 24
> +#define CLK_GOUT_SPI0_EXT_CLK 25
> +#define CLK_GOUT_SPI1_PCLK 26
> +#define CLK_GOUT_SPI1_EXT_CLK 27
> +#define CLK_GOUT_UART0_EXT_UCLK 28
> +#define CLK_GOUT_UART0_PCLK 29
> +#define CLK_GOUT_UART1_EXT_UCLK 30
> +#define CLK_GOUT_UART1_PCLK 31
> +#define CLK_GOUT_UART2_EXT_UCLK 32
> +#define CLK_GOUT_UART2_PCLK 33
> +#define CLK_GOUT_USI0_PCLK 34
> +#define CLK_GOUT_USI0_SCLK 35
> +#define CLK_GOUT_USI1_PCLK 36
> +#define CLK_GOUT_USI1_SCLK 37
> +#define CLK_GOUT_USI2_PCLK 38
> +#define CLK_GOUT_USI2_SCLK 39
> +#define CLK_GOUT_MCT_PCLK 40
> +#define CLK_GOUT_SYSREG_PERI_PCLK 41
> +#define CLK_GOUT_WDT0_PCLK 42
> +#define CLK_GOUT_WDT1_PCLK 43
> +#define PERI_NR_CLK 44
> +
> +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
> --
> 2.34.1
>

2021-12-07 18:23:46

[permalink] [raw]

Subject: Re: [PATCH v4 2/7] dt-bindings: clock: Document Exynos7885 CMU bindings

On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>
> Provide dt-schema documentation for Exynos7885 SoC clock controller.
> Description is modified from Exynos850 clock controller documentation as
> I couldn't describe it any better, that was written by Sam Protsenko.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: David Virag <[email protected]>
> ---

Reviewed-by: Sam Protsenko <[email protected]>

> Changes in v2:
> - Fixed double : in description
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Fix leading 0x in example.
>
> .../clock/samsung,exynos7885-clock.yaml | 166 ++++++++++++++++++
> 1 file changed, 166 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
> new file mode 100644
> index 000000000000..7e5a9cac2fd2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
> @@ -0,0 +1,166 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos7885 SoC clock controller
> +
> +maintainers:
> + - Dávid Virág <[email protected]>
> + - Chanwoo Choi <[email protected]>
> + - Krzysztof Kozlowski <[email protected]>
> + - Sylwester Nawrocki <[email protected]>
> + - Tomasz Figa <[email protected]>
> +
> +description: |
> + Exynos7885 clock controller is comprised of several CMU units, generating
> + clocks for different domains. Those CMU units are modeled as separate device
> + tree nodes, and might depend on each other. The root clock in that root tree
> + is an external clock: OSCCLK (26 MHz). This external clock must be defined
> + as a fixed-rate clock in dts.
> +
> + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> + Each clock is assigned an identifier and client nodes can use this identifier
> + to specify the clock which they consume. All clocks available for usage
> + in clock consumer nodes are defined as preprocessor macros in
> + 'dt-bindings/clock/exynos7885.h' header.
> +
> +properties:
> + compatible:
> + enum:
> + - samsung,exynos7885-cmu-top
> + - samsung,exynos7885-cmu-core
> + - samsung,exynos7885-cmu-peri
> +
> + clocks:
> + minItems: 1
> + maxItems: 10
> +
> + clock-names:
> + minItems: 1
> + maxItems: 10
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7885-cmu-top
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> +
> + clock-names:
> + items:
> + - const: oscclk
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7885-cmu-core
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_CORE bus clock (from CMU_TOP)
> + - description: CCI clock (from CMU_TOP)
> + - description: G3D clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_core_bus
> + - const: dout_core_cci
> + - const: dout_core_g3d
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos7885-cmu-peri
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_PERI bus clock (from CMU_TOP)
> + - description: SPI0 clock (from CMU_TOP)
> + - description: SPI1 clock (from CMU_TOP)
> + - description: UART0 clock (from CMU_TOP)
> + - description: UART1 clock (from CMU_TOP)
> + - description: UART2 clock (from CMU_TOP)
> + - description: USI0 clock (from CMU_TOP)
> + - description: USI1 clock (from CMU_TOP)
> + - description: USI2 clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_peri_bus
> + - const: dout_peri_spi0
> + - const: dout_peri_spi1
> + - const: dout_peri_uart0
> + - const: dout_peri_uart1
> + - const: dout_peri_uart2
> + - const: dout_peri_usi0
> + - const: dout_peri_usi1
> + - const: dout_peri_usi2
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - clocks
> + - clock-names
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock controller node for CMU_PERI
> + - |
> + #include <dt-bindings/clock/exynos7885.h>
> +
> + cmu_peri: clock-controller@10010000 {
> + compatible = "samsung,exynos7885-cmu-peri";
> + reg = <0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>,
> + <&cmu_top CLK_DOUT_PERI_BUS>,
> + <&cmu_top CLK_DOUT_PERI_SPI0>,
> + <&cmu_top CLK_DOUT_PERI_SPI1>,
> + <&cmu_top CLK_DOUT_PERI_UART0>,
> + <&cmu_top CLK_DOUT_PERI_UART1>,
> + <&cmu_top CLK_DOUT_PERI_UART2>,
> + <&cmu_top CLK_DOUT_PERI_USI0>,
> + <&cmu_top CLK_DOUT_PERI_USI1>,
> + <&cmu_top CLK_DOUT_PERI_USI2>;
> + clock-names = "oscclk",
> + "dout_peri_bus",
> + "dout_peri_spi0",
> + "dout_peri_spi1",
> + "dout_peri_uart0",
> + "dout_peri_uart1",
> + "dout_peri_uart2",
> + "dout_peri_usi0",
> + "dout_peri_usi1",
> + "dout_peri_usi2";
> + };
> +
> +...
> --
> 2.34.1
>

2021-12-07 18:26:29

[permalink] [raw]

Subject: Re: [PATCH v4 3/7] dt-bindings: arm: samsung: document jackpotlte board binding

On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>
> Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)).
>
> Signed-off-by: David Virag <[email protected]>
> ---

Reviewed-by: Sam Protsenko <[email protected]>

> Changes in v2:
> - Nothing
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Nothing
>
> .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> index ef6dc14be4b5..d88571202713 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> @@ -199,6 +199,12 @@ properties:
> - samsung,exynos7-espresso # Samsung Exynos7 Espresso
> - const: samsung,exynos7
>
> + - description: Exynos7885 based boards
> + items:
> + - enum:
> + - samsung,jackpotlte # Samsung Galaxy A8 (2018)
> + - const: samsung,exynos7885
> +
> - description: Exynos Auto v9 based boards
> items:
> - enum:
> --
> 2.34.1
>

2021-12-07 18:54:01

[permalink] [raw]

Subject: Re: [PATCH v4 4/7] clk: samsung: Make exynos850_register_cmu shared

On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>
> Rename exynos850_register_cmu to exynos_arm64_register_cmu and move it
> to a new file called "clk-exynos-arm64.c".
>
> This should have no functional changes, but it will allow this code to
> be shared between other arm64 Exynos SoCs, like the Exynos7885 and
> possibly ExynosAuto V9.
>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - New patch
>
> Changes in v3:
> - Fix SPDX comment style in clk-exynos-arm64.h
>
> Changes in v4:
> - Fix missing headers but still remove of_address.h
> - "__SAMSUNG_CLK_ARM64_H" -> "__CLK_EXYNOS_ARM64_H" in
> clk-exynos-arm64.h everywhere (only the comment at the end had the
> latter by accident)
>
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos-arm64.c | 94 ++++++++++++++++++++++++++
> drivers/clk/samsung/clk-exynos-arm64.h | 20 ++++++
> drivers/clk/samsung/clk-exynos850.c | 88 ++----------------------
> 4 files changed, 119 insertions(+), 84 deletions(-)
> create mode 100644 drivers/clk/samsung/clk-exynos-arm64.c
> create mode 100644 drivers/clk/samsung/clk-exynos-arm64.h
>
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index c46cf11e4d0b..901e6333c5f0 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_EXYNOS_5420_COMMON_CLK) += clk-exynos5-subcmu.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
> obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
> obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
> +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
> obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
> diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/clk-exynos-arm64.c
> new file mode 100644
> index 000000000000..b921b9a1134a
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos-arm64.c
> @@ -0,0 +1,94 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2021 Linaro Ltd.
> + * Copyright (C) 2021 Dávid Virág <[email protected]>
> + * Author: Sam Protsenko <[email protected]>
> + * Author: Dávid Virág <[email protected]>
> + *
> + * This file contains shared functions used by some arm64 Exynos SoCs,
> + * such as Exynos7885 or Exynos850 to register and init CMUs.
> + */

Please add empty line here (if you're going to send another version).
Other than that:

Reviewed-by: Sam Protsenko <[email protected]>

> +#include <linux/clk.h>
> +#include <linux/of_address.h>
> +
> +#include "clk-exynos-arm64.h"
> +
> +/* Gate register bits */
> +#define GATE_MANUAL BIT(20)
> +#define GATE_ENABLE_HWACG BIT(28)
> +
> +/* Gate register offsets range */
> +#define GATE_OFF_START 0x2000
> +#define GATE_OFF_END 0x2fff
> +
> +/**
> + * exynos_arm64_init_clocks - Set clocks initial configuration
> + * @np: CMU device tree node with "reg" property (CMU addr)
> + * @reg_offs: Register offsets array for clocks to init
> + * @reg_offs_len: Number of register offsets in reg_offs array
> + *
> + * Set manual control mode for all gate clocks.
> + */
> +static void __init exynos_arm64_init_clocks(struct device_node *np,
> + const unsigned long *reg_offs, size_t reg_offs_len)
> +{
> + void __iomem *reg_base;
> + size_t i;
> +
> + reg_base = of_iomap(np, 0);
> + if (!reg_base)
> + panic("%s: failed to map registers\n", __func__);
> +
> + for (i = 0; i < reg_offs_len; ++i) {
> + void __iomem *reg = reg_base + reg_offs[i];
> + u32 val;
> +
> + /* Modify only gate clock registers */
> + if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
> + continue;
> +
> + val = readl(reg);
> + val |= GATE_MANUAL;
> + val &= ~GATE_ENABLE_HWACG;
> + writel(val, reg);
> + }
> +
> + iounmap(reg_base);
> +}
> +
> +/**
> + * exynos_arm64_register_cmu - Register specified Exynos CMU domain
> + * @dev: Device object; may be NULL if this function is not being
> + * called from platform driver probe function
> + * @np: CMU device tree node
> + * @cmu: CMU data
> + *
> + * Register specified CMU domain, which includes next steps:
> + *
> + * 1. Enable parent clock of @cmu CMU
> + * 2. Set initial registers configuration for @cmu CMU clocks
> + * 3. Register @cmu CMU clocks using Samsung clock framework API
> + */
> +void __init exynos_arm64_register_cmu(struct device *dev,
> + struct device_node *np, const struct samsung_cmu_info *cmu)
> +{
> + /* Keep CMU parent clock running (needed for CMU registers access) */
> + if (cmu->clk_name) {
> + struct clk *parent_clk;
> +
> + if (dev)
> + parent_clk = clk_get(dev, cmu->clk_name);
> + else
> + parent_clk = of_clk_get_by_name(np, cmu->clk_name);
> +
> + if (IS_ERR(parent_clk)) {
> + pr_err("%s: could not find bus clock %s; err = %ld\n",
> + __func__, cmu->clk_name, PTR_ERR(parent_clk));
> + } else {
> + clk_prepare_enable(parent_clk);
> + }
> + }
> +
> + exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
> + samsung_cmu_register_one(np, cmu);
> +}
> diff --git a/drivers/clk/samsung/clk-exynos-arm64.h b/drivers/clk/samsung/clk-exynos-arm64.h
> new file mode 100644
> index 000000000000..0dd174693935
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos-arm64.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2021 Linaro Ltd.
> + * Copyright (C) 2021 Dávid Virág <[email protected]>
> + * Author: Sam Protsenko <[email protected]>
> + * Author: Dávid Virág <[email protected]>
> + *
> + * This file contains shared functions used by some arm64 Exynos SoCs,
> + * such as Exynos7885 or Exynos850 to register and init CMUs.
> + */
> +
> +#ifndef __CLK_EXYNOS_ARM64_H
> +#define __CLK_EXYNOS_ARM64_H
> +
> +#include "clk.h"
> +
> +void exynos_arm64_register_cmu(struct device *dev,
> + struct device_node *np, const struct samsung_cmu_info *cmu);
> +
> +#endif /* __CLK_EXYNOS_ARM64_H */
> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
> index 568ac97c8120..17413135196d 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -9,93 +9,13 @@
> #include <linux/clk.h>
> #include <linux/clk-provider.h>
> #include <linux/of.h>
> -#include <linux/of_address.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
>
> #include <dt-bindings/clock/exynos850.h>
>
> #include "clk.h"
> -
> -/* Gate register bits */
> -#define GATE_MANUAL BIT(20)
> -#define GATE_ENABLE_HWACG BIT(28)
> -
> -/* Gate register offsets range */
> -#define GATE_OFF_START 0x2000
> -#define GATE_OFF_END 0x2fff
> -
> -/**
> - * exynos850_init_clocks - Set clocks initial configuration
> - * @np: CMU device tree node with "reg" property (CMU addr)
> - * @reg_offs: Register offsets array for clocks to init
> - * @reg_offs_len: Number of register offsets in reg_offs array
> - *
> - * Set manual control mode for all gate clocks.
> - */
> -static void __init exynos850_init_clocks(struct device_node *np,
> - const unsigned long *reg_offs, size_t reg_offs_len)
> -{
> - void __iomem *reg_base;
> - size_t i;
> -
> - reg_base = of_iomap(np, 0);
> - if (!reg_base)
> - panic("%s: failed to map registers\n", __func__);
> -
> - for (i = 0; i < reg_offs_len; ++i) {
> - void __iomem *reg = reg_base + reg_offs[i];
> - u32 val;
> -
> - /* Modify only gate clock registers */
> - if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
> - continue;
> -
> - val = readl(reg);
> - val |= GATE_MANUAL;
> - val &= ~GATE_ENABLE_HWACG;
> - writel(val, reg);
> - }
> -
> - iounmap(reg_base);
> -}
> -
> -/**
> - * exynos850_register_cmu - Register specified Exynos850 CMU domain
> - * @dev: Device object; may be NULL if this function is not being
> - * called from platform driver probe function
> - * @np: CMU device tree node
> - * @cmu: CMU data
> - *
> - * Register specified CMU domain, which includes next steps:
> - *
> - * 1. Enable parent clock of @cmu CMU
> - * 2. Set initial registers configuration for @cmu CMU clocks
> - * 3. Register @cmu CMU clocks using Samsung clock framework API
> - */
> -static void __init exynos850_register_cmu(struct device *dev,
> - struct device_node *np, const struct samsung_cmu_info *cmu)
> -{
> - /* Keep CMU parent clock running (needed for CMU registers access) */
> - if (cmu->clk_name) {
> - struct clk *parent_clk;
> -
> - if (dev)
> - parent_clk = clk_get(dev, cmu->clk_name);
> - else
> - parent_clk = of_clk_get_by_name(np, cmu->clk_name);
> -
> - if (IS_ERR(parent_clk)) {
> - pr_err("%s: could not find bus clock %s; err = %ld\n",
> - __func__, cmu->clk_name, PTR_ERR(parent_clk));
> - } else {
> - clk_prepare_enable(parent_clk);
> - }
> - }
> -
> - exynos850_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
> - samsung_cmu_register_one(np, cmu);
> -}
> +#include "clk-exynos-arm64.h"
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -404,7 +324,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
>
> static void __init exynos850_cmu_top_init(struct device_node *np)
> {
> - exynos850_register_cmu(NULL, np, &top_cmu_info);
> + exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
> }
>
> /* Register CMU_TOP early, as it's a dependency for other early domains */
> @@ -892,7 +812,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
>
> static void __init exynos850_cmu_peri_init(struct device_node *np)
> {
> - exynos850_register_cmu(NULL, np, &peri_cmu_info);
> + exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
> }
>
> /* Register CMU_PERI early, as it's needed for MCT timer */
> @@ -1069,7 +989,7 @@ static int __init exynos850_cmu_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
>
> info = of_device_get_match_data(dev);
> - exynos850_register_cmu(dev, dev->of_node, info);
> + exynos_arm64_register_cmu(dev, dev->of_node, info);
>
> return 0;
> }
> --
> 2.34.1
>

2021-12-07 19:01:00

[permalink] [raw]

Subject: Re: [PATCH v4 5/7] clk: samsung: clk-pll: Add support for pll1417x

On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>
> pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
> It is similar enough to pll0822x that practically the same code can
> handle both. The difference that's to be noted is that when defining a
> pl1417x PLL, the "con" parameter of the PLL macro should be set to the
> CON1 register instead of CON3, like this:
>
> PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
> NULL),
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Nothing
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Added R-b tag by Krzysztof Kozlowski
>
> drivers/clk/samsung/clk-pll.c | 1 +
> drivers/clk/samsung/clk-pll.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 83d1b03647db..70cdc87f714e 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> else
> init.ops = &samsung_pll35xx_clk_ops;
> break;
> + case pll_1417x:

I wonder why this switch have a bunch of fall through cases, but none
marked with "fallthrough;" line, and both checkpatch and "make" turn
blind eye on that? Anyway, I guess it's ok as is, just an observation.

Reviewed-by: Sam Protsenko <[email protected]>

> case pll_0822x:
> pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index a739f2b7ae80..c83a20195f6d 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -32,6 +32,7 @@ enum samsung_pll_type {
> pll_2550xx,
> pll_2650x,
> pll_2650xx,
> + pll_1417x,
> pll_1450x,
> pll_1451x,
> pll_1452x,
> --
> 2.34.1
>

2021-12-07 19:15:01

[permalink] [raw]

Subject: Re: [PATCH v4 6/7] clk: samsung: Add initial Exynos7885 clock driver

On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>
> This is an initial implementation adding basic clocks, such as UART,
> USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the
> Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which
> was made by Sam Protsenko, thus the copyright and author lines were
> kept.
>
> Bus clocks are enabled by default as well to avoid hangs while trying to
> access CMU registers.
>
> Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of
> CMU_CORE, and most of CMU_PERI is implemented as of now.
>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Use shared code between Exynos850 and 7885 clock drivers
> - As the code that was from the Exynos850 clock driver was moved to
> clk-exynos-arm64.c and what remains is mostly SoC specific data,
> move the Linaro copyright and Sam Protsenko author lines there.
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Fixed missing headers
>
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos7885.c | 597 +++++++++++++++++++++++++++
> 2 files changed, 598 insertions(+)
> create mode 100644 drivers/clk/samsung/clk-exynos7885.c
>
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index 901e6333c5f0..0df74916a895 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
> obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
> +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
> obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
> obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
> diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
> new file mode 100644
> index 000000000000..a7b106302706
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos7885.c
> @@ -0,0 +1,597 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2021 Dávid Virág <[email protected]>
> + * Author: Dávid Virág <[email protected]>
> + *
> + * Common Clock Framework support for Exynos7885 SoC.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/exynos7885.h>
> +
> +#include "clk.h"
> +#include "clk-exynos-arm64.h"
> +
> +/* ---- CMU_TOP ------------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_TOP (0x12060000) */
> +#define PLL_LOCKTIME_PLL_SHARED0 0x0000
> +#define PLL_LOCKTIME_PLL_SHARED1 0x0004
> +#define PLL_CON0_PLL_SHARED0 0x0100
> +#define PLL_CON0_PLL_SHARED1 0x0120
> +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
> +#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
> +#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x101c
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1058
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0 0x105c
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1 0x1060
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART0 0x1064
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART1 0x1068
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART2 0x106c
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI0 0x1070
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI1 0x1074
> +#define CLK_CON_MUX_MUX_CLKCMU_PERI_USI2 0x1078
> +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
> +#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1820
> +#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1824
> +#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1874
> +#define CLK_CON_DIV_CLKCMU_PERI_SPI0 0x1878
> +#define CLK_CON_DIV_CLKCMU_PERI_SPI1 0x187c
> +#define CLK_CON_DIV_CLKCMU_PERI_UART0 0x1880
> +#define CLK_CON_DIV_CLKCMU_PERI_UART1 0x1884
> +#define CLK_CON_DIV_CLKCMU_PERI_UART2 0x1888
> +#define CLK_CON_DIV_CLKCMU_PERI_USI0 0x188c
> +#define CLK_CON_DIV_CLKCMU_PERI_USI1 0x1890
> +#define CLK_CON_DIV_CLKCMU_PERI_USI2 0x1894
> +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x189c
> +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18a0
> +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18a4
> +#define CLK_CON_DIV_PLL_SHARED0_DIV5 0x18a8
> +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18ac
> +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b0
> +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18b4
> +#define CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1 0x2004
> +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
> +#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
> +#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2024
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x207c
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0 0x2080
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1 0x2084
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART0 0x2088
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART2 0x208c
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI0 0x2090
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI1 0x2094
> +#define CLK_CON_GAT_GATE_CLKCMU_PERI_USI2 0x2098
> +
> +static const unsigned long top_clk_regs[] __initconst = {
> + PLL_LOCKTIME_PLL_SHARED0,
> + PLL_LOCKTIME_PLL_SHARED1,
> + PLL_CON0_PLL_SHARED0,
> + PLL_CON0_PLL_SHARED1,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_UART0,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_UART1,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_UART2,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_USI0,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_USI1,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_USI2,
> + CLK_CON_DIV_CLKCMU_CORE_BUS,
> + CLK_CON_DIV_CLKCMU_CORE_CCI,
> + CLK_CON_DIV_CLKCMU_CORE_G3D,
> + CLK_CON_DIV_CLKCMU_PERI_BUS,
> + CLK_CON_DIV_CLKCMU_PERI_SPI0,
> + CLK_CON_DIV_CLKCMU_PERI_SPI1,
> + CLK_CON_DIV_CLKCMU_PERI_UART0,
> + CLK_CON_DIV_CLKCMU_PERI_UART1,
> + CLK_CON_DIV_CLKCMU_PERI_UART2,
> + CLK_CON_DIV_CLKCMU_PERI_USI0,
> + CLK_CON_DIV_CLKCMU_PERI_USI1,
> + CLK_CON_DIV_CLKCMU_PERI_USI2,
> + CLK_CON_DIV_PLL_SHARED0_DIV2,
> + CLK_CON_DIV_PLL_SHARED0_DIV3,
> + CLK_CON_DIV_PLL_SHARED0_DIV4,
> + CLK_CON_DIV_PLL_SHARED0_DIV5,
> + CLK_CON_DIV_PLL_SHARED1_DIV2,
> + CLK_CON_DIV_PLL_SHARED1_DIV3,
> + CLK_CON_DIV_PLL_SHARED1_DIV4,
> + CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1,
> + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
> + CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_UART0,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_UART2,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_USI0,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_USI1,
> + CLK_CON_GAT_GATE_CLKCMU_PERI_USI2,
> +};
> +
> +static const struct samsung_pll_clock top_pll_clks[] __initconst = {
> + PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
> + NULL),
> + PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
> + PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1,
> + NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
> +PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "dout_shared0_div3", "dout_shared0_div3" };
> +PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "dout_shared0_div3", "dout_shared0_div3" };
> +PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "dout_shared0_div3", "dout_shared0_div3" };
> +
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
> +PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
> +PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
> +PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
> +PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
> +PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
> +PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
> +PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
> +PNAME(mout_peri_usi1_p) = { "oscclk", "dout_shared0_div4" };
> +PNAME(mout_peri_usi2_p) = { "oscclk", "dout_shared0_div4" };
> +
> +static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> + /* CORE */
> + MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> + MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2),
> + MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
> + CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2),
> +
> + /* PERI */
> + MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
> + MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0, 0, 1),
> + MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1, 0, 1),
> + MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_UART0, 0, 1),
> + MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_UART1, 0, 1),
> + MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_UART2, 0, 1),
> + MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_USI0, 0, 1),
> + MUX(CLK_MOUT_PERI_USI1, "mout_peri_usi1", mout_peri_usi1_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),
> + MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,
> + CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),
> +};
> +
> +static const struct samsung_div_clock top_div_clks[] __initconst = {
> + /* TOP */
> + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> + DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
> + CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
> + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
> + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> +
> + /* CORE */
> + DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
> + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 3),
> + DIV(CLK_DOUT_CORE_CCI, "dout_core_cci", "gout_core_cci",
> + CLK_CON_DIV_CLKCMU_CORE_CCI, 0, 3),
> + DIV(CLK_DOUT_CORE_G3D, "dout_core_g3d", "gout_core_g3d",
> + CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 3),
> +
> + /* PERI */
> + DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
> + CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
> + DIV(CLK_DOUT_PERI_SPI0, "dout_peri_spi0", "gout_peri_spi0",
> + CLK_CON_DIV_CLKCMU_PERI_SPI0, 0, 6),
> + DIV(CLK_DOUT_PERI_SPI1, "dout_peri_spi1", "gout_peri_spi1",
> + CLK_CON_DIV_CLKCMU_PERI_SPI1, 0, 6),
> + DIV(CLK_DOUT_PERI_UART0, "dout_peri_uart0", "gout_peri_uart0",
> + CLK_CON_DIV_CLKCMU_PERI_UART0, 0, 4),
> + DIV(CLK_DOUT_PERI_UART1, "dout_peri_uart1", "gout_peri_uart1",
> + CLK_CON_DIV_CLKCMU_PERI_UART1, 0, 4),
> + DIV(CLK_DOUT_PERI_UART2, "dout_peri_uart2", "gout_peri_uart2",
> + CLK_CON_DIV_CLKCMU_PERI_UART2, 0, 4),
> + DIV(CLK_DOUT_PERI_USI0, "dout_peri_usi0", "gout_peri_usi0",
> + CLK_CON_DIV_CLKCMU_PERI_USI0, 0, 4),
> + DIV(CLK_DOUT_PERI_USI1, "dout_peri_usi1", "gout_peri_usi1",
> + CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),
> + DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",
> + CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),
> +};
> +
> +static const struct samsung_gate_clock top_gate_clks[] __initconst = {
> + /* CORE */
> + GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
> + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
> + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, 0, 0),
> + GATE(CLK_GOUT_CORE_G3D, "gout_core_g3d", "mout_core_g3d",
> + CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, 0, 0),
> +
> + /* PERI */
> + GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_SPI0, "gout_peri_spi0", "mout_peri_spi0",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_SPI1, "gout_peri_spi1", "mout_peri_spi1",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_UART0, "gout_peri_uart0", "mout_peri_uart0",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_UART0, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_UART1, "gout_peri_uart1", "mout_peri_uart1",
> + CLK_CON_GAT_GATE_CLKCMUC_PERI_UART1, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_UART2, "gout_peri_uart2", "mout_peri_uart2",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_UART2, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_USI0, "gout_peri_usi0", "mout_peri_usi0",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_USI0, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_USI1, "gout_peri_usi1", "mout_peri_usi1",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),
> + GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",
> + CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info top_cmu_info __initconst = {
> + .pll_clks = top_pll_clks,
> + .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
> + .mux_clks = top_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
> + .div_clks = top_div_clks,
> + .nr_div_clks = ARRAY_SIZE(top_div_clks),
> + .gate_clks = top_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
> + .nr_clk_ids = TOP_NR_CLK,
> + .clk_regs = top_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
> +};
> +
> +static void __init exynos7885_cmu_top_init(struct device_node *np)
> +{
> + exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
> +}
> +
> +/* Register CMU_TOP early, as it's a dependency for other early domains */
> +CLK_OF_DECLARE(exynos7885_cmu_top, "samsung,exynos7885-cmu-top",
> + exynos7885_cmu_top_init);
> +
> +/* ---- CMU_PERI ------------------------------------------------------------ */
> +
> +/* Register Offset definitions for CMU_PERI (0x10010000) */
> +#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100
> +#define PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER 0x0120
> +#define PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER 0x0140
> +#define PLL_CON0_MUX_CLKCMU_PERI_UART0_USER 0x0160
> +#define PLL_CON0_MUX_CLKCMU_PERI_UART1_USER 0x0180
> +#define PLL_CON0_MUX_CLKCMU_PERI_UART2_USER 0x01a0
> +#define PLL_CON0_MUX_CLKCMU_PERI_USI0_USER 0x01c0
> +#define PLL_CON0_MUX_CLKCMU_PERI_USI1_USER 0x01e0
> +#define PLL_CON0_MUX_CLKCMU_PERI_USI2_USER 0x0200
> +#define CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK 0x2028
> +#define CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK 0x202c
> +#define CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK 0x2030
> +#define CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK 0x2034
> +#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x2038
> +#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x203c
> +#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2040
> +#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2044
> +#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x2048
> +#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x204c
> +#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2050
> +#define CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK 0x2054
> +#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK 0x2058
> +#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x205c
> +#define CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK 0x2060
> +#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x2064
> +#define CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK 0x2068
> +#define CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK 0x206c
> +#define CLK_CON_GAT_GOUT_PERI_UART_0_PCLK 0x2070
> +#define CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK 0x2074
> +#define CLK_CON_GAT_GOUT_PERI_UART_1_PCLK 0x2078
> +#define CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK 0x207c
> +#define CLK_CON_GAT_GOUT_PERI_UART_2_PCLK 0x2080
> +#define CLK_CON_GAT_GOUT_PERI_USI0_PCLK 0x2084
> +#define CLK_CON_GAT_GOUT_PERI_USI0_SCLK 0x2088
> +#define CLK_CON_GAT_GOUT_PERI_USI1_PCLK 0x208c
> +#define CLK_CON_GAT_GOUT_PERI_USI1_SCLK 0x2090
> +#define CLK_CON_GAT_GOUT_PERI_USI2_PCLK 0x2094
> +#define CLK_CON_GAT_GOUT_PERI_USI2_SCLK 0x2098
> +#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x20a0
> +#define CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK 0x20b0
> +#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20b4
> +#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20b8
> +
> +static const unsigned long peri_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_UART0_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_UART1_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_UART2_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_USI0_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_USI1_USER,
> + PLL_CON0_MUX_CLKCMU_PERI_USI2_USER,
> + CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK,
> + CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK,
> + CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK,
> + CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK,
> + CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK,
> + CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK,
> + CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK,
> + CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK,
> + CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK,
> + CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK,
> + CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK,
> + CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK,
> + CLK_CON_GAT_GOUT_PERI_UART_0_PCLK,
> + CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK,
> + CLK_CON_GAT_GOUT_PERI_UART_1_PCLK,
> + CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK,
> + CLK_CON_GAT_GOUT_PERI_UART_2_PCLK,
> + CLK_CON_GAT_GOUT_PERI_USI0_PCLK,
> + CLK_CON_GAT_GOUT_PERI_USI0_SCLK,
> + CLK_CON_GAT_GOUT_PERI_USI1_PCLK,
> + CLK_CON_GAT_GOUT_PERI_USI1_SCLK,
> + CLK_CON_GAT_GOUT_PERI_USI2_PCLK,
> + CLK_CON_GAT_GOUT_PERI_USI2_SCLK,
> + CLK_CON_GAT_GOUT_PERI_MCT_PCLK,
> + CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK,
> + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK,
> + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_PERI */
> +PNAME(mout_peri_bus_user_p) = { "oscclk", "dout_peri_bus" };
> +PNAME(mout_peri_spi0_user_p) = { "oscclk", "dout_peri_spi0" };
> +PNAME(mout_peri_spi1_user_p) = { "oscclk", "dout_peri_spi1" };
> +PNAME(mout_peri_uart0_user_p) = { "oscclk", "dout_peri_uart0" };
> +PNAME(mout_peri_uart1_user_p) = { "oscclk", "dout_peri_uart1" };
> +PNAME(mout_peri_uart2_user_p) = { "oscclk", "dout_peri_uart2" };
> +PNAME(mout_peri_usi0_user_p) = { "oscclk", "dout_peri_usi0" };
> +PNAME(mout_peri_usi1_user_p) = { "oscclk", "dout_peri_usi1" };
> +PNAME(mout_peri_usi2_user_p) = { "oscclk", "dout_peri_usi2" };
> +
> +static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p,
> + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_SPI0_USER, "mout_peri_spi0_user", mout_peri_spi0_user_p,

Nit-pick: here and below in this file, please try to keep max line
length at 80 characters. I know it's not mandatory anymore, but I'd
personally prefer it to be that away (otherwise it's not consistent
with most of lines that are 80 char long). It's easy to spot that with
"checkpatch.pl --strict".

> + PLL_CON0_MUX_CLKCMU_PERI_SPI0_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_SPI1_USER, "mout_peri_spi1_user", mout_peri_spi1_user_p,
> + PLL_CON0_MUX_CLKCMU_PERI_SPI1_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_UART0_USER, "mout_peri_uart0_user",
> + mout_peri_uart0_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART0_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_UART1_USER, "mout_peri_uart1_user",
> + mout_peri_uart1_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART1_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_UART2_USER, "mout_peri_uart2_user",
> + mout_peri_uart2_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART2_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_USI0_USER, "mout_peri_usi0_user",
> + mout_peri_usi0_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI0_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_USI1_USER, "mout_peri_usi1_user",
> + mout_peri_usi1_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI1_USER, 4, 1),
> + MUX(CLK_MOUT_PERI_USI2_USER, "mout_peri_usi2_user",
> + mout_peri_usi2_user_p, PLL_CON0_MUX_CLKCMU_PERI_USI2_USER, 4, 1),
> +};
> +
> +static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
> + /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
> + GATE(CLK_GOUT_GPIO_TOP_PCLK, "gout_gpio_top_pclk",
> + "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_GPIO_TOP_PCLK, 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_HSI2C0_PCLK, "gout_hsi2c0_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_HSI2C_0_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2C1_PCLK, "gout_hsi2c1_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_HSI2C_1_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2C2_PCLK, "gout_hsi2c2_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_HSI2C_2_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_HSI2C3_PCLK, "gout_hsi2c3_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_HSI2C_3_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C0_PCLK, "gout_i2c0_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C1_PCLK, "gout_i2c1_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C2_PCLK, "gout_i2c2_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C3_PCLK, "gout_i2c3_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C4_PCLK, "gout_i2c4_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C5_PCLK, "gout_i2c5_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C6_PCLK, "gout_i2c6_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_I2C7_PCLK, "gout_i2c7_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_I2C_7_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
> + "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_SPI0_PCLK, "gout_spi0_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_SPI0_EXT_CLK, "gout_spi0_ipclk", "mout_peri_spi0_user",
> + CLK_CON_GAT_GOUT_PERI_SPI_0_EXT_CLK, 21, 0, 0),
> + GATE(CLK_GOUT_SPI1_PCLK, "gout_spi1_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_SPI1_EXT_CLK, "gout_spi1_ipclk", "mout_peri_spi1_user",
> + CLK_CON_GAT_GOUT_PERI_SPI_1_EXT_CLK, 21, 0, 0),
> + GATE(CLK_GOUT_UART0_EXT_UCLK, "gout_uart0_ext_uclk", "mout_peri_uart0_user",
> + CLK_CON_GAT_GOUT_PERI_UART_0_EXT_UCLK, 21, 0, 0),
> + GATE(CLK_GOUT_UART0_PCLK, "gout_uart0_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_UART_0_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_UART1_EXT_UCLK, "gout_uart1_ext_uclk", "mout_peri_uart1_user",
> + CLK_CON_GAT_GOUT_PERI_UART_1_EXT_UCLK, 21, 0, 0),
> + GATE(CLK_GOUT_UART1_PCLK, "gout_uart1_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_UART_1_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_UART2_EXT_UCLK, "gout_uart2_ext_uclk", "mout_peri_uart2_user",
> + CLK_CON_GAT_GOUT_PERI_UART_2_EXT_UCLK, 21, 0, 0),
> + GATE(CLK_GOUT_UART2_PCLK, "gout_uart2_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_UART_2_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_USI0_PCLK, "gout_usi0_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_USI0_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_USI0_SCLK, "gout_usi0_sclk", "mout_peri_usi0_user",
> + CLK_CON_GAT_GOUT_PERI_USI0_SCLK, 21, 0, 0),
> + GATE(CLK_GOUT_USI1_PCLK, "gout_usi1_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_USI1_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_USI1_SCLK, "gout_usi1_sclk", "mout_peri_usi1_user",
> + CLK_CON_GAT_GOUT_PERI_USI1_SCLK, 21, 0, 0),
> + GATE(CLK_GOUT_USI2_PCLK, "gout_usi2_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_USI2_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_USI2_SCLK, "gout_usi2_sclk", "mout_peri_usi2_user",
> + CLK_CON_GAT_GOUT_PERI_USI2_SCLK, 21, 0, 0),
> + GATE(CLK_GOUT_MCT_PCLK, "gout_mct_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_SYSREG_PERI_PCLK, "gout_sysreg_peri_pclk",
> + "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_SYSREG_PERI_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_WDT0_PCLK, "gout_wdt0_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_WDT1_PCLK, "gout_wdt1_pclk", "mout_peri_bus_user",
> + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info peri_cmu_info __initconst = {
> + .mux_clks = peri_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
> + .gate_clks = peri_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
> + .nr_clk_ids = PERI_NR_CLK,
> + .clk_regs = peri_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
> + .clk_name = "dout_peri_bus",
> +};
> +
> +static void __init exynos7885_cmu_peri_init(struct device_node *np)
> +{
> + exynos_arm64_register_cmu(NULL, np, &peri_cmu_info);
> +}
> +
> +/* Register CMU_PERI early, as it's needed for MCT timer */
> +CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",
> + exynos7885_cmu_peri_init);
> +
> +/* ---- CMU_CORE ------------------------------------------------------------ */
> +
> +/* Register Offset definitions for CMU_CORE (0x12000000) */
> +#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100
> +#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120
> +#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140
> +#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000
> +#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
> +#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2054
> +#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK 0x2058
> +
> +static const unsigned long core_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
> + PLL_CON0_MUX_CLKCMU_CORE_CCI_USER,
> + PLL_CON0_MUX_CLKCMU_CORE_G3D_USER,
> + CLK_CON_MUX_MUX_CLK_CORE_GIC,
> + CLK_CON_DIV_DIV_CLK_CORE_BUSP,
> + CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
> + CLK_CON_GAT_GOUT_CORE_GIC400_CLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_CORE */
> +PNAME(mout_core_bus_user_p) = { "oscclk", "dout_core_bus" };
> +PNAME(mout_core_cci_user_p) = { "oscclk", "dout_core_cci" };
> +PNAME(mout_core_g3d_user_p) = { "oscclk", "dout_core_g3d" };
> +PNAME(mout_core_gic_p) = { "dout_core_busp", "oscclk" };
> +
> +static const struct samsung_mux_clock core_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_CORE_BUS_USER, "mout_core_bus_user", mout_core_bus_user_p,
> + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_CORE_CCI_USER, "mout_core_cci_user", mout_core_cci_user_p,
> + PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1),
> + MUX(CLK_MOUT_CORE_G3D_USER, "mout_core_g3d_user", mout_core_g3d_user_p,
> + PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1),
> + MUX(CLK_MOUT_CORE_GIC, "mout_core_gic", mout_core_gic_p,
> + CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1),
> +};
> +
> +static const struct samsung_div_clock core_div_clks[] __initconst = {
> + DIV(CLK_DOUT_CORE_BUSP, "dout_core_busp", "mout_core_bus_user",
> + CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2),
> +};
> +
> +static const struct samsung_gate_clock core_gate_clks[] __initconst = {
> + /* CCI (interconnect) clock must be always running */
> + GATE(CLK_GOUT_CCI_ACLK, "gout_cci_aclk", "mout_core_cci_user",
> + CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, 21, CLK_IS_CRITICAL, 0),
> + /* GIC (interrupt controller) clock must be always running */
> + GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",
> + CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),
> +};
> +
> +static const struct samsung_cmu_info core_cmu_info __initconst = {
> + .mux_clks = core_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(core_mux_clks),
> + .div_clks = core_div_clks,
> + .nr_div_clks = ARRAY_SIZE(core_div_clks),
> + .gate_clks = core_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
> + .nr_clk_ids = CORE_NR_CLK,
> + .clk_regs = core_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
> + .clk_name = "dout_core_bus",
> +};
> +
> +/* ---- platform_driver ----------------------------------------------------- */
> +
> +static int __init exynos7885_cmu_probe(struct platform_device *pdev)
> +{
> + const struct samsung_cmu_info *info;
> + struct device *dev = &pdev->dev;
> +
> + info = of_device_get_match_data(dev);
> + exynos_arm64_register_cmu(dev, dev->of_node, info);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id exynos7885_cmu_of_match[] = {
> + {
> + .compatible = "samsung,exynos7885-cmu-core",
> + .data = &core_cmu_info,
> + }, {
> + },
> +};
> +
> +static struct platform_driver exynos7885_cmu_driver __refdata = {
> + .driver = {
> + .name = "exynos7885-cmu",
> + .of_match_table = exynos7885_cmu_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = exynos7885_cmu_probe,
> +};
> +
> +static int __init exynos7885_cmu_init(void)
> +{
> + return platform_driver_register(&exynos7885_cmu_driver);
> +}
> +core_initcall(exynos7885_cmu_init);
> --
> 2.34.1
>

2021-12-07 19:42:35

by Marc Zyngier

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On 2021-12-06 15:31, David Virag wrote:
> Add initial Exynos7885 device tree nodes with dts for the Samsung
> Galaxy
> A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> Currently this includes some clock support, UART support, and I2C
> nodes.
>
> Signed-off-by: David Virag <[email protected]>

[...]

> + psci {
> + compatible = "arm,psci";
> + method = "smc";
> + cpu_suspend = <0xc4000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;

Aren't these the standard PSCI 0.2 function numbers? Can't you
make the compatible "arm,psci-0.2" instead?

> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + /* Hypervisor Virtual Timer interrupt is not wired to GIC */

I don't understand this comment. You seem to have a bunch of
ARMv8.0 cores, for which there is no such thing as a hypervisor
virtual timer (this is an ARMv8.1 addition).

> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
> IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };

Thanks,

M.
--
Jazz is not dead. It just smells funny...

2021-12-07 20:19:20

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>
> Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy
> A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> Currently this includes some clock support, UART support, and I2C nodes.
>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Remove address-cells, and size-cells from dts, since they are
> already in the dtsi.
> - Lower case hex in memory node
> - Fix node names with underscore instead of hyphen
> - Fix line breaks
> - Fix "-key" missing from gpio keys node names
> - Use the form without "key" in gpio key labels on all keys
> - Suffix pin configuration node names with "-pins"
> - Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
> - Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
> - Add comment about Arm PMU
> - Rename "clock-oscclk" to "osc-clock"
> - Include exynos-syscon-restart.dtsi instead of rewriting its contents
>
> Changes in v3:
> - Fix typo (seperate -> separate)
>
> Changes in v4:
> - Fixed leading 0x in clock-controller nodes
> - Actually suffixed pin configuration node names with "-pins"
> - Seperated Cortex-A53 and Cortex-A73 PMU
>
> arch/arm64/boot/dts/exynos/Makefile | 7 +-
> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
> .../boot/dts/exynos/exynos7885-pinctrl.dtsi | 865 ++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 438 +++++++++
> 4 files changed, 1402 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts

Shouldn't SoC and board files be sent as two separate patches? For
example, I've checked exynos5433 and exynos7, SoC support

> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi
>
> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> index b41e86df0a84..c68c4ad577ac 100644
> --- a/arch/arm64/boot/dts/exynos/Makefile
> +++ b/arch/arm64/boot/dts/exynos/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_EXYNOS) += \
> - exynos5433-tm2.dtb \
> - exynos5433-tm2e.dtb \
> - exynos7-espresso.dtb \
> + exynos5433-tm2.dtb \
> + exynos5433-tm2e.dtb \
> + exynos7-espresso.dtb \
> + exynos7885-jackpotlte.dtb \
> exynosautov9-sadk.dtb
> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> new file mode 100644
> index 000000000000..f5941dc4c374
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
> + *
> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2021 Dávid Virág
> + *

This line is not needed.

> + */
> +
> +/dts-v1/;

Suggest adding empty line here.

> +#include "exynos7885.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "Samsung Galaxy A8 (2018)";
> + compatible = "samsung,jackpotlte", "samsung,exynos7885";
> + chassis-type = "handset";
> +
> + aliases {
> + serial0 = &serial_0;
> + serial1 = &serial_1;
> + serial2 = &serial_2;

Suggestion: add aliases also for i2c nodes, to keep i2c instance
numbers fixed in run-time (e.g. in "i2cdetect -l" output).

> + };
> +
> + chosen {
> + stdout-path = &serial_2;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x3da00000>,
> + <0x0 0xc0000000 0x40000000>,
> + <0x8 0x80000000 0x40000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&key_volup &key_voldown &key_power>;
> +
> + volup-key {
> + label = "Volume Up";
> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;

Here and below: what is 0, why it's needed? Also, isn't it enough to
have just "gpios", and remove interrupt*? Need to check "gpio-keys"
driver and bindings doc, but AFAIR it should be enough to have just
"gpios =" or just "interrupts =".

> + interrupt-parent = <&gpa1>;
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
> + };
> +
> + voldown-key {
> + label = "Volume Down";
> + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-parent = <&gpa1>;
> + linux,code = <KEY_VOLUMEDOWN>;
> + gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
> + };
> +
> + power-key {
> + label = "Power";
> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-parent = <&gpa1>;
> + linux,code = <KEY_POWER>;
> + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> + };
> + };
> +};
> +

If there are some LEDs by chance on that board -- it might be useful
to define those here with "gpio-leds" as well. Maybe even set some
default trigger like "heartbeat".

> +&serial_2 {
> + status = "okay";
> +};
> +
> +&pinctrl_alive {
> + key_volup: key-volup-pins {
> + samsung,pins = "gpa1-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;

Maybe EXYNOS_PIN_FUNC_EINT is more self-explanatory? Just a suggestion though.

> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;

Here and below: please use EXYNOS5420_PIN_DRV_LV1 (means drive level = 1x).

> + };
> +
> + key_voldown: key-voldown-pins {
> + samsung,pins = "gpa1-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + };
> +
> + key_power: key-power-pins {
> + samsung,pins = "gpa1-7";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> new file mode 100644
> index 000000000000..8336b2e48858
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> @@ -0,0 +1,865 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2021 Dávid Virág
> + *
> + * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
> + * device tree nodes in this file.
> + */
> +
> +#include <dt-bindings/pinctrl/samsung.h>

You probably also need <dt-bindings/interrupt-controller/arm-gic.h>
here for GIC_SPI definition.

> +
> +&pinctrl_alive {
> + etc0: etc0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + etc1: etc1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };

Hmm, what are these two? I can't find anything related in
exynos7885.dtsi. If it's just some leftover from downstream vendor
kernel -- please remove it.

> +
> + gpa0: gpa0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpa1: gpa1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpa2: gpa2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpq0: gpq0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + sim1_det_gpio: sim1-det-gpio-pins {
> + samsung,pins = "gpa2-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + sim0_det_gpio: sim0-det-gpio-pins {
> + samsung,pins = "gpa2-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + speedy_bus: speedy-bus-pins {
> + samsung,pins = "gpq0-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;

Here and below: suggest using EXYNOS5420_PIN_DRV_LV* constants. Then
stuff like "sd1_clk_fast_slew_rate_4x" is going to make sense.

> + };
> +
> + /* UART_DEBUG */
> + uart2_bus: uart2-bus-pins {
> + samsung,pins = "gpq0-4", "gpq0-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +};
> +
> +&pinctrl_dispaud {
> + gpb0: gpb0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb1: gpb1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb2: gpb2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + aud_codec_mclk: aud-codec-mclk-pins {
> + samsung,pins = "gpb0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_codec_mclk_idle: aud-codec-mclk-idle-pins {
> + samsung,pins = "gpb0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_codec_bus: aud-codec-bus-pins {
> + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_codec_bus_idle: aud-codec-bus-idle-pins {
> + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_loopback_bus: aud-loopback-bus-pins {
> + samsung,pins = "gpb1-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_loopback_bus_idle: aud-loopback-bus-idle-pins {
> + samsung,pins = "gpb1-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_fm_bus: aud-fm-bus-pins {
> + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_fm_bus_idle: aud-fm-bus-idle-pins {
> + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_spk_bus: aud-spk-bus-pins {
> + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +
> + aud_spk_bus_idle: aud-spk-bus-idle-pins {
> + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + };
> +};
> +
> +&pinctrl_fsys {
> + gpf0: gpf0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf2: gpf2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf3: gpf3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf4: gpf4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + sd0_clk: sd0-clk-pins {
> + samsung,pins = "gpf0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {
> + samsung,pins = "gpf0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + };
> +
> + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {
> + samsung,pins = "gpf0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <1>;
> + };
> +
> + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {
> + samsung,pins = "gpf0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {
> + samsung,pins = "gpf0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_cmd: sd0-cmd-pins {
> + samsung,pins = "gpf0-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_rdqs: sd0-rdqs-pins {
> + samsung,pins = "gpf0-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus1: sd0-bus-width1-pins {
> + samsung,pins = "gpf2-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus4: sd0-bus-width4-pins {
> + samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus8: sd0-bus-width8-pins {
> + samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_clk: sd1-clk-pins {
> + samsung,pins = "gpf3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins {
> + samsung,pins = "gpf3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + };
> +
> + sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins {
> + samsung,pins = "gpf3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <1>;
> + };
> +
> + sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins {
> + samsung,pins = "gpf3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins {
> + samsung,pins = "gpf3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_cmd: sd1-cmd-pins {
> + samsung,pins = "gpf3-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd1_bus1: sd1-bus-width1-pins {
> + samsung,pins = "gpf3-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd1_bus4: sd1-bus-width4-pins {
> + samsung,pins = "gpf3-3", "gpf3-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd2_clk: sd2-clk-pins {
> + samsung,pins = "gpf4-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> + samsung,pins = "gpf4-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + };
> +
> + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> + samsung,pins = "gpf4-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <1>;
> + };
> +
> + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> + samsung,pins = "gpf4-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> + samsung,pins = "gpf4-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_cmd: sd2-cmd-pins {
> + samsung,pins = "gpf4-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd2_bus1: sd2-bus-width1-pins {
> + samsung,pins = "gpf4-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd2_bus4: sd2-bus-width4-pins {
> + samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <2>;
> + };
> +};
> +
> +&pinctrl_top {
> + gpc0: gpc0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc1: gpc1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc2: gpc2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg0: gpg0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg1: gpg1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg2: gpg2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg3: gpg3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg4: gpg4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp0: gpp0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp1: gpp1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp2: gpp2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp3: gpp3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp4: gpp4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp5: gpp5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp6: gpp6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp7: gpp7 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpp8: gpp8 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + /* DECON TE */
> + decon_f_te_on: decon_f_te_on-pins {
> + samsung,pins = "gpc0-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> + };
> +
> + decon_f_te_off: decon_f_te_off-pins {
> + samsung,pins = "gpc0-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> + };
> +
> + hs_i2c0_bus: hs-i2c0-bus-pins {
> + samsung,pins = "gpc1-1", "gpc1-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c1_bus: hs-i2c1-bus-pins {
> + samsung,pins = "gpc1-3", "gpc1-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + hs_i2c2_bus: hs-i2c2-bus-pins {
> + samsung,pins = "gpc1-5", "gpc1-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + hs_i2c3_bus: hs-i2c3-bus-pins {
> + samsung,pins = "gpc1-7", "gpc1-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + /* USI0 UART */
> + uart3_bus_single: uart3-bus-single-pins {
> + samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + /* USI0 UART_HSI2C1 */
> + uart3_bus_dual: uart3-bus-dual-pins {
> + samsung,pins = "gpc2-1", "gpc2-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + /* USI0 HSI2C0 */
> + hs_i2c4_bus: hs-i2c4-bus-pins {
> + samsung,pins = "gpc2-1", "gpc2-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + /* USI0 HSI2C1 */
> + hs_i2c5_bus: hs-i2c5-bus-pins {
> + samsung,pins = "gpc2-3", "gpc2-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + /* USI0 SPI */
> + spi2_bus: spi2-bus-pins {
> + samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi2_cs: spi2-cs-pins {
> + samsung,pins = "gpc2-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + /* USI1 UART */
> + uart4_bus_single: uart4-bus-single-pins {
> + samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + /* USI1 UART_HSI2C1*/
> + uart4_bus_dual: uart4-bus-dual-pins {
> + samsung,pins = "gpc2-5", "gpc2-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + /* USI1 HSI2C0 */
> + hs_i2c6_bus: hs-i2c6-bus-pins {
> + samsung,pins = "gpc2-5", "gpc2-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + /* USI1 HSI2C1 */
> + hs_i2c7_bus: hs-i2c7-bus-pins {
> + samsung,pins = "gpc2-7", "gpc2-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + /* USI1 SPI */
> + spi3_bus: spi3-bus-pins {
> + samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi3_cs: spi3-cs-pins {
> + samsung,pins = "gpc2-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fm_lna_en: fm-lna-en-pins {
> + samsung,pins = "gpg0-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-val = <1>;
> + };
> +
> + uart1_bus: uart1-bus-pins {
> + samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + i2c7_bus: i2c7-bus-pins {
> + samsung,pins = "gpg1-5", "gpg1-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + aud_dmic_on: aud-dmic-on-pins {
> + samsung,pins = "gpg2-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-val = <1>;
> + };
> +
> + aud_dmic_off: aud-dmic-off-pins {
> + samsung,pins = "gpg2-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-val = <0>;
> + };
> +
> + /* UART_HEALTH */
> + uart0_bus: uart0-bus-pins {
> + samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + i2c0_bus: i2c0-bus-pins {
> + samsung,pins = "gpp1-1", "gpp1-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2c1_bus: i2c1-bus-pins {
> + samsung,pins = "gpp1-3", "gpp1-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2c2_bus: i2c2-bus-pins {
> + samsung,pins = "gpp2-1", "gpp2-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2c3_bus: i2c3-bus-pins {
> + samsung,pins = "gpp3-1", "gpp3-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2c4_bus: i2c4-bus-pins {
> + samsung,pins = "gpp4-1", "gpp4-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2c5_bus: i2c5-bus-pins {
> + samsung,pins = "gpp4-3", "gpp4-2";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2c6_bus: i2c6-bus-pins {
> + samsung,pins = "gpp4-5", "gpp4-4";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + /* SPI_ESE */
> + spi0_bus: spi0-bus-pins {
> + samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi0_cs: spi0-cs-pins {
> + samsung,pins = "gpp5-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + /* SPI_FP */
> + spi1_bus: spi1-bus-pins {
> + samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi1_cs: spi1-cs-pins {
> + samsung,pins = "gpp6-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + /* USI2 UART */
> + uart5_bus_single: uart5-bus-single-pins {
> + samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + /* USI2 UART_HSI2C1 */
> + uart5_bus_dual: uart5-bus-dual-pins {
> + samsung,pins = "gpp7-1", "gpp7-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + };
> +
> + /* USI2 HSI2C0 */
> + hs_i2c8_bus: hs-i2c8-bus-pins {
> + samsung,pins = "gpp7-1", "gpp7-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + /* USI2 HSI2C1 */
> + hs_i2c9_bus: hs-i2c9-bus-pins {
> + samsung,pins = "gpp8-1", "gpp8-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <0>;
> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> + };
> +
> + /* USI2 SPI */
> + spi4_bus: spi4-bus-pins {
> + samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi4_cs: spi4-cs-pins {
> + samsung,pins = "gpp8-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> new file mode 100644
> index 000000000000..cc7a5ce0c103
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> @@ -0,0 +1,438 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung Exynos7885 SoC device tree source
> + *
> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> + * Copyright (c) 2021 Dávid Virág
> + *

This line is not needed.

> + */
> +
> +#include <dt-bindings/clock/exynos7885.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "samsung,exynos7885";
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + pinctrl0 = &pinctrl_alive;
> + pinctrl1 = &pinctrl_dispaud;
> + pinctrl2 = &pinctrl_fsys;
> + pinctrl3 = &pinctrl_top;
> + };
> +
> + arm-a53-pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>,
> + <&cpu1>,
> + <&cpu2>,
> + <&cpu3>,
> + <&cpu4>,
> + <&cpu5>;

Maybe have cpu0..cpu3 on one line, and cpu4..cpu5 on second line?

> + };
> +
> + arm-a73-pmu {
> + compatible = "arm,cortex-a73-pmu";
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu6>,
> + <&cpu7>;

Both cpus can be on the same line here.

> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + core4 {
> + cpu = <&cpu4>;
> + };
> + core5 {
> + cpu = <&cpu5>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu6>;
> + };
> + core1 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x100>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x101>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x102>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x103>;
> + enable-method = "psci";
> + };
> +
> + cpu4: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x200>;
> + enable-method = "psci";
> + };
> +
> + cpu5: cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x201>;
> + enable-method = "psci";
> + };
> +
> + cpu6: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x0>;
> + enable-method = "psci";
> + };
> +
> + cpu7: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x1>;
> + enable-method = "psci";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci";
> + method = "smc";
> + cpu_suspend = <0xc4000001>;
> + cpu_off = <0x84000002>;
> + cpu_on = <0xc4000003>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + /* Hypervisor Virtual Timer interrupt is not wired to GIC */
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

Can you please make it fit 80 characters per line?

> + };
> +
> + fixed-rate-clocks {
> + oscclk: osc-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;

Hmm, maybe it's better to set this clock frequency in board dts?

> + clock-output-names = "oscclk";
> + };
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x20000000>;
> +
> + chipid@10000000 {
> + compatible = "samsung,exynos850-chipid";
> + reg = <0x10000000 0x24>;
> + };
> +
> + gic: interrupt-controller@12301000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x12301000 0x1000>,
> + <0x12302000 0x2000>,
> + <0x12304000 0x2000>,
> + <0x12306000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + cmu_peri: clock-controller@10010000 {
> + compatible = "samsung,exynos7885-cmu-peri";
> + reg = <0x10010000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>,
> + <&cmu_top CLK_DOUT_PERI_BUS>,
> + <&cmu_top CLK_DOUT_PERI_SPI0>,
> + <&cmu_top CLK_DOUT_PERI_SPI1>,
> + <&cmu_top CLK_DOUT_PERI_UART0>,
> + <&cmu_top CLK_DOUT_PERI_UART1>,
> + <&cmu_top CLK_DOUT_PERI_UART2>,
> + <&cmu_top CLK_DOUT_PERI_USI0>,
> + <&cmu_top CLK_DOUT_PERI_USI1>,
> + <&cmu_top CLK_DOUT_PERI_USI2>;
> + clock-names = "oscclk",
> + "dout_peri_bus",
> + "dout_peri_spi0",
> + "dout_peri_spi1",
> + "dout_peri_uart0",
> + "dout_peri_uart1",
> + "dout_peri_uart2",
> + "dout_peri_usi0",
> + "dout_peri_usi1",
> + "dout_peri_usi2";
> + };
> +
> + cmu_core: clock-controller@12000000 {
> + compatible = "samsung,exynos7885-cmu-core";
> + reg = <0x12000000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>,
> + <&cmu_top CLK_DOUT_CORE_BUS>,
> + <&cmu_top CLK_DOUT_CORE_CCI>,
> + <&cmu_top CLK_DOUT_CORE_G3D>;
> + clock-names = "oscclk", "dout_core_bus", "dout_core_cci", "dout_core_g3d";

80 characters per line, please. Also, please keep the style
consistent: in cmu_peri you have each clock per line, here all clocks
are on one line.

> + };
> +
> + cmu_top: clock-controller@12060000 {

I'd move cmu_top above, to be the first CMU node.

> + compatible = "samsung,exynos7885-cmu-top";
> + reg = <0x12060000 0x8000>;
> + #clock-cells = <1>;
> +
> + clocks = <&oscclk>;
> + clock-names = "oscclk";
> + };
> +
> + pinctrl_alive: pinctrl@11cb0000 {
> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x11cb0000 0x1000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +
> + wakeup-interrupt-controller {
> + compatible = "samsung,exynos7-wakeup-eint";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + pinctrl_dispaud: pinctrl@148f0000 {
> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x148f0000 0x1000>;
> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_fsys: pinctrl@13430000 {
> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x13430000 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pinctrl_top: pinctrl@139b0000 {
> + compatible = "samsung,exynos7885-pinctrl";
> + reg = <0x139b0000 0x1000>;
> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pmu_system_controller: system-controller@11c80000 {
> + compatible = "samsung,exynos7-pmu", "syscon";
> + reg = <0x11c80000 0x10000>;
> + };
> +
> + serial_0: serial@13800000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x13800000 0x100>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_bus>;
> + clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
> + <&cmu_peri CLK_GOUT_UART0_PCLK>;

AFAIU, usually PCLK is a bus clock. Are you sure it should be UART baud clock?

> + clock-names = "uart", "clk_uart_baud0";
> + samsung,uart-fifosize = <64>;
> + status = "disabled";
> + };
> +
> + serial_1: serial@13810000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x13810000 0x100>;
> + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_bus>;
> + clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
> + <&cmu_peri CLK_GOUT_UART1_PCLK>;
> + clock-names = "uart", "clk_uart_baud0";
> + samsung,uart-fifosize = <256>;
> + status = "disabled";
> + };
> +
> + serial_2: serial@13820000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x13820000 0x100>;
> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_bus>;
> + clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
> + <&cmu_peri CLK_GOUT_UART2_PCLK>;
> + clock-names = "uart", "clk_uart_baud0";
> + samsung,uart-fifosize = <256>;
> + status = "disabled";
> + };
> +
> + i2c_0: i2c@13830000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x13830000 0x100>;
> + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> +
> + i2c_1: i2c@13840000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x13840000 0x100>;
> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> +
> + i2c_2: i2c@13850000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x13850000 0x100>;
> + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> +
> + i2c_3: i2c@13860000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x13860000 0x100>;
> + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c3_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> +
> + i2c_4: i2c@13870000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x13870000 0x100>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c4_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> +
> + i2c_5: i2c@13880000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x13880000 0x100>;
> + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c5_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> +
> + i2c_6: i2c@13890000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x13890000 0x100>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c6_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> +
> + i2c_7: i2c@11cd0000 {
> + compatible = "samsung,s3c2440-i2c";
> + reg = <0x11cd0000 0x100>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c7_bus>;
> + clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
> + clock-names = "i2c";
> + status = "disabled";
> + };
> + };
> +};
> +
> +#include "exynos7885-pinctrl.dtsi"
> +#include "arm/exynos-syscon-restart.dtsi"

Have you verified both reboot and power off functions from this file?
I guess if some doesn't work, it's better to avoid including this, but
instead add corresponding sub-nodes into your pmu_sytem_controller.

> --
> 2.34.1
>

2021-12-07 22:30:48

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On Tue, 2021-12-07 at 22:19 +0200, Sam Protsenko wrote:
> On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]>
> wrote:
> >
> > Add initial Exynos7885 device tree nodes with dts for the Samsung
> > Galaxy
> > A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> > Currently this includes some clock support, UART support, and I2C
> > nodes.
> >
> > Signed-off-by: David Virag <[email protected]>
> > ---
> > Changes in v2:
> > - Remove address-cells, and size-cells from dts, since they are
> >     already in the dtsi.
> > - Lower case hex in memory node
> > - Fix node names with underscore instead of hyphen
> > - Fix line breaks
> > - Fix "-key" missing from gpio keys node names
> > - Use the form without "key" in gpio key labels on all keys
> > - Suffix pin configuration node names with "-pins"
> > - Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
> > - Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
> > - Add comment about Arm PMU
> > - Rename "clock-oscclk" to "osc-clock"
> > - Include exynos-syscon-restart.dtsi instead of rewriting its
> > contents
> >
> > Changes in v3:
> > - Fix typo (seperate -> separate)
> >
> > Changes in v4:
> > - Fixed leading 0x in clock-controller nodes
> > - Actually suffixed pin configuration node names with "-pins"
> > - Seperated Cortex-A53 and Cortex-A73 PMU
> >
> > arch/arm64/boot/dts/exynos/Makefile           |   7 +-
> > .../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
> > .../boot/dts/exynos/exynos7885-pinctrl.dtsi   | 865
> > ++++++++++++++++++
> > arch/arm64/boot/dts/exynos/exynos7885.dtsi    | 438 +++++++++
> > 4 files changed, 1402 insertions(+), 3 deletions(-)
> > create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-
> > jackpotlte.dts
>
> Shouldn't SoC and board files be sent as two separate patches? For
> example, I've checked exynos5433 and exynos7, SoC support

For some reason I remembered ExynosAutoV9 sending them together but I
was wrong, will seperate in the future.

>
> > create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-
> > pinctrl.dtsi
> > create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/exynos/Makefile
> > b/arch/arm64/boot/dts/exynos/Makefile
> > index b41e86df0a84..c68c4ad577ac 100644
> > --- a/arch/arm64/boot/dts/exynos/Makefile
> > +++ b/arch/arm64/boot/dts/exynos/Makefile
> > @@ -1,6 +1,7 @@
> > # SPDX-License-Identifier: GPL-2.0
> > dtb-$(CONFIG_ARCH_EXYNOS) += \
> > -       exynos5433-tm2.dtb      \
> > -       exynos5433-tm2e.dtb     \
> > -       exynos7-espresso.dtb    \
> > +       exynos5433-tm2.dtb              \
> > +       exynos5433-tm2e.dtb             \
> > +       exynos7-espresso.dtb            \
> > +       exynos7885-jackpotlte.dtb       \
> >         exynosautov9-sadk.dtb
> > diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> > b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> > new file mode 100644
> > index 000000000000..f5941dc4c374
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
> > + *
> > + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> > + * Copyright (c) 2021 Dávid Virág
> > + *
>
> This line is not needed.
>
> > + */
> > +
> > +/dts-v1/;
>
> Suggest adding empty line here.
>
> > +#include "exynos7885.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +       model = "Samsung Galaxy A8 (2018)";
> > +       compatible = "samsung,jackpotlte", "samsung,exynos7885";
> > +       chassis-type = "handset";
> > +
> > +       aliases {
> > +               serial0 = &serial_0;
> > +               serial1 = &serial_1;
> > +               serial2 = &serial_2;
>
> Suggestion: add aliases also for i2c nodes, to keep i2c instance
> numbers fixed in run-time (e.g. in "i2cdetect -l" output).
>
> > +       };
> > +
> > +       chosen {
> > +               stdout-path = &serial_2;
> > +       };
> > +
> > +       memory@80000000 {
> > +               device_type = "memory";
> > +               reg = <0x0 0x80000000 0x3da00000>,
> > +                     <0x0 0xc0000000 0x40000000>,
> > +                     <0x8 0x80000000 0x40000000>;
> > +       };
> > +
> > +       gpio-keys {
> > +               compatible = "gpio-keys";
> > +               pinctrl-names = "default";
> > +               pinctrl-0 = <&key_volup &key_voldown &key_power>;
> > +
> > +               volup-key {
> > +                       label = "Volume Up";
> > +                       interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
>
> Here and below: what is 0, why it's needed? Also, isn't it enough to
> have just "gpios", and remove interrupt*? Need to check "gpio-keys"
> driver and bindings doc, but AFAIR it should be enough to have just
> "gpios =" or just "interrupts =".

Well, if we have both an interrupt and gpio access, why not provide
both? According to the documentation, `Specifying both properties is
allowed.`

>
>
> > +                       interrupt-parent = <&gpa1>;
> > +                       linux,code = <KEY_VOLUMEUP>;
> > +                       gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
> > +               };
> > +
> > +               voldown-key {
> > +                       label = "Volume Down";
> > +                       interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       interrupt-parent = <&gpa1>;
> > +                       linux,code = <KEY_VOLUMEDOWN>;
> > +                       gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
> > +               };
> > +
> > +               power-key {
> > +                       label = "Power";
> > +                       interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
> > +                       interrupt-parent = <&gpa1>;
> > +                       linux,code = <KEY_POWER>;
> > +                       gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
> > +                       wakeup-source;
> > +               };
> > +       };
> > +};
> > +
>
> If there are some LEDs by chance on that board -- it might be useful
> to define those here with "gpio-leds" as well. Maybe even set some
> default trigger like "heartbeat".

There is a front RGB led, but IIRC that is accessed through the S2MU004
MFD using I2C. There's also a rear "ktd2692" flash, which might or
might not be controllable using that, will need to check that one.

>
> > +&serial_2 {
> > +       status = "okay";
> > +};
> > +
> > +&pinctrl_alive {
> > +       key_volup: key-volup-pins {
> > +               samsung,pins = "gpa1-5";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>
> Maybe EXYNOS_PIN_FUNC_EINT is more self-explanatory? Just a
> suggestion though.

Was wondering about this too, but a quick grep showed that
EXYNOS_PIN_FUNC_EINT was not used in any dts, and in fact only used in
"drivers/pinctrl/samsung/pinctrl-exynos.c". The one that was used in
dts/dtsis is EXYNOS_PIN_FUNC_F.

>
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
>
> Here and below: please use EXYNOS5420_PIN_DRV_LV1 (means drive level
> = 1x).

Just found "exynos_gpio_config_macros.dtsi" in the downstream code not
long ago, I guess you are right!

>
> > +       };
> > +
> > +       key_voldown: key-voldown-pins {
> > +               samsung,pins = "gpa1-6";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       key_power: key-power-pins {
> > +               samsung,pins = "gpa1-7";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +};
> > diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> > b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..8336b2e48858
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> > @@ -0,0 +1,865 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Samsung Exynos7885 SoC pin-mux and pin-config device tree
> > source
> > + *
> > + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> > + * Copyright (c) 2021 Dávid Virág
> > + *
> > + * Samsung's Exynos7885 SoC pin-mux and pin-config options are
> > listed as
> > + * device tree nodes in this file.
> > + */
> > +
> > +#include <dt-bindings/pinctrl/samsung.h>
>
> You probably also need <dt-bindings/interrupt-controller/arm-gic.h>
> here for GIC_SPI definition.

Good catch! Will add it!

>
> > +
> > +&pinctrl_alive {
> > +       etc0: etc0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       etc1: etc1 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
>
> Hmm, what are these two? I can't find anything related in
> exynos7885.dtsi. If it's just some leftover from downstream vendor
> kernel -- please remove it.

They are real pins (as in they do something inside the SoC for sure),
but don't seem to be used for much. Some dtsis show "AP_JTAG_TRST_N"
being on etc0-0. I'm guessing these are some kind of debug pins? Have
you seen anything about them on the 850?

>
> > +
> > +       gpa0: gpa0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa1: gpa1 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <3>;
> > +               interrupt-parent = <&gic>;
> > +               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       gpa2: gpa2 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpq0: gpq0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       sim1_det_gpio: sim1-det-gpio-pins {
> > +               samsung,pins = "gpa2-5";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       sim0_det_gpio: sim0-det-gpio-pins {
> > +               samsung,pins = "gpa2-6";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       speedy_bus: speedy-bus-pins {
> > +               samsung,pins = "gpq0-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
>
> Here and below: suggest using EXYNOS5420_PIN_DRV_LV* constants. Then
> stuff like "sd1_clk_fast_slew_rate_4x" is going to make sense.
>
> > +       };
> > +
> > +       /* UART_DEBUG */
> > +       uart2_bus: uart2-bus-pins {
> > +               samsung,pins = "gpq0-4", "gpq0-3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +};
> > +
> > +&pinctrl_dispaud {
> > +       gpb0: gpb0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpb1: gpb1 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpb2: gpb2 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       aud_codec_mclk: aud-codec-mclk-pins {
> > +               samsung,pins = "gpb0-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_codec_mclk_idle: aud-codec-mclk-idle-pins {
> > +               samsung,pins = "gpb0-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_codec_bus: aud-codec-bus-pins {
> > +               samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-
> > 4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_codec_bus_idle: aud-codec-bus-idle-pins {
> > +               samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-
> > 4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_loopback_bus: aud-loopback-bus-pins {
> > +               samsung,pins = "gpb1-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_loopback_bus_idle: aud-loopback-bus-idle-pins {
> > +               samsung,pins = "gpb1-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_fm_bus: aud-fm-bus-pins {
> > +               samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_fm_bus_idle: aud-fm-bus-idle-pins {
> > +               samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_spk_bus: aud-spk-bus-pins {
> > +               samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-
> > 3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +
> > +       aud_spk_bus_idle: aud-spk-bus-idle-pins {
> > +               samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-
> > 3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +       };
> > +};
> > +
> > +&pinctrl_fsys {
> > +       gpf0: gpf0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpf2: gpf2 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpf3: gpf3 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpf4: gpf4 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       sd0_clk: sd0-clk-pins {
> > +               samsung,pins = "gpf0-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {
> > +               samsung,pins = "gpf0-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {
> > +               samsung,pins = "gpf0-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <1>;
> > +       };
> > +
> > +       sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {
> > +               samsung,pins = "gpf0-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {
> > +               samsung,pins = "gpf0-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd0_cmd: sd0-cmd-pins {
> > +               samsung,pins = "gpf0-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd0_rdqs: sd0-rdqs-pins {
> > +               samsung,pins = "gpf0-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd0_bus1: sd0-bus-width1-pins {
> > +               samsung,pins = "gpf2-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd0_bus4: sd0-bus-width4-pins {
> > +               samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd0_bus8: sd0-bus-width8-pins {
> > +               samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-
> > 7";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd1_clk: sd1-clk-pins {
> > +               samsung,pins = "gpf3-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins {
> > +               samsung,pins = "gpf3-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins {
> > +               samsung,pins = "gpf3-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <1>;
> > +       };
> > +
> > +       sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins {
> > +               samsung,pins = "gpf3-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins {
> > +               samsung,pins = "gpf3-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd1_cmd: sd1-cmd-pins {
> > +               samsung,pins = "gpf3-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd1_bus1: sd1-bus-width1-pins {
> > +               samsung,pins = "gpf3-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd1_bus4: sd1-bus-width4-pins {
> > +               samsung,pins = "gpf3-3", "gpf3-5";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd2_clk: sd2-clk-pins {
> > +               samsung,pins = "gpf4-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> > +               samsung,pins = "gpf4-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> > +               samsung,pins = "gpf4-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <1>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> > +               samsung,pins = "gpf4-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> > +               samsung,pins = "gpf4-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <3>;
> > +       };
> > +
> > +       sd2_cmd: sd2-cmd-pins {
> > +               samsung,pins = "gpf4-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd2_bus1: sd2-bus-width1-pins {
> > +               samsung,pins = "gpf4-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +
> > +       sd2_bus4: sd2-bus-width4-pins {
> > +               samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <2>;
> > +       };
> > +};
> > +
> > +&pinctrl_top {
> > +       gpc0: gpc0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpc1: gpc1 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpc2: gpc2 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpg0: gpg0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpg1: gpg1 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpg2: gpg2 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpg3: gpg3 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpg4: gpg4 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp0: gpp0 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp1: gpp1 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp2: gpp2 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp3: gpp3 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp4: gpp4 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp5: gpp5 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp6: gpp6 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp7: gpp7 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       gpp8: gpp8 {
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +
> > +               interrupt-controller;
> > +               #interrupt-cells = <2>;
> > +       };
> > +
> > +       /* DECON TE */
> > +       decon_f_te_on: decon_f_te_on-pins {
> > +               samsung,pins = "gpc0-3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> > +       };
> > +
> > +       decon_f_te_off: decon_f_te_off-pins {
> > +               samsung,pins = "gpc0-3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> > +       };
> > +
> > +       hs_i2c0_bus: hs-i2c0-bus-pins {
> > +               samsung,pins = "gpc1-1", "gpc1-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       hs_i2c1_bus: hs-i2c1-bus-pins {
> > +               samsung,pins = "gpc1-3", "gpc1-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       hs_i2c2_bus: hs-i2c2-bus-pins {
> > +               samsung,pins = "gpc1-5", "gpc1-4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       hs_i2c3_bus: hs-i2c3-bus-pins {
> > +               samsung,pins = "gpc1-7", "gpc1-6";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       /* USI0 UART */
> > +       uart3_bus_single: uart3-bus-single-pins {
> > +               samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-
> > 0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       /* USI0 UART_HSI2C1 */
> > +       uart3_bus_dual: uart3-bus-dual-pins {
> > +               samsung,pins = "gpc2-1", "gpc2-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       /* USI0 HSI2C0 */
> > +       hs_i2c4_bus: hs-i2c4-bus-pins {
> > +               samsung,pins = "gpc2-1", "gpc2-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       /* USI0 HSI2C1 */
> > +       hs_i2c5_bus: hs-i2c5-bus-pins {
> > +               samsung,pins = "gpc2-3", "gpc2-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       /* USI0 SPI */
> > +       spi2_bus: spi2-bus-pins {
> > +               samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       spi2_cs: spi2-cs-pins {
> > +               samsung,pins = "gpc2-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       /* USI1 UART */
> > +       uart4_bus_single: uart4-bus-single-pins {
> > +               samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-
> > 4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       /* USI1 UART_HSI2C1*/
> > +       uart4_bus_dual: uart4-bus-dual-pins {
> > +               samsung,pins = "gpc2-5", "gpc2-4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       /* USI1 HSI2C0 */
> > +       hs_i2c6_bus: hs-i2c6-bus-pins {
> > +               samsung,pins = "gpc2-5", "gpc2-4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       /* USI1 HSI2C1 */
> > +       hs_i2c7_bus: hs-i2c7-bus-pins {
> > +               samsung,pins = "gpc2-7", "gpc2-6";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       /* USI1 SPI */
> > +       spi3_bus: spi3-bus-pins {
> > +               samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       spi3_cs: spi3-cs-pins {
> > +               samsung,pins = "gpc2-6";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       fm_lna_en: fm-lna-en-pins {
> > +               samsung,pins = "gpg0-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-val = <1>;
> > +       };
> > +
> > +       uart1_bus: uart1-bus-pins {
> > +               samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-
> > 0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       i2c7_bus: i2c7-bus-pins {
> > +               samsung,pins = "gpg1-5", "gpg1-4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       aud_dmic_on: aud-dmic-on-pins {
> > +               samsung,pins = "gpg2-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> > +               samsung,pin-val = <1>;
> > +       };
> > +
> > +       aud_dmic_off: aud-dmic-off-pins {
> > +               samsung,pins = "gpg2-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> > +               samsung,pin-val = <0>;
> > +       };
> > +
> > +       /* UART_HEALTH */
> > +       uart0_bus: uart0-bus-pins {
> > +               samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-
> > 0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       i2c0_bus: i2c0-bus-pins {
> > +               samsung,pins = "gpp1-1", "gpp1-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       i2c1_bus: i2c1-bus-pins {
> > +               samsung,pins = "gpp1-3", "gpp1-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       i2c2_bus: i2c2-bus-pins {
> > +               samsung,pins = "gpp2-1", "gpp2-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       i2c3_bus: i2c3-bus-pins {
> > +               samsung,pins = "gpp3-1", "gpp3-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       i2c4_bus: i2c4-bus-pins {
> > +               samsung,pins = "gpp4-1", "gpp4-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       i2c5_bus: i2c5-bus-pins {
> > +               samsung,pins = "gpp4-3", "gpp4-2";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       i2c6_bus: i2c6-bus-pins {
> > +               samsung,pins = "gpp4-5", "gpp4-4";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       /* SPI_ESE */
> > +       spi0_bus: spi0-bus-pins {
> > +               samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       spi0_cs: spi0-cs-pins {
> > +               samsung,pins = "gpp5-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       /* SPI_FP */
> > +       spi1_bus: spi1-bus-pins {
> > +               samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       spi1_cs: spi1-cs-pins {
> > +               samsung,pins = "gpp6-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       /* USI2 UART */
> > +       uart5_bus_single: uart5-bus-single-pins {
> > +               samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-
> > 0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +         };
> > +
> > +       /* USI2 UART_HSI2C1 */
> > +       uart5_bus_dual: uart5-bus-dual-pins {
> > +               samsung,pins = "gpp7-1", "gpp7-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +       };
> > +
> > +       /* USI2 HSI2C0 */
> > +       hs_i2c8_bus: hs-i2c8-bus-pins {
> > +               samsung,pins = "gpp7-1", "gpp7-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       /* USI2 HSI2C1 */
> > +       hs_i2c9_bus: hs-i2c9-bus-pins {
> > +               samsung,pins = "gpp8-1", "gpp8-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> > +               samsung,pin-drv = <0>;
> > +               samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> > +               samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> > +       };
> > +
> > +       /* USI2 SPI */
> > +       spi4_bus: spi4-bus-pins {
> > +               samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +
> > +       spi4_cs: spi4-cs-pins {
> > +               samsung,pins = "gpp8-0";
> > +               samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> > +               samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> > +               samsung,pin-drv = <0>;
> > +       };
> > +};
> > diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> > b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> > new file mode 100644
> > index 000000000000..cc7a5ce0c103
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> > @@ -0,0 +1,438 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Samsung Exynos7885 SoC device tree source
> > + *
> > + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> > + * Copyright (c) 2021 Dávid Virág
> > + *
>
> This line is not needed.
>
> > + */
> > +
> > +#include <dt-bindings/clock/exynos7885.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +       compatible = "samsung,exynos7885";
> > +       #address-cells = <2>;
> > +       #size-cells = <1>;
> > +
> > +       interrupt-parent = <&gic>;
> > +
> > +       aliases {
> > +               pinctrl0 = &pinctrl_alive;
> > +               pinctrl1 = &pinctrl_dispaud;
> > +               pinctrl2 = &pinctrl_fsys;
> > +               pinctrl3 = &pinctrl_top;
> > +       };
> > +
> > +       arm-a53-pmu {
> > +               compatible = "arm,cortex-a53-pmu";
> > +               interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
> > +               interrupt-affinity = <&cpu0>,
> > +                                    <&cpu1>,
> > +                                    <&cpu2>,
> > +                                    <&cpu3>,
> > +                                    <&cpu4>,
> > +                                    <&cpu5>;
>
> Maybe have cpu0..cpu3 on one line, and cpu4..cpu5 on second line?
>
> > +       };
> > +
> > +       arm-a73-pmu {
> > +               compatible = "arm,cortex-a73-pmu";
> > +               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> > +                            <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > +               interrupt-affinity = <&cpu6>,
> > +                                    <&cpu7>;
>
> Both cpus can be on the same line here.
>
> > +       };
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu-map {
> > +                       cluster0 {
> > +                               core0 {
> > +                                       cpu = <&cpu0>;
> > +                               };
> > +                               core1 {
> > +                                       cpu = <&cpu1>;
> > +                               };
> > +                               core2 {
> > +                                       cpu = <&cpu2>;
> > +                               };
> > +                               core3 {
> > +                                       cpu = <&cpu3>;
> > +                               };
> > +                               core4 {
> > +                                       cpu = <&cpu4>;
> > +                               };
> > +                               core5 {
> > +                                       cpu = <&cpu5>;
> > +                               };
> > +                       };
> > +
> > +                       cluster1 {
> > +                               core0 {
> > +                                       cpu = <&cpu6>;
> > +                               };
> > +                               core1 {
> > +                                       cpu = <&cpu7>;
> > +                               };
> > +                       };
> > +               };
> > +
> > +               cpu0: cpu@100 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x100>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu1: cpu@101 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x101>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu2: cpu@102 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x102>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu3: cpu@103 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x103>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu4: cpu@200 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x200>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu5: cpu@201 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a53";
> > +                       reg = <0x201>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu6: cpu@0 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a73";
> > +                       reg = <0x0>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu7: cpu@1 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a73";
> > +                       reg = <0x1>;
> > +                       enable-method = "psci";
> > +               };
> > +       };
> > +
> > +       psci {
> > +               compatible = "arm,psci";
> > +               method = "smc";
> > +               cpu_suspend = <0xc4000001>;
> > +               cpu_off = <0x84000002>;
> > +               cpu_on = <0xc4000003>;
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               /* Hypervisor Virtual Timer interrupt is not wired
> > to GIC */
> > +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>;
>
> Can you please make it fit 80 characters per line?

Sure, these are easy to miss.

>
> > +       };
> > +
> > +       fixed-rate-clocks {
> > +               oscclk: osc-clock {
> > +                       compatible = "fixed-clock";
> > +                       #clock-cells = <0>;
> > +                       clock-frequency = <26000000>;
>
> Hmm, maybe it's better to set this clock frequency in board dts?

Well, every known 7885 device has 26000000 but I guess it does belong
to the board dts.

>
> > +                       clock-output-names = "oscclk";
> > +               };
> > +       };
> > +
> > +       soc: soc@0 {
> > +               compatible = "simple-bus";
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               ranges = <0x0 0x0 0x0 0x20000000>;
> > +
> > +               chipid@10000000 {
> > +                       compatible = "samsung,exynos850-chipid";
> > +                       reg = <0x10000000 0x24>;
> > +               };
> > +
> > +               gic: interrupt-controller@12301000 {
> > +                       compatible = "arm,gic-400";
> > +                       #interrupt-cells = <3>;
> > +                       #address-cells = <0>;
> > +                       interrupt-controller;
> > +                       reg = <0x12301000 0x1000>,
> > +                             <0x12302000 0x2000>,
> > +                             <0x12304000 0x2000>,
> > +                             <0x12306000 0x2000>;
> > +                       interrupts = <GIC_PPI 9
> > (GIC_CPU_MASK_SIMPLE(8) |
> > +
> > IRQ_TYPE_LEVEL_HIGH)>;
> > +               };
> > +
> > +               cmu_peri: clock-controller@10010000 {
> > +                       compatible = "samsung,exynos7885-cmu-peri";
> > +                       reg = <0x10010000 0x8000>;
> > +                       #clock-cells = <1>;
> > +
> > +                       clocks = <&oscclk>,
> > +                                <&cmu_top CLK_DOUT_PERI_BUS>,
> > +                                <&cmu_top CLK_DOUT_PERI_SPI0>,
> > +                                <&cmu_top CLK_DOUT_PERI_SPI1>,
> > +                                <&cmu_top CLK_DOUT_PERI_UART0>,
> > +                                <&cmu_top CLK_DOUT_PERI_UART1>,
> > +                                <&cmu_top CLK_DOUT_PERI_UART2>,
> > +                                <&cmu_top CLK_DOUT_PERI_USI0>,
> > +                                <&cmu_top CLK_DOUT_PERI_USI1>,
> > +                                <&cmu_top CLK_DOUT_PERI_USI2>;
> > +                       clock-names = "oscclk",
> > +                                     "dout_peri_bus",
> > +                                     "dout_peri_spi0",
> > +                                     "dout_peri_spi1",
> > +                                     "dout_peri_uart0",
> > +                                     "dout_peri_uart1",
> > +                                     "dout_peri_uart2",
> > +                                     "dout_peri_usi0",
> > +                                     "dout_peri_usi1",
> > +                                     "dout_peri_usi2";
> > +               };
> > +
> > +               cmu_core: clock-controller@12000000 {
> > +                       compatible = "samsung,exynos7885-cmu-core";
> > +                       reg = <0x12000000 0x8000>;
> > +                       #clock-cells = <1>;
> > +
> > +                       clocks = <&oscclk>,
> > +                                <&cmu_top CLK_DOUT_CORE_BUS>,
> > +                                <&cmu_top CLK_DOUT_CORE_CCI>,
> > +                                <&cmu_top CLK_DOUT_CORE_G3D>;
> > +                       clock-names = "oscclk", "dout_core_bus",
> > "dout_core_cci", "dout_core_g3d";
>
> 80 characters per line, please. Also, please keep the style
> consistent: in cmu_peri you have each clock per line, here all clocks
> are on one line.
>
> > +               };
> > +
> > +               cmu_top: clock-controller@12060000 {
>
> I'd move cmu_top above, to be the first CMU node.
>
> > +                       compatible = "samsung,exynos7885-cmu-top";
> > +                       reg = <0x12060000 0x8000>;
> > +                       #clock-cells = <1>;
> > +
> > +                       clocks = <&oscclk>;
> > +                       clock-names = "oscclk";
> > +               };
> > +
> > +               pinctrl_alive: pinctrl@11cb0000 {
> > +                       compatible = "samsung,exynos7885-pinctrl";
> > +                       reg = <0x11cb0000 0x1000>;
> > +                       interrupts = <GIC_SPI 0
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 1
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 2
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 3
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 4
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 5
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 6
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 7
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 8
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 9
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 10
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 11
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 12
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 13
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 14
> > IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 15
> > IRQ_TYPE_LEVEL_HIGH>;
> > +
> > +                       wakeup-interrupt-controller {
> > +                               compatible = "samsung,exynos7-
> > wakeup-eint";
> > +                               interrupt-parent = <&gic>;
> > +                               interrupts = <GIC_SPI 130
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       };
> > +               };
> > +
> > +               pinctrl_dispaud: pinctrl@148f0000 {
> > +                       compatible = "samsung,exynos7885-pinctrl";
> > +                       reg = <0x148f0000 0x1000>;
> > +                       interrupts = <GIC_SPI 130
> > IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               pinctrl_fsys: pinctrl@13430000 {
> > +                       compatible = "samsung,exynos7885-pinctrl";
> > +                       reg = <0x13430000 0x1000>;
> > +                       interrupts = <GIC_SPI 150
> > IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               pinctrl_top: pinctrl@139b0000 {
> > +                       compatible = "samsung,exynos7885-pinctrl";
> > +                       reg = <0x139b0000 0x1000>;
> > +                       interrupts = <GIC_SPI 266
> > IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> > +
> > +               pmu_system_controller: system-controller@11c80000 {
> > +                       compatible = "samsung,exynos7-pmu",
> > "syscon";
> > +                       reg = <0x11c80000 0x10000>;
> > +               };
> > +
> > +               serial_0: serial@13800000 {
> > +                       compatible = "samsung,exynos5433-uart";
> > +                       reg = <0x13800000 0x100>;
> > +                       interrupts = <GIC_SPI 246
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&uart0_bus>;
> > +                       clocks = <&cmu_peri
> > CLK_GOUT_UART0_EXT_UCLK>,
> > +                                <&cmu_peri CLK_GOUT_UART0_PCLK>;
>
> AFAIU, usually PCLK is a bus clock. Are you sure it should be UART
> baud clock?

These are the two clocks, and it's definitely wrong swapped, as it
breaks switching baudrates, but PCLK does in fact have PERI_BUS_USER as
it's parent. while EXT_UCLK has PERI_UART0_USER as parent. Not sure
what is up with it here but it works fine this way but not the other
way around.

>
> > +                       clock-names = "uart", "clk_uart_baud0";
> > +                       samsung,uart-fifosize = <64>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               serial_1: serial@13810000 {
> > +                       compatible = "samsung,exynos5433-uart";
> > +                       reg = <0x13810000 0x100>;
> > +                       interrupts = <GIC_SPI 247
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&uart1_bus>;
> > +                       clocks = <&cmu_peri
> > CLK_GOUT_UART1_EXT_UCLK>,
> > +                                <&cmu_peri CLK_GOUT_UART1_PCLK>;
> > +                       clock-names = "uart", "clk_uart_baud0";
> > +                       samsung,uart-fifosize = <256>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               serial_2: serial@13820000 {
> > +                       compatible = "samsung,exynos5433-uart";
> > +                       reg = <0x13820000 0x100>;
> > +                       interrupts = <GIC_SPI 279
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&uart2_bus>;
> > +                       clocks = <&cmu_peri
> > CLK_GOUT_UART2_EXT_UCLK>,
> > +                                <&cmu_peri CLK_GOUT_UART2_PCLK>;
> > +                       clock-names = "uart", "clk_uart_baud0";
> > +                       samsung,uart-fifosize = <256>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_0: i2c@13830000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x13830000 0x100>;
> > +                       interrupts = <GIC_SPI 248
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c0_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_1: i2c@13840000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x13840000 0x100>;
> > +                       interrupts = <GIC_SPI 249
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c1_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_2: i2c@13850000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x13850000 0x100>;
> > +                       interrupts = <GIC_SPI 250
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c2_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_3: i2c@13860000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x13860000 0x100>;
> > +                       interrupts = <GIC_SPI 251
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c3_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_4: i2c@13870000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x13870000 0x100>;
> > +                       interrupts = <GIC_SPI 252
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c4_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_5: i2c@13880000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x13880000 0x100>;
> > +                       interrupts = <GIC_SPI 253
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c5_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_6: i2c@13890000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x13890000 0x100>;
> > +                       interrupts = <GIC_SPI 254
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c6_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +
> > +               i2c_7: i2c@11cd0000 {
> > +                       compatible = "samsung,s3c2440-i2c";
> > +                       reg = <0x11cd0000 0x100>;
> > +                       interrupts = <GIC_SPI 255
> > IRQ_TYPE_LEVEL_HIGH>;
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       pinctrl-names = "default";
> > +                       pinctrl-0 = <&i2c7_bus>;
> > +                       clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
> > +                       clock-names = "i2c";
> > +                       status = "disabled";
> > +               };
> > +       };
> > +};
> > +
> > +#include "exynos7885-pinctrl.dtsi"
> > +#include "arm/exynos-syscon-restart.dtsi"
>
> Have you verified both reboot and power off functions from this file?
> I guess if some doesn't work, it's better to avoid including this,
> but
> instead add corresponding sub-nodes into your pmu_sytem_controller.

They do in fact work on my phone ;)
One thing I noticed is that if I send a poweroff command and hold down
the power key, it will stay powered on until I release it. I guess
that's just how it's wired up.
Sometimes, very rarely a reboot does act weird though: Every once in a
while, a reboot turns the phone off, then the bootloader starts
outputting on UART before it cuts off my connection to UART by
resetting the MUIC, and the phone never powers on again by itself
after. (like.. bootloader starts then powers the phone off even before
the display would come on?) I should check the bootloader logs saved to
a last_kmsg buffer the next time this happens, but this looks like more
of a bootloader issue rather than this being wrong.

>
> > --
> > 2.34.1
> >

2021-12-08 00:55:34

by Chanho Park

[permalink] [raw]

Subject: RE: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

> > Shouldn't SoC and board files be sent as two separate patches? For
> > example, I've checked exynos5433 and exynos7, SoC support
>
> For some reason I remembered ExynosAutoV9 sending them together but I
> was wrong, will seperate in the future.

I posted it separately.
https://lore.kernel.org/linux-samsung-soc/[email protected]/

Best Regards,
Chanho Park

2021-12-08 08:50:28

[permalink] [raw]

Subject: Re: [PATCH v4 5/7] clk: samsung: clk-pll: Add support for pll1417x

On 07/12/2021 20:00, Sam Protsenko wrote:
> On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>>
>> pll1417x is used in Exynos7885 SoC for top-level integer PLLs.
>> It is similar enough to pll0822x that practically the same code can
>> handle both. The difference that's to be noted is that when defining a
>> pl1417x PLL, the "con" parameter of the PLL macro should be set to the
>> CON1 register instead of CON3, like this:
>>
>> PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
>> PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0,
>> NULL),
>>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> Signed-off-by: David Virag <[email protected]>
>> ---
>> Changes in v2:
>> - Nothing
>>
>> Changes in v3:
>> - Nothing
>>
>> Changes in v4:
>> - Added R-b tag by Krzysztof Kozlowski
>>
>> drivers/clk/samsung/clk-pll.c | 1 +
>> drivers/clk/samsung/clk-pll.h | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
>> index 83d1b03647db..70cdc87f714e 100644
>> --- a/drivers/clk/samsung/clk-pll.c
>> +++ b/drivers/clk/samsung/clk-pll.c
>> @@ -1476,6 +1476,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>> else
>> init.ops = &samsung_pll35xx_clk_ops;
>> break;
>> + case pll_1417x:
>
> I wonder why this switch have a bunch of fall through cases, but none
> marked with "fallthrough;" line, and both checkpatch and "make" turn
> blind eye on that? Anyway, I guess it's ok as is, just an observation.
>

I think the fallthrough is needed for non-obvious cases where one case
has some code and misses a break. Something like:

switch () {
case a:
case b:
case c:
foobar();
}

is obvious/explicit and does not need fallthrough.

Best regards,
Krzysztof

2021-12-08 09:05:45

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On 07/12/2021 21:19, Sam Protsenko wrote:
> On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>>
>> Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy
>> A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
>> Currently this includes some clock support, UART support, and I2C nodes.
>>
>> Signed-off-by: David Virag <[email protected]>
>> ---
>> Changes in v2:
>> - Remove address-cells, and size-cells from dts, since they are
>> already in the dtsi.
>> - Lower case hex in memory node
>> - Fix node names with underscore instead of hyphen
>> - Fix line breaks
>> - Fix "-key" missing from gpio keys node names
>> - Use the form without "key" in gpio key labels on all keys
>> - Suffix pin configuration node names with "-pins"
>> - Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
>> - Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
>> - Add comment about Arm PMU
>> - Rename "clock-oscclk" to "osc-clock"
>> - Include exynos-syscon-restart.dtsi instead of rewriting its contents
>>
>> Changes in v3:
>> - Fix typo (seperate -> separate)
>>
>> Changes in v4:
>> - Fixed leading 0x in clock-controller nodes
>> - Actually suffixed pin configuration node names with "-pins"
>> - Seperated Cortex-A53 and Cortex-A73 PMU
>>
>> arch/arm64/boot/dts/exynos/Makefile | 7 +-
>> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
>> .../boot/dts/exynos/exynos7885-pinctrl.dtsi | 865 ++++++++++++++++++
>> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 438 +++++++++
>> 4 files changed, 1402 insertions(+), 3 deletions(-)
>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
>
> Shouldn't SoC and board files be sent as two separate patches? For
> example, I've checked exynos5433 and exynos7, SoC support

Does not have to be. DTSI by itself cannot be even compiled, so keeping
it a separate commit does not bring that much benefits. Especially if it
is only one DTSI and one DTS.

>
>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
>> index b41e86df0a84..c68c4ad577ac 100644
>> --- a/arch/arm64/boot/dts/exynos/Makefile
>> +++ b/arch/arm64/boot/dts/exynos/Makefile
>> @@ -1,6 +1,7 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_EXYNOS) += \
>> - exynos5433-tm2.dtb \
>> - exynos5433-tm2e.dtb \
>> - exynos7-espresso.dtb \
>> + exynos5433-tm2.dtb \
>> + exynos5433-tm2e.dtb \
>> + exynos7-espresso.dtb \
>> + exynos7885-jackpotlte.dtb \
>> exynosautov9-sadk.dtb
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
>> new file mode 100644
>> index 000000000000..f5941dc4c374
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
>> @@ -0,0 +1,95 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
>> + *
>> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
>> + * Copyright (c) 2021 Dávid Virág
>> + *
>
> This line is not needed.
>
>> + */
>> +
>> +/dts-v1/;
>
> Suggest adding empty line here.
>
>> +#include "exynos7885.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +/ {
>> + model = "Samsung Galaxy A8 (2018)";
>> + compatible = "samsung,jackpotlte", "samsung,exynos7885";
>> + chassis-type = "handset";
>> +
>> + aliases {
>> + serial0 = &serial_0;
>> + serial1 = &serial_1;
>> + serial2 = &serial_2;
>
> Suggestion: add aliases also for i2c nodes, to keep i2c instance
> numbers fixed in run-time (e.g. in "i2cdetect -l" output).
>
>> + };
>> +
>> + chosen {
>> + stdout-path = &serial_2;
>> + };
>> +
>> + memory@80000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x80000000 0x3da00000>,
>> + <0x0 0xc0000000 0x40000000>,
>> + <0x8 0x80000000 0x40000000>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&key_volup &key_voldown &key_power>;
>> +
>> + volup-key {
>> + label = "Volume Up";
>> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
>
> Here and below: what is 0, why it's needed? Also, isn't it enough to
> have just "gpios", and remove interrupt*? Need to check "gpio-keys"
> driver and bindings doc, but AFAIR it should be enough to have just
> "gpios =" or just "interrupts =".

"gpios" is enough, because the IRQ line is derived from it. However
explicitly describing interrupts seems like a more detailed hardware
description.

>
>
>> + interrupt-parent = <&gpa1>;
>> + linux,code = <KEY_VOLUMEUP>;
>> + gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
>> + };
>> +
>> + voldown-key {
>> + label = "Volume Down";
>> + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
>> + interrupt-parent = <&gpa1>;
>> + linux,code = <KEY_VOLUMEDOWN>;
>> + gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
>> + };
>> +
>> + power-key {
>> + label = "Power";
>> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
>> + interrupt-parent = <&gpa1>;
>> + linux,code = <KEY_POWER>;
>> + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
>> + wakeup-source;
>> + };
>> + };
>> +};
>> +
>
> If there are some LEDs by chance on that board -- it might be useful
> to define those here with "gpio-leds" as well. Maybe even set some
> default trigger like "heartbeat".
>
>> +&serial_2 {
>> + status = "okay";
>> +};
>> +
>> +&pinctrl_alive {
>> + key_volup: key-volup-pins {
>> + samsung,pins = "gpa1-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>
> Maybe EXYNOS_PIN_FUNC_EINT is more self-explanatory? Just a suggestion though.
>
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>
> Here and below: please use EXYNOS5420_PIN_DRV_LV1 (means drive level = 1x).

But are these drive level 1x? The Exynos Auto v9 has different values
than older ones.

>
>> + };
>> +
>> + key_voldown: key-voldown-pins {
>> + samsung,pins = "gpa1-6";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + key_power: key-power-pins {
>> + samsung,pins = "gpa1-7";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
>> new file mode 100644
>> index 000000000000..8336b2e48858
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
>> @@ -0,0 +1,865 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
>> + *
>> + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
>> + * Copyright (c) 2021 Dávid Virág
>> + *
>> + * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
>> + * device tree nodes in this file.
>> + */
>> +
>> +#include <dt-bindings/pinctrl/samsung.h>
>
> You probably also need <dt-bindings/interrupt-controller/arm-gic.h>
> here for GIC_SPI definition.
>
>> +
>> +&pinctrl_alive {
>> + etc0: etc0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + etc1: etc1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>
> Hmm, what are these two? I can't find anything related in
> exynos7885.dtsi. If it's just some leftover from downstream vendor
> kernel -- please remove it.

This is a pinctrl DTSI file. What do you expect to find in
exynos7885.dtsi for these? Why removing them?
>
>> +
>> + gpa0: gpa0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + gpa1: gpa1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + gpa2: gpa2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpq0: gpq0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + sim1_det_gpio: sim1-det-gpio-pins {
>> + samsung,pins = "gpa2-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + sim0_det_gpio: sim0-det-gpio-pins {
>> + samsung,pins = "gpa2-6";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + speedy_bus: speedy-bus-pins {
>> + samsung,pins = "gpq0-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>
> Here and below: suggest using EXYNOS5420_PIN_DRV_LV* constants. Then
> stuff like "sd1_clk_fast_slew_rate_4x" is going to make sense.
>
>> + };
>> +
>> + /* UART_DEBUG */
>> + uart2_bus: uart2-bus-pins {
>> + samsung,pins = "gpq0-4", "gpq0-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +};
>> +
>> +&pinctrl_dispaud {
>> + gpb0: gpb0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb1: gpb1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb2: gpb2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + aud_codec_mclk: aud-codec-mclk-pins {
>> + samsung,pins = "gpb0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_codec_mclk_idle: aud-codec-mclk-idle-pins {
>> + samsung,pins = "gpb0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_codec_bus: aud-codec-bus-pins {
>> + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_codec_bus_idle: aud-codec-bus-idle-pins {
>> + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_loopback_bus: aud-loopback-bus-pins {
>> + samsung,pins = "gpb1-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_loopback_bus_idle: aud-loopback-bus-idle-pins {
>> + samsung,pins = "gpb1-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_fm_bus: aud-fm-bus-pins {
>> + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_fm_bus_idle: aud-fm-bus-idle-pins {
>> + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_spk_bus: aud-spk-bus-pins {
>> + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +
>> + aud_spk_bus_idle: aud-spk-bus-idle-pins {
>> + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + };
>> +};
>> +
>> +&pinctrl_fsys {
>> + gpf0: gpf0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf2: gpf2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf3: gpf3 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf4: gpf4 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + sd0_clk: sd0-clk-pins {
>> + samsung,pins = "gpf0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {
>> + samsung,pins = "gpf0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {
>> + samsung,pins = "gpf0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <1>;
>> + };
>> +
>> + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {
>> + samsung,pins = "gpf0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {
>> + samsung,pins = "gpf0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_cmd: sd0-cmd-pins {
>> + samsung,pins = "gpf0-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_rdqs: sd0-rdqs-pins {
>> + samsung,pins = "gpf0-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_bus1: sd0-bus-width1-pins {
>> + samsung,pins = "gpf2-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_bus4: sd0-bus-width4-pins {
>> + samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd0_bus8: sd0-bus-width8-pins {
>> + samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd1_clk: sd1-clk-pins {
>> + samsung,pins = "gpf3-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins {
>> + samsung,pins = "gpf3-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins {
>> + samsung,pins = "gpf3-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <1>;
>> + };
>> +
>> + sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins {
>> + samsung,pins = "gpf3-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins {
>> + samsung,pins = "gpf3-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd1_cmd: sd1-cmd-pins {
>> + samsung,pins = "gpf3-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd1_bus1: sd1-bus-width1-pins {
>> + samsung,pins = "gpf3-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd1_bus4: sd1-bus-width4-pins {
>> + samsung,pins = "gpf3-3", "gpf3-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd2_clk: sd2-clk-pins {
>> + samsung,pins = "gpf4-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
>> + samsung,pins = "gpf4-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
>> + samsung,pins = "gpf4-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <1>;
>> + };
>> +
>> + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
>> + samsung,pins = "gpf4-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
>> + samsung,pins = "gpf4-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <3>;
>> + };
>> +
>> + sd2_cmd: sd2-cmd-pins {
>> + samsung,pins = "gpf4-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd2_bus1: sd2-bus-width1-pins {
>> + samsung,pins = "gpf4-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <2>;
>> + };
>> +
>> + sd2_bus4: sd2-bus-width4-pins {
>> + samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <2>;
>> + };
>> +};
>> +
>> +&pinctrl_top {
>> + gpc0: gpc0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpc1: gpc1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpc2: gpc2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg0: gpg0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg1: gpg1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg2: gpg2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg3: gpg3 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg4: gpg4 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp0: gpp0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp1: gpp1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp2: gpp2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp3: gpp3 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp4: gpp4 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp5: gpp5 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp6: gpp6 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp7: gpp7 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpp8: gpp8 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + /* DECON TE */
>> + decon_f_te_on: decon_f_te_on-pins {
>> + samsung,pins = "gpc0-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>> + };
>> +
>> + decon_f_te_off: decon_f_te_off-pins {
>> + samsung,pins = "gpc0-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
>> + };
>> +
>> + hs_i2c0_bus: hs-i2c0-bus-pins {
>> + samsung,pins = "gpc1-1", "gpc1-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + hs_i2c1_bus: hs-i2c1-bus-pins {
>> + samsung,pins = "gpc1-3", "gpc1-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + hs_i2c2_bus: hs-i2c2-bus-pins {
>> + samsung,pins = "gpc1-5", "gpc1-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + hs_i2c3_bus: hs-i2c3-bus-pins {
>> + samsung,pins = "gpc1-7", "gpc1-6";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + /* USI0 UART */
>> + uart3_bus_single: uart3-bus-single-pins {
>> + samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + /* USI0 UART_HSI2C1 */
>> + uart3_bus_dual: uart3-bus-dual-pins {
>> + samsung,pins = "gpc2-1", "gpc2-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + /* USI0 HSI2C0 */
>> + hs_i2c4_bus: hs-i2c4-bus-pins {
>> + samsung,pins = "gpc2-1", "gpc2-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + /* USI0 HSI2C1 */
>> + hs_i2c5_bus: hs-i2c5-bus-pins {
>> + samsung,pins = "gpc2-3", "gpc2-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + /* USI0 SPI */
>> + spi2_bus: spi2-bus-pins {
>> + samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + spi2_cs: spi2-cs-pins {
>> + samsung,pins = "gpc2-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + /* USI1 UART */
>> + uart4_bus_single: uart4-bus-single-pins {
>> + samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + /* USI1 UART_HSI2C1*/
>> + uart4_bus_dual: uart4-bus-dual-pins {
>> + samsung,pins = "gpc2-5", "gpc2-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + /* USI1 HSI2C0 */
>> + hs_i2c6_bus: hs-i2c6-bus-pins {
>> + samsung,pins = "gpc2-5", "gpc2-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + /* USI1 HSI2C1 */
>> + hs_i2c7_bus: hs-i2c7-bus-pins {
>> + samsung,pins = "gpc2-7", "gpc2-6";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + /* USI1 SPI */
>> + spi3_bus: spi3-bus-pins {
>> + samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + spi3_cs: spi3-cs-pins {
>> + samsung,pins = "gpc2-6";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + fm_lna_en: fm-lna-en-pins {
>> + samsung,pins = "gpg0-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-val = <1>;
>> + };
>> +
>> + uart1_bus: uart1-bus-pins {
>> + samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + i2c7_bus: i2c7-bus-pins {
>> + samsung,pins = "gpg1-5", "gpg1-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + aud_dmic_on: aud-dmic-on-pins {
>> + samsung,pins = "gpg2-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
>> + samsung,pin-val = <1>;
>> + };
>> +
>> + aud_dmic_off: aud-dmic-off-pins {
>> + samsung,pins = "gpg2-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
>> + samsung,pin-val = <0>;
>> + };
>> +
>> + /* UART_HEALTH */
>> + uart0_bus: uart0-bus-pins {
>> + samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + i2c0_bus: i2c0-bus-pins {
>> + samsung,pins = "gpp1-1", "gpp1-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + i2c1_bus: i2c1-bus-pins {
>> + samsung,pins = "gpp1-3", "gpp1-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + i2c2_bus: i2c2-bus-pins {
>> + samsung,pins = "gpp2-1", "gpp2-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + i2c3_bus: i2c3-bus-pins {
>> + samsung,pins = "gpp3-1", "gpp3-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + i2c4_bus: i2c4-bus-pins {
>> + samsung,pins = "gpp4-1", "gpp4-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + i2c5_bus: i2c5-bus-pins {
>> + samsung,pins = "gpp4-3", "gpp4-2";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + i2c6_bus: i2c6-bus-pins {
>> + samsung,pins = "gpp4-5", "gpp4-4";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + /* SPI_ESE */
>> + spi0_bus: spi0-bus-pins {
>> + samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + spi0_cs: spi0-cs-pins {
>> + samsung,pins = "gpp5-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + /* SPI_FP */
>> + spi1_bus: spi1-bus-pins {
>> + samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + spi1_cs: spi1-cs-pins {
>> + samsung,pins = "gpp6-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + /* USI2 UART */
>> + uart5_bus_single: uart5-bus-single-pins {
>> + samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + /* USI2 UART_HSI2C1 */
>> + uart5_bus_dual: uart5-bus-dual-pins {
>> + samsung,pins = "gpp7-1", "gpp7-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + };
>> +
>> + /* USI2 HSI2C0 */
>> + hs_i2c8_bus: hs-i2c8-bus-pins {
>> + samsung,pins = "gpp7-1", "gpp7-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + /* USI2 HSI2C1 */
>> + hs_i2c9_bus: hs-i2c9-bus-pins {
>> + samsung,pins = "gpp8-1", "gpp8-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <0>;
>> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
>> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
>> + };
>> +
>> + /* USI2 SPI */
>> + spi4_bus: spi4-bus-pins {
>> + samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +
>> + spi4_cs: spi4-cs-pins {
>> + samsung,pins = "gpp8-0";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <0>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
>> new file mode 100644
>> index 000000000000..cc7a5ce0c103
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
>> @@ -0,0 +1,438 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Samsung Exynos7885 SoC device tree source
>> + *
>> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
>> + * Copyright (c) 2021 Dávid Virág
>> + *
>
> This line is not needed.
>
>> + */
>> +
>> +#include <dt-bindings/clock/exynos7885.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + compatible = "samsung,exynos7885";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> +
>> + interrupt-parent = <&gic>;
>> +
>> + aliases {
>> + pinctrl0 = &pinctrl_alive;
>> + pinctrl1 = &pinctrl_dispaud;
>> + pinctrl2 = &pinctrl_fsys;
>> + pinctrl3 = &pinctrl_top;
>> + };
>> +
>> + arm-a53-pmu {
>> + compatible = "arm,cortex-a53-pmu";
>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-affinity = <&cpu0>,
>> + <&cpu1>,
>> + <&cpu2>,
>> + <&cpu3>,
>> + <&cpu4>,
>> + <&cpu5>;
>
> Maybe have cpu0..cpu3 on one line, and cpu4..cpu5 on second line?

No, let's keep them aligned the same as interrupts. Easier to count
total lines :)

>
>> + };
>> +
>> + arm-a73-pmu {
>> + compatible = "arm,cortex-a73-pmu";
>> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-affinity = <&cpu6>,
>> + <&cpu7>;
>
> Both cpus can be on the same line here.

Same.

>
>> + };
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&cpu0>;
>> + };
>> + core1 {
>> + cpu = <&cpu1>;
>> + };
>> + core2 {
>> + cpu = <&cpu2>;
>> + };
>> + core3 {
>> + cpu = <&cpu3>;
>> + };
>> + core4 {
>> + cpu = <&cpu4>;
>> + };
>> + core5 {
>> + cpu = <&cpu5>;
>> + };
>> + };
>> +
>> + cluster1 {
>> + core0 {
>> + cpu = <&cpu6>;
>> + };
>> + core1 {
>> + cpu = <&cpu7>;
>> + };
>> + };
>> + };
>> +
>> + cpu0: cpu@100 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x100>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu1: cpu@101 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x101>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu2: cpu@102 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x102>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu3: cpu@103 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x103>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu4: cpu@200 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x200>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu5: cpu@201 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a53";
>> + reg = <0x201>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu6: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a73";
>> + reg = <0x0>;
>> + enable-method = "psci";
>> + };
>> +
>> + cpu7: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a73";
>> + reg = <0x1>;
>> + enable-method = "psci";
>> + };
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci";
>> + method = "smc";
>> + cpu_suspend = <0xc4000001>;
>> + cpu_off = <0x84000002>;
>> + cpu_on = <0xc4000003>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + /* Hypervisor Virtual Timer interrupt is not wired to GIC */
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>
> Can you please make it fit 80 characters per line?

This exceeds only by 9 characters and is more readable than split. Keep
it like this, please.

>
>> + };
>> +
>> + fixed-rate-clocks {
>> + oscclk: osc-clock {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <26000000>;
>
> Hmm, maybe it's better to set this clock frequency in board dts?

Good point, frequency should be in DTS.
>
>> + clock-output-names = "oscclk";
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x0 0x0 0x20000000>;
>> +
>> + chipid@10000000 {
>> + compatible = "samsung,exynos850-chipid";
>> + reg = <0x10000000 0x24>;
>> + };
>> +
>> + gic: interrupt-controller@12301000 {
>> + compatible = "arm,gic-400";
>> + #interrupt-cells = <3>;
>> + #address-cells = <0>;
>> + interrupt-controller;
>> + reg = <0x12301000 0x1000>,
>> + <0x12302000 0x2000>,
>> + <0x12304000 0x2000>,
>> + <0x12306000 0x2000>;
>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
>> + IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + cmu_peri: clock-controller@10010000 {
>> + compatible = "samsung,exynos7885-cmu-peri";
>> + reg = <0x10010000 0x8000>;
>> + #clock-cells = <1>;
>> +
>> + clocks = <&oscclk>,
>> + <&cmu_top CLK_DOUT_PERI_BUS>,
>> + <&cmu_top CLK_DOUT_PERI_SPI0>,
>> + <&cmu_top CLK_DOUT_PERI_SPI1>,
>> + <&cmu_top CLK_DOUT_PERI_UART0>,
>> + <&cmu_top CLK_DOUT_PERI_UART1>,
>> + <&cmu_top CLK_DOUT_PERI_UART2>,
>> + <&cmu_top CLK_DOUT_PERI_USI0>,
>> + <&cmu_top CLK_DOUT_PERI_USI1>,
>> + <&cmu_top CLK_DOUT_PERI_USI2>;
>> + clock-names = "oscclk",
>> + "dout_peri_bus",
>> + "dout_peri_spi0",
>> + "dout_peri_spi1",
>> + "dout_peri_uart0",
>> + "dout_peri_uart1",
>> + "dout_peri_uart2",
>> + "dout_peri_usi0",
>> + "dout_peri_usi1",
>> + "dout_peri_usi2";
>> + };
>> +
>> + cmu_core: clock-controller@12000000 {
>> + compatible = "samsung,exynos7885-cmu-core";
>> + reg = <0x12000000 0x8000>;
>> + #clock-cells = <1>;
>> +
>> + clocks = <&oscclk>,
>> + <&cmu_top CLK_DOUT_CORE_BUS>,
>> + <&cmu_top CLK_DOUT_CORE_CCI>,
>> + <&cmu_top CLK_DOUT_CORE_G3D>;
>> + clock-names = "oscclk", "dout_core_bus", "dout_core_cci", "dout_core_g3d";
>
> 80 characters per line, please. Also, please keep the style
> consistent: in cmu_peri you have each clock per line, here all clocks
> are on one line.

+1

>
>> + };
>> +
>> + cmu_top: clock-controller@12060000 {
>
> I'd move cmu_top above, to be the first CMU node.

No, let's keep them ordered by unit addresses, at least within each
group (so within clock controllers, pinctrl nodes etc). Ordering by
numbers is objective, while keeping order by some hierarchy requires
knowing this hierarchy and actually agreeing on it. :)

>
>> + compatible = "samsung,exynos7885-cmu-top";
>> + reg = <0x12060000 0x8000>;
>> + #clock-cells = <1>;
>> +
>> + clocks = <&oscclk>;
>> + clock-names = "oscclk";
>> + };
>> +
>> + pinctrl_alive: pinctrl@11cb0000 {
>> + compatible = "samsung,exynos7885-pinctrl";
>> + reg = <0x11cb0000 0x1000>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + wakeup-interrupt-controller {
>> + compatible = "samsung,exynos7-wakeup-eint";
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> + };
>> +
>> + pinctrl_dispaud: pinctrl@148f0000 {
>> + compatible = "samsung,exynos7885-pinctrl";
>> + reg = <0x148f0000 0x1000>;
>> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + pinctrl_fsys: pinctrl@13430000 {
>> + compatible = "samsung,exynos7885-pinctrl";
>> + reg = <0x13430000 0x1000>;
>> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + pinctrl_top: pinctrl@139b0000 {
>> + compatible = "samsung,exynos7885-pinctrl";
>> + reg = <0x139b0000 0x1000>;
>> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + pmu_system_controller: system-controller@11c80000 {
>> + compatible = "samsung,exynos7-pmu", "syscon";
>> + reg = <0x11c80000 0x10000>;
>> + };
>> +
>> + serial_0: serial@13800000 {
>> + compatible = "samsung,exynos5433-uart";
>> + reg = <0x13800000 0x100>;
>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
>> + <&cmu_peri CLK_GOUT_UART0_PCLK>;
>
> AFAIU, usually PCLK is a bus clock. Are you sure it should be UART baud clock?
>
>> + clock-names = "uart", "clk_uart_baud0";
>> + samsung,uart-fifosize = <64>;
>> + status = "disabled";
>> + };
>> +
>> + serial_1: serial@13810000 {
>> + compatible = "samsung,exynos5433-uart";
>> + reg = <0x13810000 0x100>;
>> + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart1_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
>> + <&cmu_peri CLK_GOUT_UART1_PCLK>;
>> + clock-names = "uart", "clk_uart_baud0";
>> + samsung,uart-fifosize = <256>;
>> + status = "disabled";
>> + };
>> +
>> + serial_2: serial@13820000 {
>> + compatible = "samsung,exynos5433-uart";
>> + reg = <0x13820000 0x100>;
>> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart2_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
>> + <&cmu_peri CLK_GOUT_UART2_PCLK>;
>> + clock-names = "uart", "clk_uart_baud0";
>> + samsung,uart-fifosize = <256>;
>> + status = "disabled";
>> + };
>> +
>> + i2c_0: i2c@13830000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x13830000 0x100>;
>> + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c0_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + i2c_1: i2c@13840000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x13840000 0x100>;
>> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c1_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + i2c_2: i2c@13850000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x13850000 0x100>;
>> + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c2_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + i2c_3: i2c@13860000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x13860000 0x100>;
>> + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c3_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + i2c_4: i2c@13870000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x13870000 0x100>;
>> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c4_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + i2c_5: i2c@13880000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x13880000 0x100>;
>> + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c5_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + i2c_6: i2c@13890000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x13890000 0x100>;
>> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c6_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + i2c_7: i2c@11cd0000 {
>> + compatible = "samsung,s3c2440-i2c";
>> + reg = <0x11cd0000 0x100>;
>> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c7_bus>;
>> + clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
>> + clock-names = "i2c";
>> + status = "disabled";
>> + };
>> + };
>> +};
>> +
>> +#include "exynos7885-pinctrl.dtsi"
>> +#include "arm/exynos-syscon-restart.dtsi"
>
> Have you verified both reboot and power off functions from this file?
> I guess if some doesn't work, it's better to avoid including this, but
> instead add corresponding sub-nodes into your pmu_sytem_controller.

Why open-coding same code work and including would not? Assuming that it
compiles, of course.

Best regards,
Krzysztof

2021-12-08 15:38:14

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On Wed, 8 Dec 2021 at 11:05, Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 07/12/2021 21:19, Sam Protsenko wrote:
> > On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
> >>
> >> Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy
> >> A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> >> Currently this includes some clock support, UART support, and I2C nodes.
> >>
> >> Signed-off-by: David Virag <[email protected]>
> >> ---
> >> Changes in v2:
> >> - Remove address-cells, and size-cells from dts, since they are
> >> already in the dtsi.
> >> - Lower case hex in memory node
> >> - Fix node names with underscore instead of hyphen
> >> - Fix line breaks
> >> - Fix "-key" missing from gpio keys node names
> >> - Use the form without "key" in gpio key labels on all keys
> >> - Suffix pin configuration node names with "-pins"
> >> - Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
> >> - Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
> >> - Add comment about Arm PMU
> >> - Rename "clock-oscclk" to "osc-clock"
> >> - Include exynos-syscon-restart.dtsi instead of rewriting its contents
> >>
> >> Changes in v3:
> >> - Fix typo (seperate -> separate)
> >>
> >> Changes in v4:
> >> - Fixed leading 0x in clock-controller nodes
> >> - Actually suffixed pin configuration node names with "-pins"
> >> - Seperated Cortex-A53 and Cortex-A73 PMU
> >>
> >> arch/arm64/boot/dts/exynos/Makefile | 7 +-
> >> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
> >> .../boot/dts/exynos/exynos7885-pinctrl.dtsi | 865 ++++++++++++++++++
> >> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 438 +++++++++
> >> 4 files changed, 1402 insertions(+), 3 deletions(-)
> >> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> >
> > Shouldn't SoC and board files be sent as two separate patches? For
> > example, I've checked exynos5433 and exynos7, SoC support
>
> Does not have to be. DTSI by itself cannot be even compiled, so keeping
> it a separate commit does not bring that much benefits. Especially if it
> is only one DTSI and one DTS.
>

Right, the only theoretical benefit I can see is reverting the board
dts in future, if another board already uses SoC dtsi. Or
cherry-picking in similar manner. Not my call though, for me it just
seems easier to review it that way, and more atomic.

> >
> >> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> >> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi
> >>
> >> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> >> index b41e86df0a84..c68c4ad577ac 100644
> >> --- a/arch/arm64/boot/dts/exynos/Makefile
> >> +++ b/arch/arm64/boot/dts/exynos/Makefile
> >> @@ -1,6 +1,7 @@
> >> # SPDX-License-Identifier: GPL-2.0
> >> dtb-$(CONFIG_ARCH_EXYNOS) += \
> >> - exynos5433-tm2.dtb \
> >> - exynos5433-tm2e.dtb \
> >> - exynos7-espresso.dtb \
> >> + exynos5433-tm2.dtb \
> >> + exynos5433-tm2e.dtb \
> >> + exynos7-espresso.dtb \
> >> + exynos7885-jackpotlte.dtb \
> >> exynosautov9-sadk.dtb
> >> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> >> new file mode 100644
> >> index 000000000000..f5941dc4c374
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> >> @@ -0,0 +1,95 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
> >> + *
> >> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> >> + * Copyright (c) 2021 Dávid Virág
> >> + *
> >
> > This line is not needed.
> >
> >> + */
> >> +
> >> +/dts-v1/;
> >
> > Suggest adding empty line here.
> >
> >> +#include "exynos7885.dtsi"
> >> +#include <dt-bindings/gpio/gpio.h>
> >> +#include <dt-bindings/input/input.h>
> >> +#include <dt-bindings/interrupt-controller/irq.h>
> >> +
> >> +/ {
> >> + model = "Samsung Galaxy A8 (2018)";
> >> + compatible = "samsung,jackpotlte", "samsung,exynos7885";
> >> + chassis-type = "handset";
> >> +
> >> + aliases {
> >> + serial0 = &serial_0;
> >> + serial1 = &serial_1;
> >> + serial2 = &serial_2;
> >
> > Suggestion: add aliases also for i2c nodes, to keep i2c instance
> > numbers fixed in run-time (e.g. in "i2cdetect -l" output).
> >
> >> + };
> >> +
> >> + chosen {
> >> + stdout-path = &serial_2;
> >> + };
> >> +
> >> + memory@80000000 {
> >> + device_type = "memory";
> >> + reg = <0x0 0x80000000 0x3da00000>,
> >> + <0x0 0xc0000000 0x40000000>,
> >> + <0x8 0x80000000 0x40000000>;
> >> + };
> >> +
> >> + gpio-keys {
> >> + compatible = "gpio-keys";
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&key_volup &key_voldown &key_power>;
> >> +
> >> + volup-key {
> >> + label = "Volume Up";
> >> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
> >
> > Here and below: what is 0, why it's needed? Also, isn't it enough to
> > have just "gpios", and remove interrupt*? Need to check "gpio-keys"
> > driver and bindings doc, but AFAIR it should be enough to have just
> > "gpios =" or just "interrupts =".
>
> "gpios" is enough, because the IRQ line is derived from it. However
> explicitly describing interrupts seems like a more detailed hardware
> description.
>

Frankly I don't think it's more detailed, it states the same thing
(gpa1 controller, line=5). Also not sure if level interrupt is needed
for a key, maybe edge type would be better. Also, I still don't
understand 0 in the end. Checking existing dts's, most of those only
define "gpios". I'd say having only "gpios" is more obvious, and will
work the same way. But that's not a strong preference on my side, just
think it's a bit misleading right now.

> >
> >
> >> + interrupt-parent = <&gpa1>;
> >> + linux,code = <KEY_VOLUMEUP>;
> >> + gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
> >> + };
> >> +
> >> + voldown-key {
> >> + label = "Volume Down";
> >> + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
> >> + interrupt-parent = <&gpa1>;
> >> + linux,code = <KEY_VOLUMEDOWN>;
> >> + gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
> >> + };
> >> +
> >> + power-key {
> >> + label = "Power";
> >> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
> >> + interrupt-parent = <&gpa1>;
> >> + linux,code = <KEY_POWER>;
> >> + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
> >> + wakeup-source;
> >> + };
> >> + };
> >> +};
> >> +
> >
> > If there are some LEDs by chance on that board -- it might be useful
> > to define those here with "gpio-leds" as well. Maybe even set some
> > default trigger like "heartbeat".
> >
> >> +&serial_2 {
> >> + status = "okay";
> >> +};
> >> +
> >> +&pinctrl_alive {
> >> + key_volup: key-volup-pins {
> >> + samsung,pins = "gpa1-5";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >
> > Maybe EXYNOS_PIN_FUNC_EINT is more self-explanatory? Just a suggestion though.
> >
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >
> > Here and below: please use EXYNOS5420_PIN_DRV_LV1 (means drive level = 1x).
>
> But are these drive level 1x? The Exynos Auto v9 has different values
> than older ones.
>

It should be that. One way to implicitly figure that out is to look at
nodes like "sd0_clk_fast_slew_rate_3x" and those pin-drv properties.
Also, in Exynos850 for most of domains those constants are
appropriate, that's why I mentioned that.

> >
> >> + };
> >> +
> >> + key_voldown: key-voldown-pins {
> >> + samsung,pins = "gpa1-6";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + key_power: key-power-pins {
> >> + samsung,pins = "gpa1-7";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +};
> >> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> >> new file mode 100644
> >> index 000000000000..8336b2e48858
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> >> @@ -0,0 +1,865 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
> >> + *
> >> + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> >> + * Copyright (c) 2021 Dávid Virág
> >> + *
> >> + * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
> >> + * device tree nodes in this file.
> >> + */
> >> +
> >> +#include <dt-bindings/pinctrl/samsung.h>
> >
> > You probably also need <dt-bindings/interrupt-controller/arm-gic.h>
> > here for GIC_SPI definition.
> >
> >> +
> >> +&pinctrl_alive {
> >> + etc0: etc0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + etc1: etc1 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >
> > Hmm, what are these two? I can't find anything related in
> > exynos7885.dtsi. If it's just some leftover from downstream vendor
> > kernel -- please remove it.
>
> This is a pinctrl DTSI file. What do you expect to find in
> exynos7885.dtsi for these? Why removing them?

etc0 and etc1 nodes are defined as gpio-controller and
interrupt-controller. So "compatible" should be provided somewhere for
those nodes. For example, for "gpa0" node below you can find its
compatible in exynos7885.dtsi. Right now I don't understand how those
etc0 and etc1 can be used at all. So maybe it's better to just remove
those? Those are not used anywhere and we probably don't even know
what those nodes represent. My point is, if those are actually some
leftovers from vendor kernel and those are not going to be used (and I
don't see how, without "compatible"), then we probablly better off
without those.

> >
> >> +
> >> + gpa0: gpa0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + interrupt-parent = <&gic>;
> >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +
> >> + gpa1: gpa1 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <3>;
> >> + interrupt-parent = <&gic>;
> >> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +
> >> + gpa2: gpa2 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpq0: gpq0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + sim1_det_gpio: sim1-det-gpio-pins {
> >> + samsung,pins = "gpa2-5";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + sim0_det_gpio: sim0-det-gpio-pins {
> >> + samsung,pins = "gpa2-6";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + speedy_bus: speedy-bus-pins {
> >> + samsung,pins = "gpq0-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >
> > Here and below: suggest using EXYNOS5420_PIN_DRV_LV* constants. Then
> > stuff like "sd1_clk_fast_slew_rate_4x" is going to make sense.
> >
> >> + };
> >> +
> >> + /* UART_DEBUG */
> >> + uart2_bus: uart2-bus-pins {
> >> + samsung,pins = "gpq0-4", "gpq0-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +};
> >> +
> >> +&pinctrl_dispaud {
> >> + gpb0: gpb0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpb1: gpb1 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpb2: gpb2 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + aud_codec_mclk: aud-codec-mclk-pins {
> >> + samsung,pins = "gpb0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_codec_mclk_idle: aud-codec-mclk-idle-pins {
> >> + samsung,pins = "gpb0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_codec_bus: aud-codec-bus-pins {
> >> + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_codec_bus_idle: aud-codec-bus-idle-pins {
> >> + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_loopback_bus: aud-loopback-bus-pins {
> >> + samsung,pins = "gpb1-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_loopback_bus_idle: aud-loopback-bus-idle-pins {
> >> + samsung,pins = "gpb1-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_fm_bus: aud-fm-bus-pins {
> >> + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_fm_bus_idle: aud-fm-bus-idle-pins {
> >> + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_spk_bus: aud-spk-bus-pins {
> >> + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +
> >> + aud_spk_bus_idle: aud-spk-bus-idle-pins {
> >> + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + };
> >> +};
> >> +
> >> +&pinctrl_fsys {
> >> + gpf0: gpf0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpf2: gpf2 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpf3: gpf3 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpf4: gpf4 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + sd0_clk: sd0-clk-pins {
> >> + samsung,pins = "gpf0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins {
> >> + samsung,pins = "gpf0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins {
> >> + samsung,pins = "gpf0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <1>;
> >> + };
> >> +
> >> + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins {
> >> + samsung,pins = "gpf0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins {
> >> + samsung,pins = "gpf0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd0_cmd: sd0-cmd-pins {
> >> + samsung,pins = "gpf0-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd0_rdqs: sd0-rdqs-pins {
> >> + samsung,pins = "gpf0-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd0_bus1: sd0-bus-width1-pins {
> >> + samsung,pins = "gpf2-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd0_bus4: sd0-bus-width4-pins {
> >> + samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd0_bus8: sd0-bus-width8-pins {
> >> + samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd1_clk: sd1-clk-pins {
> >> + samsung,pins = "gpf3-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins {
> >> + samsung,pins = "gpf3-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins {
> >> + samsung,pins = "gpf3-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <1>;
> >> + };
> >> +
> >> + sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins {
> >> + samsung,pins = "gpf3-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins {
> >> + samsung,pins = "gpf3-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd1_cmd: sd1-cmd-pins {
> >> + samsung,pins = "gpf3-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd1_bus1: sd1-bus-width1-pins {
> >> + samsung,pins = "gpf3-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd1_bus4: sd1-bus-width4-pins {
> >> + samsung,pins = "gpf3-3", "gpf3-5";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd2_clk: sd2-clk-pins {
> >> + samsung,pins = "gpf4-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins {
> >> + samsung,pins = "gpf4-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins {
> >> + samsung,pins = "gpf4-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <1>;
> >> + };
> >> +
> >> + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins {
> >> + samsung,pins = "gpf4-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins {
> >> + samsung,pins = "gpf4-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <3>;
> >> + };
> >> +
> >> + sd2_cmd: sd2-cmd-pins {
> >> + samsung,pins = "gpf4-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd2_bus1: sd2-bus-width1-pins {
> >> + samsung,pins = "gpf4-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +
> >> + sd2_bus4: sd2-bus-width4-pins {
> >> + samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <2>;
> >> + };
> >> +};
> >> +
> >> +&pinctrl_top {
> >> + gpc0: gpc0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpc1: gpc1 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpc2: gpc2 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpg0: gpg0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpg1: gpg1 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpg2: gpg2 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpg3: gpg3 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpg4: gpg4 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp0: gpp0 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp1: gpp1 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp2: gpp2 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp3: gpp3 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp4: gpp4 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp5: gpp5 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp6: gpp6 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp7: gpp7 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + gpp8: gpp8 {
> >> + gpio-controller;
> >> + #gpio-cells = <2>;
> >> +
> >> + interrupt-controller;
> >> + #interrupt-cells = <2>;
> >> + };
> >> +
> >> + /* DECON TE */
> >> + decon_f_te_on: decon_f_te_on-pins {
> >> + samsung,pins = "gpc0-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >> + };
> >> +
> >> + decon_f_te_off: decon_f_te_off-pins {
> >> + samsung,pins = "gpc0-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
> >> + };
> >> +
> >> + hs_i2c0_bus: hs-i2c0-bus-pins {
> >> + samsung,pins = "gpc1-1", "gpc1-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + hs_i2c1_bus: hs-i2c1-bus-pins {
> >> + samsung,pins = "gpc1-3", "gpc1-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + hs_i2c2_bus: hs-i2c2-bus-pins {
> >> + samsung,pins = "gpc1-5", "gpc1-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + hs_i2c3_bus: hs-i2c3-bus-pins {
> >> + samsung,pins = "gpc1-7", "gpc1-6";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + /* USI0 UART */
> >> + uart3_bus_single: uart3-bus-single-pins {
> >> + samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + /* USI0 UART_HSI2C1 */
> >> + uart3_bus_dual: uart3-bus-dual-pins {
> >> + samsung,pins = "gpc2-1", "gpc2-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + /* USI0 HSI2C0 */
> >> + hs_i2c4_bus: hs-i2c4-bus-pins {
> >> + samsung,pins = "gpc2-1", "gpc2-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + /* USI0 HSI2C1 */
> >> + hs_i2c5_bus: hs-i2c5-bus-pins {
> >> + samsung,pins = "gpc2-3", "gpc2-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + /* USI0 SPI */
> >> + spi2_bus: spi2-bus-pins {
> >> + samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + spi2_cs: spi2-cs-pins {
> >> + samsung,pins = "gpc2-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + /* USI1 UART */
> >> + uart4_bus_single: uart4-bus-single-pins {
> >> + samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + /* USI1 UART_HSI2C1*/
> >> + uart4_bus_dual: uart4-bus-dual-pins {
> >> + samsung,pins = "gpc2-5", "gpc2-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + /* USI1 HSI2C0 */
> >> + hs_i2c6_bus: hs-i2c6-bus-pins {
> >> + samsung,pins = "gpc2-5", "gpc2-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + /* USI1 HSI2C1 */
> >> + hs_i2c7_bus: hs-i2c7-bus-pins {
> >> + samsung,pins = "gpc2-7", "gpc2-6";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + /* USI1 SPI */
> >> + spi3_bus: spi3-bus-pins {
> >> + samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + spi3_cs: spi3-cs-pins {
> >> + samsung,pins = "gpc2-6";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + fm_lna_en: fm-lna-en-pins {
> >> + samsung,pins = "gpg0-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-val = <1>;
> >> + };
> >> +
> >> + uart1_bus: uart1-bus-pins {
> >> + samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + i2c7_bus: i2c7-bus-pins {
> >> + samsung,pins = "gpg1-5", "gpg1-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + aud_dmic_on: aud-dmic-on-pins {
> >> + samsung,pins = "gpg2-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> >> + samsung,pin-val = <1>;
> >> + };
> >> +
> >> + aud_dmic_off: aud-dmic-off-pins {
> >> + samsung,pins = "gpg2-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> >> + samsung,pin-val = <0>;
> >> + };
> >> +
> >> + /* UART_HEALTH */
> >> + uart0_bus: uart0-bus-pins {
> >> + samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + i2c0_bus: i2c0-bus-pins {
> >> + samsung,pins = "gpp1-1", "gpp1-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + i2c1_bus: i2c1-bus-pins {
> >> + samsung,pins = "gpp1-3", "gpp1-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_PREV>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + i2c2_bus: i2c2-bus-pins {
> >> + samsung,pins = "gpp2-1", "gpp2-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + i2c3_bus: i2c3-bus-pins {
> >> + samsung,pins = "gpp3-1", "gpp3-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + i2c4_bus: i2c4-bus-pins {
> >> + samsung,pins = "gpp4-1", "gpp4-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + i2c5_bus: i2c5-bus-pins {
> >> + samsung,pins = "gpp4-3", "gpp4-2";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + i2c6_bus: i2c6-bus-pins {
> >> + samsung,pins = "gpp4-5", "gpp4-4";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + /* SPI_ESE */
> >> + spi0_bus: spi0-bus-pins {
> >> + samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + spi0_cs: spi0-cs-pins {
> >> + samsung,pins = "gpp5-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + /* SPI_FP */
> >> + spi1_bus: spi1-bus-pins {
> >> + samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + spi1_cs: spi1-cs-pins {
> >> + samsung,pins = "gpp6-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + /* USI2 UART */
> >> + uart5_bus_single: uart5-bus-single-pins {
> >> + samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + /* USI2 UART_HSI2C1 */
> >> + uart5_bus_dual: uart5-bus-dual-pins {
> >> + samsung,pins = "gpp7-1", "gpp7-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + };
> >> +
> >> + /* USI2 HSI2C0 */
> >> + hs_i2c8_bus: hs-i2c8-bus-pins {
> >> + samsung,pins = "gpp7-1", "gpp7-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + /* USI2 HSI2C1 */
> >> + hs_i2c9_bus: hs-i2c9-bus-pins {
> >> + samsung,pins = "gpp8-1", "gpp8-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >> + samsung,pin-drv = <0>;
> >> + samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT1>;
> >> + samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_UP>;
> >> + };
> >> +
> >> + /* USI2 SPI */
> >> + spi4_bus: spi4-bus-pins {
> >> + samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +
> >> + spi4_cs: spi4-cs-pins {
> >> + samsung,pins = "gpp8-0";
> >> + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
> >> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> >> + samsung,pin-drv = <0>;
> >> + };
> >> +};
> >> diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> >> new file mode 100644
> >> index 000000000000..cc7a5ce0c103
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
> >> @@ -0,0 +1,438 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Samsung Exynos7885 SoC device tree source
> >> + *
> >> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> >> + * Copyright (c) 2021 Dávid Virág
> >> + *
> >
> > This line is not needed.
> >
> >> + */
> >> +
> >> +#include <dt-bindings/clock/exynos7885.h>
> >> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +
> >> +/ {
> >> + compatible = "samsung,exynos7885";
> >> + #address-cells = <2>;
> >> + #size-cells = <1>;
> >> +
> >> + interrupt-parent = <&gic>;
> >> +
> >> + aliases {
> >> + pinctrl0 = &pinctrl_alive;
> >> + pinctrl1 = &pinctrl_dispaud;
> >> + pinctrl2 = &pinctrl_fsys;
> >> + pinctrl3 = &pinctrl_top;
> >> + };
> >> +
> >> + arm-a53-pmu {
> >> + compatible = "arm,cortex-a53-pmu";
> >> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
> >> + interrupt-affinity = <&cpu0>,
> >> + <&cpu1>,
> >> + <&cpu2>,
> >> + <&cpu3>,
> >> + <&cpu4>,
> >> + <&cpu5>;
> >
> > Maybe have cpu0..cpu3 on one line, and cpu4..cpu5 on second line?
>
> No, let's keep them aligned the same as interrupts. Easier to count
> total lines :)
>
> >
> >> + };
> >> +
> >> + arm-a73-pmu {
> >> + compatible = "arm,cortex-a73-pmu";
> >> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> >> + interrupt-affinity = <&cpu6>,
> >> + <&cpu7>;
> >
> > Both cpus can be on the same line here.
>
> Same.
>
> >
> >> + };
> >> +
> >> + cpus {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + cpu-map {
> >> + cluster0 {
> >> + core0 {
> >> + cpu = <&cpu0>;
> >> + };
> >> + core1 {
> >> + cpu = <&cpu1>;
> >> + };
> >> + core2 {
> >> + cpu = <&cpu2>;
> >> + };
> >> + core3 {
> >> + cpu = <&cpu3>;
> >> + };
> >> + core4 {
> >> + cpu = <&cpu4>;
> >> + };
> >> + core5 {
> >> + cpu = <&cpu5>;
> >> + };
> >> + };
> >> +
> >> + cluster1 {
> >> + core0 {
> >> + cpu = <&cpu6>;
> >> + };
> >> + core1 {
> >> + cpu = <&cpu7>;
> >> + };
> >> + };
> >> + };
> >> +
> >> + cpu0: cpu@100 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a53";
> >> + reg = <0x100>;
> >> + enable-method = "psci";
> >> + };
> >> +
> >> + cpu1: cpu@101 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a53";
> >> + reg = <0x101>;
> >> + enable-method = "psci";
> >> + };
> >> +
> >> + cpu2: cpu@102 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a53";
> >> + reg = <0x102>;
> >> + enable-method = "psci";
> >> + };
> >> +
> >> + cpu3: cpu@103 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a53";
> >> + reg = <0x103>;
> >> + enable-method = "psci";
> >> + };
> >> +
> >> + cpu4: cpu@200 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a53";
> >> + reg = <0x200>;
> >> + enable-method = "psci";
> >> + };
> >> +
> >> + cpu5: cpu@201 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a53";
> >> + reg = <0x201>;
> >> + enable-method = "psci";
> >> + };
> >> +
> >> + cpu6: cpu@0 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a73";
> >> + reg = <0x0>;
> >> + enable-method = "psci";
> >> + };
> >> +
> >> + cpu7: cpu@1 {
> >> + device_type = "cpu";
> >> + compatible = "arm,cortex-a73";
> >> + reg = <0x1>;
> >> + enable-method = "psci";
> >> + };
> >> + };
> >> +
> >> + psci {
> >> + compatible = "arm,psci";
> >> + method = "smc";
> >> + cpu_suspend = <0xc4000001>;
> >> + cpu_off = <0x84000002>;
> >> + cpu_on = <0xc4000003>;
> >> + };
> >> +
> >> + timer {
> >> + compatible = "arm,armv8-timer";
> >> + /* Hypervisor Virtual Timer interrupt is not wired to GIC */
> >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> >
> > Can you please make it fit 80 characters per line?
>
> This exceeds only by 9 characters and is more readable than split. Keep
> it like this, please.
>
> >
> >> + };
> >> +
> >> + fixed-rate-clocks {
> >> + oscclk: osc-clock {
> >> + compatible = "fixed-clock";
> >> + #clock-cells = <0>;
> >> + clock-frequency = <26000000>;
> >
> > Hmm, maybe it's better to set this clock frequency in board dts?
>
> Good point, frequency should be in DTS.
> >
> >> + clock-output-names = "oscclk";
> >> + };
> >> + };
> >> +
> >> + soc: soc@0 {
> >> + compatible = "simple-bus";
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + ranges = <0x0 0x0 0x0 0x20000000>;
> >> +
> >> + chipid@10000000 {
> >> + compatible = "samsung,exynos850-chipid";
> >> + reg = <0x10000000 0x24>;
> >> + };
> >> +
> >> + gic: interrupt-controller@12301000 {
> >> + compatible = "arm,gic-400";
> >> + #interrupt-cells = <3>;
> >> + #address-cells = <0>;
> >> + interrupt-controller;
> >> + reg = <0x12301000 0x1000>,
> >> + <0x12302000 0x2000>,
> >> + <0x12304000 0x2000>,
> >> + <0x12306000 0x2000>;
> >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
> >> + IRQ_TYPE_LEVEL_HIGH)>;
> >> + };
> >> +
> >> + cmu_peri: clock-controller@10010000 {
> >> + compatible = "samsung,exynos7885-cmu-peri";
> >> + reg = <0x10010000 0x8000>;
> >> + #clock-cells = <1>;
> >> +
> >> + clocks = <&oscclk>,
> >> + <&cmu_top CLK_DOUT_PERI_BUS>,
> >> + <&cmu_top CLK_DOUT_PERI_SPI0>,
> >> + <&cmu_top CLK_DOUT_PERI_SPI1>,
> >> + <&cmu_top CLK_DOUT_PERI_UART0>,
> >> + <&cmu_top CLK_DOUT_PERI_UART1>,
> >> + <&cmu_top CLK_DOUT_PERI_UART2>,
> >> + <&cmu_top CLK_DOUT_PERI_USI0>,
> >> + <&cmu_top CLK_DOUT_PERI_USI1>,
> >> + <&cmu_top CLK_DOUT_PERI_USI2>;
> >> + clock-names = "oscclk",
> >> + "dout_peri_bus",
> >> + "dout_peri_spi0",
> >> + "dout_peri_spi1",
> >> + "dout_peri_uart0",
> >> + "dout_peri_uart1",
> >> + "dout_peri_uart2",
> >> + "dout_peri_usi0",
> >> + "dout_peri_usi1",
> >> + "dout_peri_usi2";
> >> + };
> >> +
> >> + cmu_core: clock-controller@12000000 {
> >> + compatible = "samsung,exynos7885-cmu-core";
> >> + reg = <0x12000000 0x8000>;
> >> + #clock-cells = <1>;
> >> +
> >> + clocks = <&oscclk>,
> >> + <&cmu_top CLK_DOUT_CORE_BUS>,
> >> + <&cmu_top CLK_DOUT_CORE_CCI>,
> >> + <&cmu_top CLK_DOUT_CORE_G3D>;
> >> + clock-names = "oscclk", "dout_core_bus", "dout_core_cci", "dout_core_g3d";
> >
> > 80 characters per line, please. Also, please keep the style
> > consistent: in cmu_peri you have each clock per line, here all clocks
> > are on one line.
>
> +1
>
> >
> >> + };
> >> +
> >> + cmu_top: clock-controller@12060000 {
> >
> > I'd move cmu_top above, to be the first CMU node.
>
> No, let's keep them ordered by unit addresses, at least within each
> group (so within clock controllers, pinctrl nodes etc). Ordering by
> numbers is objective, while keeping order by some hierarchy requires
> knowing this hierarchy and actually agreeing on it. :)
>
> >
> >> + compatible = "samsung,exynos7885-cmu-top";
> >> + reg = <0x12060000 0x8000>;
> >> + #clock-cells = <1>;
> >> +
> >> + clocks = <&oscclk>;
> >> + clock-names = "oscclk";
> >> + };
> >> +
> >> + pinctrl_alive: pinctrl@11cb0000 {
> >> + compatible = "samsung,exynos7885-pinctrl";
> >> + reg = <0x11cb0000 0x1000>;
> >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> >> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> >> +
> >> + wakeup-interrupt-controller {
> >> + compatible = "samsung,exynos7-wakeup-eint";
> >> + interrupt-parent = <&gic>;
> >> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> + };
> >> +
> >> + pinctrl_dispaud: pinctrl@148f0000 {
> >> + compatible = "samsung,exynos7885-pinctrl";
> >> + reg = <0x148f0000 0x1000>;
> >> + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +
> >> + pinctrl_fsys: pinctrl@13430000 {
> >> + compatible = "samsung,exynos7885-pinctrl";
> >> + reg = <0x13430000 0x1000>;
> >> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +
> >> + pinctrl_top: pinctrl@139b0000 {
> >> + compatible = "samsung,exynos7885-pinctrl";
> >> + reg = <0x139b0000 0x1000>;
> >> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> >> + };
> >> +
> >> + pmu_system_controller: system-controller@11c80000 {
> >> + compatible = "samsung,exynos7-pmu", "syscon";
> >> + reg = <0x11c80000 0x10000>;
> >> + };
> >> +
> >> + serial_0: serial@13800000 {
> >> + compatible = "samsung,exynos5433-uart";
> >> + reg = <0x13800000 0x100>;
> >> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&uart0_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
> >> + <&cmu_peri CLK_GOUT_UART0_PCLK>;
> >
> > AFAIU, usually PCLK is a bus clock. Are you sure it should be UART baud clock?
> >
> >> + clock-names = "uart", "clk_uart_baud0";
> >> + samsung,uart-fifosize = <64>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + serial_1: serial@13810000 {
> >> + compatible = "samsung,exynos5433-uart";
> >> + reg = <0x13810000 0x100>;
> >> + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&uart1_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
> >> + <&cmu_peri CLK_GOUT_UART1_PCLK>;
> >> + clock-names = "uart", "clk_uart_baud0";
> >> + samsung,uart-fifosize = <256>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + serial_2: serial@13820000 {
> >> + compatible = "samsung,exynos5433-uart";
> >> + reg = <0x13820000 0x100>;
> >> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&uart2_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
> >> + <&cmu_peri CLK_GOUT_UART2_PCLK>;
> >> + clock-names = "uart", "clk_uart_baud0";
> >> + samsung,uart-fifosize = <256>;
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_0: i2c@13830000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x13830000 0x100>;
> >> + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c0_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_1: i2c@13840000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x13840000 0x100>;
> >> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c1_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_2: i2c@13850000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x13850000 0x100>;
> >> + interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c2_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_3: i2c@13860000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x13860000 0x100>;
> >> + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c3_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_4: i2c@13870000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x13870000 0x100>;
> >> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c4_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_5: i2c@13880000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x13880000 0x100>;
> >> + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c5_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_6: i2c@13890000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x13890000 0x100>;
> >> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c6_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> +
> >> + i2c_7: i2c@11cd0000 {
> >> + compatible = "samsung,s3c2440-i2c";
> >> + reg = <0x11cd0000 0x100>;
> >> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&i2c7_bus>;
> >> + clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
> >> + clock-names = "i2c";
> >> + status = "disabled";
> >> + };
> >> + };
> >> +};
> >> +
> >> +#include "exynos7885-pinctrl.dtsi"
> >> +#include "arm/exynos-syscon-restart.dtsi"
> >
> > Have you verified both reboot and power off functions from this file?
> > I guess if some doesn't work, it's better to avoid including this, but
> > instead add corresponding sub-nodes into your pmu_sytem_controller.
>
> Why open-coding same code work and including would not? Assuming that it
> compiles, of course.
>

For example, in case of Exynos850 the "power off" node from this file
wasn't suitable. In that case it's not worth including it. But David
already confirmed both work fine for him, so it doesn't matter
anymore.

>
> Best regards,
> Krzysztof

2021-12-08 16:29:10

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On 08/12/2021 16:37, Sam Protsenko wrote:
> On Wed, 8 Dec 2021 at 11:05, Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> On 07/12/2021 21:19, Sam Protsenko wrote:
>>> On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
>>>>
>>>> Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy
>>>> A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
>>>> Currently this includes some clock support, UART support, and I2C nodes.
>>>>
>>>> Signed-off-by: David Virag <[email protected]>
>>>> ---
>>>> Changes in v2:
>>>> - Remove address-cells, and size-cells from dts, since they are
>>>> already in the dtsi.
>>>> - Lower case hex in memory node
>>>> - Fix node names with underscore instead of hyphen
>>>> - Fix line breaks
>>>> - Fix "-key" missing from gpio keys node names
>>>> - Use the form without "key" in gpio key labels on all keys
>>>> - Suffix pin configuration node names with "-pins"
>>>> - Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
>>>> - Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
>>>> - Add comment about Arm PMU
>>>> - Rename "clock-oscclk" to "osc-clock"
>>>> - Include exynos-syscon-restart.dtsi instead of rewriting its contents
>>>>
>>>> Changes in v3:
>>>> - Fix typo (seperate -> separate)
>>>>
>>>> Changes in v4:
>>>> - Fixed leading 0x in clock-controller nodes
>>>> - Actually suffixed pin configuration node names with "-pins"
>>>> - Seperated Cortex-A53 and Cortex-A73 PMU
>>>>
>>>> arch/arm64/boot/dts/exynos/Makefile | 7 +-
>>>> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
>>>> .../boot/dts/exynos/exynos7885-pinctrl.dtsi | 865 ++++++++++++++++++
>>>> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 438 +++++++++
>>>> 4 files changed, 1402 insertions(+), 3 deletions(-)
>>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
>>>
>>> Shouldn't SoC and board files be sent as two separate patches? For
>>> example, I've checked exynos5433 and exynos7, SoC support
>>
>> Does not have to be. DTSI by itself cannot be even compiled, so keeping
>> it a separate commit does not bring that much benefits. Especially if it
>> is only one DTSI and one DTS.
>>
>
> Right, the only theoretical benefit I can see is reverting the board
> dts in future, if another board already uses SoC dtsi. Or
> cherry-picking in similar manner. Not my call though, for me it just
> seems easier to review it that way, and more atomic.
>
>>>
>>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
>>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
>>>> index b41e86df0a84..c68c4ad577ac 100644
>>>> --- a/arch/arm64/boot/dts/exynos/Makefile
>>>> +++ b/arch/arm64/boot/dts/exynos/Makefile
>>>> @@ -1,6 +1,7 @@
>>>> # SPDX-License-Identifier: GPL-2.0
>>>> dtb-$(CONFIG_ARCH_EXYNOS) += \
>>>> - exynos5433-tm2.dtb \
>>>> - exynos5433-tm2e.dtb \
>>>> - exynos7-espresso.dtb \
>>>> + exynos5433-tm2.dtb \
>>>> + exynos5433-tm2e.dtb \
>>>> + exynos7-espresso.dtb \
>>>> + exynos7885-jackpotlte.dtb \
>>>> exynosautov9-sadk.dtb
>>>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
>>>> new file mode 100644
>>>> index 000000000000..f5941dc4c374
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
>>>> @@ -0,0 +1,95 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
>>>> + *
>>>> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
>>>> + * Copyright (c) 2021 Dávid Virág
>>>> + *
>>>
>>> This line is not needed.
>>>
>>>> + */
>>>> +
>>>> +/dts-v1/;
>>>
>>> Suggest adding empty line here.
>>>
>>>> +#include "exynos7885.dtsi"
>>>> +#include <dt-bindings/gpio/gpio.h>
>>>> +#include <dt-bindings/input/input.h>
>>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>>> +
>>>> +/ {
>>>> + model = "Samsung Galaxy A8 (2018)";
>>>> + compatible = "samsung,jackpotlte", "samsung,exynos7885";
>>>> + chassis-type = "handset";
>>>> +
>>>> + aliases {
>>>> + serial0 = &serial_0;
>>>> + serial1 = &serial_1;
>>>> + serial2 = &serial_2;
>>>
>>> Suggestion: add aliases also for i2c nodes, to keep i2c instance
>>> numbers fixed in run-time (e.g. in "i2cdetect -l" output).
>>>
>>>> + };
>>>> +
>>>> + chosen {
>>>> + stdout-path = &serial_2;
>>>> + };
>>>> +
>>>> + memory@80000000 {
>>>> + device_type = "memory";
>>>> + reg = <0x0 0x80000000 0x3da00000>,
>>>> + <0x0 0xc0000000 0x40000000>,
>>>> + <0x8 0x80000000 0x40000000>;
>>>> + };
>>>> +
>>>> + gpio-keys {
>>>> + compatible = "gpio-keys";
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&key_volup &key_voldown &key_power>;
>>>> +
>>>> + volup-key {
>>>> + label = "Volume Up";
>>>> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
>>>
>>> Here and below: what is 0, why it's needed? Also, isn't it enough to
>>> have just "gpios", and remove interrupt*? Need to check "gpio-keys"
>>> driver and bindings doc, but AFAIR it should be enough to have just
>>> "gpios =" or just "interrupts =".
>>
>> "gpios" is enough, because the IRQ line is derived from it. However
>> explicitly describing interrupts seems like a more detailed hardware
>> description.
>>
>
> Frankly I don't think it's more detailed, it states the same thing
> (gpa1 controller, line=5).

It states that interrupt is exactly the same as GPIO which not
explicitly coming from bindings.

> Also not sure if level interrupt is needed
> for a key, maybe edge type would be better. Also, I still don't
> understand 0 in the end.

Indeed this part looks not correct - the leve and 0 at the end. In such
case better to skip it then define misleading property.

> Checking existing dts's, most of those only
> define "gpios". I'd say having only "gpios" is more obvious, and will
> work the same way. But that's not a strong preference on my side, just
> think it's a bit misleading right now.

Yep.

>
>>>
>>>
>>>> + interrupt-parent = <&gpa1>;
>>>> + linux,code = <KEY_VOLUMEUP>;
>>>> + gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
>>>> + };
>>>> +
>>>> + voldown-key {
>>>> + label = "Volume Down";
>>>> + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
>>>> + interrupt-parent = <&gpa1>;
>>>> + linux,code = <KEY_VOLUMEDOWN>;
>>>> + gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
>>>> + };
>>>> +
>>>> + power-key {
>>>> + label = "Power";
>>>> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
>>>> + interrupt-parent = <&gpa1>;
>>>> + linux,code = <KEY_POWER>;
>>>> + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
>>>> + wakeup-source;
>>>> + };
>>>> + };
>>>> +};
>>>> +
>>>
>>> If there are some LEDs by chance on that board -- it might be useful
>>> to define those here with "gpio-leds" as well. Maybe even set some
>>> default trigger like "heartbeat".
>>>
>>>> +&serial_2 {
>>>> + status = "okay";
>>>> +};
>>>> +
>>>> +&pinctrl_alive {
>>>> + key_volup: key-volup-pins {
>>>> + samsung,pins = "gpa1-5";
>>>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>>>
>>> Maybe EXYNOS_PIN_FUNC_EINT is more self-explanatory? Just a suggestion though.
>>>
>>>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>>>> + samsung,pin-drv = <0>;
>>>
>>> Here and below: please use EXYNOS5420_PIN_DRV_LV1 (means drive level = 1x).
>>
>> But are these drive level 1x? The Exynos Auto v9 has different values
>> than older ones.
>>
>
> It should be that. One way to implicitly figure that out is to look at
> nodes like "sd0_clk_fast_slew_rate_3x" and those pin-drv properties.
> Also, in Exynos850 for most of domains those constants are
> appropriate, that's why I mentioned that.

Then I agree, use existing macros. The macros can be skipped for cases
when the meaning is different.

>
>>>
>>>> + };
>>>> +
>>>> + key_voldown: key-voldown-pins {
>>>> + samsung,pins = "gpa1-6";
>>>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>>>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>>>> + samsung,pin-drv = <0>;
>>>> + };
>>>> +
>>>> + key_power: key-power-pins {
>>>> + samsung,pins = "gpa1-7";
>>>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
>>>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>>>> + samsung,pin-drv = <0>;
>>>> + };
>>>> +};
>>>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
>>>> new file mode 100644
>>>> index 000000000000..8336b2e48858
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
>>>> @@ -0,0 +1,865 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
>>>> + *
>>>> + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
>>>> + * Copyright (c) 2021 Dávid Virág
>>>> + *
>>>> + * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
>>>> + * device tree nodes in this file.
>>>> + */
>>>> +
>>>> +#include <dt-bindings/pinctrl/samsung.h>
>>>
>>> You probably also need <dt-bindings/interrupt-controller/arm-gic.h>
>>> here for GIC_SPI definition.
>>>
>>>> +
>>>> +&pinctrl_alive {
>>>> + etc0: etc0 {
>>>> + gpio-controller;
>>>> + #gpio-cells = <2>;
>>>> +
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <2>;
>>>> + };
>>>> +
>>>> + etc1: etc1 {
>>>> + gpio-controller;
>>>> + #gpio-cells = <2>;
>>>> +
>>>> + interrupt-controller;
>>>> + #interrupt-cells = <2>;
>>>> + };
>>>
>>> Hmm, what are these two? I can't find anything related in
>>> exynos7885.dtsi. If it's just some leftover from downstream vendor
>>> kernel -- please remove it.
>>
>> This is a pinctrl DTSI file. What do you expect to find in
>> exynos7885.dtsi for these? Why removing them?
>
> etc0 and etc1 nodes are defined as gpio-controller and
> interrupt-controller. So "compatible" should be provided somewhere for
> those nodes. For example, for "gpa0" node below you can find its
> compatible in exynos7885.dtsi.

I am sorry, I still don't get it. gpa0 below does not have compatible.

> Right now I don't understand how those
> etc0 and etc1 can be used at all.

Exactly the same as gpa0, nothing changes here.

> So maybe it's better to just remove
> those? Those are not used anywhere and we probably don't even know
> what those nodes represent. My point is, if those are actually some
> leftovers from vendor kernel and those are not going to be used (and I
> don't see how, without "compatible"), then we probablly better off
> without those.

I don't have the manual but in other SoCs these are not left-overs, but
real GPIO banks. Their configurability depends on the SoCs. I agree that
usually they are not used (because one of the uses is debugging), but
they can be included for completness of HW description. Assuming they exist.

(...)

>>>> +#include "exynos7885-pinctrl.dtsi"
>>>> +#include "arm/exynos-syscon-restart.dtsi"
>>>
>>> Have you verified both reboot and power off functions from this file?
>>> I guess if some doesn't work, it's better to avoid including this, but
>>> instead add corresponding sub-nodes into your pmu_sytem_controller.
>>
>> Why open-coding same code work and including would not? Assuming that it
>> compiles, of course.
>>
>
> For example, in case of Exynos850 the "power off" node from this file
> wasn't suitable. In that case it's not worth including it. But David
> already confirmed both work fine for him, so it doesn't matter
> anymore.

These nodes were here before and since they duplicated common syscon, I
asked to use DTSI. The boards which do not use the same syscon
registers/methods should not include it, obviously. :)

Best regards,
Krzysztof

2021-12-08 16:52:00

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On Wed, 8 Dec 2021 at 18:29, Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 08/12/2021 16:37, Sam Protsenko wrote:
> > On Wed, 8 Dec 2021 at 11:05, Krzysztof Kozlowski
> > <[email protected]> wrote:
> >>
> >> On 07/12/2021 21:19, Sam Protsenko wrote:
> >>> On Mon, 6 Dec 2021 at 17:32, David Virag <[email protected]> wrote:
> >>>>
> >>>> Add initial Exynos7885 device tree nodes with dts for the Samsung Galaxy
> >>>> A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> >>>> Currently this includes some clock support, UART support, and I2C nodes.
> >>>>
> >>>> Signed-off-by: David Virag <[email protected]>
> >>>> ---
> >>>> Changes in v2:
> >>>> - Remove address-cells, and size-cells from dts, since they are
> >>>> already in the dtsi.
> >>>> - Lower case hex in memory node
> >>>> - Fix node names with underscore instead of hyphen
> >>>> - Fix line breaks
> >>>> - Fix "-key" missing from gpio keys node names
> >>>> - Use the form without "key" in gpio key labels on all keys
> >>>> - Suffix pin configuration node names with "-pins"
> >>>> - Remove "fimc_is_mclk" nodes from pinctrl dtsi for now
> >>>> - Use macros for "samsung,pin-con-pdn", and "samsung,pin-con-pdn"
> >>>> - Add comment about Arm PMU
> >>>> - Rename "clock-oscclk" to "osc-clock"
> >>>> - Include exynos-syscon-restart.dtsi instead of rewriting its contents
> >>>>
> >>>> Changes in v3:
> >>>> - Fix typo (seperate -> separate)
> >>>>
> >>>> Changes in v4:
> >>>> - Fixed leading 0x in clock-controller nodes
> >>>> - Actually suffixed pin configuration node names with "-pins"
> >>>> - Seperated Cortex-A53 and Cortex-A73 PMU
> >>>>
> >>>> arch/arm64/boot/dts/exynos/Makefile | 7 +-
> >>>> .../boot/dts/exynos/exynos7885-jackpotlte.dts | 95 ++
> >>>> .../boot/dts/exynos/exynos7885-pinctrl.dtsi | 865 ++++++++++++++++++
> >>>> arch/arm64/boot/dts/exynos/exynos7885.dtsi | 438 +++++++++
> >>>> 4 files changed, 1402 insertions(+), 3 deletions(-)
> >>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> >>>
> >>> Shouldn't SoC and board files be sent as two separate patches? For
> >>> example, I've checked exynos5433 and exynos7, SoC support
> >>
> >> Does not have to be. DTSI by itself cannot be even compiled, so keeping
> >> it a separate commit does not bring that much benefits. Especially if it
> >> is only one DTSI and one DTS.
> >>
> >
> > Right, the only theoretical benefit I can see is reverting the board
> > dts in future, if another board already uses SoC dtsi. Or
> > cherry-picking in similar manner. Not my call though, for me it just
> > seems easier to review it that way, and more atomic.
> >
> >>>
> >>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> >>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos7885.dtsi
> >>>>
> >>>> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> >>>> index b41e86df0a84..c68c4ad577ac 100644
> >>>> --- a/arch/arm64/boot/dts/exynos/Makefile
> >>>> +++ b/arch/arm64/boot/dts/exynos/Makefile
> >>>> @@ -1,6 +1,7 @@
> >>>> # SPDX-License-Identifier: GPL-2.0
> >>>> dtb-$(CONFIG_ARCH_EXYNOS) += \
> >>>> - exynos5433-tm2.dtb \
> >>>> - exynos5433-tm2e.dtb \
> >>>> - exynos7-espresso.dtb \
> >>>> + exynos5433-tm2.dtb \
> >>>> + exynos5433-tm2e.dtb \
> >>>> + exynos7-espresso.dtb \
> >>>> + exynos7885-jackpotlte.dtb \
> >>>> exynosautov9-sadk.dtb
> >>>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> >>>> new file mode 100644
> >>>> index 000000000000..f5941dc4c374
> >>>> --- /dev/null
> >>>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
> >>>> @@ -0,0 +1,95 @@
> >>>> +// SPDX-License-Identifier: GPL-2.0
> >>>> +/*
> >>>> + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
> >>>> + *
> >>>> + * Copyright (c) 2021 Samsung Electronics Co., Ltd.
> >>>> + * Copyright (c) 2021 Dávid Virág
> >>>> + *
> >>>
> >>> This line is not needed.
> >>>
> >>>> + */
> >>>> +
> >>>> +/dts-v1/;
> >>>
> >>> Suggest adding empty line here.
> >>>
> >>>> +#include "exynos7885.dtsi"
> >>>> +#include <dt-bindings/gpio/gpio.h>
> >>>> +#include <dt-bindings/input/input.h>
> >>>> +#include <dt-bindings/interrupt-controller/irq.h>
> >>>> +
> >>>> +/ {
> >>>> + model = "Samsung Galaxy A8 (2018)";
> >>>> + compatible = "samsung,jackpotlte", "samsung,exynos7885";
> >>>> + chassis-type = "handset";
> >>>> +
> >>>> + aliases {
> >>>> + serial0 = &serial_0;
> >>>> + serial1 = &serial_1;
> >>>> + serial2 = &serial_2;
> >>>
> >>> Suggestion: add aliases also for i2c nodes, to keep i2c instance
> >>> numbers fixed in run-time (e.g. in "i2cdetect -l" output).
> >>>
> >>>> + };
> >>>> +
> >>>> + chosen {
> >>>> + stdout-path = &serial_2;
> >>>> + };
> >>>> +
> >>>> + memory@80000000 {
> >>>> + device_type = "memory";
> >>>> + reg = <0x0 0x80000000 0x3da00000>,
> >>>> + <0x0 0xc0000000 0x40000000>,
> >>>> + <0x8 0x80000000 0x40000000>;
> >>>> + };
> >>>> +
> >>>> + gpio-keys {
> >>>> + compatible = "gpio-keys";
> >>>> + pinctrl-names = "default";
> >>>> + pinctrl-0 = <&key_volup &key_voldown &key_power>;
> >>>> +
> >>>> + volup-key {
> >>>> + label = "Volume Up";
> >>>> + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
> >>>
> >>> Here and below: what is 0, why it's needed? Also, isn't it enough to
> >>> have just "gpios", and remove interrupt*? Need to check "gpio-keys"
> >>> driver and bindings doc, but AFAIR it should be enough to have just
> >>> "gpios =" or just "interrupts =".
> >>
> >> "gpios" is enough, because the IRQ line is derived from it. However
> >> explicitly describing interrupts seems like a more detailed hardware
> >> description.
> >>
> >
> > Frankly I don't think it's more detailed, it states the same thing
> > (gpa1 controller, line=5).
>
> It states that interrupt is exactly the same as GPIO which not
> explicitly coming from bindings.
>
> > Also not sure if level interrupt is needed
> > for a key, maybe edge type would be better. Also, I still don't
> > understand 0 in the end.
>
> Indeed this part looks not correct - the leve and 0 at the end. In such
> case better to skip it then define misleading property.
>
> > Checking existing dts's, most of those only
> > define "gpios". I'd say having only "gpios" is more obvious, and will
> > work the same way. But that's not a strong preference on my side, just
> > think it's a bit misleading right now.
>
> Yep.
>
> >
> >>>
> >>>
> >>>> + interrupt-parent = <&gpa1>;
> >>>> + linux,code = <KEY_VOLUMEUP>;
> >>>> + gpios = <&gpa1 5 GPIO_ACTIVE_LOW>;
> >>>> + };
> >>>> +
> >>>> + voldown-key {
> >>>> + label = "Volume Down";
> >>>> + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
> >>>> + interrupt-parent = <&gpa1>;
> >>>> + linux,code = <KEY_VOLUMEDOWN>;
> >>>> + gpios = <&gpa1 6 GPIO_ACTIVE_LOW>;
> >>>> + };
> >>>> +
> >>>> + power-key {
> >>>> + label = "Power";
> >>>> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
> >>>> + interrupt-parent = <&gpa1>;
> >>>> + linux,code = <KEY_POWER>;
> >>>> + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>;
> >>>> + wakeup-source;
> >>>> + };
> >>>> + };
> >>>> +};
> >>>> +
> >>>
> >>> If there are some LEDs by chance on that board -- it might be useful
> >>> to define those here with "gpio-leds" as well. Maybe even set some
> >>> default trigger like "heartbeat".
> >>>
> >>>> +&serial_2 {
> >>>> + status = "okay";
> >>>> +};
> >>>> +
> >>>> +&pinctrl_alive {
> >>>> + key_volup: key-volup-pins {
> >>>> + samsung,pins = "gpa1-5";
> >>>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >>>
> >>> Maybe EXYNOS_PIN_FUNC_EINT is more self-explanatory? Just a suggestion though.
> >>>
> >>>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >>>> + samsung,pin-drv = <0>;
> >>>
> >>> Here and below: please use EXYNOS5420_PIN_DRV_LV1 (means drive level = 1x).
> >>
> >> But are these drive level 1x? The Exynos Auto v9 has different values
> >> than older ones.
> >>
> >
> > It should be that. One way to implicitly figure that out is to look at
> > nodes like "sd0_clk_fast_slew_rate_3x" and those pin-drv properties.
> > Also, in Exynos850 for most of domains those constants are
> > appropriate, that's why I mentioned that.
>
> Then I agree, use existing macros. The macros can be skipped for cases
> when the meaning is different.
>
> >
> >>>
> >>>> + };
> >>>> +
> >>>> + key_voldown: key-voldown-pins {
> >>>> + samsung,pins = "gpa1-6";
> >>>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >>>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >>>> + samsung,pin-drv = <0>;
> >>>> + };
> >>>> +
> >>>> + key_power: key-power-pins {
> >>>> + samsung,pins = "gpa1-7";
> >>>> + samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
> >>>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> >>>> + samsung,pin-drv = <0>;
> >>>> + };
> >>>> +};
> >>>> diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> >>>> new file mode 100644
> >>>> index 000000000000..8336b2e48858
> >>>> --- /dev/null
> >>>> +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi
> >>>> @@ -0,0 +1,865 @@
> >>>> +// SPDX-License-Identifier: GPL-2.0
> >>>> +/*
> >>>> + * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
> >>>> + *
> >>>> + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> >>>> + * Copyright (c) 2021 Dávid Virág
> >>>> + *
> >>>> + * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
> >>>> + * device tree nodes in this file.
> >>>> + */
> >>>> +
> >>>> +#include <dt-bindings/pinctrl/samsung.h>
> >>>
> >>> You probably also need <dt-bindings/interrupt-controller/arm-gic.h>
> >>> here for GIC_SPI definition.
> >>>
> >>>> +
> >>>> +&pinctrl_alive {
> >>>> + etc0: etc0 {
> >>>> + gpio-controller;
> >>>> + #gpio-cells = <2>;
> >>>> +
> >>>> + interrupt-controller;
> >>>> + #interrupt-cells = <2>;
> >>>> + };
> >>>> +
> >>>> + etc1: etc1 {
> >>>> + gpio-controller;
> >>>> + #gpio-cells = <2>;
> >>>> +
> >>>> + interrupt-controller;
> >>>> + #interrupt-cells = <2>;
> >>>> + };
> >>>
> >>> Hmm, what are these two? I can't find anything related in
> >>> exynos7885.dtsi. If it's just some leftover from downstream vendor
> >>> kernel -- please remove it.
> >>
> >> This is a pinctrl DTSI file. What do you expect to find in
> >> exynos7885.dtsi for these? Why removing them?
> >
> > etc0 and etc1 nodes are defined as gpio-controller and
> > interrupt-controller. So "compatible" should be provided somewhere for
> > those nodes. For example, for "gpa0" node below you can find its
> > compatible in exynos7885.dtsi.
>
> I am sorry, I still don't get it. gpa0 below does not have compatible.
>

I was probably groggy and missed the fact those etc* nodes are child
nodes of pinctrl_alive :) And now I can see those are actually
described in pinctrl-exynos-arm64.c (in linux-next, where 7885 pinctrl
support is added). Please ignore my request w.r.t. etc* nodes, those
should stay of course.

> > Right now I don't understand how those
> > etc0 and etc1 can be used at all.
>
> Exactly the same as gpa0, nothing changes here.
>
> > So maybe it's better to just remove
> > those? Those are not used anywhere and we probably don't even know
> > what those nodes represent. My point is, if those are actually some
> > leftovers from vendor kernel and those are not going to be used (and I
> > don't see how, without "compatible"), then we probablly better off
> > without those.
>
> I don't have the manual but in other SoCs these are not left-overs, but
> real GPIO banks. Their configurability depends on the SoCs. I agree that
> usually they are not used (because one of the uses is debugging), but
> they can be included for completness of HW description. Assuming they exist.
>
> (...)
>
> >>>> +#include "exynos7885-pinctrl.dtsi"
> >>>> +#include "arm/exynos-syscon-restart.dtsi"
> >>>
> >>> Have you verified both reboot and power off functions from this file?
> >>> I guess if some doesn't work, it's better to avoid including this, but
> >>> instead add corresponding sub-nodes into your pmu_sytem_controller.
> >>
> >> Why open-coding same code work and including would not? Assuming that it
> >> compiles, of course.
> >>
> >
> > For example, in case of Exynos850 the "power off" node from this file
> > wasn't suitable. In that case it's not worth including it. But David
> > already confirmed both work fine for him, so it doesn't matter
> > anymore.
>
> These nodes were here before and since they duplicated common syscon, I
> asked to use DTSI. The boards which do not use the same syscon
> registers/methods should not include it, obviously. :)
>
>
> Best regards,
> Krzysztof

2021-12-10 21:27:01

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU

On Mon, 06 Dec 2021 16:31:15 +0100, David Virag wrote:
> Just like on Exynos850, the clock controller driver is designed to have
> separate instances for each particular CMU, so clock IDs start from 1
> for each CMU in this bindings header too.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Nothing
>
> include/dt-bindings/clock/exynos7885.h | 115 +++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 include/dt-bindings/clock/exynos7885.h
>

Acked-by: Rob Herring <[email protected]>

2021-12-10 21:28:22

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH v4 2/7] dt-bindings: clock: Document Exynos7885 CMU bindings

On Mon, 06 Dec 2021 16:31:16 +0100, David Virag wrote:
> Provide dt-schema documentation for Exynos7885 SoC clock controller.
> Description is modified from Exynos850 clock controller documentation as
> I couldn't describe it any better, that was written by Sam Protsenko.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Fixed double : in description
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Fix leading 0x in example.
>
> .../clock/samsung,exynos7885-clock.yaml | 166 ++++++++++++++++++
> 1 file changed, 166 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml
>

Reviewed-by: Rob Herring <[email protected]>

2021-12-10 21:30:09

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH v4 3/7] dt-bindings: arm: samsung: document jackpotlte board binding

On Mon, 06 Dec 2021 16:31:17 +0100, David Virag wrote:
> Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)).
>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Nothing
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Nothing
>
> .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>

Reviewed-by: Rob Herring <[email protected]>

2021-12-12 18:39:20

[permalink] [raw]

Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU

On 06/12/2021 16:31, David Virag wrote:
> Just like on Exynos850, the clock controller driver is designed to have
> separate instances for each particular CMU, so clock IDs start from 1
> for each CMU in this bindings header too.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: David Virag <[email protected]>
> ---
> Changes in v2:
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v3:
> - Nothing
>
> Changes in v4:
> - Nothing
>
> include/dt-bindings/clock/exynos7885.h | 115 +++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 include/dt-bindings/clock/exynos7885.h
>

Hi Sylwester,

The DTS/DTSI patch (7/7) depends on this one, just like the clock driver.

Since some time Arnd and Olof prefer not to have external trees going
into the arm-soc, even if this is only the header change. They recommend
one of:
1. to hard-code the numbers in DTS and replace numbers->macros later,
2. merge headers to arm-soc tree with DTS and provide the header to an
external (e.g. clk) tree,
3. wait with merging DTSI till headers reach mainline.

I propose that I take the clock headers, put on separate branch and
provide them to you as stable tag. You can base clk driver changes on
top of it.

Are you okay with this?

Best regards,
Krzysztof

2021-12-15 16:22:11

[permalink] [raw]

Subject: Re: (subset) [PATCH v4 3/7] dt-bindings: arm: samsung: document jackpotlte board binding

On Mon, 6 Dec 2021 16:31:17 +0100, David Virag wrote:
> Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)).
>
>

Applied, thanks!

[3/7] dt-bindings: arm: samsung: document jackpotlte board binding
commit: c96ebc5fde274edcc02543dcfb6a1ee097f98070

Best regards,
--
Krzysztof Kozlowski <[email protected]>

2021-12-19 14:37:21

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On Tue, 2021-12-07 at 19:42 +0000, Marc Zyngier wrote:
> On 2021-12-06 15:31, David Virag wrote:
> > Add initial Exynos7885 device tree nodes with dts for the Samsung
> > Galaxy
> > A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> > Currently this includes some clock support, UART support, and I2C
> > nodes.
> >
> > Signed-off-by: David Virag <[email protected]>
>
> [...]
>
> > +       psci {
> > +               compatible = "arm,psci";
> > +               method = "smc";
> > +               cpu_suspend = <0xc4000001>;
> > +               cpu_off = <0x84000002>;
> > +               cpu_on = <0xc4000003>;
>
> Aren't these the standard PSCI 0.2 function numbers? Can't you
> make the compatible "arm,psci-0.2" instead?

This is not a proper PSCI 0.2 implementation. For example 0.2 has a get
version call which is definitely not implemented properly as after
setting the compatible to 0.2 I get the following:

[ 0.000000] psci: PSCIv65535.65535 detected in firmware.

Which is obviously not right.

>
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               /* Hypervisor Virtual Timer interrupt is not wired
> > to GIC */
>
> I don't understand this comment. You seem to have a bunch of
> ARMv8.0 cores, for which there is no such thing as a hypervisor
> virtual timer (this is an ARMv8.1 addition).

My bad, will remove it! Should have read docs better.

>
> > +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>,
> > +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
> > IRQ_TYPE_LEVEL_LOW)>;
> > +       };
>
> Thanks,
>
>          M.

2021-12-19 14:54:37

[permalink] [raw]

Subject: Re: (subset) [PATCH v4 3/7] dt-bindings: arm: samsung: document jackpotlte board binding

On Wed, 2021-12-15 at 17:21 +0100, Krzysztof Kozlowski wrote:
> On Mon, 6 Dec 2021 16:31:17 +0100, David Virag wrote:
> > Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)).
> >
> >
>
> Applied, thanks!
>
> [3/7] dt-bindings: arm: samsung: document jackpotlte board binding
> commit: c96ebc5fde274edcc02543dcfb6a1ee097f98070
>
> Best regards,

Hi Krzysztof!

Thanks! As I'll be sending v5 of this series soon (only really adding
r-by, acked-by tags and only real changes in dts/dtsi patch), should I
omit this patch from it since it has been applied? Or should I really
only send the dts/dtsi patch at this point? Sorry if this is obvious, I
just haven't sent that many patches before to know this.

Best regards,
David

2021-12-19 22:53:03

by Sylwester Nawrocki

[permalink] [raw]

Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU

On 06.12.2021 16:31, David Virag wrote:
> Just like on Exynos850, the clock controller driver is designed to have
> separate instances for each particular CMU, so clock IDs start from 1
> for each CMU in this bindings header too.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: David Virag <[email protected]>

Applied patches 1,2,4,5,6, thanks.

2021-12-20 08:44:50

by Marc Zyngier

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

On Sun, 19 Dec 2021 14:36:20 +0000,
David Virag <[email protected]> wrote:
>
> On Tue, 2021-12-07 at 19:42 +0000, Marc Zyngier wrote:
> > On 2021-12-06 15:31, David Virag wrote:
> > > Add initial Exynos7885 device tree nodes with dts for the Samsung
> > > Galaxy
> > > A8 (2018), a.k.a. "jackpotlte", with model number "SM-A530F".
> > > Currently this includes some clock support, UART support, and I2C
> > > nodes.
> > >
> > > Signed-off-by: David Virag <[email protected]>
> >
> > [...]
> >
> > > +       psci {
> > > +               compatible = "arm,psci";
> > > +               method = "smc";
> > > +               cpu_suspend = <0xc4000001>;
> > > +               cpu_off = <0x84000002>;
> > > +               cpu_on = <0xc4000003>;
> >
> > Aren't these the standard PSCI 0.2 function numbers? Can't you
> > make the compatible "arm,psci-0.2" instead?
>
> This is not a proper PSCI 0.2 implementation. For example 0.2 has a get
> version call which is definitely not implemented properly as after
> setting the compatible to 0.2 I get the following:
>
> [ 0.000000] psci: PSCIv65535.65535 detected in firmware.
>
> Which is obviously not right.

Indeed. That's a bloody -1 returned by the firmware. Quality
implementation, as usual...

Thanks,

M.

--
Without deviation from the norm, progress is not possible.

2021-12-20 09:38:50

[permalink] [raw]

Subject: Re: (subset) [PATCH v4 3/7] dt-bindings: arm: samsung: document jackpotlte board binding

On 19/12/2021 15:53, David Virag wrote:
> On Wed, 2021-12-15 at 17:21 +0100, Krzysztof Kozlowski wrote:
>> On Mon, 6 Dec 2021 16:31:17 +0100, David Virag wrote:
>>> Add binding for the jackpotlte board (Samsung Galaxy A8 (2018)).
>>>
>>>
>>
>> Applied, thanks!
>>
>> [3/7] dt-bindings: arm: samsung: document jackpotlte board binding
>> commit: c96ebc5fde274edcc02543dcfb6a1ee097f98070
>>
>> Best regards,
>
> Hi Krzysztof!
>
> Thanks! As I'll be sending v5 of this series soon (only really adding
> r-by, acked-by tags and only real changes in dts/dtsi patch), should I
> omit this patch from it since it has been applied? Or should I really
> only send the dts/dtsi patch at this point? Sorry if this is obvious, I
> just haven't sent that many patches before to know this.

Skip this one, please.

Best regards,
Krzysztof

2021-12-20 09:40:46

[permalink] [raw]

Subject: Re: [PATCH v4 1/7] dt-bindings: clock: Add bindings definitions for Exynos7885 CMU

On 12/12/2021 19:39, Krzysztof Kozlowski wrote:
> On 06/12/2021 16:31, David Virag wrote:
>> Just like on Exynos850, the clock controller driver is designed to have
>> separate instances for each particular CMU, so clock IDs start from 1
>> for each CMU in this bindings header too.
>>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> Signed-off-by: David Virag <[email protected]>
>> ---
>> Changes in v2:
>> - Added R-b tag by Krzysztof Kozlowski
>>
>> Changes in v3:
>> - Nothing
>>
>> Changes in v4:
>> - Nothing
>>
>> include/dt-bindings/clock/exynos7885.h | 115 +++++++++++++++++++++++++
>> 1 file changed, 115 insertions(+)
>> create mode 100644 include/dt-bindings/clock/exynos7885.h
>>
>
> Hi Sylwester,
>
> The DTS/DTSI patch (7/7) depends on this one, just like the clock driver.
>
> Since some time Arnd and Olof prefer not to have external trees going
> into the arm-soc, even if this is only the header change. They recommend
> one of:
> 1. to hard-code the numbers in DTS and replace numbers->macros later,
> 2. merge headers to arm-soc tree with DTS and provide the header to an
> external (e.g. clk) tree,
> 3. wait with merging DTSI till headers reach mainline.
>
> I propose that I take the clock headers, put on separate branch and
> provide them to you as stable tag. You can base clk driver changes on
> top of it.
>
> Are you okay with this?

Hi Sylwester,

I see you applied the patches, so I understand we are not going with
this proposal.

David,

Your DTSI and DTS will have to either wait for next cycle or please
resend with clock macros replaced with numbers + TODO note.

Best regards,
Krzysztof

2022-02-01 20:42:38

[permalink] [raw]

Subject: Re: [PATCH v4 7/7] arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC

2022-02-02 00:05:48