From: Peng Fan <[email protected]>
Add mcore_booted boot parameter which could simplify AMP clock
management. To i.MX8M, there is CCM(clock control Module) to generate
clock root clock, anatop(analog PLL module) to generate PLL, and CCGR
(clock gating) to gate clocks to peripherals. As below:
anatop->ccm->ccgr->peripheral
Linux handles the clock management and the auxiliary core is under
control of Linux. Although there is per hardware domain control for CCGR
and CCM, auxiliary core normally only use CCGR hardware domain control
to avoid linux gate off the clk to peripherals and leave CCM ana anatop
to Linux.
Per NXP hardware design, because CCGR already support gate to
peripherals, and clk root gate power leakage is negligible. So
when in AMP case, we could not register the clk root gate.
Signed-off-by: Peng Fan <[email protected]>
---
V2:
Switch to use module parameter, tested on i.MX8MP-EVK
drivers/clk/imx/clk-imx8mm.c | 2 ++
drivers/clk/imx/clk-imx8mn.c | 2 ++
drivers/clk/imx/clk-imx8mp.c | 2 ++
drivers/clk/imx/clk-imx8mq.c | 2 ++
drivers/clk/imx/clk.c | 3 +++
drivers/clk/imx/clk.h | 1 +
6 files changed, 12 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index e8cbe181ec06..a452fd1bb891 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -639,6 +639,8 @@ static struct platform_driver imx8mm_clk_driver = {
},
};
module_platform_driver(imx8mm_clk_driver);
+module_param(mcore_booted, bool, S_IRUGO);
+MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
MODULE_AUTHOR("Bai Ping <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MM clock driver");
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index 92fcbab4f5be..dc69b7464b3d 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -594,6 +594,8 @@ static struct platform_driver imx8mn_clk_driver = {
},
};
module_platform_driver(imx8mn_clk_driver);
+module_param(mcore_booted, bool, S_IRUGO);
+MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
MODULE_AUTHOR("Anson Huang <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MN clock driver");
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 18f5b7c3ca9d..250e45d9f844 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -721,6 +721,8 @@ static struct platform_driver imx8mp_clk_driver = {
},
};
module_platform_driver(imx8mp_clk_driver);
+module_param(mcore_booted, bool, S_IRUGO);
+MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
MODULE_AUTHOR("Anson Huang <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MP clock driver");
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 83cc2b1c3294..33897b56130d 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -632,6 +632,8 @@ static struct platform_driver imx8mq_clk_driver = {
},
};
module_platform_driver(imx8mq_clk_driver);
+module_param(mcore_booted, bool, S_IRUGO);
+MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
MODULE_AUTHOR("Abel Vesa <[email protected]>");
MODULE_DESCRIPTION("NXP i.MX8MQ clock driver");
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 7cc669934253..4bd6ad060eea 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -17,6 +17,9 @@
DEFINE_SPINLOCK(imx_ccm_lock);
EXPORT_SYMBOL_GPL(imx_ccm_lock);
+bool mcore_booted;
+EXPORT_SYMBOL_GPL(mcore_booted);
+
void imx_unregister_clocks(struct clk *clks[], unsigned int count)
{
unsigned int i;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index a7cbbcd1a3f4..5061a06468df 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -7,6 +7,7 @@
#include <linux/clk-provider.h>
extern spinlock_t imx_ccm_lock;
+extern bool mcore_booted;
void imx_check_clocks(struct clk *clks[], unsigned int count);
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
--
2.25.1
From: Peng Fan <[email protected]>
If mcore_booted is true, ignore the clk root gate registration and
this will simplify AMP clock management and avoid system hang unexpectly
especially Linux shutdown clk used by mcore.
Signed-off-by: Peng Fan <[email protected]>
---
V2:
None
drivers/clk/imx/clk-composite-8m.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 2dfd6149e528..b16c2c0ea9f6 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -223,14 +223,19 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
div->lock = &imx_ccm_lock;
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
- gate = kzalloc(sizeof(*gate), GFP_KERNEL);
- if (!gate)
- goto fail;
-
- gate_hw = &gate->hw;
- gate->reg = reg;
- gate->bit_idx = PCG_CGC_SHIFT;
- gate->lock = &imx_ccm_lock;
+ /* skip registering the gate ops if M4 is enabled */
+ if (mcore_booted) {
+ gate_hw = NULL;
+ } else {
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto fail;
+
+ gate_hw = &gate->hw;
+ gate->reg = reg;
+ gate->bit_idx = PCG_CGC_SHIFT;
+ gate->lock = &imx_ccm_lock;
+ }
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
mux_hw, mux_ops, div_hw,
--
2.25.1
Quoting Peng Fan (OSS) (2022-02-28 04:41:11)
> From: Peng Fan <[email protected]>
>
> Add mcore_booted boot parameter which could simplify AMP clock
> management. To i.MX8M, there is CCM(clock control Module) to generate
> clock root clock, anatop(analog PLL module) to generate PLL, and CCGR
> (clock gating) to gate clocks to peripherals. As below:
> anatop->ccm->ccgr->peripheral
>
> Linux handles the clock management and the auxiliary core is under
> control of Linux. Although there is per hardware domain control for CCGR
> and CCM, auxiliary core normally only use CCGR hardware domain control
> to avoid linux gate off the clk to peripherals and leave CCM ana anatop
> to Linux.
>
> Per NXP hardware design, because CCGR already support gate to
> peripherals, and clk root gate power leakage is negligible. So
> when in AMP case, we could not register the clk root gate.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
>
> V2:
> Switch to use module parameter, tested on i.MX8MP-EVK
Why is a module parameter being used? I'd expect this informatioon that
mcore is booted to come from devicetree/firmware somehow.
Quoting Peng Fan (OSS) (2022-02-28 04:41:12)
> From: Peng Fan <[email protected]>
>
> If mcore_booted is true, ignore the clk root gate registration and
> this will simplify AMP clock management and avoid system hang unexpectly
> especially Linux shutdown clk used by mcore.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
>
> V2:
> None
>
> drivers/clk/imx/clk-composite-8m.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
> index 2dfd6149e528..b16c2c0ea9f6 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -223,14 +223,19 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
> div->lock = &imx_ccm_lock;
> div->flags = CLK_DIVIDER_ROUND_CLOSEST;
>
> - gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> - if (!gate)
> - goto fail;
> -
> - gate_hw = &gate->hw;
> - gate->reg = reg;
> - gate->bit_idx = PCG_CGC_SHIFT;
> - gate->lock = &imx_ccm_lock;
> + /* skip registering the gate ops if M4 is enabled */
> + if (mcore_booted) {
> + gate_hw = NULL;
It could even use the protected-clocks property and then parse it to
figure out to not register this gate?
> + } else {
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto fail;
> +
> + gate_hw = &gate->hw;
> + gate->reg = reg;
> + gate->bit_idx = PCG_CGC_SHIFT;
> + gate->lock = &imx_ccm_lock;
> + }
> Subject: Re: [PATCH V2 2/2] clk: imx8m: check mcore_booted before register
> clk
>
> Quoting Peng Fan (OSS) (2022-02-28 04:41:12)
> > From: Peng Fan <[email protected]>
> >
> > If mcore_booted is true, ignore the clk root gate registration and
> > this will simplify AMP clock management and avoid system hang
> > unexpectly especially Linux shutdown clk used by mcore.
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> >
> > V2:
> > None
> >
> > drivers/clk/imx/clk-composite-8m.c | 21 +++++++++++++--------
> > 1 file changed, 13 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c
> > b/drivers/clk/imx/clk-composite-8m.c
> > index 2dfd6149e528..b16c2c0ea9f6 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -223,14 +223,19 @@ struct clk_hw
> *__imx8m_clk_hw_composite(const char *name,
> > div->lock = &imx_ccm_lock;
> > div->flags = CLK_DIVIDER_ROUND_CLOSEST;
> >
> > - gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> > - if (!gate)
> > - goto fail;
> > -
> > - gate_hw = &gate->hw;
> > - gate->reg = reg;
> > - gate->bit_idx = PCG_CGC_SHIFT;
> > - gate->lock = &imx_ccm_lock;
> > + /* skip registering the gate ops if M4 is enabled */
> > + if (mcore_booted) {
> > + gate_hw = NULL;
>
> It could even use the protected-clocks property and then parse it to figure out
> to not register this gate?
Because of hardware design as I replied in patch 1/2, that means we will add
hundreds of clk entry in device tree. I would not do that.
Thanks,
Peng.
>
> > + } else {
> > + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> > + if (!gate)
> > + goto fail;
> > +
> > + gate_hw = &gate->hw;
> > + gate->reg = reg;
> > + gate->bit_idx = PCG_CGC_SHIFT;
> > + gate->lock = &imx_ccm_lock;
> > + }
> Subject: Re: [PATCH V2 1/2] clk: imx: add mcore_booted module paratemter
>
> Quoting Peng Fan (OSS) (2022-02-28 04:41:11)
> > From: Peng Fan <[email protected]>
> >
> > Add mcore_booted boot parameter which could simplify AMP clock
> > management. To i.MX8M, there is CCM(clock control Module) to generate
> > clock root clock, anatop(analog PLL module) to generate PLL, and CCGR
> > (clock gating) to gate clocks to peripherals. As below:
> > anatop->ccm->ccgr->peripheral
> >
> > Linux handles the clock management and the auxiliary core is under
> > control of Linux. Although there is per hardware domain control for
> > CCGR and CCM, auxiliary core normally only use CCGR hardware domain
> > control to avoid linux gate off the clk to peripherals and leave CCM
> > ana anatop to Linux.
> >
> > Per NXP hardware design, because CCGR already support gate to
> > peripherals, and clk root gate power leakage is negligible. So when in
> > AMP case, we could not register the clk root gate.
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> >
> > V2:
> > Switch to use module parameter, tested on i.MX8MP-EVK
>
> Why is a module parameter being used? I'd expect this informatioon that
> mcore is booted to come from devicetree/firmware somehow.
In i.MX platform design, mcore could be kicked by U-Boot or Linux remoteproc.
The hardware clk IP has CCM(clock root composite) and CCGR(clock gate).
CCGR support multiple hardware domain control, but CCM not.
Linux handles clock management, mcore only handles CCGR, so that means
Linux CCM operation maybe shutdown and cause CCGR has not clk input.
So when we need mcore run, we should not register CCM clk gate in
the composite. To mcore is booted by U-boot, we previous use information
from hardware, but to mcore is booted by remoteproc, we have no way,
because linux already registered all clocks.
So now we use a module parameter to let user decide.
Hope this is clear.
Thanks,
Peng.
On 22-02-28 20:41:11, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Add mcore_booted boot parameter which could simplify AMP clock
> management. To i.MX8M, there is CCM(clock control Module) to generate
> clock root clock, anatop(analog PLL module) to generate PLL, and CCGR
> (clock gating) to gate clocks to peripherals. As below:
> anatop->ccm->ccgr->peripheral
>
> Linux handles the clock management and the auxiliary core is under
> control of Linux. Although there is per hardware domain control for CCGR
> and CCM, auxiliary core normally only use CCGR hardware domain control
> to avoid linux gate off the clk to peripherals and leave CCM ana anatop
> to Linux.
>
> Per NXP hardware design, because CCGR already support gate to
> peripherals, and clk root gate power leakage is negligible. So
> when in AMP case, we could not register the clk root gate.
>
> Signed-off-by: Peng Fan <[email protected]>
Applied both, thanks.
> ---
>
> V2:
> Switch to use module parameter, tested on i.MX8MP-EVK
>
> drivers/clk/imx/clk-imx8mm.c | 2 ++
> drivers/clk/imx/clk-imx8mn.c | 2 ++
> drivers/clk/imx/clk-imx8mp.c | 2 ++
> drivers/clk/imx/clk-imx8mq.c | 2 ++
> drivers/clk/imx/clk.c | 3 +++
> drivers/clk/imx/clk.h | 1 +
> 6 files changed, 12 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index e8cbe181ec06..a452fd1bb891 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -639,6 +639,8 @@ static struct platform_driver imx8mm_clk_driver = {
> },
> };
> module_platform_driver(imx8mm_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Bai Ping <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MM clock driver");
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 92fcbab4f5be..dc69b7464b3d 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -594,6 +594,8 @@ static struct platform_driver imx8mn_clk_driver = {
> },
> };
> module_platform_driver(imx8mn_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Anson Huang <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MN clock driver");
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 18f5b7c3ca9d..250e45d9f844 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -721,6 +721,8 @@ static struct platform_driver imx8mp_clk_driver = {
> },
> };
> module_platform_driver(imx8mp_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Anson Huang <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MP clock driver");
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 83cc2b1c3294..33897b56130d 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -632,6 +632,8 @@ static struct platform_driver imx8mq_clk_driver = {
> },
> };
> module_platform_driver(imx8mq_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Abel Vesa <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MQ clock driver");
> diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
> index 7cc669934253..4bd6ad060eea 100644
> --- a/drivers/clk/imx/clk.c
> +++ b/drivers/clk/imx/clk.c
> @@ -17,6 +17,9 @@
> DEFINE_SPINLOCK(imx_ccm_lock);
> EXPORT_SYMBOL_GPL(imx_ccm_lock);
>
> +bool mcore_booted;
> +EXPORT_SYMBOL_GPL(mcore_booted);
> +
> void imx_unregister_clocks(struct clk *clks[], unsigned int count)
> {
> unsigned int i;
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index a7cbbcd1a3f4..5061a06468df 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -7,6 +7,7 @@
> #include <linux/clk-provider.h>
>
> extern spinlock_t imx_ccm_lock;
> +extern bool mcore_booted;
>
> void imx_check_clocks(struct clk *clks[], unsigned int count);
> void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
> --
> 2.25.1
>
On 22-02-28 20:41:12, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> If mcore_booted is true, ignore the clk root gate registration and
> this will simplify AMP clock management and avoid system hang unexpectly
> especially Linux shutdown clk used by mcore.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
>
> V2:
> None
>
> drivers/clk/imx/clk-composite-8m.c | 21 +++++++++++++--------
> 1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
> index 2dfd6149e528..b16c2c0ea9f6 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -223,14 +223,19 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
> div->lock = &imx_ccm_lock;
> div->flags = CLK_DIVIDER_ROUND_CLOSEST;
>
> - gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> - if (!gate)
> - goto fail;
> -
> - gate_hw = &gate->hw;
> - gate->reg = reg;
> - gate->bit_idx = PCG_CGC_SHIFT;
> - gate->lock = &imx_ccm_lock;
> + /* skip registering the gate ops if M4 is enabled */
> + if (mcore_booted) {
> + gate_hw = NULL;
Lets have the gate_hw set to NULL when declared and get rid of this if
case.
> + } else {
And then lets do here:
if (!mcore_booted) {
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto fail;
> +
> + gate_hw = &gate->hw;
> + gate->reg = reg;
> + gate->bit_idx = PCG_CGC_SHIFT;
> + gate->lock = &imx_ccm_lock;
> + }
>
Would look a bit cleaner this way.
With that done:
Reviewed-by: Abel Vesa <[email protected]>
> hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> mux_hw, mux_ops, div_hw,
> --
> 2.25.1
>
On 22-02-28 20:41:11, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Add mcore_booted boot parameter which could simplify AMP clock
> management. To i.MX8M, there is CCM(clock control Module) to generate
> clock root clock, anatop(analog PLL module) to generate PLL, and CCGR
> (clock gating) to gate clocks to peripherals. As below:
> anatop->ccm->ccgr->peripheral
>
> Linux handles the clock management and the auxiliary core is under
> control of Linux. Although there is per hardware domain control for CCGR
> and CCM, auxiliary core normally only use CCGR hardware domain control
> to avoid linux gate off the clk to peripherals and leave CCM ana anatop
> to Linux.
>
> Per NXP hardware design, because CCGR already support gate to
> peripherals, and clk root gate power leakage is negligible. So
> when in AMP case, we could not register the clk root gate.
>
> Signed-off-by: Peng Fan <[email protected]>
I agree with this approach since every other option complicates things
more.
Reviewed-by: Abel Vesa <[email protected]>
> ---
>
> V2:
> Switch to use module parameter, tested on i.MX8MP-EVK
>
> drivers/clk/imx/clk-imx8mm.c | 2 ++
> drivers/clk/imx/clk-imx8mn.c | 2 ++
> drivers/clk/imx/clk-imx8mp.c | 2 ++
> drivers/clk/imx/clk-imx8mq.c | 2 ++
> drivers/clk/imx/clk.c | 3 +++
> drivers/clk/imx/clk.h | 1 +
> 6 files changed, 12 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index e8cbe181ec06..a452fd1bb891 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -639,6 +639,8 @@ static struct platform_driver imx8mm_clk_driver = {
> },
> };
> module_platform_driver(imx8mm_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Bai Ping <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MM clock driver");
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index 92fcbab4f5be..dc69b7464b3d 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -594,6 +594,8 @@ static struct platform_driver imx8mn_clk_driver = {
> },
> };
> module_platform_driver(imx8mn_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Anson Huang <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MN clock driver");
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 18f5b7c3ca9d..250e45d9f844 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -721,6 +721,8 @@ static struct platform_driver imx8mp_clk_driver = {
> },
> };
> module_platform_driver(imx8mp_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Anson Huang <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MP clock driver");
> diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
> index 83cc2b1c3294..33897b56130d 100644
> --- a/drivers/clk/imx/clk-imx8mq.c
> +++ b/drivers/clk/imx/clk-imx8mq.c
> @@ -632,6 +632,8 @@ static struct platform_driver imx8mq_clk_driver = {
> },
> };
> module_platform_driver(imx8mq_clk_driver);
> +module_param(mcore_booted, bool, S_IRUGO);
> +MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
>
> MODULE_AUTHOR("Abel Vesa <[email protected]>");
> MODULE_DESCRIPTION("NXP i.MX8MQ clock driver");
> diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
> index 7cc669934253..4bd6ad060eea 100644
> --- a/drivers/clk/imx/clk.c
> +++ b/drivers/clk/imx/clk.c
> @@ -17,6 +17,9 @@
> DEFINE_SPINLOCK(imx_ccm_lock);
> EXPORT_SYMBOL_GPL(imx_ccm_lock);
>
> +bool mcore_booted;
> +EXPORT_SYMBOL_GPL(mcore_booted);
> +
> void imx_unregister_clocks(struct clk *clks[], unsigned int count)
> {
> unsigned int i;
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index a7cbbcd1a3f4..5061a06468df 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -7,6 +7,7 @@
> #include <linux/clk-provider.h>
>
> extern spinlock_t imx_ccm_lock;
> +extern bool mcore_booted;
>
> void imx_check_clocks(struct clk *clks[], unsigned int count);
> void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
> --
> 2.25.1
>
On 22-04-12 11:11:17, Abel Vesa wrote:
> On 22-02-28 20:41:12, Peng Fan (OSS) wrote:
> > From: Peng Fan <[email protected]>
> >
> > If mcore_booted is true, ignore the clk root gate registration and
> > this will simplify AMP clock management and avoid system hang unexpectly
> > especially Linux shutdown clk used by mcore.
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> >
> > V2:
> > None
> >
> > drivers/clk/imx/clk-composite-8m.c | 21 +++++++++++++--------
> > 1 file changed, 13 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
> > index 2dfd6149e528..b16c2c0ea9f6 100644
> > --- a/drivers/clk/imx/clk-composite-8m.c
> > +++ b/drivers/clk/imx/clk-composite-8m.c
> > @@ -223,14 +223,19 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
> > div->lock = &imx_ccm_lock;
> > div->flags = CLK_DIVIDER_ROUND_CLOSEST;
> >
> > - gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> > - if (!gate)
> > - goto fail;
> > -
> > - gate_hw = &gate->hw;
> > - gate->reg = reg;
> > - gate->bit_idx = PCG_CGC_SHIFT;
> > - gate->lock = &imx_ccm_lock;
> > + /* skip registering the gate ops if M4 is enabled */
> > + if (mcore_booted) {
> > + gate_hw = NULL;
>
> Lets have the gate_hw set to NULL when declared and get rid of this if
> case.
>
On a second thought, no need to resend, I'll squash this in myself.
> > + } else {
>
> And then lets do here:
>
> if (!mcore_booted) {
> > + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> > + if (!gate)
> > + goto fail;
> > +
> > + gate_hw = &gate->hw;
> > + gate->reg = reg;
> > + gate->bit_idx = PCG_CGC_SHIFT;
> > + gate->lock = &imx_ccm_lock;
> > + }
> >
>
> Would look a bit cleaner this way.
>
> With that done:
>
> Reviewed-by: Abel Vesa <[email protected]>
>
> > hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> > mux_hw, mux_ops, div_hw,
> > --
> > 2.25.1
> >