The patch set in general is to add support for the VSC7512, and
eventually the VSC7511, VSC7513 and VSC7514 devices controlled over
SPI. Specifically this patch set enables pinctrl, serial gpio expander
access, and control of an internal and an external MDIO bus.
I have mentioned previously:
The hardware setup I'm using for development is a beaglebone black, with
jumpers from SPI0 to the microchip VSC7512 dev board. The microchip dev
board has been modified to not boot from flash, but wait for SPI. An
ethernet cable is connected from the beaglebone ethernet to port 0 of
the dev board. Network functionality will be included in a future patch set.
The device tree I'm using is included in the documentation, so I'll not
include that in this cover letter. I have exported the serial GPIOs to the
LEDs, and verified functionality via
"echo heartbeat > sys/class/leds/port0led/trigger"
/ {
vscleds {
compatible = "gpio-leds";
vscled@0 {
label = "port0led";
gpios = <&sgpio_out1 0 0 GPIO_ACTIVE_LOW>;
default-state = "off";
};
vscled@1 {
label = "port0led1";
gpios = <&sgpio_out1 0 1 GPIO_ACTIVE_LOW>;
default-state = "off";
};
[ ... ]
};
};
And I'll include the relevant dmesg prints - I don't love the "invalid
resource" prints, as they seem to be misleading. They're a byproduct of
looking for IO resources before falling back to REG, which succeeds.
Booting Linux on physical CPU 0x0
Linux version 5.19.0-rc3-00662-gb661f062e865
...
[ 1.930121] pinctrl-ocelot ocelot-pinctrl.0.auto: DMA mask not set
[ 1.930287] pinctrl-ocelot ocelot-pinctrl.0.auto: invalid resource
[ 1.930861] gpiochip_find_base: found new base at 2026
[ 1.930912] gpio gpiochip4: (ocelot-gpio): created GPIO range 0->21 ==> ocelot-pinctrl.0.auto PIN 0->21
[ 1.933211] gpio gpiochip4: (ocelot-gpio): added GPIO chardev (254:4)
[ 1.933358] gpio gpiochip4: registered GPIOs 2026 to 2047 on ocelot-gpio
[ 1.933378] pinctrl-ocelot ocelot-pinctrl.0.auto: driver registered
[ 1.951876] pinctrl-microchip-sgpio ocelot-sgpio.1.auto: DMA mask not set
[ 1.952100] pinctrl-microchip-sgpio ocelot-sgpio.1.auto: invalid resource
[ 1.952971] gpiochip_find_base: found new base at 1962
[ 1.953710] gpio_stub_drv gpiochip5: (ocelot-sgpio.1.auto-input): added GPIO chardev (254:5)
[ 1.953822] gpio_stub_drv gpiochip5: registered GPIOs 1962 to 2025 on ocelot-sgpio.1.auto-input
[ 1.954612] gpiochip_find_base: found new base at 1898
[ 1.955513] gpio_stub_drv gpiochip6: (ocelot-sgpio.1.auto-output): added GPIO chardev (254:6)
[ 1.955611] gpio_stub_drv gpiochip6: registered GPIOs 1898 to 1961 on ocelot-sgpio.1.auto-output
[ 1.963280] mscc-miim ocelot-miim0.2.auto: DMA mask not set
[ 1.963432] mscc-miim ocelot-miim0.2.auto: invalid resource
[ 1.963585] mscc-miim ocelot-miim0.2.auto: invalid resource
[ 1.964633] mdio_bus ocelot-miim0.2.auto-mii: GPIO lookup for consumer reset
[ 1.964651] mdio_bus ocelot-miim0.2.auto-mii: using device tree for GPIO lookup
[ 1.964676] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/interconnect@48000000/segment@0/target-module@30000/spi@0/switch@0/mdio@7107009c[0]'
[ 1.964767] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/interconnect@48000000/segment@0/target-module@30000/spi@0/switch@0/mdio@7107009c[0]'
[ 1.964857] mdio_bus ocelot-miim0.2.auto-mii: using lookup tables for GPIO lookup
[ 1.964868] mdio_bus ocelot-miim0.2.auto-mii: No GPIO consumer reset found
I only have hardware to test the last patch, so any testers are welcome.
I've been extra cautious about the
ocelot_platform_init_regmap_from_resource helper function, both before
and after the last patch. I accidentally broke it in the past and would
like to avoid doing so again.
RFC history:
v1 (accidentally named vN)
* Initial architecture. Not functional
* General concepts laid out
v2
* Near functional. No CPU port communication, but control over all
external ports
* Cleaned up regmap implementation from v1
v3
* Functional
* Shared MDIO transactions routed through mdio-mscc-miim
* CPU / NPI port enabled by way of vsc7512_enable_npi_port /
felix->info->enable_npi_port
* NPI port tagging functional - Requires a CPU port driver that supports
frames of 1520 bytes. Verified with a patch to the cpsw driver
v4
* Functional
* Device tree fixes
* Add hooks for pinctrl-ocelot - some functionality by way of sysfs
* Add hooks for pinctrl-microsemi-sgpio - not yet fully functional
* Remove lynx_pcs interface for a generic phylink_pcs. The goal here
is to have an ocelot_pcs that will work for each configuration of
every port.
v5
* Restructured to MFD
* Several commits were split out, submitted, and accepted
* pinctrl-ocelot believed to be fully functional (requires commits
from the linux-pinctrl tree)
* External MDIO bus believed to be fully functional
v6
* Applied several suggestions from the last RFC from Lee Jones. I
hope I didn't miss anything.
* Clean up MFD core - SPI interaction. They no longer use callbacks.
* regmaps get registered to the child device, and don't attempt to
get shared. It seems if a regmap is to be shared, that should be
solved with syscon, not dev or mfd.
v7
* Applied as much as I could from Lee and Vladimir's suggestions. As
always, the feedback is greatly appreciated!
* Remove "ocelot_spi" container complication
* Move internal MDIO bus from ocelot_ext to MFD, with a devicetree
change to match
* Add initial HSIO support
* Switch to IORESOURCE_REG for resource definitions
v8
* Applied another round of suggestions from Lee and Vladimir
* Utilize regmap bus reads, which speeds bulk transfers up by an
order of magnitude
* Add two additional patches to utilize phylink_generic_validate
* Changed GPL V2 to GPL in licenses where applicable (checkpatch)
* Remove initial hsio/serdes changes from the RFC
v9
* Submitting as a PATCH instead of an RFC
* Remove switch functionality - will be a separate patch set
* Remove Kconfig tristate module options
* Another round of suggestions from Lee, Vladimir, and Andy. Many
thanks!
* Add documentation
* Update maintainers
v10
* Fix warming by removing unused function
v11
* Suggestions from Rob and Andy. Thanks!
* Add pinctrl module functionality back and fixing those features
* Fix aarch64 compiler error
Colin Foster (9):
mfd: ocelot: add helper to get regmap from a resource
net: mdio: mscc-miim: add ability to be used in a non-mmio
configuration
pinctrl: ocelot: allow pinctrl-ocelot to be loaded as a module
pinctrl: ocelot: add ability to be used in a non-mmio configuration
pinctrl: microchip-sgpio: allow sgpio driver to be used as a module
pinctrl: microchip-sgpio: add ability to be used in a non-mmio
configuration
resource: add define macro for register address resources
dt-bindings: mfd: ocelot: add bindings for VSC7512
mfd: ocelot: add support for the vsc7512 chip via spi
.../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 +++++++++
MAINTAINERS | 7 +
drivers/mfd/Kconfig | 18 +
drivers/mfd/Makefile | 2 +
drivers/mfd/ocelot-core.c | 175 ++++++++++
drivers/mfd/ocelot-spi.c | 313 ++++++++++++++++++
drivers/mfd/ocelot.h | 28 ++
drivers/net/mdio/mdio-mscc-miim.c | 35 +-
drivers/pinctrl/Kconfig | 4 +-
drivers/pinctrl/pinctrl-microchip-sgpio.c | 14 +-
drivers/pinctrl/pinctrl-ocelot.c | 15 +-
include/linux/ioport.h | 5 +
include/linux/mfd/ocelot.h | 35 ++
13 files changed, 773 insertions(+), 38 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
create mode 100644 drivers/mfd/ocelot-core.c
create mode 100644 drivers/mfd/ocelot-spi.c
create mode 100644 drivers/mfd/ocelot.h
create mode 100644 include/linux/mfd/ocelot.h
--
2.25.1
There are a few Ocelot chips that contain the logic for this bus, but are
controlled externally. Specifically the VSC7511, 7512, 7513, and 7514. In
the externally controlled configurations these registers are not
memory-mapped.
Add support for these non-memory-mapped configurations.
Signed-off-by: Colin Foster <[email protected]>
---
drivers/net/mdio/mdio-mscc-miim.c | 35 +++++++++++--------------------
1 file changed, 12 insertions(+), 23 deletions(-)
diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c
index 08541007b18a..157c0b196eab 100644
--- a/drivers/net/mdio/mdio-mscc-miim.c
+++ b/drivers/net/mdio/mdio-mscc-miim.c
@@ -12,6 +12,7 @@
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mdio/mdio-mscc-miim.h>
+#include <linux/mfd/ocelot.h>
#include <linux/module.h>
#include <linux/of_mdio.h>
#include <linux/phy.h>
@@ -270,40 +271,27 @@ static int mscc_miim_clk_set(struct mii_bus *bus)
static int mscc_miim_probe(struct platform_device *pdev)
{
- struct regmap *mii_regmap, *phy_regmap = NULL;
struct device_node *np = pdev->dev.of_node;
+ struct regmap *mii_regmap, *phy_regmap;
struct device *dev = &pdev->dev;
- void __iomem *regs, *phy_regs;
struct mscc_miim_dev *miim;
- struct resource *res;
struct mii_bus *bus;
int ret;
- regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
- if (IS_ERR(regs)) {
- dev_err(dev, "Unable to map MIIM registers\n");
- return PTR_ERR(regs);
- }
-
- mii_regmap = devm_regmap_init_mmio(dev, regs, &mscc_miim_regmap_config);
-
+ mii_regmap = ocelot_platform_init_regmap_from_resource(pdev, 0,
+ &mscc_miim_regmap_config);
if (IS_ERR(mii_regmap)) {
dev_err(dev, "Unable to create MIIM regmap\n");
return PTR_ERR(mii_regmap);
}
- /* This resource is optional */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (res) {
- phy_regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(phy_regs)) {
- dev_err(dev, "Unable to map internal phy registers\n");
- return PTR_ERR(phy_regs);
- }
-
- phy_regmap = devm_regmap_init_mmio(dev, phy_regs,
- &mscc_miim_phy_regmap_config);
- if (IS_ERR(phy_regmap)) {
+ /* This resource is optional, so ENOENT can be ignored */
+ phy_regmap = ocelot_platform_init_regmap_from_resource(pdev, 1,
+ &mscc_miim_phy_regmap_config);
+ if (IS_ERR(phy_regmap)) {
+ if (phy_regmap == ERR_PTR(-ENOENT)) {
+ phy_regmap = NULL;
+ } else {
dev_err(dev, "Unable to create phy register regmap\n");
return PTR_ERR(phy_regmap);
}
@@ -404,3 +392,4 @@ module_platform_driver(mscc_miim_driver);
MODULE_DESCRIPTION("Microsemi MIIM driver");
MODULE_AUTHOR("Alexandre Belloni <[email protected]>");
MODULE_LICENSE("Dual MIT/GPL");
+MODULE_IMPORT_NS(MFD_OCELOT);
--
2.25.1
Work is being done to allow external control of Ocelot chips. When pinctrl
drivers are used internally, it wouldn't make much sense to allow them to
be loaded as modules. In the case where the Ocelot chip is controlled
externally, this scenario becomes practical.
Signed-off-by: Colin Foster <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
---
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-ocelot.c | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f52960d2dfbe..257b06752747 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -311,7 +311,7 @@ config PINCTRL_MICROCHIP_SGPIO
LED controller.
config PINCTRL_OCELOT
- bool "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
+ tristate "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs"
depends on OF
depends on HAS_IOMEM
select GPIOLIB
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index 5f4a8c5c6650..5554c3014448 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -1889,6 +1889,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = {
{ .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
{},
};
+MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);
static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
{
@@ -1985,3 +1986,6 @@ static struct platform_driver ocelot_pinctrl_driver = {
.probe = ocelot_pinctrl_probe,
};
builtin_platform_driver(ocelot_pinctrl_driver);
+
+MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver");
+MODULE_LICENSE("Dual MIT/GPL");
--
2.25.1
There are a few Ocelot chips that can contain SGPIO logic, but can be
controlled externally. Specifically the VSC7511, 7512, 7513, and 7514. In
the externally controlled configurations these registers are not
memory-mapped.
Add support for these non-memory-mapped configurations.
Signed-off-by: Colin Foster <[email protected]>
---
drivers/pinctrl/pinctrl-microchip-sgpio.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c
index 47b479c1fb7c..c924605f9d03 100644
--- a/drivers/pinctrl/pinctrl-microchip-sgpio.c
+++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c
@@ -12,6 +12,7 @@
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
+#include <linux/mfd/ocelot.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/pinctrl/pinmux.h>
@@ -904,7 +905,6 @@ static int microchip_sgpio_probe(struct platform_device *pdev)
struct reset_control *reset;
struct sgpio_priv *priv;
struct clk *clk;
- u32 __iomem *regs;
u32 val;
struct regmap_config regmap_config = {
.reg_bits = 32,
@@ -937,11 +937,8 @@ static int microchip_sgpio_probe(struct platform_device *pdev)
return -EINVAL;
}
- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
- return PTR_ERR(regs);
-
- priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config);
+ priv->regs = ocelot_platform_init_regmap_from_resource(pdev, 0,
+ ®map_config);
if (IS_ERR(priv->regs))
return PTR_ERR(priv->regs);
@@ -1013,3 +1010,4 @@ builtin_platform_driver(microchip_sgpio_pinctrl_driver);
MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");
MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS(MFD_OCELOT);
--
2.25.1
Add devicetree bindings for SPI-controlled Ocelot chips, specifically the
VSC7512.
Signed-off-by: Colin Foster <[email protected]>
---
.../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 161 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
new file mode 100644
index 000000000000..24fab9f5e319
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ocelot Externally-Controlled Ethernet Switch
+
+maintainers:
+ - Colin Foster <[email protected]>
+
+description: |
+ The Ocelot ethernet switch family contains chips that have an internal CPU
+ (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
+ the option to be controlled externally, which is the purpose of this driver.
+
+ The switch family is a multi-port networking switch that supports many
+ interfaces. Additionally, the device can perform pin control, MDIO buses, and
+ external GPIO expanders.
+
+properties:
+ compatible:
+ enum:
+ - mscc,vsc7512-spi
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ spi-max-frequency:
+ maxItems: 1
+
+patternProperties:
+ "^pinctrl@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
+
+ "^gpio@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
+ properties:
+ compatible:
+ enum:
+ - mscc,ocelot-sgpio
+
+ "^mdio@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/net/mscc,miim.yaml
+ properties:
+ compatible:
+ enum:
+ - mscc,ocelot-miim
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - spi-max-frequency
+
+additionalProperties: false
+
+examples:
+ - |
+ ocelot_clock: ocelot-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ switch@0 {
+ compatible = "mscc,vsc7512";
+ spi-max-frequency = <2500000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mdio@7107009c {
+ compatible = "mscc,ocelot-miim";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x7107009c 0x24>;
+
+ sw_phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ };
+ };
+
+ mdio@710700c0 {
+ compatible = "mscc,ocelot-miim";
+ pinctrl-names = "default";
+ pinctrl-0 = <&miim1_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x710700c0 0x24>;
+
+ sw_phy4: ethernet-phy@4 {
+ reg = <0x4>;
+ };
+ };
+
+ gpio: pinctrl@71070034 {
+ compatible = "mscc,ocelot-pinctrl";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&gpio 0 0 22>;
+ reg = <0x71070034 0x6c>;
+
+ sgpio_pins: sgpio-pins {
+ pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
+ function = "sg0";
+ };
+
+ miim1_pins: miim1-pins {
+ pins = "GPIO_14", "GPIO_15";
+ function = "miim";
+ };
+ };
+
+ gpio@710700f8 {
+ compatible = "mscc,ocelot-sgpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus-frequency = <12500000>;
+ clocks = <&ocelot_clock>;
+ microchip,sgpio-port-ranges = <0 15>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sgpio_pins>;
+ reg = <0x710700f8 0x100>;
+
+ sgpio_in0: gpio@0 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <64>;
+ };
+
+ sgpio_out1: gpio@1 {
+ compatible = "microchip,sparx5-sgpio-bank";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ ngpios = <64>;
+ };
+ };
+ };
+ };
+
+...
+
diff --git a/MAINTAINERS b/MAINTAINERS
index 4d9ccec78f18..03eba7fd2141 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14416,6 +14416,7 @@ F: tools/testing/selftests/drivers/net/ocelot/*
OCELOT EXTERNAL SWITCH CONTROL
M: Colin Foster <[email protected]>
S: Supported
+F: Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
F: include/linux/mfd/ocelot.h
OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER
--
2.25.1
DEFINE_RES_ macros have been created for the commonly used resource types,
but not IORESOURCE_REG. Add the macro so it can be used in a similar manner
to all other resource types.
Signed-off-by: Colin Foster <[email protected]>
---
include/linux/ioport.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index ec5f71f7135b..b0d09b6f2ecf 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -171,6 +171,11 @@ enum {
#define DEFINE_RES_MEM(_start, _size) \
DEFINE_RES_MEM_NAMED((_start), (_size), NULL)
+#define DEFINE_RES_REG_NAMED(_start, _size, _name) \
+ DEFINE_RES_NAMED((_start), (_size), (_name), IORESOURCE_REG)
+#define DEFINE_RES_REG(_start, _size) \
+ DEFINE_RES_REG_NAMED((_start), (_size), NULL)
+
#define DEFINE_RES_IRQ_NAMED(_irq, _name) \
DEFINE_RES_NAMED((_irq), 1, (_name), IORESOURCE_IRQ)
#define DEFINE_RES_IRQ(_irq) \
--
2.25.1
On Tue, Jun 28, 2022 at 10:17 AM Colin Foster
<[email protected]> wrote:
>
> Work is being done to allow external control of Ocelot chips. When pinctrl
> drivers are used internally, it wouldn't make much sense to allow them to
> be loaded as modules. In the case where the Ocelot chip is controlled
> externally, this scenario becomes practical.
...
> builtin_platform_driver(ocelot_pinctrl_driver);
This contradicts the logic behind this change. Perhaps you need to
move to module_platform_driver(). (Yes, I think functionally it won't
be any changes if ->remove() is not needed, but for the sake of
logical correctness...)
--
With Best Regards,
Andy Shevchenko
On Tue, 28 Jun 2022 01:17:08 -0700, Colin Foster wrote:
> Add devicetree bindings for SPI-controlled Ocelot chips, specifically the
> VSC7512.
>
> Signed-off-by: Colin Foster <[email protected]>
> ---
> .../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 161 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mfd/mscc,ocelot.example.dtb:0:0: /example-0/spi/switch@0: failed to match any schema with compatible: ['mscc,vsc7512']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Tue, Jun 28, 2022 at 01:17:02AM -0700, Colin Foster wrote:
> There are a few Ocelot chips that contain the logic for this bus, but are
> controlled externally. Specifically the VSC7511, 7512, 7513, and 7514. In
> the externally controlled configurations these registers are not
> memory-mapped.
>
> Add support for these non-memory-mapped configurations.
>
> Signed-off-by: Colin Foster <[email protected]>
> ---
These "add ability to be used in a non-MMIO configuration" commit
messages are very confusing when you are only adding support for
non-MMIO in ocelot_platform_init_regmap_from_resource() in patch 9/9.
May I suggest a reorder?
Hi Rob,
On Tue, Jun 28, 2022 at 07:15:23AM -0600, Rob Herring wrote:
> On Tue, 28 Jun 2022 01:17:08 -0700, Colin Foster wrote:
> > Add devicetree bindings for SPI-controlled Ocelot chips, specifically the
> > VSC7512.
> >
> > Signed-off-by: Colin Foster <[email protected]>
> > ---
> > .../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++
> > MAINTAINERS | 1 +
> > 2 files changed, 161 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/mfd/mscc,ocelot.example.dtb:0:0: /example-0/spi/switch@0: failed to match any schema with compatible: ['mscc,vsc7512']
>
Thanks for this info. I'll run this on my end before the next go round.
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
>
Hi Andy,
On Tue, Jun 28, 2022 at 02:53:49PM +0200, Andy Shevchenko wrote:
> On Tue, Jun 28, 2022 at 10:17 AM Colin Foster
> <[email protected]> wrote:
> >
> > Work is being done to allow external control of Ocelot chips. When pinctrl
> > drivers are used internally, it wouldn't make much sense to allow them to
> > be loaded as modules. In the case where the Ocelot chip is controlled
> > externally, this scenario becomes practical.
>
> ...
>
> > builtin_platform_driver(ocelot_pinctrl_driver);
>
> This contradicts the logic behind this change. Perhaps you need to
> move to module_platform_driver(). (Yes, I think functionally it won't
> be any changes if ->remove() is not needed, but for the sake of
> logical correctness...)
I'll do this. Thanks.
Process question: If I make this change is it typical to remove all
Reviewed-By tags? I assume "yes"
>
> --
> With Best Regards,
> Andy Shevchenko
Hi Vladimir,
On Tue, Jun 28, 2022 at 04:26:05PM +0000, Vladimir Oltean wrote:
> On Tue, Jun 28, 2022 at 01:17:02AM -0700, Colin Foster wrote:
> > There are a few Ocelot chips that contain the logic for this bus, but are
> > controlled externally. Specifically the VSC7511, 7512, 7513, and 7514. In
> > the externally controlled configurations these registers are not
> > memory-mapped.
> >
> > Add support for these non-memory-mapped configurations.
> >
> > Signed-off-by: Colin Foster <[email protected]>
> > ---
>
> These "add ability to be used in a non-MMIO configuration" commit
> messages are very confusing when you are only adding support for
> non-MMIO in ocelot_platform_init_regmap_from_resource() in patch 9/9.
> May I suggest a reorder?
Initially my plan was to get the MFD base functionality (SPI protocol,
chip reset, etc.) in and roll in each peripheral one at a time. That was
changed in v6 I believe...
Maybe a commit reword to suggest "utilize a helper function"?
On Tue, Jun 28, 2022 at 8:25 PM Colin Foster
<[email protected]> wrote:
> On Tue, Jun 28, 2022 at 02:53:49PM +0200, Andy Shevchenko wrote:
> > On Tue, Jun 28, 2022 at 10:17 AM Colin Foster
> > <[email protected]> wrote:
...
> > > builtin_platform_driver(ocelot_pinctrl_driver);
> >
> > This contradicts the logic behind this change. Perhaps you need to
> > move to module_platform_driver(). (Yes, I think functionally it won't
> > be any changes if ->remove() is not needed, but for the sake of
> > logical correctness...)
>
> I'll do this. Thanks.
>
> Process question: If I make this change is it typical to remove all
> Reviewed-By tags? I assume "yes"
I would not. This change is logical continuation and I truly believe
every reviewer will agree on it.
--
With Best Regards,
Andy Shevchenko
On Tue, Jun 28, 2022 at 9:00 PM Andy Shevchenko
<[email protected]> wrote:
>
> On Tue, Jun 28, 2022 at 8:25 PM Colin Foster
> <[email protected]> wrote:
> > On Tue, Jun 28, 2022 at 02:53:49PM +0200, Andy Shevchenko wrote:
> > > On Tue, Jun 28, 2022 at 10:17 AM Colin Foster
> > > <[email protected]> wrote:
>
> ...
>
> > > > builtin_platform_driver(ocelot_pinctrl_driver);
> > >
> > > This contradicts the logic behind this change. Perhaps you need to
> > > move to module_platform_driver(). (Yes, I think functionally it won't
> > > be any changes if ->remove() is not needed, but for the sake of
> > > logical correctness...)
> >
> > I'll do this. Thanks.
> >
> > Process question: If I make this change is it typical to remove all
> > Reviewed-By tags? I assume "yes"
>
> I would not. This change is logical continuation and I truly believe
> every reviewer will agree on it.
I would have to think hard to remember a single review comment from Andy
where I didn't think "ah, yeah he's right", so definately keep mine.
Yours,
Linus Walleij
On Tue, Jun 28, 2022 at 01:17:08AM -0700, Colin Foster wrote:
> Add devicetree bindings for SPI-controlled Ocelot chips, specifically the
> VSC7512.
>
> Signed-off-by: Colin Foster <[email protected]>
> ---
> .../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 161 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
> new file mode 100644
> index 000000000000..24fab9f5e319
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ocelot Externally-Controlled Ethernet Switch
> +
> +maintainers:
> + - Colin Foster <[email protected]>
> +
> +description: |
> + The Ocelot ethernet switch family contains chips that have an internal CPU
> + (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
> + the option to be controlled externally, which is the purpose of this driver.
> +
> + The switch family is a multi-port networking switch that supports many
> + interfaces. Additionally, the device can perform pin control, MDIO buses, and
> + external GPIO expanders.
> +
> +properties:
> + compatible:
> + enum:
> + - mscc,vsc7512-spi
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + spi-max-frequency:
> + maxItems: 1
> +
> +patternProperties:
> + "^pinctrl@[0-9a-f]+$":
> + type: object
> + $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
> +
> + "^gpio@[0-9a-f]+$":
> + type: object
> + $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
> + properties:
> + compatible:
> + enum:
> + - mscc,ocelot-sgpio
> +
> + "^mdio@[0-9a-f]+$":
> + type: object
> + $ref: /schemas/net/mscc,miim.yaml
> + properties:
> + compatible:
> + enum:
> + - mscc,ocelot-miim
> +
> +required:
> + - compatible
> + - reg
> + - '#address-cells'
> + - '#size-cells'
> + - spi-max-frequency
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + ocelot_clock: ocelot-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch@0 {
I wonder if "switch" is the best name for the top-level node, since
there should also be another "switch" child node inside for the _actual_
DSA bindings, which this example is not showing (leading to further
confusion IMO).
Hmm, would "soc" be an exaggerated name? It's a SPI-controlled SoC after
all.
> + compatible = "mscc,vsc7512";
> + spi-max-frequency = <2500000>;
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + mdio@7107009c {
> + compatible = "mscc,ocelot-miim";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x7107009c 0x24>;
> +
> + sw_phy0: ethernet-phy@0 {
> + reg = <0x0>;
> + };
> + };
> +
> + mdio@710700c0 {
> + compatible = "mscc,ocelot-miim";
> + pinctrl-names = "default";
> + pinctrl-0 = <&miim1_pins>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x710700c0 0x24>;
> +
> + sw_phy4: ethernet-phy@4 {
> + reg = <0x4>;
> + };
> + };
> +
> + gpio: pinctrl@71070034 {
> + compatible = "mscc,ocelot-pinctrl";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&gpio 0 0 22>;
> + reg = <0x71070034 0x6c>;
> +
> + sgpio_pins: sgpio-pins {
> + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
> + function = "sg0";
> + };
> +
> + miim1_pins: miim1-pins {
> + pins = "GPIO_14", "GPIO_15";
> + function = "miim";
> + };
> + };
> +
> + gpio@710700f8 {
> + compatible = "mscc,ocelot-sgpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + bus-frequency = <12500000>;
> + clocks = <&ocelot_clock>;
> + microchip,sgpio-port-ranges = <0 15>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sgpio_pins>;
> + reg = <0x710700f8 0x100>;
> +
> + sgpio_in0: gpio@0 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + ngpios = <64>;
> + };
> +
> + sgpio_out1: gpio@1 {
> + compatible = "microchip,sparx5-sgpio-bank";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <3>;
> + ngpios = <64>;
> + };
> + };
> + };
> + };
> +
> +...
> +
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 4d9ccec78f18..03eba7fd2141 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14416,6 +14416,7 @@ F: tools/testing/selftests/drivers/net/ocelot/*
> OCELOT EXTERNAL SWITCH CONTROL
> M: Colin Foster <[email protected]>
> S: Supported
> +F: Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml
> F: include/linux/mfd/ocelot.h
>
> OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER
> --
> 2.25.1
>