Hello,
This series adds HS-G4 support to the Qcom UFS driver and PHY driver.
The newer Qcom platforms support configuring the UFS controller and PHY
in dual gears (i.e., controller/PHY can be configured to run in two gear
speeds). This is accomplished by adding two different PHY init sequences
to the PHY driver and the UFS driver requesting the one that's required
based on the platform configuration.
Initially the ufs-qcom driver will use the default gear G2 for enumerating
the UFS device. Afer enumeration, the max gear supported by both the
controller and device would be found out and that will be used thereafter.
But for using the max gear after enumeration, the ufs-qcom driver requires
the UFS device to be reinitialized. For this purpose, a separate quirk has
been introduced in the UFS core along with a callback and those will be used
by the ufs-qcom driver.
This series has been tested on following platforms:
* Qcom RB5 development platform powered by SM8250 SoC
* SM8450 based dev board
Merging Strategy:
-----------------
The PHY patches are expected to go through PHY tree and UFS, MAINTAINERS
patches are expected to go through SCSI tree.
NOTE: Since this series targets multiple SoCs (base like SM8350) and
(derivative like SC8280XP), testing on all of these platforms is really
appreciated. Although, if the series works for base SoC, then for derivatives
also it should work.
Thanks,
Mani
Changes in v4:
* Dropped HS G3 specific setting from SM8350 default init sequence
* Added G4 support to SM8350 and SC8280XP
* Covered all qcom files under drivers/ufs/host in MAINTAINERS file
* Added missing Suggested-by tags for Can Guo
* Rebased on top of linux-next 20221201
Changes in v3:
* Dropped the "device-max-gear" DT property and switched to reinitialization (Krzysztof)
* Added HS-G4 support to all compatible SoCs (SM8150, SM8250 and SM8450). This will also
benefit the derivative SoCs of these platforms like SC8180x, SC8280x etc...
* Splitted the qmp_phy_init_tbl changes into separate patches (Vinod)
* Collected reviews from Andrew H
Changes in v2:
* Collected reviews from Dmitry
* Renamed "max-gear" property to "max-device-gear"
* Used min() for deciding which gear to use instead of open comparision
* Added comment about the old register name
Manivannan Sadhasivam (23):
phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl
definitions
phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions
phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct
phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode
phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode
phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC
phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC
phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC
phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC
scsi: ufs: ufs-qcom: Remove un-necessary goto statements
scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON()
scsi: ufs: ufs-qcom: Use bitfields where appropriate
scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error
scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0
scsi: ufs: core: Add reinit_notify() callback
scsi: ufs: core: Add support for reinitializing the UFS device
scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear
scsi: ufs: ufs-qcom: Add support for reinitializing the UFS device
scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms
MAINTAINERS: Add myself as the maintainer for Qcom UFS drivers
MAINTAINERS | 8 +
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 454 +++++++++++++-----
drivers/ufs/core/ufshcd-priv.h | 6 +
drivers/ufs/core/ufshcd.c | 63 ++-
drivers/ufs/host/ufs-qcom.c | 170 +++----
drivers/ufs/host/ufs-qcom.h | 70 +--
include/ufs/ufshcd.h | 8 +
8 files changed, 532 insertions(+), 248 deletions(-)
--
2.25.1
goto in error path is useful if the function needs to do cleanup other
than returning the error code. But in this driver, goto statements are
used for just returning the error code in many places. This really
makes it hard to read the code.
So let's get rid of those goto statements and just return the error code
directly.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++---------------------
1 file changed, 41 insertions(+), 59 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 8ad1415e10b6..7cd996ac180b 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
{
- int err = 0;
+ int err;
struct device *dev = host->hba->dev;
if (host->is_lane_clks_enabled)
@@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
host->rx_l0_sync_clk);
if (err)
- goto out;
+ return err;
err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
host->tx_l0_sync_clk);
@@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
goto disable_rx_l1;
host->is_lane_clks_enabled = true;
- goto out;
+
+ return 0;
disable_rx_l1:
clk_disable_unprepare(host->rx_l1_sync_clk);
@@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
clk_disable_unprepare(host->tx_l0_sync_clk);
disable_rx_l0:
clk_disable_unprepare(host->rx_l0_sync_clk);
-out:
+
return err;
}
@@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
&host->rx_l0_sync_clk, false);
if (err)
- goto out;
+ return err;
err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
&host->tx_l0_sync_clk, false);
if (err)
- goto out;
+ return err;
/* In case of single lane per direction, don't read lane1 clocks */
if (host->hba->lanes_per_direction > 1) {
err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
&host->rx_l1_sync_clk, false);
if (err)
- goto out;
+ return err;
err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
&host->tx_l1_sync_clk, true);
}
-out:
- return err;
+
+ return 0;
}
static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
@@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
if (!host->core_reset) {
dev_warn(hba->dev, "%s: reset control not set\n", __func__);
- goto out;
+ return 0;
}
reenable_intr = hba->is_irq_enabled;
@@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
if (ret) {
dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
__func__, ret);
- goto out;
+ return ret;
}
/*
@@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
hba->is_irq_enabled = true;
}
-out:
- return ret;
+ return 0;
}
static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct phy *phy = host->generic_phy;
- int ret = 0;
+ int ret;
bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B;
/* Reset UFS Host Controller and PHY */
@@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
if (ret) {
dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
__func__, ret);
- goto out;
+ return ret;
}
/* power on phy - start serdes and phy's power and clocks */
@@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
out_disable_phy:
phy_exit(phy);
-out:
+
return ret;
}
@@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
u32 hs, u32 rate, bool update_link_startup_timer)
{
- int ret = 0;
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct ufs_clk_info *clki;
u32 core_clk_period_in_ns;
@@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
* Aggregation logic.
*/
if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
- goto out;
+ return 0;
if (gear == 0) {
dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
- goto out_error;
+ return -EINVAL;
}
list_for_each_entry(clki, &hba->clk_list_head, list) {
@@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
}
if (ufs_qcom_cap_qunipro(host))
- goto out;
+ return 0;
core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
@@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
"%s: index %d exceeds table size %zu\n",
__func__, gear,
ARRAY_SIZE(hs_fr_table_rA));
- goto out_error;
+ return -EINVAL;
}
tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
} else if (rate == PA_HS_MODE_B) {
@@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
"%s: index %d exceeds table size %zu\n",
__func__, gear,
ARRAY_SIZE(hs_fr_table_rB));
- goto out_error;
+ return -EINVAL;
}
tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
} else {
dev_err(hba->dev, "%s: invalid rate = %d\n",
__func__, rate);
- goto out_error;
+ return -EINVAL;
}
break;
case SLOWAUTO_MODE:
@@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
"%s: index %d exceeds table size %zu\n",
__func__, gear,
ARRAY_SIZE(pwm_fr_table));
- goto out_error;
+ return -EINVAL;
}
tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
break;
case UNCHANGED:
default:
dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
- goto out_error;
+ return -EINVAL;
}
if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
@@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
*/
mb();
}
- goto out;
-out_error:
- ret = -EINVAL;
-out:
- return ret;
+ return 0;
}
static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
@@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
0, true)) {
dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
__func__);
- err = -EINVAL;
- goto out;
+ return -EINVAL;
}
if (ufs_qcom_cap_qunipro(host))
@@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
break;
}
-out:
return err;
}
@@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
if (!dev_req_params) {
pr_err("%s: incoming dev_req_params is NULL\n", __func__);
- ret = -EINVAL;
- goto out;
+ return -EINVAL;
}
switch (status) {
@@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
if (ret) {
pr_err("%s: failed to determine capabilities\n",
__func__);
- goto out;
+ return ret;
}
/* enable the device ref clock before changing to HS mode */
@@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
ret = -EINVAL;
break;
}
-out:
+
return ret;
}
@@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
&pa_vs_config_reg1);
if (err)
- goto out;
+ return err;
/* Allow extension of MSB bits of PA_SaveConfigTime attribute */
- err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
+ return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
(pa_vs_config_reg1 | (1 << 12)));
-
-out:
- return err;
}
static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
@@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba)
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
if (!host) {
- err = -ENOMEM;
dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
- goto out;
+ return -ENOMEM;
}
/* Make a two way bind between the qcom host and the hba */
@@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba)
host->rcdev.owner = dev->driver->owner;
host->rcdev.nr_resets = 1;
err = devm_reset_controller_register(dev, &host->rcdev);
- if (err) {
+ if (err)
dev_warn(dev, "Failed to register reset controller\n");
- err = 0;
- }
if (!has_acpi_companion(dev)) {
host->generic_phy = devm_phy_get(dev, "ufsphy");
@@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba)
host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
ufs_qcom_get_default_testbus_cfg(host);
err = ufs_qcom_testbus_config(host);
- if (err) {
+ if (err)
+ /* Failure is non-fatal */
dev_warn(dev, "%s: failed to configure the testbus %d\n",
__func__, err);
- err = 0;
- }
- goto out;
+ return 0;
out_variant_clear:
ufshcd_set_variant(hba, NULL);
-out:
+
return err;
}
@@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
&core_clk_ctrl_reg);
if (err)
- goto out;
+ return err;
core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
core_clk_ctrl_reg |= clk_cycles;
@@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
/* Clear CORE_CLK_DIV_EN */
core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
- err = ufshcd_dme_set(hba,
+ return ufshcd_dme_set(hba,
UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
core_clk_ctrl_reg);
-out:
- return err;
}
static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
@@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
if (err || !dev_req_params) {
ufshcd_uic_hibern8_exit(hba);
- goto out;
+ return err;
}
ufs_qcom_cfg_timers(hba,
@@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
ufshcd_uic_hibern8_exit(hba);
}
-out:
- return err;
+ return 0;
}
static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
--
2.25.1
Use bitfield macros where appropriate to simplify the driver.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++--------------------
1 file changed, 28 insertions(+), 33 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 44466a395bb5..9d96ac71b27f 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -17,12 +17,9 @@
#define DEFAULT_CLK_RATE_HZ 1000000
#define BUS_VECTOR_NAME_LEN 32
-#define UFS_HW_VER_MAJOR_SHFT (28)
-#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT)
-#define UFS_HW_VER_MINOR_SHFT (16)
-#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT)
-#define UFS_HW_VER_STEP_SHFT (0)
-#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT)
+#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28)
+#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16)
+#define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
/* vendor specific pre-defined parameters */
#define SLOW 1
@@ -76,24 +73,28 @@ enum {
#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
/* bit definitions for REG_UFS_CFG1 register */
-#define QUNIPRO_SEL 0x1
-#define UTP_DBG_RAMS_EN 0x20000
+#define QUNIPRO_SEL BIT(0)
+#define UFS_PHY_SOFT_RESET BIT(1)
+#define UTP_DBG_RAMS_EN BIT(17)
#define TEST_BUS_EN BIT(18)
#define TEST_BUS_SEL GENMASK(22, 19)
#define UFS_REG_TEST_BUS_EN BIT(30)
+#define UFS_PHY_RESET_ENABLE 1
+#define UFS_PHY_RESET_DISABLE 0
+
/* bit definitions for REG_UFS_CFG2 register */
-#define UAWM_HW_CGC_EN (1 << 0)
-#define UARM_HW_CGC_EN (1 << 1)
-#define TXUC_HW_CGC_EN (1 << 2)
-#define RXUC_HW_CGC_EN (1 << 3)
-#define DFC_HW_CGC_EN (1 << 4)
-#define TRLUT_HW_CGC_EN (1 << 5)
-#define TMRLUT_HW_CGC_EN (1 << 6)
-#define OCSC_HW_CGC_EN (1 << 7)
+#define UAWM_HW_CGC_EN BIT(0)
+#define UARM_HW_CGC_EN BIT(1)
+#define TXUC_HW_CGC_EN BIT(2)
+#define RXUC_HW_CGC_EN BIT(3)
+#define DFC_HW_CGC_EN BIT(4)
+#define TRLUT_HW_CGC_EN BIT(5)
+#define TMRLUT_HW_CGC_EN BIT(6)
+#define OCSC_HW_CGC_EN BIT(7)
/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
-#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */
+#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
#define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
@@ -101,17 +102,11 @@ enum {
TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
/* bit offset */
-enum {
- OFFSET_UFS_PHY_SOFT_RESET = 1,
- OFFSET_CLK_NS_REG = 10,
-};
+#define OFFSET_CLK_NS_REG 0xa
/* bit masks */
-enum {
- MASK_UFS_PHY_SOFT_RESET = 0x2,
- MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF,
- MASK_CLK_NS_REG = 0xFFFC00,
-};
+#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0)
+#define MASK_CLK_NS_REG GENMASK(23, 10)
/* QCOM UFS debug print bit mask */
#define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0)
@@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba,
{
u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
- *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
- *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
- *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
+ *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
+ *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
+ *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
};
static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
{
- ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
- 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
+ ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE),
+ REG_UFS_CFG1);
/*
* Make sure assertion of ufs phy reset is written to
@@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
{
- ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
- 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
+ ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE),
+ REG_UFS_CFG1);
/*
* Make sure de-assertion of ufs phy reset is written to
--
2.25.1
Starting from Qualcomm UFS version 4, the UFS device needs to be
reinitialized after switching to maximum gear by the UFS core. Hence, add
support for it by enabling the UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH
quirk, implementing reinit_notify() callback and using the agreed gear
speed for setting the PHY mode.
Suggested-by: Can Guo <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 26 ++++++++++++++++++++++----
drivers/ufs/host/ufs-qcom.h | 2 ++
2 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 919b6eae439d..3efef2f36e69 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -302,7 +302,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct phy *phy = host->generic_phy;
int ret;
- bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B;
/* Reset UFS Host Controller and PHY */
ret = ufs_qcom_host_reset(hba);
@@ -310,9 +309,6 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
dev_warn(hba->dev, "%s: host reset returned %d\n",
__func__, ret);
- if (is_rate_B)
- phy_set_mode(phy, PHY_MODE_UFS_HS_B);
-
/* phy initialization - calibrate the phy */
ret = phy_init(phy);
if (ret) {
@@ -321,6 +317,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
return ret;
}
+ phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear);
+
/* power on phy - start serdes and phy's power and clocks */
ret = phy_power_on(phy);
if (ret) {
@@ -723,6 +721,9 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
return ret;
}
+ /* Use the agreed gear */
+ host->hs_gear = dev_req_params->gear_tx;
+
/* enable the device ref clock before changing to HS mode */
if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
ufshcd_is_hs_mode(dev_req_params))
@@ -836,6 +837,9 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
| UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
| UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP);
}
+
+ if (host->hw_ver.major > 0x3)
+ hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
}
static void ufs_qcom_set_caps(struct ufs_hba *hba)
@@ -1044,6 +1048,12 @@ static int ufs_qcom_init(struct ufs_hba *hba)
dev_warn(dev, "%s: failed to configure the testbus %d\n",
__func__, err);
+ /*
+ * Power up the PHY using the minimum supported gear (UFS_HS_G2).
+ * Switching to max gear will be performed during reinit if supported.
+ */
+ host->hs_gear = UFS_HS_G2;
+
return 0;
out_variant_clear:
@@ -1410,6 +1420,13 @@ static void ufs_qcom_config_scaling_param(struct ufs_hba *hba,
}
#endif
+static void ufs_qcom_reinit_notify(struct ufs_hba *hba)
+{
+ struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+
+ phy_power_off(host->generic_phy);
+}
+
/*
* struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
*
@@ -1433,6 +1450,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
.device_reset = ufs_qcom_device_reset,
.config_scaling_param = ufs_qcom_config_scaling_param,
.program_key = ufs_qcom_ice_program_key,
+ .reinit_notify = ufs_qcom_reinit_notify,
};
/**
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 7fe928b82753..4b00c67e9d7f 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -217,6 +217,8 @@ struct ufs_qcom_host {
struct reset_controller_dev rcdev;
struct gpio_desc *device_reset;
+
+ u32 hs_gear;
};
static inline u32
--
2.25.1
UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 97d0baa9bac3..269f96a0f752 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -374,6 +374,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
};
+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
+};
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
@@ -411,6 +415,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
};
+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+};
+
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
@@ -421,6 +444,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
+};
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
@@ -762,6 +790,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
+ .tbls_hs_g4 = {
+ .tx = sm8150_ufsphy_hs_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
+ .rx = sm8150_ufsphy_hs_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
+ .pcs = sm8150_ufsphy_hs_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
--
2.25.1
Starting from Qcom UFS version 4.0, vendor specific REG_UFS_PARAM0 register
can be used to determine the maximum gear supported by the controller.
Suggested-by: Can Guo <[email protected]>
Reviewed-by: Andrew Halaney <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 2 ++
drivers/ufs/host/ufs-qcom.h | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 3efef2f36e69..607fddb7b4c3 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -291,6 +291,8 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
* Hence downgrade the maximum supported gear to HS-G2.
*/
return UFS_HS_G2;
+ } else if (host->hw_ver.major >= 0x4) {
+ return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0));
}
/* Default is HS-G3 */
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 4b00c67e9d7f..dd3abd23ec22 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -94,6 +94,10 @@ enum {
#define TMRLUT_HW_CGC_EN BIT(6)
#define OCSC_HW_CGC_EN BIT(7)
+/* bit definitions for REG_UFS_PARAM0 */
+#define MAX_HS_GEAR_MASK GENMASK(6, 4)
+#define UFS_QCOM_MAX_GEAR(x) FIELD_GET(MAX_HS_GEAR_MASK, (x))
+
/* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
--
2.25.1
SM8350 default init sequence sets some PCS registers to HS G3, thereby
disabling HS G4 mode. This has the effect on MPHY capability negotiation
between the host and the device during link startup and causes the
PA_MAXHSGEAR to G3 irrespective of device max gear.
Due to that, the agreed gear speed determined by the UFS core will become
G3 only and the platform won't run at G4.
So, let's remove setting these registers for SM8350 as like other G4
compatible platforms. One downside of this is that, when the board design
uses non-G4 compatible device, then MPHY will continue to run in the
default mode (G4) even if UFSHCD runs in G3. But this is the case for
other platforms as well.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index d5324c4e8513..6c7c6a06fe3b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -567,13 +567,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
};
--
2.25.1
Since now there is support for configuring the HS Rate B mode properly,
let's move the register setting to tbls_hs_b struct for all SoCs.
This allows the PHY to be configured in Rate A initially and then in
Rate B if requested by the UFS driver.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 37 +++++++++++++++++++++----
1 file changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 82be9b754e8e..97d0baa9bac3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -214,8 +214,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
+};
- /* Rate B */
+static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
};
@@ -291,8 +292,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
+};
- /* Rate B */
+static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
};
@@ -357,8 +359,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+};
- /* Rate B */
+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
};
@@ -406,7 +409,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
-
};
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
@@ -444,8 +446,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
+};
- /* Rate B */
+static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
};
@@ -679,6 +682,10 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.pcs = sm8350_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8350_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -699,6 +706,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.pcs = sdm845_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sdm845_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -721,6 +732,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.pcs = sm6115_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm6115_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -743,6 +758,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.pcs = sm8150_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8150_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -763,6 +782,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.pcs = sm8350_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8350_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -783,6 +806,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.pcs = sm8350_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8350_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
+ },
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
--
2.25.1
Some platforms like Qcom, requires the UFS device to be reinitialized
after switching to maximum gear speed. So add support for that in UFS
core by introducing a new quirk (UFSHCD_CAP_REINIT_AFTER_MAX_GEAR_SWITCH)
and doing the reinitialization, if the quirk is enabled by the controller
driver.
Suggested-by: Can Guo <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/core/ufshcd.c | 63 +++++++++++++++++++++++++++++----------
include/ufs/ufshcd.h | 6 ++++
2 files changed, 53 insertions(+), 16 deletions(-)
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index e18c9f4463ec..55714accdfd4 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -8153,27 +8153,18 @@ static int ufshcd_add_lus(struct ufs_hba *hba)
return ret;
}
-/**
- * ufshcd_probe_hba - probe hba to detect device and initialize it
- * @hba: per-adapter instance
- * @init_dev_params: whether or not to call ufshcd_device_params_init().
- *
- * Execute link-startup and verify device initialization
- */
-static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
+static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
{
int ret;
- unsigned long flags;
- ktime_t start = ktime_get();
hba->ufshcd_state = UFSHCD_STATE_RESET;
ret = ufshcd_link_startup(hba);
if (ret)
- goto out;
+ return ret;
if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
- goto out;
+ return ret;
/* Debug counters initialization */
ufshcd_clear_dbg_ufs_stats(hba);
@@ -8184,12 +8175,12 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
/* Verify device initialization by sending NOP OUT UPIU */
ret = ufshcd_verify_dev_init(hba);
if (ret)
- goto out;
+ return ret;
/* Initiate UFS initialization, and waiting until completion */
ret = ufshcd_complete_dev_init(hba);
if (ret)
- goto out;
+ return ret;
/*
* Initialize UFS device parameters used by driver, these
@@ -8198,7 +8189,7 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
if (init_dev_params) {
ret = ufshcd_device_params_init(hba);
if (ret)
- goto out;
+ return ret;
}
ufshcd_tune_unipro_params(hba);
@@ -8219,11 +8210,51 @@ static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
if (ret) {
dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
__func__, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * ufshcd_probe_hba - probe hba to detect device and initialize it
+ * @hba: per-adapter instance
+ * @init_dev_params: whether or not to call ufshcd_device_params_init().
+ *
+ * Execute link-startup and verify device initialization
+ */
+static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
+{
+ ktime_t start = ktime_get();
+ unsigned long flags;
+ int ret;
+
+ ret = ufshcd_device_init(hba, init_dev_params);
+ if (ret)
+ goto out;
+
+ if (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH) {
+ /* Reset the device and controller before doing reinit */
+ ufshcd_device_reset(hba);
+ ufshcd_hba_stop(hba);
+ ufshcd_vops_reinit_notify(hba);
+ ret = ufshcd_hba_enable(hba);
+ if (ret) {
+ dev_err(hba->dev, "Host controller enable failed\n");
+ ufshcd_print_evt_hist(hba);
+ ufshcd_print_host_state(hba);
goto out;
}
- ufshcd_print_pwr_info(hba);
+
+ /* Reinit the device */
+ ret = ufshcd_device_init(hba, init_dev_params);
+ if (ret)
+ goto out;
}
+ ufshcd_print_pwr_info(hba);
+
/*
* bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
* and for removable UFS card as well, hence always set the parameter.
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index af8c95077d96..443403d3be72 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -595,6 +595,12 @@ enum ufshcd_quirks {
* auto-hibernate capability but it's FASTAUTO only.
*/
UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
+
+ /*
+ * This quirk needs to be enabled if the host controller needs
+ * to reinit the device after switching to maximum gear.
+ */
+ UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
};
enum ufshcd_caps {
--
2.25.1
UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance. This
also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
.../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 62 ++++++++++++++++++-
2 files changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
index bcca23493b7e..3aa4232f84a6 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
@@ -13,6 +13,7 @@
#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
+#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 269f96a0f752..d5324c4e8513 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -449,6 +449,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
};
+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
+};
+
+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
+};
+
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
@@ -805,6 +833,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.regs = sm8150_ufsphy_regs_layout,
};
+static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
+ .lanes = 2,
+
+ .tbls = {
+ .serdes = sm8150_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
+ .tx = sm8150_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
+ .rx = sm8150_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
+ .pcs = sm8150_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
+ },
+ .tbls_hs_b = {
+ .serdes = sm8150_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
+ },
+ .tbls_hs_g4 = {
+ .tx = sm8250_ufsphy_hs_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
+ .rx = sm8250_ufsphy_hs_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
+ .pcs = sm8150_ufsphy_hs_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ },
+ .clk_list = sdm845_ufs_phy_clk_l,
+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8150_ufsphy_regs_layout,
+};
+
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
@@ -1297,7 +1357,7 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
.data = &sm8150_ufsphy_cfg,
}, {
.compatible = "qcom,sm8250-qmp-ufs-phy",
- .data = &sm8150_ufsphy_cfg,
+ .data = &sm8250_ufsphy_cfg,
}, {
.compatible = "qcom,sm8350-qmp-ufs-phy",
.data = &sm8350_ufsphy_cfg,
--
2.25.1
UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 96e03d4249da..9f5526758985 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -763,6 +763,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
+ .tbls_hs_g4 = {
+ .tx = sm8350_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
+ .rx = sm8350_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
+ .pcs = sm8350_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
--
2.25.1
Make use of dev_err_probe() for printing the probe error.
Reviewed-by: Andrew Halaney <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 8bb0f4415f1a..38e2ed749d75 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1441,9 +1441,9 @@ static int ufs_qcom_probe(struct platform_device *pdev)
/* Perform generic probe */
err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
if (err)
- dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
+ return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
- return err;
+ return 0;
}
/**
--
2.25.1
Add separate tables_hs_g4 instance to allow the PHY driver to configure the
PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and
PCS register setting in tables_hs_g4 and the UFS driver can request the
Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 2d5dd336aeb2..82be9b754e8e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -20,6 +20,7 @@
#include <linux/reset.h>
#include <linux/slab.h>
+#include <ufs/unipro.h>
#include "phy-qcom-qmp.h"
/* QPHY_SW_RESET bit */
@@ -549,6 +550,8 @@ struct qmp_phy_cfg {
const struct qmp_phy_cfg_tbls tbls;
/* Additional sequence for HS Series B */
const struct qmp_phy_cfg_tbls tbls_hs_b;
+ /* Additional sequence for HS G4 */
+ const struct qmp_phy_cfg_tbls tbls_hs_g4;
/* clock ids to be requested */
const char * const *clk_list;
@@ -583,6 +586,7 @@ struct qmp_ufs {
struct phy *phy;
u32 mode;
+ u32 submode;
};
static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
@@ -847,7 +851,11 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
if (qmp->mode == PHY_MODE_UFS_HS_B)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
qmp_ufs_lanes_init(qmp, &cfg->tbls);
+ if (qmp->submode == UFS_HS_G4)
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
qmp_ufs_pcs_init(qmp, &cfg->tbls);
+ if (qmp->submode == UFS_HS_G4)
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -1021,6 +1029,7 @@ static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
struct qmp_ufs *qmp = phy_get_drvdata(phy);
qmp->mode = mode;
+ qmp->submode = submode;
return 0;
}
--
2.25.1
In the reset assert and deassert callbacks, the supplied "id" is not used
at all and only the hba reset is performed all the time. So there is no
reason to use a WARN_ON on the "id".
Reviewed-by: Andrew Halaney <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 7cd996ac180b..8bb0f4415f1a 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -895,8 +895,6 @@ ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
- /* Currently this code only knows about a single reset. */
- WARN_ON(id);
ufs_qcom_assert_reset(host->hba);
/* provide 1ms delay to let the reset pulse propagate. */
usleep_range(1000, 1100);
@@ -908,8 +906,6 @@ ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
- /* Currently this code only knows about a single reset. */
- WARN_ON(id);
ufs_qcom_deassert_reset(host->hba);
/*
--
2.25.1
On newer UFS revisions, the register at offset 0xD0 is called,
REG_UFS_PARAM0. Since the existing register, RETRY_TIMER_REG is not used
anywhere, it is safe to use the new name.
Reviewed-by: Andrew Halaney <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 9d96ac71b27f..7fe928b82753 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -33,7 +33,8 @@ enum {
REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
REG_UFS_PA_ERR_CODE = 0xCC,
- REG_UFS_RETRY_TIMER_REG = 0xD0,
+ /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
+ REG_UFS_PARAM0 = 0xD0,
REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8,
REG_UFS_CFG1 = 0xDC,
REG_UFS_CFG2 = 0xE0,
--
2.25.1
In the preparation of adding support for new gears, let's move the
logic that finds the gear for each platform to a new function. This helps
with code readability and also allows the logic to be used in other places
of the driver in future.
While at it, let's make it clear that this driver only supports symmetric
gear setting (hs_tx_gear == hs_rx_gear).
Reviewed-by: Andrew Halaney <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 34 +++++++++++++++++++++-------------
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 38e2ed749d75..919b6eae439d 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -278,6 +278,25 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
return 0;
}
+static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
+{
+ struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+
+ if (host->hw_ver.major == 0x1) {
+ /*
+ * HS-G3 operations may not reliably work on legacy QCOM
+ * UFS host controller hardware even though capability
+ * exchange during link startup phase may end up
+ * negotiating maximum supported gear as G3.
+ * Hence downgrade the maximum supported gear to HS-G2.
+ */
+ return UFS_HS_G2;
+ }
+
+ /* Default is HS-G3 */
+ return UFS_HS_G3;
+}
+
static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -692,19 +711,8 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
- if (host->hw_ver.major == 0x1) {
- /*
- * HS-G3 operations may not reliably work on legacy QCOM
- * UFS host controller hardware even though capability
- * exchange during link startup phase may end up
- * negotiating maximum supported gear as G3.
- * Hence downgrade the maximum supported gear to HS-G2.
- */
- if (ufs_qcom_cap.hs_tx_gear > UFS_HS_G2)
- ufs_qcom_cap.hs_tx_gear = UFS_HS_G2;
- if (ufs_qcom_cap.hs_rx_gear > UFS_HS_G2)
- ufs_qcom_cap.hs_rx_gear = UFS_HS_G2;
- }
+ /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
+ ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
dev_max_params,
--
2.25.1
Add separate tables_hs_b instance to allow the PHY driver to configure the
PHY in HS Series B mode. The individual SoC configs need to supply the
serdes register setting in tables_hs_b and the UFS driver can request the
Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 516027e356f0..2d5dd336aeb2 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -547,6 +547,8 @@ struct qmp_phy_cfg {
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
const struct qmp_phy_cfg_tbls tbls;
+ /* Additional sequence for HS Series B */
+ const struct qmp_phy_cfg_tbls tbls_hs_b;
/* clock ids to be requested */
const char * const *clk_list;
@@ -580,6 +582,7 @@ struct qmp_ufs {
struct reset_control *ufs_reset;
struct phy *phy;
+ u32 mode;
};
static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
@@ -841,6 +844,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
{
qmp_ufs_serdes_init(qmp, &cfg->tbls);
+ if (qmp->mode == PHY_MODE_UFS_HS_B)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
qmp_ufs_lanes_init(qmp, &cfg->tbls);
qmp_ufs_pcs_init(qmp, &cfg->tbls);
}
@@ -1011,9 +1016,19 @@ static int qmp_ufs_disable(struct phy *phy)
return qmp_ufs_exit(phy);
}
+static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct qmp_ufs *qmp = phy_get_drvdata(phy);
+
+ qmp->mode = mode;
+
+ return 0;
+}
+
static const struct phy_ops qcom_qmp_ufs_phy_ops = {
.power_on = qmp_ufs_enable,
.power_off = qmp_ufs_disable,
+ .set_mode = qmp_ufs_set_mode,
.owner = THIS_MODULE,
};
--
2.25.1
reinit_notify() callback can be used by the UFS controllers to perform
changes required for UFS core reinit.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/ufs/core/ufshcd-priv.h | 6 ++++++
include/ufs/ufshcd.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h
index a9e8e1f5afe7..2ce3c98e0711 100644
--- a/drivers/ufs/core/ufshcd-priv.h
+++ b/drivers/ufs/core/ufshcd-priv.h
@@ -226,6 +226,12 @@ static inline void ufshcd_vops_config_scaling_param(struct ufs_hba *hba,
hba->vops->config_scaling_param(hba, p, data);
}
+static inline void ufshcd_vops_reinit_notify(struct ufs_hba *hba)
+{
+ if (hba->vops && hba->vops->reinit_notify)
+ hba->vops->reinit_notify(hba);
+}
+
extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
/**
diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
index 5cf81dff60aa..af8c95077d96 100644
--- a/include/ufs/ufshcd.h
+++ b/include/ufs/ufshcd.h
@@ -297,6 +297,7 @@ struct ufs_pwr_mode_info {
* @config_scaling_param: called to configure clock scaling parameters
* @program_key: program or evict an inline encryption key
* @event_notify: called to notify important events
+ * @reinit_notify: called to notify UFS core reinit
*/
struct ufs_hba_variant_ops {
const char *name;
@@ -335,6 +336,7 @@ struct ufs_hba_variant_ops {
const union ufs_crypto_cfg_entry *cfg, int slot);
void (*event_notify)(struct ufs_hba *hba,
enum ufs_event_type evt, void *data);
+ void (*reinit_notify)(struct ufs_hba *);
};
/* clock gating state */
--
2.25.1
UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init
sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
reusing the G4 init sequence of SM8350.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 75e55c4181c9..96e03d4249da 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
+ .tbls_hs_g4 = {
+ .tx = sm8350_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
+ .rx = sm8350_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
+ .pcs = sm8350_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ },
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
--
2.25.1
On Thu, Dec 01, 2022 at 11:13:05PM +0530, Manivannan Sadhasivam wrote:
> Hello,
>
> This series adds HS-G4 support to the Qcom UFS driver and PHY driver.
> The newer Qcom platforms support configuring the UFS controller and PHY
> in dual gears (i.e., controller/PHY can be configured to run in two gear
> speeds). This is accomplished by adding two different PHY init sequences
> to the PHY driver and the UFS driver requesting the one that's required
> based on the platform configuration.
>
> Initially the ufs-qcom driver will use the default gear G2 for enumerating
> the UFS device. Afer enumeration, the max gear supported by both the
> controller and device would be found out and that will be used thereafter.
> But for using the max gear after enumeration, the ufs-qcom driver requires
> the UFS device to be reinitialized. For this purpose, a separate quirk has
> been introduced in the UFS core along with a callback and those will be used
> by the ufs-qcom driver.
>
> This series has been tested on following platforms:
>
> * Qcom RB5 development platform powered by SM8250 SoC
> * SM8450 based dev board
>
> Merging Strategy:
> -----------------
>
> The PHY patches are expected to go through PHY tree and UFS, MAINTAINERS
> patches are expected to go through SCSI tree.
>
> NOTE: Since this series targets multiple SoCs (base like SM8350) and
> (derivative like SC8280XP), testing on all of these platforms is really
> appreciated. Although, if the series works for base SoC, then for derivatives
> also it should work.
Tested-by: Andrew Halaney <[email protected]> # Qdrive3/sa8540p-ride
Without this patch series, the board's operating in gear 3. With it the
board's operating in gear 4. Gentle reminder sa8540p-ride is a SC8280XP
derivative.
I'm not really proficient in storage benchmarking, but a simple dd test
showed the following (sorry for the poor output, console got a
little wacky on the output).
Gear 3:
[root@localhost ~]# dd bs=4k oflag=direct if=/dev/zero of=/dev/disk/by-partlabel/userdata
dd: error writing '/dev/disk/by-partlabel/userdata': No space left on device
19873276+0 records in
19873275+0 records out
81400934400 bytes (81 GB, 76 GiB) copied, 864.111 s, 94.2 MB/s
[root@localhost ~]# dd bs=4k if=/dev/disk/by-partlabel/userdata of=/dev/null
19873275+0 records in
19873275+0 records out
81400934400 bytes (81 GB, 76 GiB) copied, 75.7823 s, 1.1 GB/s
[root@localhost ~]#
Gear 4:
[root@localhost ~]# dd bs=4k oflag=direct if=/dev/zero of=/dev/disk/by-partlabel/userdata
[ 81.651598] ufshcd-qcom 1d84000.ufs: ufs_qcom_get_hs_gear: 296: UFS_HS_G4
[ 81.658592] ufshcd-qcom 1d84000.ufs: ufs_qcom_pwr_change_notify: 731: Agreed gear: 4
[root@localhost ~]# GB, 76 GiB) copied, 738.015 s, 110 MB/s
[root@localhost ~]# dd bs=4k if=/dev/disk/by-partlabel/userdata of=/dev/null
19873275+0 records in
19873275+0 records out
81400934400 bytes (81 GB, 76 GiB) copied, 63.9846 s, 1.3 GB/s
[root@localhost ~]#
So a bit of a performance gain was seen with this patch series :)
Thanks,
Andrew
>
> Thanks,
> Mani
>
> Changes in v4:
>
> * Dropped HS G3 specific setting from SM8350 default init sequence
> * Added G4 support to SM8350 and SC8280XP
> * Covered all qcom files under drivers/ufs/host in MAINTAINERS file
> * Added missing Suggested-by tags for Can Guo
> * Rebased on top of linux-next 20221201
>
> Changes in v3:
>
> * Dropped the "device-max-gear" DT property and switched to reinitialization (Krzysztof)
> * Added HS-G4 support to all compatible SoCs (SM8150, SM8250 and SM8450). This will also
> benefit the derivative SoCs of these platforms like SC8180x, SC8280x etc...
> * Splitted the qmp_phy_init_tbl changes into separate patches (Vinod)
> * Collected reviews from Andrew H
>
> Changes in v2:
>
> * Collected reviews from Dmitry
> * Renamed "max-gear" property to "max-device-gear"
> * Used min() for deciding which gear to use instead of open comparision
> * Added comment about the old register name
>
> Manivannan Sadhasivam (23):
> phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl
> definitions
> phy: qcom-qmp-ufs: Rename MSM8996 PHY definitions
> phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls struct
> phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode
> phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 mode
> phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b
> phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoC
> phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoC
> phy: qcom-qmp-ufs: Avoid setting HS G3 specific registers
> phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC
> phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoC
> phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoC
> scsi: ufs: ufs-qcom: Remove un-necessary goto statements
> scsi: ufs: ufs-qcom: Remove un-necessary WARN_ON()
> scsi: ufs: ufs-qcom: Use bitfields where appropriate
> scsi: ufs: ufs-qcom: Use dev_err_probe() for printing probe error
> scsi: ufs: ufs-qcom: Fix the Qcom register name for offset 0xD0
> scsi: ufs: core: Add reinit_notify() callback
> scsi: ufs: core: Add support for reinitializing the UFS device
> scsi: ufs: ufs-qcom: Factor out the logic finding the HS Gear
> scsi: ufs: ufs-qcom: Add support for reinitializing the UFS device
> scsi: ufs: ufs-qcom: Add support for finding max gear on new platforms
> MAINTAINERS: Add myself as the maintainer for Qcom UFS drivers
>
> MAINTAINERS | 8 +
> .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 +
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 454 +++++++++++++-----
> drivers/ufs/core/ufshcd-priv.h | 6 +
> drivers/ufs/core/ufshcd.c | 63 ++-
> drivers/ufs/host/ufs-qcom.c | 170 +++----
> drivers/ufs/host/ufs-qcom.h | 70 +--
> include/ufs/ufshcd.h | 8 +
> 8 files changed, 532 insertions(+), 248 deletions(-)
>
> --
> 2.25.1
>
On Thu, Dec 01 2022 at 09:45 -0800, Manivannan Sadhasivam wrote:
>Make use of dev_err_probe() for printing the probe error.
>
>Reviewed-by: Andrew Halaney <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/ufs/host/ufs-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Asutosh Das <[email protected]>
>diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>index 8bb0f4415f1a..38e2ed749d75 100644
>--- a/drivers/ufs/host/ufs-qcom.c
>+++ b/drivers/ufs/host/ufs-qcom.c
>@@ -1441,9 +1441,9 @@ static int ufs_qcom_probe(struct platform_device *pdev)
> /* Perform generic probe */
> err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops);
> if (err)
>- dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
>+ return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n");
>
>- return err;
>+ return 0;
> }
>
> /**
>--
>2.25.1
>
On Thu, Dec 01 2022 at 09:45 -0800, Manivannan Sadhasivam wrote:
>On newer UFS revisions, the register at offset 0xD0 is called,
>REG_UFS_PARAM0. Since the existing register, RETRY_TIMER_REG is not used
>anywhere, it is safe to use the new name.
>
>Reviewed-by: Andrew Halaney <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/ufs/host/ufs-qcom.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Asutosh Das <[email protected]>
>diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
>index 9d96ac71b27f..7fe928b82753 100644
>--- a/drivers/ufs/host/ufs-qcom.h
>+++ b/drivers/ufs/host/ufs-qcom.h
>@@ -33,7 +33,8 @@ enum {
> REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
> REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
> REG_UFS_PA_ERR_CODE = 0xCC,
>- REG_UFS_RETRY_TIMER_REG = 0xD0,
>+ /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
>+ REG_UFS_PARAM0 = 0xD0,
> REG_UFS_PA_LINK_STARTUP_TIMER = 0xD8,
> REG_UFS_CFG1 = 0xDC,
> REG_UFS_CFG2 = 0xE0,
>--
>2.25.1
>
On Thu, Dec 01 2022 at 09:45 -0800, Manivannan Sadhasivam wrote:
>goto in error path is useful if the function needs to do cleanup other
>than returning the error code. But in this driver, goto statements are
>used for just returning the error code in many places. This really
>makes it hard to read the code.
>
>So let's get rid of those goto statements and just return the error code
>directly.
>
>Reviewed-by: Dmitry Baryshkov <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++---------------------
> 1 file changed, 41 insertions(+), 59 deletions(-)
LGTM.
Reviewed-by: Asutosh Das <[email protected]>
>
>diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>index 8ad1415e10b6..7cd996ac180b 100644
>--- a/drivers/ufs/host/ufs-qcom.c
>+++ b/drivers/ufs/host/ufs-qcom.c
>@@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
>
> static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> {
>- int err = 0;
>+ int err;
> struct device *dev = host->hba->dev;
>
> if (host->is_lane_clks_enabled)
>@@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
> host->rx_l0_sync_clk);
> if (err)
>- goto out;
>+ return err;
>
> err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
> host->tx_l0_sync_clk);
>@@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> goto disable_rx_l1;
>
> host->is_lane_clks_enabled = true;
>- goto out;
>+
>+ return 0;
>
> disable_rx_l1:
> clk_disable_unprepare(host->rx_l1_sync_clk);
>@@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> clk_disable_unprepare(host->tx_l0_sync_clk);
> disable_rx_l0:
> clk_disable_unprepare(host->rx_l0_sync_clk);
>-out:
>+
> return err;
> }
>
>@@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
> err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
> &host->rx_l0_sync_clk, false);
> if (err)
>- goto out;
>+ return err;
>
> err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
> &host->tx_l0_sync_clk, false);
> if (err)
>- goto out;
>+ return err;
>
> /* In case of single lane per direction, don't read lane1 clocks */
> if (host->hba->lanes_per_direction > 1) {
> err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
> &host->rx_l1_sync_clk, false);
> if (err)
>- goto out;
>+ return err;
>
> err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
> &host->tx_l1_sync_clk, true);
> }
>-out:
>- return err;
>+
>+ return 0;
> }
>
> static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>@@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
>
> if (!host->core_reset) {
> dev_warn(hba->dev, "%s: reset control not set\n", __func__);
>- goto out;
>+ return 0;
> }
>
> reenable_intr = hba->is_irq_enabled;
>@@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
> if (ret) {
> dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
> __func__, ret);
>- goto out;
>+ return ret;
> }
>
> /*
>@@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
> hba->is_irq_enabled = true;
> }
>
>-out:
>- return ret;
>+ return 0;
> }
>
> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> struct phy *phy = host->generic_phy;
>- int ret = 0;
>+ int ret;
> bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B;
>
> /* Reset UFS Host Controller and PHY */
>@@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> if (ret) {
> dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
> __func__, ret);
>- goto out;
>+ return ret;
> }
>
> /* power on phy - start serdes and phy's power and clocks */
>@@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>
> out_disable_phy:
> phy_exit(phy);
>-out:
>+
> return ret;
> }
>
>@@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
> static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> u32 hs, u32 rate, bool update_link_startup_timer)
> {
>- int ret = 0;
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> struct ufs_clk_info *clki;
> u32 core_clk_period_in_ns;
>@@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> * Aggregation logic.
> */
> if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
>- goto out;
>+ return 0;
>
> if (gear == 0) {
> dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
>- goto out_error;
>+ return -EINVAL;
> }
>
> list_for_each_entry(clki, &hba->clk_list_head, list) {
>@@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> }
>
> if (ufs_qcom_cap_qunipro(host))
>- goto out;
>+ return 0;
>
> core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
> core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
>@@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> "%s: index %d exceeds table size %zu\n",
> __func__, gear,
> ARRAY_SIZE(hs_fr_table_rA));
>- goto out_error;
>+ return -EINVAL;
> }
> tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
> } else if (rate == PA_HS_MODE_B) {
>@@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> "%s: index %d exceeds table size %zu\n",
> __func__, gear,
> ARRAY_SIZE(hs_fr_table_rB));
>- goto out_error;
>+ return -EINVAL;
> }
> tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
> } else {
> dev_err(hba->dev, "%s: invalid rate = %d\n",
> __func__, rate);
>- goto out_error;
>+ return -EINVAL;
> }
> break;
> case SLOWAUTO_MODE:
>@@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> "%s: index %d exceeds table size %zu\n",
> __func__, gear,
> ARRAY_SIZE(pwm_fr_table));
>- goto out_error;
>+ return -EINVAL;
> }
> tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
> break;
> case UNCHANGED:
> default:
> dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
>- goto out_error;
>+ return -EINVAL;
> }
>
> if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
>@@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> */
> mb();
> }
>- goto out;
>
>-out_error:
>- ret = -EINVAL;
>-out:
>- return ret;
>+ return 0;
> }
>
> static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>@@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
> 0, true)) {
> dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
> __func__);
>- err = -EINVAL;
>- goto out;
>+ return -EINVAL;
> }
>
> if (ufs_qcom_cap_qunipro(host))
>@@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
> break;
> }
>
>-out:
> return err;
> }
>
>@@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> if (!dev_req_params) {
> pr_err("%s: incoming dev_req_params is NULL\n", __func__);
>- ret = -EINVAL;
>- goto out;
>+ return -EINVAL;
> }
>
> switch (status) {
>@@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> if (ret) {
> pr_err("%s: failed to determine capabilities\n",
> __func__);
>- goto out;
>+ return ret;
> }
>
> /* enable the device ref clock before changing to HS mode */
>@@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> ret = -EINVAL;
> break;
> }
>-out:
>+
> return ret;
> }
>
>@@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
> err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
> &pa_vs_config_reg1);
> if (err)
>- goto out;
>+ return err;
>
> /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
>- err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
>+ return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
> (pa_vs_config_reg1 | (1 << 12)));
>-
>-out:
>- return err;
> }
>
> static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
>@@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>
> host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> if (!host) {
>- err = -ENOMEM;
> dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
>- goto out;
>+ return -ENOMEM;
> }
>
> /* Make a two way bind between the qcom host and the hba */
>@@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> host->rcdev.owner = dev->driver->owner;
> host->rcdev.nr_resets = 1;
> err = devm_reset_controller_register(dev, &host->rcdev);
>- if (err) {
>+ if (err)
> dev_warn(dev, "Failed to register reset controller\n");
>- err = 0;
>- }
>
> if (!has_acpi_companion(dev)) {
> host->generic_phy = devm_phy_get(dev, "ufsphy");
>@@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
> ufs_qcom_get_default_testbus_cfg(host);
> err = ufs_qcom_testbus_config(host);
>- if (err) {
>+ if (err)
>+ /* Failure is non-fatal */
> dev_warn(dev, "%s: failed to configure the testbus %d\n",
> __func__, err);
>- err = 0;
>- }
>
>- goto out;
>+ return 0;
>
> out_variant_clear:
> ufshcd_set_variant(hba, NULL);
>-out:
>+
> return err;
> }
>
>@@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
> UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
> &core_clk_ctrl_reg);
> if (err)
>- goto out;
>+ return err;
>
> core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
> core_clk_ctrl_reg |= clk_cycles;
>@@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
> /* Clear CORE_CLK_DIV_EN */
> core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
>
>- err = ufshcd_dme_set(hba,
>+ return ufshcd_dme_set(hba,
> UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
> core_clk_ctrl_reg);
>-out:
>- return err;
> }
>
> static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
>@@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
>
> if (err || !dev_req_params) {
> ufshcd_uic_hibern8_exit(hba);
>- goto out;
>+ return err;
> }
>
> ufs_qcom_cfg_timers(hba,
>@@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
> ufshcd_uic_hibern8_exit(hba);
> }
>
>-out:
>- return err;
>+ return 0;
> }
>
> static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
>--
>2.25.1
>
On Thu, Dec 01 2022 at 09:45 -0800, Manivannan Sadhasivam wrote:
>In the reset assert and deassert callbacks, the supplied "id" is not used
>at all and only the hba reset is performed all the time. So there is no
>reason to use a WARN_ON on the "id".
>
>Reviewed-by: Andrew Halaney <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/ufs/host/ufs-qcom.c | 4 ----
> 1 file changed, 4 deletions(-)
>
LGTM.
Reviewed-by: Asutosh Das <[email protected]>
>diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>index 7cd996ac180b..8bb0f4415f1a 100644
>--- a/drivers/ufs/host/ufs-qcom.c
>+++ b/drivers/ufs/host/ufs-qcom.c
>@@ -895,8 +895,6 @@ ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
> {
> struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
>
>- /* Currently this code only knows about a single reset. */
>- WARN_ON(id);
> ufs_qcom_assert_reset(host->hba);
> /* provide 1ms delay to let the reset pulse propagate. */
> usleep_range(1000, 1100);
>@@ -908,8 +906,6 @@ ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
> {
> struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev);
>
>- /* Currently this code only knows about a single reset. */
>- WARN_ON(id);
> ufs_qcom_deassert_reset(host->hba);
>
> /*
>--
>2.25.1
>
On Thu, Dec 01 2022 at 09:45 -0800, Manivannan Sadhasivam wrote:
>Use bitfield macros where appropriate to simplify the driver.
>
>Reviewed-by: Dmitry Baryshkov <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/ufs/host/ufs-qcom.h | 61 +++++++++++++++++--------------------
> 1 file changed, 28 insertions(+), 33 deletions(-)
>
LGTM.
Reviewed-by: Asutosh Das <[email protected]>
>diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
>index 44466a395bb5..9d96ac71b27f 100644
>--- a/drivers/ufs/host/ufs-qcom.h
>+++ b/drivers/ufs/host/ufs-qcom.h
>@@ -17,12 +17,9 @@
> #define DEFAULT_CLK_RATE_HZ 1000000
> #define BUS_VECTOR_NAME_LEN 32
>
>-#define UFS_HW_VER_MAJOR_SHFT (28)
>-#define UFS_HW_VER_MAJOR_MASK (0x000F << UFS_HW_VER_MAJOR_SHFT)
>-#define UFS_HW_VER_MINOR_SHFT (16)
>-#define UFS_HW_VER_MINOR_MASK (0x0FFF << UFS_HW_VER_MINOR_SHFT)
>-#define UFS_HW_VER_STEP_SHFT (0)
>-#define UFS_HW_VER_STEP_MASK (0xFFFF << UFS_HW_VER_STEP_SHFT)
>+#define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28)
>+#define UFS_HW_VER_MINOR_MASK GENMASK(27, 16)
>+#define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
>
> /* vendor specific pre-defined parameters */
> #define SLOW 1
>@@ -76,24 +73,28 @@ enum {
> #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
>
> /* bit definitions for REG_UFS_CFG1 register */
>-#define QUNIPRO_SEL 0x1
>-#define UTP_DBG_RAMS_EN 0x20000
>+#define QUNIPRO_SEL BIT(0)
>+#define UFS_PHY_SOFT_RESET BIT(1)
>+#define UTP_DBG_RAMS_EN BIT(17)
> #define TEST_BUS_EN BIT(18)
> #define TEST_BUS_SEL GENMASK(22, 19)
> #define UFS_REG_TEST_BUS_EN BIT(30)
>
>+#define UFS_PHY_RESET_ENABLE 1
>+#define UFS_PHY_RESET_DISABLE 0
>+
> /* bit definitions for REG_UFS_CFG2 register */
>-#define UAWM_HW_CGC_EN (1 << 0)
>-#define UARM_HW_CGC_EN (1 << 1)
>-#define TXUC_HW_CGC_EN (1 << 2)
>-#define RXUC_HW_CGC_EN (1 << 3)
>-#define DFC_HW_CGC_EN (1 << 4)
>-#define TRLUT_HW_CGC_EN (1 << 5)
>-#define TMRLUT_HW_CGC_EN (1 << 6)
>-#define OCSC_HW_CGC_EN (1 << 7)
>+#define UAWM_HW_CGC_EN BIT(0)
>+#define UARM_HW_CGC_EN BIT(1)
>+#define TXUC_HW_CGC_EN BIT(2)
>+#define RXUC_HW_CGC_EN BIT(3)
>+#define DFC_HW_CGC_EN BIT(4)
>+#define TRLUT_HW_CGC_EN BIT(5)
>+#define TMRLUT_HW_CGC_EN BIT(6)
>+#define OCSC_HW_CGC_EN BIT(7)
>
> /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
>-#define TEST_BUS_SUB_SEL_MASK 0x1F /* All XXX_SEL fields are 5 bits wide */
>+#define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
>
> #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
> TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
>@@ -101,17 +102,11 @@ enum {
> TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
>
> /* bit offset */
>-enum {
>- OFFSET_UFS_PHY_SOFT_RESET = 1,
>- OFFSET_CLK_NS_REG = 10,
>-};
>+#define OFFSET_CLK_NS_REG 0xa
>
> /* bit masks */
>-enum {
>- MASK_UFS_PHY_SOFT_RESET = 0x2,
>- MASK_TX_SYMBOL_CLK_1US_REG = 0x3FF,
>- MASK_CLK_NS_REG = 0xFFFC00,
>-};
>+#define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0)
>+#define MASK_CLK_NS_REG GENMASK(23, 10)
>
> /* QCOM UFS debug print bit mask */
> #define UFS_QCOM_DBG_PRINT_REGS_EN BIT(0)
>@@ -135,15 +130,15 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba,
> {
> u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
>
>- *major = (ver & UFS_HW_VER_MAJOR_MASK) >> UFS_HW_VER_MAJOR_SHFT;
>- *minor = (ver & UFS_HW_VER_MINOR_MASK) >> UFS_HW_VER_MINOR_SHFT;
>- *step = (ver & UFS_HW_VER_STEP_MASK) >> UFS_HW_VER_STEP_SHFT;
>+ *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
>+ *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
>+ *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
> };
>
> static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
> {
>- ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
>- 1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
>+ ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE),
>+ REG_UFS_CFG1);
>
> /*
> * Make sure assertion of ufs phy reset is written to
>@@ -154,8 +149,8 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
>
> static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
> {
>- ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
>- 0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
>+ ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE),
>+ REG_UFS_CFG1);
>
> /*
> * Make sure de-assertion of ufs phy reset is written to
>--
>2.25.1
>
On 1 December 2022 20:43:09 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
>Add separate tables_hs_b instance to allow the PHY driver to configure the
>PHY in HS Series B mode. The individual SoC configs need to supply the
>serdes register setting in tables_hs_b and the UFS driver can request the
>Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B.
>
>Reviewed-by: Dmitry Baryshkov <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>index 516027e356f0..2d5dd336aeb2 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>@@ -547,6 +547,8 @@ struct qmp_phy_cfg {
>
> /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
> const struct qmp_phy_cfg_tbls tbls;
>+ /* Additional sequence for HS Series B */
>+ const struct qmp_phy_cfg_tbls tbls_hs_b;
>
> /* clock ids to be requested */
> const char * const *clk_list;
>@@ -580,6 +582,7 @@ struct qmp_ufs {
> struct reset_control *ufs_reset;
>
> struct phy *phy;
>+ u32 mode;
> };
>
> static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
>@@ -841,6 +844,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> qmp_ufs_serdes_init(qmp, &cfg->tbls);
>+ if (qmp->mode == PHY_MODE_UFS_HS_B)
>+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
I still think that qmp_ufs_init_registers() is a way to go here , see the pcie driver.
> qmp_ufs_lanes_init(qmp, &cfg->tbls);
> qmp_ufs_pcs_init(qmp, &cfg->tbls);
> }
>@@ -1011,9 +1016,19 @@ static int qmp_ufs_disable(struct phy *phy)
> return qmp_ufs_exit(phy);
> }
>
>+static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
>+{
>+ struct qmp_ufs *qmp = phy_get_drvdata(phy);
>+
>+ qmp->mode = mode;
>+
>+ return 0;
>+}
>+
> static const struct phy_ops qcom_qmp_ufs_phy_ops = {
> .power_on = qmp_ufs_enable,
> .power_off = qmp_ufs_disable,
>+ .set_mode = qmp_ufs_set_mode,
> .owner = THIS_MODULE,
> };
>
--
With best wishes
Dmitry
On 1 December 2022 20:43:16 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
>UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init
>sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
>reusing the G4 init sequence of SM8350.
Reviewed-by: Dmitry Baryshkov <[email protected]>
>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>index 75e55c4181c9..96e03d4249da 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>@@ -935,6 +935,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
>+ .tbls_hs_g4 = {
>+ .tx = sm8350_ufsphy_g4_tx,
>+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
>+ .rx = sm8350_ufsphy_g4_rx,
>+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
>+ .pcs = sm8350_ufsphy_g4_pcs,
>+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
>+ },
> .clk_list = sm8450_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
--
With best wishes
Dmitry
On 1 December 2022 20:43:12 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
>UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the
>required register settings using the tables_hs_g4 struct instance.
>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
>---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 36 +++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>index 97d0baa9bac3..269f96a0f752 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>@@ -374,6 +374,10 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
> QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
> };
>
>+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
>+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
>+};
>+
> static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
> QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
>@@ -411,6 +415,25 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
> };
>
>+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
>+};
>+
> static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
> QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
>@@ -421,6 +444,11 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> };
>
>+static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
>+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
>+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
>+};
>+
> static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
> QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
>@@ -762,6 +790,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> .serdes = sm8150_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> },
>+ .tbls_hs_g4 = {
>+ .tx = sm8150_ufsphy_hs_g4_tx,
>+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
>+ .rx = sm8150_ufsphy_hs_g4_rx,
>+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
>+ .pcs = sm8150_ufsphy_hs_g4_pcs,
>+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
>+ },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
--
With best wishes
Dmitry
On 1 December 2022 20:43:13 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
>UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the
>required register settings using the tables_hs_g4 struct instance. This
>also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150.
>
>Reviewed-by: Dmitry Baryshkov <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
>---
> .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 1 +
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 62 ++++++++++++++++++-
> 2 files changed, 62 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
>index bcca23493b7e..3aa4232f84a6 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h
>@@ -13,6 +13,7 @@
> #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
> #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
> #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
>+#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
> #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>index 269f96a0f752..d5324c4e8513 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>@@ -449,6 +449,34 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
> };
>
>+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
>+ QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
>+};
>+
>+static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
>+ QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
>+};
>+
> static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
> QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
>@@ -805,6 +833,38 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> .regs = sm8150_ufsphy_regs_layout,
> };
>
>+static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
>+ .lanes = 2,
>+
>+ .tbls = {
>+ .serdes = sm8150_ufsphy_serdes,
>+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
>+ .tx = sm8150_ufsphy_tx,
>+ .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx),
>+ .rx = sm8150_ufsphy_rx,
>+ .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx),
>+ .pcs = sm8150_ufsphy_pcs,
>+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
>+ },
>+ .tbls_hs_b = {
>+ .serdes = sm8150_ufsphy_hs_b_serdes,
>+ .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
>+ },
>+ .tbls_hs_g4 = {
>+ .tx = sm8250_ufsphy_hs_g4_tx,
>+ .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
>+ .rx = sm8250_ufsphy_hs_g4_rx,
>+ .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
>+ .pcs = sm8150_ufsphy_hs_g4_pcs,
>+ .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
>+ },
>+ .clk_list = sdm845_ufs_phy_clk_l,
>+ .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
>+ .vreg_list = qmp_phy_vreg_l,
>+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>+ .regs = sm8150_ufsphy_regs_layout,
>+};
>+
> static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> .lanes = 2,
>
>@@ -1297,7 +1357,7 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
> .data = &sm8150_ufsphy_cfg,
> }, {
> .compatible = "qcom,sm8250-qmp-ufs-phy",
>- .data = &sm8150_ufsphy_cfg,
>+ .data = &sm8250_ufsphy_cfg,
> }, {
> .compatible = "qcom,sm8350-qmp-ufs-phy",
> .data = &sm8350_ufsphy_cfg,
--
With best wishes
Dmitry
On 1 December 2022 20:43:17 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
>UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init
>sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance
>reusing the G4 init sequence of SM8350.
>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
>---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>index 96e03d4249da..9f5526758985 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>@@ -763,6 +763,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
>+ .tbls_hs_g4 = {
>+ .tx = sm8350_ufsphy_g4_tx,
>+ .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
>+ .rx = sm8350_ufsphy_g4_rx,
>+ .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
>+ .pcs = sm8350_ufsphy_g4_pcs,
>+ .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
>+ },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
--
With best wishes
Dmitry
On 1 December 2022 20:43:18 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
>goto in error path is useful if the function needs to do cleanup other
>than returning the error code. But in this driver, goto statements are
>used for just returning the error code in many places. This really
>makes it hard to read the code.
>
>So let's get rid of those goto statements and just return the error code
>directly.
>
>Reviewed-by: Dmitry Baryshkov <[email protected]>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
>---
> drivers/ufs/host/ufs-qcom.c | 100 +++++++++++++++---------------------
> 1 file changed, 41 insertions(+), 59 deletions(-)
>
>diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>index 8ad1415e10b6..7cd996ac180b 100644
>--- a/drivers/ufs/host/ufs-qcom.c
>+++ b/drivers/ufs/host/ufs-qcom.c
>@@ -110,7 +110,7 @@ static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host)
>
> static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> {
>- int err = 0;
>+ int err;
> struct device *dev = host->hba->dev;
>
> if (host->is_lane_clks_enabled)
>@@ -119,7 +119,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk",
> host->rx_l0_sync_clk);
> if (err)
>- goto out;
>+ return err;
>
> err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk",
> host->tx_l0_sync_clk);
>@@ -137,7 +137,8 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> goto disable_rx_l1;
>
> host->is_lane_clks_enabled = true;
>- goto out;
>+
>+ return 0;
>
> disable_rx_l1:
> clk_disable_unprepare(host->rx_l1_sync_clk);
>@@ -145,7 +146,7 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
> clk_disable_unprepare(host->tx_l0_sync_clk);
> disable_rx_l0:
> clk_disable_unprepare(host->rx_l0_sync_clk);
>-out:
>+
> return err;
> }
>
>@@ -160,25 +161,25 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
> err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk",
> &host->rx_l0_sync_clk, false);
> if (err)
>- goto out;
>+ return err;
>
> err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk",
> &host->tx_l0_sync_clk, false);
> if (err)
>- goto out;
>+ return err;
>
> /* In case of single lane per direction, don't read lane1 clocks */
> if (host->hba->lanes_per_direction > 1) {
> err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
> &host->rx_l1_sync_clk, false);
> if (err)
>- goto out;
>+ return err;
>
> err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
> &host->tx_l1_sync_clk, true);
> }
>-out:
>- return err;
>+
>+ return 0;
> }
>
> static int ufs_qcom_check_hibern8(struct ufs_hba *hba)
>@@ -241,7 +242,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
>
> if (!host->core_reset) {
> dev_warn(hba->dev, "%s: reset control not set\n", __func__);
>- goto out;
>+ return 0;
> }
>
> reenable_intr = hba->is_irq_enabled;
>@@ -252,7 +253,7 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
> if (ret) {
> dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",
> __func__, ret);
>- goto out;
>+ return ret;
> }
>
> /*
>@@ -274,15 +275,14 @@ static int ufs_qcom_host_reset(struct ufs_hba *hba)
> hba->is_irq_enabled = true;
> }
>
>-out:
>- return ret;
>+ return 0;
> }
>
> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> struct phy *phy = host->generic_phy;
>- int ret = 0;
>+ int ret;
> bool is_rate_B = UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B;
>
> /* Reset UFS Host Controller and PHY */
>@@ -299,7 +299,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> if (ret) {
> dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
> __func__, ret);
>- goto out;
>+ return ret;
> }
>
> /* power on phy - start serdes and phy's power and clocks */
>@@ -316,7 +316,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>
> out_disable_phy:
> phy_exit(phy);
>-out:
>+
> return ret;
> }
>
>@@ -374,7 +374,6 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba,
> static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> u32 hs, u32 rate, bool update_link_startup_timer)
> {
>- int ret = 0;
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> struct ufs_clk_info *clki;
> u32 core_clk_period_in_ns;
>@@ -409,11 +408,11 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> * Aggregation logic.
> */
> if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba))
>- goto out;
>+ return 0;
>
> if (gear == 0) {
> dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
>- goto out_error;
>+ return -EINVAL;
> }
>
> list_for_each_entry(clki, &hba->clk_list_head, list) {
>@@ -436,7 +435,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> }
>
> if (ufs_qcom_cap_qunipro(host))
>- goto out;
>+ return 0;
>
> core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
> core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
>@@ -451,7 +450,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> "%s: index %d exceeds table size %zu\n",
> __func__, gear,
> ARRAY_SIZE(hs_fr_table_rA));
>- goto out_error;
>+ return -EINVAL;
> }
> tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1];
> } else if (rate == PA_HS_MODE_B) {
>@@ -460,13 +459,13 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> "%s: index %d exceeds table size %zu\n",
> __func__, gear,
> ARRAY_SIZE(hs_fr_table_rB));
>- goto out_error;
>+ return -EINVAL;
> }
> tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1];
> } else {
> dev_err(hba->dev, "%s: invalid rate = %d\n",
> __func__, rate);
>- goto out_error;
>+ return -EINVAL;
> }
> break;
> case SLOWAUTO_MODE:
>@@ -476,14 +475,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> "%s: index %d exceeds table size %zu\n",
> __func__, gear,
> ARRAY_SIZE(pwm_fr_table));
>- goto out_error;
>+ return -EINVAL;
> }
> tx_clk_cycles_per_us = pwm_fr_table[gear-1][1];
> break;
> case UNCHANGED:
> default:
> dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs);
>- goto out_error;
>+ return -EINVAL;
> }
>
> if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) !=
>@@ -507,12 +506,8 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear,
> */
> mb();
> }
>- goto out;
>
>-out_error:
>- ret = -EINVAL;
>-out:
>- return ret;
>+ return 0;
> }
>
> static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
>@@ -527,8 +522,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
> 0, true)) {
> dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
> __func__);
>- err = -EINVAL;
>- goto out;
>+ return -EINVAL;
> }
>
> if (ufs_qcom_cap_qunipro(host))
>@@ -554,7 +548,6 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba,
> break;
> }
>
>-out:
> return err;
> }
>
>@@ -691,8 +684,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> if (!dev_req_params) {
> pr_err("%s: incoming dev_req_params is NULL\n", __func__);
>- ret = -EINVAL;
>- goto out;
>+ return -EINVAL;
> }
>
> switch (status) {
>@@ -720,7 +712,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> if (ret) {
> pr_err("%s: failed to determine capabilities\n",
> __func__);
>- goto out;
>+ return ret;
> }
>
> /* enable the device ref clock before changing to HS mode */
>@@ -761,7 +753,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> ret = -EINVAL;
> break;
> }
>-out:
>+
> return ret;
> }
>
>@@ -773,14 +765,11 @@ static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba)
> err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
> &pa_vs_config_reg1);
> if (err)
>- goto out;
>+ return err;
>
> /* Allow extension of MSB bits of PA_SaveConfigTime attribute */
>- err = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
>+ return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1),
> (pa_vs_config_reg1 | (1 << 12)));
>-
>-out:
>- return err;
> }
>
> static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba)
>@@ -957,9 +946,8 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>
> host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
> if (!host) {
>- err = -ENOMEM;
> dev_err(dev, "%s: no memory for qcom ufs host\n", __func__);
>- goto out;
>+ return -ENOMEM;
> }
>
> /* Make a two way bind between the qcom host and the hba */
>@@ -980,10 +968,8 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> host->rcdev.owner = dev->driver->owner;
> host->rcdev.nr_resets = 1;
> err = devm_reset_controller_register(dev, &host->rcdev);
>- if (err) {
>+ if (err)
> dev_warn(dev, "Failed to register reset controller\n");
>- err = 0;
>- }
>
> if (!has_acpi_companion(dev)) {
> host->generic_phy = devm_phy_get(dev, "ufsphy");
>@@ -1049,17 +1035,16 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;
> ufs_qcom_get_default_testbus_cfg(host);
> err = ufs_qcom_testbus_config(host);
>- if (err) {
>+ if (err)
>+ /* Failure is non-fatal */
> dev_warn(dev, "%s: failed to configure the testbus %d\n",
> __func__, err);
>- err = 0;
>- }
>
>- goto out;
>+ return 0;
>
> out_variant_clear:
> ufshcd_set_variant(hba, NULL);
>-out:
>+
> return err;
> }
>
>@@ -1085,7 +1070,7 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
> UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
> &core_clk_ctrl_reg);
> if (err)
>- goto out;
>+ return err;
>
> core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
> core_clk_ctrl_reg |= clk_cycles;
>@@ -1093,11 +1078,9 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
> /* Clear CORE_CLK_DIV_EN */
> core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
>
>- err = ufshcd_dme_set(hba,
>+ return ufshcd_dme_set(hba,
> UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL),
> core_clk_ctrl_reg);
>-out:
>- return err;
> }
>
> static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba)
>@@ -1180,7 +1163,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
>
> if (err || !dev_req_params) {
> ufshcd_uic_hibern8_exit(hba);
>- goto out;
>+ return err;
> }
>
> ufs_qcom_cfg_timers(hba,
>@@ -1191,8 +1174,7 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba,
> ufshcd_uic_hibern8_exit(hba);
> }
>
>-out:
>- return err;
>+ return 0;
> }
>
> static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
--
With best wishes
Dmitry
On 1 December 2022 20:43:14 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
>SM8350 default init sequence sets some PCS registers to HS G3, thereby
>disabling HS G4 mode. This has the effect on MPHY capability negotiation
>between the host and the device during link startup and causes the
>PA_MAXHSGEAR to G3 irrespective of device max gear.
>
>Due to that, the agreed gear speed determined by the UFS core will become
>G3 only and the platform won't run at G4.
>
>So, let's remove setting these registers for SM8350 as like other G4
>compatible platforms. One downside of this is that, when the board design
>uses non-G4 compatible device, then MPHY will continue to run in the
QMP PHY?
>default mode (G4) even if UFSHCD runs in G3. But this is the case for
>other platforms as well.
Should this be fixed by adding a separate set of tables used to setup g3?
>
>Signed-off-by: Manivannan Sadhasivam <[email protected]>
>---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 -------
> 1 file changed, 7 deletions(-)
>
>diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>index d5324c4e8513..6c7c6a06fe3b 100644
>--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>@@ -567,13 +567,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
>- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
>- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
>- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
>- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
>- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
>- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
>- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> };
--
With best wishes
Dmitry
On Tue, Dec 06, 2022 at 12:55:06AM +0300, Dmitry Baryshkov wrote:
>
>
> On 1 December 2022 20:43:14 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
> >SM8350 default init sequence sets some PCS registers to HS G3, thereby
> >disabling HS G4 mode. This has the effect on MPHY capability negotiation
> >between the host and the device during link startup and causes the
> >PA_MAXHSGEAR to G3 irrespective of device max gear.
> >
> >Due to that, the agreed gear speed determined by the UFS core will become
> >G3 only and the platform won't run at G4.
> >
> >So, let's remove setting these registers for SM8350 as like other G4
> >compatible platforms. One downside of this is that, when the board design
> >uses non-G4 compatible device, then MPHY will continue to run in the
>
> QMP PHY?
>
No. MPHY is the actual IP that does the negotiation.
> >default mode (G4) even if UFSHCD runs in G3. But this is the case for
> >other platforms as well.
>
> Should this be fixed by adding a separate set of tables used to setup g3?
>
The default table is G3 only but the issue here is that, with these register
writes, the UFS device PA_MAXHSGEAR register becomes G3 only during MPHY
negotiation. So the host cannot scale up to G4 even if the UFSHCD supports it.
Thanks,
Mani
>
> >
> >Signed-off-by: Manivannan Sadhasivam <[email protected]>
> >---
> > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 -------
> > 1 file changed, 7 deletions(-)
> >
> >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >index d5324c4e8513..6c7c6a06fe3b 100644
> >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >@@ -567,13 +567,6 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
> >- QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
> > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> > };
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்
On Tue, Dec 06, 2022 at 12:51:42AM +0300, Dmitry Baryshkov wrote:
>
>
> On 1 December 2022 20:43:09 GMT+03:00, Manivannan Sadhasivam <[email protected]> wrote:
> >Add separate tables_hs_b instance to allow the PHY driver to configure the
> >PHY in HS Series B mode. The individual SoC configs need to supply the
> >serdes register setting in tables_hs_b and the UFS driver can request the
> >Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B.
> >
> >Reviewed-by: Dmitry Baryshkov <[email protected]>
> >Signed-off-by: Manivannan Sadhasivam <[email protected]>
> >---
> > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >index 516027e356f0..2d5dd336aeb2 100644
> >--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> >@@ -547,6 +547,8 @@ struct qmp_phy_cfg {
> >
> > /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
> > const struct qmp_phy_cfg_tbls tbls;
> >+ /* Additional sequence for HS Series B */
> >+ const struct qmp_phy_cfg_tbls tbls_hs_b;
> >
> > /* clock ids to be requested */
> > const char * const *clk_list;
> >@@ -580,6 +582,7 @@ struct qmp_ufs {
> > struct reset_control *ufs_reset;
> >
> > struct phy *phy;
> >+ u32 mode;
> > };
> >
> > static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
> >@@ -841,6 +844,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> > static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> > {
> > qmp_ufs_serdes_init(qmp, &cfg->tbls);
> >+ if (qmp->mode == PHY_MODE_UFS_HS_B)
> >+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
>
> I still think that qmp_ufs_init_registers() is a way to go here , see the pcie driver.
>
I did use qmp_ufs_init_registers() as a wrapper. Only difference here is that
there is one more level of abstraction which looks cleaner to me.
Thanks,
Mani
> > qmp_ufs_lanes_init(qmp, &cfg->tbls);
> > qmp_ufs_pcs_init(qmp, &cfg->tbls);
> > }
> >@@ -1011,9 +1016,19 @@ static int qmp_ufs_disable(struct phy *phy)
> > return qmp_ufs_exit(phy);
> > }
> >
> >+static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> >+{
> >+ struct qmp_ufs *qmp = phy_get_drvdata(phy);
> >+
> >+ qmp->mode = mode;
> >+
> >+ return 0;
> >+}
> >+
> > static const struct phy_ops qcom_qmp_ufs_phy_ops = {
> > .power_on = qmp_ufs_enable,
> > .power_off = qmp_ufs_disable,
> >+ .set_mode = qmp_ufs_set_mode,
> > .owner = THIS_MODULE,
> > };
> >
>
> --
> With best wishes
> Dmitry
--
மணிவண்ணன் சதாசிவம்