The following series of patches add support for the following
on J721S2 common processor board,
- USB
- SerDes
- OSPI
- PCIe
Changes from v13:
* Rebased on linux-next master as there were merge conflicts
Changes from v12:
* Disabled only the nodes that need additonal info
Changes from v11:
* Cleaned up comments for disabled nodes
* Removed deprecated properties for flash node
Changes from v10:
* Removed the ti,j721e-system-controller bindings document
patch introduced in v9
* Updated mux-controller node with "reg" property to fix dtbs
warnings
* For the nodes which are disabled by default, added comments to
provide the reason behind it
* Dropped Link tags in all patches
Changes from v9:
* Disabled nodes in main.dtsi and enable them in the board
specific DT file
Changes from v8:
* Update the ti,j721e-system-controller bindings document
* Fix dtbs warnings
Changes from v7:
* Fix node names as per bindings document
Changes from v6:
* Changes to ti,j721s2-wiz-10g compatible string from ti,am64-wiz-10g but
requires this series to be merged first
Ref: https://lore.kernel.org/linux-arm-kernel/[email protected]/
* Removed unused pcie1_ep based on feedback
* Switch from incorrect "ti,j721e-system-controller", "syscon", "simple-mfd" compatible for
SPI node to "simple-bus"
Changes from v5:
* Removed Cc from commit messages to reduce clutter
* Squashed changes for device tree nodes that get modified latter in the patchset
series
Changes from v4:
* Add my Signed-off-by lines to all patchsets
Changes from v3:
* Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes'
* Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and
send it own series to avoid a dependency that would hold up other patches in this
series.
Changes from v2:
* Added PCIe RC + EP enablement patchsets
* Added device-id for j722s2 PCIe host in dt documentation
* Reworked SERDES + WIZ enablement patchset to use properies for clocks
defines versus entire devicetree nodes. Results in cleaner code that
doesn't break dt-schema or the driver functionality.
Changes from v1:
* Resolve issues with dt schema reporting
* Minor changes related to consistency on node naming and value
v13: https://lore.kernel.org/all/[email protected]/
v12: https://lore.kernel.org/all/[email protected]/
v11: https://lore.kernel.org/all/[email protected]/
v10: https://lore.kernel.org/all/[email protected]/
v9: https://lore.kernel.org/all/[email protected]/
v8: https://lore.kernel.org/all/[email protected]/
v7: https://lore.kernel.org/all/[email protected]/
v6: https://lore.kernel.org/all/[email protected]/
v5: https://lore.kernel.org/all/[email protected]/
v4: https://lore.kernel.org/all/[email protected]/
v3: https://lore.kernel.org/all/[email protected]/
v2: https://lore.kernel.org/all/[email protected]/
v1: https://lore.kernel.org/all/[email protected]/
Aswath Govindraju (7):
arm64: dts: ti: k3-j721s2-main: Add support for USB
arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
Matt Ranostay (1):
arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
.../dts/ti/k3-j721s2-common-proc-board.dts | 87 +++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 145 ++++++++++++++++++
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 ++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 41 +++++
4 files changed, 317 insertions(+)
base-commit: 4b0f4525dc4fe8af17b3daefe585f0c2eb0fe0a5
--
2.17.1
From: Aswath Govindraju <[email protected]>
Add support for two instance of OSPI in J721S2 SoC.
Reviewed-by: Vaishnav Achath <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
Changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* Disabled only nodes that need additional info
Changes from v11:
* Cleaned up comments
Changes from v10:
* Documented the reason for disabling the nodes by default.
* Removed Link tag from commmit message
Changes from v9:
* Disabled fss, ospi nodes by default in common DT file
Changes from v8:
* Updated "ranges" property to fix dtbs warnings
Changes from v7:
* Removed "reg" property from syscon node
* Renamed the "syscon" node to "bus" to after change in
compatible property
Changes from v6:
* Fixed the syscon node's compatible property
Changes from v5:
* Updated the syscon node's compatible property
* Removed Cc tags from commit message
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* No change
Changes from v1:
* No change
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index a353705a7463..6e981fe4727e 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -379,4 +379,48 @@
compatible = "ti,am3359-adc";
};
};
+
+ fss: bus@47000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x05 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x07 0x00000000 0x01 0x00000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* Needs pinmux */
+ };
+ };
};
--
2.17.1
From: Matt Ranostay <[email protected]>
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
I had reviewed this patch in the v7 series [0].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
[0] - https://lore.kernel.org/lkml/[email protected]/
Changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* Disabled only nodes that need additional info
Changes from v11:
* Cleaned up comments
Changes from v10:
* Fixed dtbs warnings by adding "reg" property to the mux-controller nodes
* Documented the reason for disabling the nodes by default
* Removed Link tag from commit message
Changes from v9:
* Disabled serdes related nodes by default in common DT file
Changes from v8:
* No change
Changes from v7:
* Updated mux-controller node name
Changes from v6:
* Fixed the incorrect "compatible" property
Changes from v5:
* Removed Cc tag from commit message
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* Reworked SERDES + WIZ enablement patchset to use properies for clocks
defines versus entire devicetree nodes. Results in cleaner code that
doesn't break dt-schema or the driver functionality.
Changes from v1:
* Update mux-controller node name
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 57 ++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 8d7b64728f88..931263919086 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -39,6 +50,14 @@
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
+
+ serdes_ln_ctrl: mux-controller@80 {
+ compatible = "mmio-mux";
+ reg = <0x80 0x10>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
};
gic500: interrupt-controller@1800000 {
@@ -790,6 +809,44 @@
};
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721s2-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 365 3>,
+ <&k3_clks 365 3>,
+ <&k3_clks 365 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.17.1
From: Aswath Govindraju <[email protected]>
Configure first lane to PCIe, the second lane to USB and the last two lanes
to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
connected to PCIe.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
I had reviewed this patch in the v5 series [0].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
[0] - https://lore.kernel.org/all/[email protected]/
changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* Removed enabling of "serdes_wiz" node that is already enabled in [2/8]
in this version
Changes from v11:
* No change
Changes from v10:
* Removed Link tag from commit message
Changes from v9:
* Enabled serdes related nodes
Changes from v8:
* No change
Changes from v7:
* No change
Changes from v6:
* No change
Changes from v5:
* Removed Cc tags from commit message
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* No change
Changes from v1:
* No change
.../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index b4b9edfe2d12..1afefaf3f974 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -9,6 +9,9 @@
#include "k3-j721s2-som-p0.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
/ {
compatible = "ti,j721s2-evm", "ti,j721s2";
@@ -322,6 +325,26 @@
phy-handle = <&phy0>;
};
+&serdes_ln_ctrl {
+ idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
+ <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
From: Aswath Govindraju <[email protected]>
The board uses lane 1 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that up to 2 protocols can be used at a time. The SERDES is
wired for PCIe, eDP and USB super-speed. It has been
chosen to use PCIe and eDP as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
I had reviewed this patch in the v5 series [0].
Since I'm taking over upstreaming this series, I removed the self
Reviewed-by tag.
[0] - https://lore.kernel.org/all/[email protected]/
Changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* No change
Changes from v11:
* No change
Changes from v10:
* Removed Link tag from commit message
Changes from v9:
* Enabled USB nodes
Changes from v8:
* No change
Changes from v7:
* No change
Changes from v6:
* No change
Changes from v5:
* Removed Cc tags from commit message
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* No change
Changes from v1:
* No change
.../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 1afefaf3f974..5c4ffb8124ca 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -147,6 +147,12 @@
J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx0 {
@@ -345,6 +351,23 @@
};
};
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 1 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
From: Aswath Govindraju <[email protected]>
J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a
QSPI NOR flash on the common processor board connected to the OSPI1
instance. Add support for the same
Reviewed-by: Vaishnav Achath <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
Changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* Removed enabling of "fss" node that is already enabled in [3/8] in
this version
Changes from v11:
* Remove deprecated properties
Changes from v10:
* Removed Link tag from commit message
Changes from v9:
* Enabled fss and ospi nodes
Changes from v8:
* No change
Changes from v7:
* No change
Changes from v6:
* No change
Changes from v5:
* Removed Cc tags from commit message
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* No change
Changes from v1:
* No change
.../dts/ti/k3-j721s2-common-proc-board.dts | 33 +++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 41 +++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 5c4ffb8124ca..e6d99f19a55f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -232,6 +232,20 @@
J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */
>;
};
+
+ mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */
+ J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */
+ J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */
+ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */
+ J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */
+ J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */
+ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */
+ J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */
+ J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */
+ >;
+ };
};
&main_gpio2 {
@@ -368,6 +382,25 @@
maximum-speed = "high-speed";
};
+&ospi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
+
+ flash@0{
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <2>;
+ };
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
index 6930efff8a5a..d473d79c2757 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
@@ -39,6 +39,28 @@
};
};
+&wkup_pmx0 {
+ mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
+ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
+ J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */
+ J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */
+ J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */
+ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
+ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
+ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
+ J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
+ J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
+ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
+ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
+ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
+ J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
+ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
+ >;
+ };
+};
+
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
@@ -79,3 +101,22 @@
pinctrl-names = "default";
phys = <&transceiver0>;
};
+
+&ospi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <25000000>;
+ cdns,tshsl-ns = <60>;
+ cdns,tsd2d-ns = <60>;
+ cdns,tchsh-ns = <60>;
+ cdns,tslch-ns = <60>;
+ cdns,read-delay = <4>;
+ };
+};
--
2.17.1
From: Aswath Govindraju <[email protected]>
Add PCIe1 RC device tree node for the single PCIe instance present on
the J721S2.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
Changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* No change
Changes from v11:
* Cleaned up comments
Changes from v10:
* Removed Link tag from commit message
Changes from v9:
* No change
Changes from v8:
* No change
Changes from v7:
* No change
Changes from v6:
* Remove the pcie_ep node as device cannot act as RC and EP
at the same time
Changes from v5:
* No change
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* Patch newly added to the series
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 931263919086..6629b2989180 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -847,6 +847,49 @@
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x800000>,
+ <0x00 0x18000000 0x00 0x1000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 276 41>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb013>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
+ <0 0 0 2 &pcie1_intc 0>, /* INT B */
+ <0 0 0 3 &pcie1_intc 0>, /* INT C */
+ <0 0 0 4 &pcie1_intc 0>; /* INT D */
+
+ status = "disabled"; /* Needs gpio and serdes info */
+
+ pcie1_intc: interrupt-controller {
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.17.1
From: Aswath Govindraju <[email protected]>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
Changes from v13:
* No changes. Only rebased on top of linux-next
Changes from v12:
* No change
Changes from v11:
* No change
Changes from v10:
* Removed Link tag from commit message
Changes from v9:
* No change
Changes from v8:
* No change
Changes from v7:
* No change
Changes from v6:
* Removed pcie_ep node update
Changes from v5:
* No change
Changes from v4:
* No change
Changes from v3:
* No change
Changes from v2:
* Patch newly added to the series
arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index e6d99f19a55f..90f90b7b37e1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -401,6 +401,14 @@
};
};
+&pcie1_rc {
+ status = "okay";
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.17.1
Hi,
On 31/03/2023 12:00, Ravi Gunasekaran wrote:
> From: Aswath Govindraju <[email protected]>
>
> Add support for two instance of OSPI in J721S2 SoC.
>
> Reviewed-by: Vaishnav Achath <[email protected]>
> Signed-off-by: Aswath Govindraju <[email protected]>
> Signed-off-by: Matt Ranostay <[email protected]>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> Changes from v13:
> * No changes. Only rebased on top of linux-next
>
> Changes from v12:
> * Disabled only nodes that need additional info
>
> Changes from v11:
> * Cleaned up comments
>
> Changes from v10:
> * Documented the reason for disabling the nodes by default.
> * Removed Link tag from commmit message
>
> Changes from v9:
> * Disabled fss, ospi nodes by default in common DT file
>
> Changes from v8:
> * Updated "ranges" property to fix dtbs warnings
>
> Changes from v7:
> * Removed "reg" property from syscon node
> * Renamed the "syscon" node to "bus" to after change in
> compatible property
>
> Changes from v6:
> * Fixed the syscon node's compatible property
>
> Changes from v5:
> * Updated the syscon node's compatible property
> * Removed Cc tags from commit message
>
> Changes from v4:
> * No change
>
> Changes from v3:
> * No change
>
> Changes from v2:
> * No change
>
> Changes from v1:
> * No change
>
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 +++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index a353705a7463..6e981fe4727e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -379,4 +379,48 @@
> compatible = "ti,am3359-adc";
> };
> };
> +
> + fss: bus@47000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
> + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
> + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
> +
> + ospi0: spi@47040000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47040000 0x00 0x100>,
> + <0x05 0x00000000 0x01 0x00000000>;
> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 109 5>;
> + assigned-clocks = <&k3_clks 109 5>;
> + assigned-clock-parents = <&k3_clks 109 7>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled"; /* Needs pinmux */
> + };
> +
> + ospi1: spi@47050000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47050000 0x00 0x100>,
> + <0x07 0x00000000 0x01 0x00000000>;
> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 110 5>;
What about clock parent and clock rate assignment like it was done for osip0?
> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled"; /* Needs pinmux */
> + };
> + };
> };
cheers,
-roger
Hi,
On 31/03/2023 12:00, Ravi Gunasekaran wrote:
> From: Aswath Govindraju <[email protected]>
>
> Configure first lane to PCIe, the second lane to USB and the last two lanes
> to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
> connected to PCIe.
Is USB0 expected to work in super-speed on this board?
If yes then you need to add USB0 lane information as well.
Otherwise please ignore my comment.
>
> Signed-off-by: Aswath Govindraju <[email protected]>
> Signed-off-by: Matt Ranostay <[email protected]>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> I had reviewed this patch in the v5 series [0].
> Since I'm taking over upstreaming this series, I removed the self
> Reviewed-by tag.
>
> [0] - https://lore.kernel.org/all/[email protected]/
>
> changes from v13:
> * No changes. Only rebased on top of linux-next
>
> Changes from v12:
> * Removed enabling of "serdes_wiz" node that is already enabled in [2/8]
> in this version
>
> Changes from v11:
> * No change
>
> Changes from v10:
> * Removed Link tag from commit message
>
> Changes from v9:
> * Enabled serdes related nodes
>
> Changes from v8:
> * No change
>
> Changes from v7:
> * No change
>
> Changes from v6:
> * No change
>
> Changes from v5:
> * Removed Cc tags from commit message
>
> Changes from v4:
> * No change
>
> Changes from v3:
> * No change
>
> Changes from v2:
> * No change
>
> Changes from v1:
> * No change
>
> .../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> index b4b9edfe2d12..1afefaf3f974 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> @@ -9,6 +9,9 @@
>
> #include "k3-j721s2-som-p0.dtsi"
> #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy-cadence.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/mux/ti-serdes.h>
>
> / {
> compatible = "ti,j721s2-evm", "ti,j721s2";
> @@ -322,6 +325,26 @@
> phy-handle = <&phy0>;
> };
>
> +&serdes_ln_ctrl {
> + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
> + <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>;
> +};
> +
> +&serdes_refclk {
> + clock-frequency = <100000000>;
> +};
> +
> +&serdes0 {
> + status = "okay";
> + serdes0_pcie_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_PCIE>;
> + resets = <&serdes_wiz0 1>;
> + };
> +};
> +
> &mcu_mcan0 {
> status = "okay";
> pinctrl-names = "default";
cheers,
-roger
On 31/03/2023 12:00, Ravi Gunasekaran wrote:
> From: Aswath Govindraju <[email protected]>
>
> The board uses lane 1 of SERDES for USB. Set the mux
> accordingly.
>
> The USB controller and EVM supports super-speed for USB0
> on the Type-C port. However, the SERDES has a limitation
> that up to 2 protocols can be used at a time. The SERDES is
> wired for PCIe, eDP and USB super-speed. It has been
> chosen to use PCIe and eDP as default. So restrict
> USB0 to high-speed mode.
>
> Signed-off-by: Aswath Govindraju <[email protected]>
> Signed-off-by: Matt Ranostay <[email protected]>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> I had reviewed this patch in the v5 series [0].
> Since I'm taking over upstreaming this series, I removed the self
> Reviewed-by tag.
>
> [0] - https://lore.kernel.org/all/[email protected]/
>
> Changes from v13:
> * No changes. Only rebased on top of linux-next
>
> Changes from v12:
> * No change
>
> Changes from v11:
> * No change
>
> Changes from v10:
> * Removed Link tag from commit message
>
> Changes from v9:
> * Enabled USB nodes
>
> Changes from v8:
> * No change
>
> Changes from v7:
> * No change
>
> Changes from v6:
> * No change
>
> Changes from v5:
> * Removed Cc tags from commit message
>
> Changes from v4:
> * No change
>
> Changes from v3:
> * No change
>
> Changes from v2:
> * No change
>
> Changes from v1:
> * No change
>
> .../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> index 1afefaf3f974..5c4ffb8124ca 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> @@ -147,6 +147,12 @@
> J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
> >;
> };
> +
> + main_usbss0_pins_default: main-usbss0-pins-default {
> + pinctrl-single,pins = <
> + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
What about USB0_ID pin?
> + >;
> + };
> };
>
> &wkup_pmx0 {
> @@ -345,6 +351,23 @@
> };
> };
>
> +&usb_serdes_mux {
> + idle-states = <1>; /* USB0 to SERDES lane 1 */
> +};
> +
> +&usbss0 {
> + status = "okay";
> + pinctrl-0 = <&main_usbss0_pins_default>;
> + pinctrl-names = "default";
> + ti,vbus-divider;
> + ti,usb2-only;
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + maximum-speed = "high-speed";
Why is super-speed not possible?
I understood that SERDES lane 1 can be used for USB super-speed.
> +};
> +
> &mcu_mcan0 {
> status = "okay";
> pinctrl-names = "default";
cheers,
-roger
Roger,
On 25/04/23 5:15 pm, Roger Quadros wrote:
> Hi,
>
> On 31/03/2023 12:00, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju <[email protected]>
>>
>> Configure first lane to PCIe, the second lane to USB and the last two lanes
>> to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is
>> connected to PCIe.
>
> Is USB0 expected to work in super-speed on this board?
> If yes then you need to add USB0 lane information as well.
> Otherwise please ignore my comment.
>
The SerDes on J721S2 can simultaneously support only two protocols.
By default PCIe and DP will be supported. Due to this, USB is configured
in high-speed and this does not require any SerDes lane configuration.
>>
>> Signed-off-by: Aswath Govindraju <[email protected]>
>> Signed-off-by: Matt Ranostay <[email protected]>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
[...]
>
> cheers,
> -roger
--
Regards,
Ravi
On 25/04/23 5:31 pm, Roger Quadros wrote:
>
>
> On 31/03/2023 12:00, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju <[email protected]>
>>
>> The board uses lane 1 of SERDES for USB. Set the mux
>> accordingly.
>>
>> The USB controller and EVM supports super-speed for USB0
>> on the Type-C port. However, the SERDES has a limitation
>> that up to 2 protocols can be used at a time. The SERDES is
>> wired for PCIe, eDP and USB super-speed. It has been
>> chosen to use PCIe and eDP as default. So restrict
>> USB0 to high-speed mode.
>>
>> Signed-off-by: Aswath Govindraju <[email protected]>
>> Signed-off-by: Matt Ranostay <[email protected]>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> I had reviewed this patch in the v5 series [0].
>> Since I'm taking over upstreaming this series, I removed the self
>> Reviewed-by tag.
>>
[...]
>> * No change
>>
>> .../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> index 1afefaf3f974..5c4ffb8124ca 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> @@ -147,6 +147,12 @@
>> J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>> >;
>> };
>> +
>> + main_usbss0_pins_default: main-usbss0-pins-default {
>> + pinctrl-single,pins = <
>> + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
>
> What about USB0_ID pin?
>
The pin (AC9) for USB0_ID signal is not multiplexed with any other signals.
Please see Page 51 in [0].
>> + >;
>> + };
>> };
>>
[...]
>> +
>> +&usb0 {
>> + dr_mode = "otg";
>> + maximum-speed = "high-speed";
>
> Why is super-speed not possible?
> I understood that SERDES lane 1 can be used for USB super-speed.
The SerDes on J721S2 can simultaneously support only two protocols.
By default PCIe and DP will be supported. Due to this, USB is configured
in high-speed and this does not require any SerDes lane configuration.
>
>> +};
>> +
>> &mcu_mcan0 {
>> status = "okay";
>> pinctrl-names = "default";
>
> cheers,
> -roger
[0] https://www.ti.com/lit/gpn/TDA4AL-Q1
--
Regards,
Ravi
On 31/03/2023 12:00, Ravi Gunasekaran wrote:
> The following series of patches add support for the following
> on J721S2 common processor board,
>
> - USB
> - SerDes
> - OSPI
> - PCIe
>
> Changes from v13:
> * Rebased on linux-next master as there were merge conflicts
>
> Changes from v12:
> * Disabled only the nodes that need additonal info
>
> Changes from v11:
> * Cleaned up comments for disabled nodes
> * Removed deprecated properties for flash node
>
> Changes from v10:
> * Removed the ti,j721e-system-controller bindings document
> patch introduced in v9
> * Updated mux-controller node with "reg" property to fix dtbs
> warnings
> * For the nodes which are disabled by default, added comments to
> provide the reason behind it
> * Dropped Link tags in all patches
>
> Changes from v9:
> * Disabled nodes in main.dtsi and enable them in the board
> specific DT file
>
> Changes from v8:
> * Update the ti,j721e-system-controller bindings document
> * Fix dtbs warnings
>
> Changes from v7:
> * Fix node names as per bindings document
>
> Changes from v6:
> * Changes to ti,j721s2-wiz-10g compatible string from ti,am64-wiz-10g but
> requires this series to be merged first
> Ref: https://lore.kernel.org/linux-arm-kernel/[email protected]/
> * Removed unused pcie1_ep based on feedback
> * Switch from incorrect "ti,j721e-system-controller", "syscon", "simple-mfd" compatible for
> SPI node to "simple-bus"
>
> Changes from v5:
> * Removed Cc from commit messages to reduce clutter
> * Squashed changes for device tree nodes that get modified latter in the patchset
> series
>
> Changes from v4:
> * Add my Signed-off-by lines to all patchsets
>
> Changes from v3:
> * Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes'
> * Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and
> send it own series to avoid a dependency that would hold up other patches in this
> series.
>
> Changes from v2:
> * Added PCIe RC + EP enablement patchsets
> * Added device-id for j722s2 PCIe host in dt documentation
> * Reworked SERDES + WIZ enablement patchset to use properies for clocks
> defines versus entire devicetree nodes. Results in cleaner code that
> doesn't break dt-schema or the driver functionality.
>
> Changes from v1:
> * Resolve issues with dt schema reporting
> * Minor changes related to consistency on node naming and value
>
> v13: https://lore.kernel.org/all/[email protected]/
> v12: https://lore.kernel.org/all/[email protected]/
> v11: https://lore.kernel.org/all/[email protected]/
> v10: https://lore.kernel.org/all/[email protected]/
> v9: https://lore.kernel.org/all/[email protected]/
> v8: https://lore.kernel.org/all/[email protected]/
> v7: https://lore.kernel.org/all/[email protected]/
> v6: https://lore.kernel.org/all/[email protected]/
> v5: https://lore.kernel.org/all/[email protected]/
> v4: https://lore.kernel.org/all/[email protected]/
> v3: https://lore.kernel.org/all/[email protected]/
> v2: https://lore.kernel.org/all/[email protected]/
> v1: https://lore.kernel.org/all/[email protected]/
>
> Aswath Govindraju (7):
> arm64: dts: ti: k3-j721s2-main: Add support for USB
> arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
> arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
> arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
> arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
> arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
> arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
>
> Matt Ranostay (1):
> arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
>
> .../dts/ti/k3-j721s2-common-proc-board.dts | 87 +++++++++++
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 145 ++++++++++++++++++
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 ++++++
> arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 41 +++++
> 4 files changed, 317 insertions(+)
>
>
> base-commit: 4b0f4525dc4fe8af17b3daefe585f0c2eb0fe0a5
For this series:
Reviewed-by: Roger Quadros <[email protected]>
Roger,
On 4/25/2023 5:02 PM, Roger Quadros wrote:
> Hi,
>
> On 31/03/2023 12:00, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju <[email protected]>
>>
>> Add support for two instance of OSPI in J721S2 SoC.
>>
>> Reviewed-by: Vaishnav Achath <[email protected]>
>> Signed-off-by: Aswath Govindraju <[email protected]>
>> Signed-off-by: Matt Ranostay <[email protected]>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
[...]
>> + clocks = <&k3_clks 109 5>;
>> + assigned-clocks = <&k3_clks 109 5>;
>> + assigned-clock-parents = <&k3_clks 109 7>;
>> + assigned-clock-rates = <166666666>;
>> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled"; /* Needs pinmux */
>> + };
>> +
>> + ospi1: spi@47050000 {
>> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
>> + reg = <0x00 0x47050000 0x00 0x100>,
>> + <0x07 0x00000000 0x01 0x00000000>;
>> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
>> + cdns,fifo-depth = <256>;
>> + cdns,fifo-width = <4>;
>> + cdns,trigger-address = <0x0>;
>> + clocks = <&k3_clks 110 5>;
> What about clock parent and clock rate assignment like it was done for osip0?
ospi1 uses default values.
>> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled"; /* Needs pinmux */
>> + };
>> + };
>> };
> cheers,
> -roger
Hi Ravi Gunasekaran,
On Fri, 31 Mar 2023 14:30:20 +0530, Ravi Gunasekaran wrote:
> The following series of patches add support for the following
> on J721S2 common processor board,
>
> - USB
> - SerDes
> - OSPI
> - PCIe
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/8] arm64: dts: ti: k3-j721s2-main: Add support for USB
commit: 20fcf9d691ff6cde865f8486288b7babe1826b49
[2/8] arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
commit: 393eee04065d26d53e9167e3721ad9a0ff89d40f
[3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
commit: 80cfbf2f4ac735ab8e72a3c70188c433f06810c1
[4/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
commit: da61731dc7f5d7a676acd81124229b57e6fbe0ef
[5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
commit: 7743a9d7517a6a1f3b21d32db3bc1d00d6b16983
[6/8] arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
commit: bbabba4ece74c51b98e7c8dbd8fa4725d0ae9baf
[7/8] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
commit: b6f18aa80f4eee59f9292f0007c021cb7e7dbbec
[8/8] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
commit: 715084ecc25adafe7f724721807b64fcc3a13e4a
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh