This Patch series adds support for 32 bits per word trasfers using DMA
and some defensive checks around dma controller capabilities.
---
V1 Changes : Add support for AxSize=4 bytes to support 32bits/word.
---
V1->V2 Changes : Add dma capability check to make sure address widths
are supported.
---
V2->V3 Changes : Split changes , add DMA direction check and other
cosmetic chnages.
---
V3->V4 Changes : Fix Sparce Warning
| Reported-by: kernel test robot <[email protected]>
| Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
---
V4->V5 Changes : Preserve reverse xmas Tree order, move direction
check before initalisation of further capabilities, remove zero
initialisations, remove error OR'ing.
---
V5->V6 Changes :
-Remove case of n_bytes=3 using 4_bytes buswidth
-Avoid forward decaration
-Break capability check patch into 2
-round n_bytes to power of 2 ( Bug Fix)
-Add more explanation in commit text.
---
V6->V7 Changes : Remove extra spaces, refer to functions in commit as
func()
---
Joy Chakraborty (5):
spi: dw: Add 32 bpw support to SPI DW DMA driver
spi: dw: Move dw_spi_can_dma()
spi: dw: Add DMA directional capability check
spi: dw: Add DMA address widths capability check
spi: dw: Round of n_bytes to power of 2
drivers/spi/spi-dw-core.c | 2 +-
drivers/spi/spi-dw-dma.c | 75 +++++++++++++++++++++++++++++----------
drivers/spi/spi-dw.h | 1 +
3 files changed, 59 insertions(+), 19 deletions(-)
--
2.40.0.634.g4ca3ef3211-goog
Move dw_spi_can_dma() implementation below dw_spi_dma_convert_width()
for handing compile dependency in future patches.
Signed-off-by: Joy Chakraborty <[email protected]>
---
drivers/spi/spi-dw-dma.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index c1b42cb59965..f19c092920a1 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -198,14 +198,6 @@ static irqreturn_t dw_spi_dma_transfer_handler(struct dw_spi *dws)
return IRQ_HANDLED;
}
-static bool dw_spi_can_dma(struct spi_controller *master,
- struct spi_device *spi, struct spi_transfer *xfer)
-{
- struct dw_spi *dws = spi_controller_get_devdata(master);
-
- return xfer->len > dws->fifo_len;
-}
-
static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
{
switch (n_bytes) {
@@ -220,6 +212,14 @@ static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
}
}
+static bool dw_spi_can_dma(struct spi_controller *master,
+ struct spi_device *spi, struct spi_transfer *xfer)
+{
+ struct dw_spi *dws = spi_controller_get_devdata(master);
+
+ return xfer->len > dws->fifo_len;
+}
+
static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
{
unsigned long long ms;
--
2.40.0.634.g4ca3ef3211-goog
Store address width capabilities of DMA controller during init and check
the same per transfer to make sure the bits/word requirement can be met.
Current DW DMA driver requires both tx and rx channel to be configured
and functional hence a subset of both tx and rx channel address width
capability is checked with the width requirement(n_bytes) for a
transfer.
Signed-off-by: Joy Chakraborty <[email protected]>
---
drivers/spi/spi-dw-dma.c | 16 +++++++++++++++-
drivers/spi/spi-dw.h | 1 +
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index 22d0727a3789..45980c46946d 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -97,6 +97,14 @@ static int dw_spi_dma_caps_init(struct dw_spi *dws)
dws->dma_sg_burst = rx.max_sg_burst;
else
dws->dma_sg_burst = 0;
+
+ /*
+ * Assuming both channels belong to the same DMA controller hence the
+ * address width capabilities most likely would be the same.
+ */
+ dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths;
+
+ return 0;
}
static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
@@ -237,8 +245,14 @@ static bool dw_spi_can_dma(struct spi_controller *master,
struct spi_device *spi, struct spi_transfer *xfer)
{
struct dw_spi *dws = spi_controller_get_devdata(master);
+ enum dma_slave_buswidth dma_bus_width;
+
+ if (xfer->len <= dws->fifo_len)
+ return false;
+
+ dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes);
- return xfer->len > dws->fifo_len;
+ return dws->dma_addr_widths & BIT(dma_bus_width);
}
static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 9e8eb2b52d5c..3962e6dcf880 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -190,6 +190,7 @@ struct dw_spi {
struct dma_chan *rxchan;
u32 rxburst;
u32 dma_sg_burst;
+ u32 dma_addr_widths;
unsigned long dma_chan_busy;
dma_addr_t dma_addr; /* phy address of the Data register */
const struct dw_spi_dma_ops *dma_ops;
--
2.40.0.634.g4ca3ef3211-goog
Add Support for AxSize = 4 bytes configuration from dw dma driver if
n_bytes i.e. number of bytes per write to fifo is 4.
Number of bytes written to fifo per write is depended on the bits/word
configuration being used which the DW core driver translates to n_bytes.
Hence, for bits per word values between 17 and 32 n_bytes should be
equal to 4.
Signed-off-by: Joy Chakraborty <[email protected]>
---
drivers/spi/spi-dw-dma.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index ababb910b391..c1b42cb59965 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -208,12 +208,16 @@ static bool dw_spi_can_dma(struct spi_controller *master,
static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
{
- if (n_bytes == 1)
+ switch (n_bytes) {
+ case 1:
return DMA_SLAVE_BUSWIDTH_1_BYTE;
- else if (n_bytes == 2)
+ case 2:
return DMA_SLAVE_BUSWIDTH_2_BYTES;
-
- return DMA_SLAVE_BUSWIDTH_UNDEFINED;
+ case 4:
+ return DMA_SLAVE_BUSWIDTH_4_BYTES;
+ default:
+ return DMA_SLAVE_BUSWIDTH_UNDEFINED;
+ }
}
static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
--
2.40.0.634.g4ca3ef3211-goog
n_bytes variable in the driver represents the number of bytes per word
that needs to be sent/copied to fifo. Bits/word can be between 8 and 32
bits from the client but in memory they are a power of 2, same is mentioned
in spi.h header:
"
* @bits_per_word: Data transfers involve one or more words; word sizes
* like eight or 12 bits are common. In-memory wordsizes are
* powers of two bytes (e.g. 20 bit samples use 32 bits).
* This may be changed by the device's driver, or left at the
* default (0) indicating protocol words are eight bit bytes.
* The spi_transfer.bits_per_word can override this for each transfer.
"
Hence, round of n_bytes to a power of 2 to avoid values like 3 which
would generate unalligned/odd accesses to memory/fifo.
Fixes: a51acc2400d4 ("spi: dw: Add support for 32-bits max xfer size")
Suggested-by: Andy Shevchenko <[email protected]>
Signed-off-by: Joy Chakraborty <[email protected]>
---
drivers/spi/spi-dw-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index c3bfb6c84cab..a6486db46c61 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -426,7 +426,7 @@ static int dw_spi_transfer_one(struct spi_controller *master,
int ret;
dws->dma_mapped = 0;
- dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+ dws->n_bytes = roundup_pow_of_two(DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE));
dws->tx = (void *)transfer->tx_buf;
dws->tx_len = transfer->len / dws->n_bytes;
dws->rx = transfer->rx_buf;
--
2.40.0.634.g4ca3ef3211-goog
Check capabilities of DMA controller during init to make sure it is
capable of handling MEM2DEV for tx channel, DEV2MEM for rx channel.
Current DW DMA driver requires both tx and rx channel to be configured
and functional for any kind of transfers to take effect including
half duplex. Hence, check for both tx and rx direction and fail on
unavailbility of either.
Signed-off-by: Joy Chakraborty <[email protected]>
---
drivers/spi/spi-dw-dma.c | 39 ++++++++++++++++++++++++++++++---------
1 file changed, 30 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
index f19c092920a1..22d0727a3789 100644
--- a/drivers/spi/spi-dw-dma.c
+++ b/drivers/spi/spi-dw-dma.c
@@ -72,12 +72,22 @@ static void dw_spi_dma_maxburst_init(struct dw_spi *dws)
dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
}
-static void dw_spi_dma_sg_burst_init(struct dw_spi *dws)
+static int dw_spi_dma_caps_init(struct dw_spi *dws)
{
- struct dma_slave_caps tx = {0}, rx = {0};
+ struct dma_slave_caps tx, rx;
+ int ret;
+
+ ret = dma_get_slave_caps(dws->txchan, &tx);
+ if (ret)
+ return ret;
+
+ ret = dma_get_slave_caps(dws->rxchan, &rx);
+ if (ret)
+ return ret;
- dma_get_slave_caps(dws->txchan, &tx);
- dma_get_slave_caps(dws->rxchan, &rx);
+ if (!(tx.directions & BIT(DMA_MEM_TO_DEV) &&
+ rx.directions & BIT(DMA_DEV_TO_MEM)))
+ return -ENXIO;
if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0)
dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst);
@@ -95,6 +105,7 @@ static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
struct dw_dma_slave dma_rx = { .src_id = 0 }, *rx = &dma_rx;
struct pci_dev *dma_dev;
dma_cap_mask_t mask;
+ int ret = -EBUSY;
/*
* Get pci device for DMA controller, currently it could only
@@ -124,20 +135,25 @@ static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
init_completion(&dws->dma_completion);
- dw_spi_dma_maxburst_init(dws);
+ ret = dw_spi_dma_caps_init(dws);
+ if (ret)
+ goto free_txchan;
- dw_spi_dma_sg_burst_init(dws);
+ dw_spi_dma_maxburst_init(dws);
pci_dev_put(dma_dev);
return 0;
+free_txchan:
+ dma_release_channel(dws->txchan);
+ dws->txchan = NULL;
free_rxchan:
dma_release_channel(dws->rxchan);
dws->rxchan = NULL;
err_exit:
pci_dev_put(dma_dev);
- return -EBUSY;
+ return ret;
}
static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
@@ -163,12 +179,17 @@ static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
init_completion(&dws->dma_completion);
- dw_spi_dma_maxburst_init(dws);
+ ret = dw_spi_dma_caps_init(dws);
+ if (ret)
+ goto free_txchan;
- dw_spi_dma_sg_burst_init(dws);
+ dw_spi_dma_maxburst_init(dws);
return 0;
+free_txchan:
+ dma_release_channel(dws->txchan);
+ dws->txchan = NULL;
free_rxchan:
dma_release_channel(dws->rxchan);
dws->rxchan = NULL;
--
2.40.0.634.g4ca3ef3211-goog
On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
> Store address width capabilities of DMA controller during init and check
> the same per transfer to make sure the bits/word requirement can be met.
>
> Current DW DMA driver requires both tx and rx channel to be configured
> and functional hence a subset of both tx and rx channel address width
> capability is checked with the width requirement(n_bytes) for a
> transfer.
...
> + /*
> + * Assuming both channels belong to the same DMA controller hence the
> + * address width capabilities most likely would be the same.
> + */
I had a small comment on this In v6 thread.
--
With Best Regards,
Andy Shevchenko
On Tue, Apr 18, 2023 at 1:08 PM Andy Shevchenko
<[email protected]> wrote:
>
> On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
> > Store address width capabilities of DMA controller during init and check
> > the same per transfer to make sure the bits/word requirement can be met.
> >
> > Current DW DMA driver requires both tx and rx channel to be configured
> > and functional hence a subset of both tx and rx channel address width
> > capability is checked with the width requirement(n_bytes) for a
> > transfer.
>
> ...
>
> > + /*
> > + * Assuming both channels belong to the same DMA controller hence the
> > + * address width capabilities most likely would be the same.
> > + */
>
> I had a small comment on this In v6 thread.
Sure,
Your comment in V6 thread:
"
I would add something to explain the side of these address width, like
* Assuming both channels belong to the same DMA controller hence
* the peripheral side address width capabilities most likely would
* be the same.
"
I do not think the address width capabilities are dependent on the
side of generation like memory or peripheral. From what I understand,
address width capabilities are solely dependent on the transaction
generation capability of the DMA controller towards the system bus.
What we intend to highlight here is the assumption that both tx and rx
channel would belong to the same DMA controller hence the transaction
generation capabilities would be the same both for read and write
(e.g. if the DMA controller is able to generate 32 bit sized reads
then it should also be able to generate 32 bit sized writes).
With this assumption we are doing a bitwise and of both tx and rx capabilities.
Please let me know if you think otherwise.
Thanks
Joy
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
On Wed, Apr 19, 2023 at 11:18:25AM +0530, Joy Chakraborty wrote:
> On Tue, Apr 18, 2023 at 1:08 PM Andy Shevchenko
> <[email protected]> wrote:
> > On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
...
> > > + /*
> > > + * Assuming both channels belong to the same DMA controller hence the
> > > + * address width capabilities most likely would be the same.
> > > + */
> >
> > I had a small comment on this In v6 thread.
>
> Sure,
>
> Your comment in V6 thread:
> "
> I would add something to explain the side of these address width, like
>
> * Assuming both channels belong to the same DMA controller hence
> * the peripheral side address width capabilities most likely would
> * be the same.
> "
>
> I do not think the address width capabilities are dependent on the
> side of generation like memory or peripheral.
Yes, they are independent. Memory could do with 4 bytes, while peripheral with
1 byte and so on.
> From what I understand,
> address width capabilities are solely dependent on the transaction
> generation capability of the DMA controller towards the system bus.
What do you mean by a SB in the above? Memory? Peripheral?
> What we intend to highlight here is the assumption that both tx and rx
> channel would belong to the same DMA controller hence the transaction
> generation capabilities would be the same both for read and write
> (e.g. if the DMA controller is able to generate 32 bit sized reads
> then it should also be able to generate 32 bit sized writes).
> With this assumption we are doing a bitwise and of both tx and rx capabilities.
>
> Please let me know if you think otherwise.
--
With Best Regards,
Andy Shevchenko
On Wed, Apr 19, 2023 at 5:19 PM Andy Shevchenko
<[email protected]> wrote:
>
> On Wed, Apr 19, 2023 at 11:18:25AM +0530, Joy Chakraborty wrote:
> > On Tue, Apr 18, 2023 at 1:08 PM Andy Shevchenko
> > <[email protected]> wrote:
> > > On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
>
> ...
>
> > > > + /*
> > > > + * Assuming both channels belong to the same DMA controller hence the
> > > > + * address width capabilities most likely would be the same.
> > > > + */
> > >
> > > I had a small comment on this In v6 thread.
> >
> > Sure,
> >
> > Your comment in V6 thread:
> > "
> > I would add something to explain the side of these address width, like
> >
> > * Assuming both channels belong to the same DMA controller hence
> > * the peripheral side address width capabilities most likely would
> > * be the same.
> > "
> >
> > I do not think the address width capabilities are dependent on the
> > side of generation like memory or peripheral.
>
> Yes, they are independent. Memory could do with 4 bytes, while peripheral with
> 1 byte and so on.
>
> > From what I understand,
> > address width capabilities are solely dependent on the transaction
> > generation capability of the DMA controller towards the system bus.
>
> What do you mean by a SB in the above? Memory? Peripheral?
By system bus I mean anything that is connecting the Memory, DMA and
the peripheral.
Something like :
+-----------+ +-------------------+
| | | |
| DMA | | PERIPHERAL |
| | | |
+----^-+---+ +-----+--^---------+
*** -->| | | |
| | | |
<------------+-v--------------------v---+------------->
SYSTEM BUS
<---------------------+--^----------------------------->
| |
| |
+----v--+-----+
| |
| MEMORY |
| |
+--------------+
*** : Address width capabilities should be the capability of the DMA
to generate transactions to the system bus on the marked interface
irrespective of whether it is destined for Peripheral or memory is
what I understand.
>
> > What we intend to highlight here is the assumption that both tx and rx
> > channel would belong to the same DMA controller hence the transaction
> > generation capabilities would be the same both for read and write
> > (e.g. if the DMA controller is able to generate 32 bit sized reads
> > then it should also be able to generate 32 bit sized writes).
> > With this assumption we are doing a bitwise and of both tx and rx capabilities.
> >
> > Please let me know if you think otherwise.
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
On Wed, Apr 19, 2023 at 6:18 PM Joy Chakraborty <[email protected]> wrote:
>
> On Wed, Apr 19, 2023 at 5:19 PM Andy Shevchenko
> <[email protected]> wrote:
> >
> > On Wed, Apr 19, 2023 at 11:18:25AM +0530, Joy Chakraborty wrote:
> > > On Tue, Apr 18, 2023 at 1:08 PM Andy Shevchenko
> > > <[email protected]> wrote:
> > > > On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
> >
> > ...
> >
> > > > > + /*
> > > > > + * Assuming both channels belong to the same DMA controller hence the
> > > > > + * address width capabilities most likely would be the same.
> > > > > + */
> > > >
> > > > I had a small comment on this In v6 thread.
> > >
> > > Sure,
> > >
> > > Your comment in V6 thread:
> > > "
> > > I would add something to explain the side of these address width, like
> > >
> > > * Assuming both channels belong to the same DMA controller hence
> > > * the peripheral side address width capabilities most likely would
> > > * be the same.
> > > "
> > >
> > > I do not think the address width capabilities are dependent on the
> > > side of generation like memory or peripheral.
> >
> > Yes, they are independent. Memory could do with 4 bytes, while peripheral with
> > 1 byte and so on.
> >
> > > From what I understand,
> > > address width capabilities are solely dependent on the transaction
> > > generation capability of the DMA controller towards the system bus.
> >
> > What do you mean by a SB in the above? Memory? Peripheral?
>
> By system bus I mean anything that is connecting the Memory, DMA and
> the peripheral.
> Something like :
>
> +-----------+ +-------------------+
> | | | |
> | DMA | | PERIPHERAL |
> | | | |
> +----^-+---+ +-----+--^---------+
> *** -->| | | |
> | | | |
> <------------+-v--------------------v---+------------->
> SYSTEM BUS
> <---------------------+--^----------------------------->
> | |
> | |
> +----v--+-----+
> | |
> | MEMORY |
> | |
> +--------------+
> *** : Address width capabilities should be the capability of the DMA
> to generate transactions to the system bus on the marked interface
> irrespective of whether it is destined for Peripheral or memory is
> what I understand.
>
Looks like the diagram did not come correctly, repasting:
+----------+ +---------------+
| | | |
| DMA | | PERIPHERAL |
| | | |
+----^-+---+ +-----+--^------+
***-->| | | |
| | | |
| | | |
<------------+-v--------------------v--+--------------->
SYSTEM BUS
<---------------------+--^----------------------------->
| |
| |
| |
+----v--+-----+
| MEMORY |
| |
+-------------+
> >
> > > What we intend to highlight here is the assumption that both tx and rx
> > > channel would belong to the same DMA controller hence the transaction
> > > generation capabilities would be the same both for read and write
> > > (e.g. if the DMA controller is able to generate 32 bit sized reads
> > > then it should also be able to generate 32 bit sized writes).
> > > With this assumption we are doing a bitwise and of both tx and rx capabilities.
> > >
> > > Please let me know if you think otherwise.
> >
> > --
> > With Best Regards,
> > Andy Shevchenko
> >
> >
On Wed, Apr 19, 2023 at 06:18:04PM +0530, Joy Chakraborty wrote:
> On Wed, Apr 19, 2023 at 5:19 PM Andy Shevchenko
> <[email protected]> wrote:
> > On Wed, Apr 19, 2023 at 11:18:25AM +0530, Joy Chakraborty wrote:
> > > On Tue, Apr 18, 2023 at 1:08 PM Andy Shevchenko
> > > <[email protected]> wrote:
> > > > On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
...
> > > > > + /*
> > > > > + * Assuming both channels belong to the same DMA controller hence the
> > > > > + * address width capabilities most likely would be the same.
> > > > > + */
> > > >
> > > > I had a small comment on this In v6 thread.
> > >
> > > Sure,
> > >
> > > Your comment in V6 thread:
> > > "
> > > I would add something to explain the side of these address width, like
> > >
> > > * Assuming both channels belong to the same DMA controller hence
> > > * the peripheral side address width capabilities most likely would
> > > * be the same.
> > > "
> > >
> > > I do not think the address width capabilities are dependent on the
> > > side of generation like memory or peripheral.
> >
> > Yes, they are independent. Memory could do with 4 bytes, while peripheral with
> > 1 byte and so on.
> >
> > > From what I understand,
> > > address width capabilities are solely dependent on the transaction
> > > generation capability of the DMA controller towards the system bus.
> >
> > What do you mean by a SB in the above? Memory? Peripheral?
>
> By system bus I mean anything that is connecting the Memory, DMA and
> the peripheral.
> Something like :
>
> +-----------+ +-------------------+
> | | | |
> | DMA | | PERIPHERAL |
> | | | |
> +----^-+---+ +-----+--^---------+
> *** -->| | | |
> | | | |
> <------------+-v--------------------v---+------------->
> SYSTEM BUS
> <---------------------+--^----------------------------->
> | |
> | |
> +----v--+-----+
> | |
> | MEMORY |
> | |
> +--------------+
> *** : Address width capabilities should be the capability of the DMA
> to generate transactions to the system bus on the marked interface
> irrespective of whether it is destined for Peripheral or memory is
> what I understand.
That's misunderstanding. You used only one possible HW design, there may be
more. For example we have Synopsys DesignWare DMA that has a lot of parameters
to configure bus mastering. One of such a case, where it makes a lot of sense,
is DesignWare SATA with the above mentioned DMA controller where it has two
masters and they are connected towards memory and towards peripheral "buses".
They have _different_ configurations.
So, generally speaking what you are saying is not true.
> > > What we intend to highlight here is the assumption that both tx and rx
> > > channel would belong to the same DMA controller hence the transaction
> > > generation capabilities would be the same both for read and write
> > > (e.g. if the DMA controller is able to generate 32 bit sized reads
> > > then it should also be able to generate 32 bit sized writes).
> > > With this assumption we are doing a bitwise and of both tx and rx capabilities.
> > >
> > > Please let me know if you think otherwise.
--
With Best Regards,
Andy Shevchenko
On Wed, Apr 19, 2023 at 11:05 PM Andy Shevchenko
<[email protected]> wrote:
>
> On Wed, Apr 19, 2023 at 06:18:04PM +0530, Joy Chakraborty wrote:
> > On Wed, Apr 19, 2023 at 5:19 PM Andy Shevchenko
> > <[email protected]> wrote:
> > > On Wed, Apr 19, 2023 at 11:18:25AM +0530, Joy Chakraborty wrote:
> > > > On Tue, Apr 18, 2023 at 1:08 PM Andy Shevchenko
> > > > <[email protected]> wrote:
> > > > > On Tue, Apr 18, 2023 at 05:29:01AM +0000, Joy Chakraborty wrote:
>
> ...
>
> > > > > > + /*
> > > > > > + * Assuming both channels belong to the same DMA controller hence the
> > > > > > + * address width capabilities most likely would be the same.
> > > > > > + */
> > > > >
> > > > > I had a small comment on this In v6 thread.
> > > >
> > > > Sure,
> > > >
> > > > Your comment in V6 thread:
> > > > "
> > > > I would add something to explain the side of these address width, like
> > > >
> > > > * Assuming both channels belong to the same DMA controller hence
> > > > * the peripheral side address width capabilities most likely would
> > > > * be the same.
> > > > "
> > > >
> > > > I do not think the address width capabilities are dependent on the
> > > > side of generation like memory or peripheral.
> > >
> > > Yes, they are independent. Memory could do with 4 bytes, while peripheral with
> > > 1 byte and so on.
> > >
> > > > From what I understand,
> > > > address width capabilities are solely dependent on the transaction
> > > > generation capability of the DMA controller towards the system bus.
> > >
> > > What do you mean by a SB in the above? Memory? Peripheral?
> >
> > By system bus I mean anything that is connecting the Memory, DMA and
> > the peripheral.
> > Something like :
> >
> > +-----------+ +-------------------+
> > | | | |
> > | DMA | | PERIPHERAL |
> > | | | |
> > +----^-+---+ +-----+--^---------+
> > *** -->| | | |
> > | | | |
> > <------------+-v--------------------v---+------------->
> > SYSTEM BUS
> > <---------------------+--^----------------------------->
> > | |
> > | |
> > +----v--+-----+
> > | |
> > | MEMORY |
> > | |
> > +--------------+
> > *** : Address width capabilities should be the capability of the DMA
> > to generate transactions to the system bus on the marked interface
> > irrespective of whether it is destined for Peripheral or memory is
> > what I understand.
>
> That's misunderstanding. You used only one possible HW design, there may be
> more. For example we have Synopsys DesignWare DMA that has a lot of parameters
> to configure bus mastering. One of such a case, where it makes a lot of sense,
> is DesignWare SATA with the above mentioned DMA controller where it has two
> masters and they are connected towards memory and towards peripheral "buses".
> They have _different_ configurations.
>
> So, generally speaking what you are saying is not true.
Got it, thank you for the clarification.
I misunderstood what you meant, that peripheral access can be from a
different path.
I shall add to the comment as you suggested and send another patch.
>
> > > > What we intend to highlight here is the assumption that both tx and rx
> > > > channel would belong to the same DMA controller hence the transaction
> > > > generation capabilities would be the same both for read and write
> > > > (e.g. if the DMA controller is able to generate 32 bit sized reads
> > > > then it should also be able to generate 32 bit sized writes).
> > > > With this assumption we are doing a bitwise and of both tx and rx capabilities.
> > > >
> > > > Please let me know if you think otherwise.
>
> --
> With Best Regards,
> Andy Shevchenko
>
>