Add bindings, driver and DT node for video clock controller on SM8450.
Taniya Das (3):
dt-bindings: clock: qcom: Add SM8450 video clock controller
clk: qcom: videocc-sm8450: Add video clock controller driver for
SM8450
arm64: dts: qcom: sm8450: Add video clock controller
.../bindings/clock/qcom,sm8450-videocc.yaml | 77 +++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm8450.c | 461 ++++++++++++++++++
.../dt-bindings/clock/qcom,sm8450-videocc.h | 38 ++
6 files changed, 598 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
create mode 100644 drivers/clk/qcom/videocc-sm8450.c
create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h
--
2.17.1
Add device node for video clock controller on Qualcomm SM8450 platform.
Signed-off-by: Taniya Das <[email protected]>
---
Changes since V3:
- None.
Changes since V2:
- No changes.
Changes since V1:
- No changes.
arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 595533aeafc4..00ff8efa53c7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -756,6 +756,18 @@
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
};
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8450-videocc";
+ reg = <0 0x0aaf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_VIDEO_AHB_CLK>;
+ power-domains = <&rpmhpd SM8450_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
gpi_dma2: dma-controller@800000 {
compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
#dma-cells = <3>;
--
2.17.1
Add device tree bindings for the video clock controller on Qualcomm
SM8450 platform.
Signed-off-by: Taniya Das <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes since V3:
- None.
Changes since V2:
- As per Stephen's comments drop clock-names to match how newer
qcom clk bindings are being done.
- Change the header file name as qcom,sm8450-videocc.h to match
latest upstream header files.
Changes since V1:
- Change the properties order to keep reg after the compatible
property.
.../bindings/clock/qcom,sm8450-videocc.yaml | 77 +++++++++++++++++++
.../dt-bindings/clock/qcom,sm8450-videocc.h | 38 +++++++++
2 files changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
new file mode 100644
index 000000000000..58e59065bb2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Video Clock & Reset Controller on SM8450
+
+maintainers:
+ - Taniya Das <[email protected]>
+
+description: |
+ Qualcomm video clock control module provides the clocks, resets and power
+ domains on SM8450.
+
+ See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
+
+properties:
+ compatible:
+ const: qcom,sm8450-videocc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Video AHB clock from GCC
+ - description: Board XO source
+
+ power-domains:
+ maxItems: 1
+ description:
+ MMCX power domain.
+
+ required-opps:
+ maxItems: 1
+ description:
+ A phandle to an OPP node describing required MMCX performance point.
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - required-opps
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sm8450-videocc";
+ reg = <0x0aaf0000 0x10000>;
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ power-domains = <&rpmhpd SM8450_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h
new file mode 100644
index 000000000000..9d795adfe4eb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_MVS0_CLK 0
+#define VIDEO_CC_MVS0_CLK_SRC 1
+#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
+#define VIDEO_CC_MVS0C_CLK 3
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
+#define VIDEO_CC_MVS1_CLK 5
+#define VIDEO_CC_MVS1_CLK_SRC 6
+#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
+#define VIDEO_CC_MVS1C_CLK 8
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
+#define VIDEO_CC_PLL0 10
+#define VIDEO_CC_PLL1 11
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0C_GDSC 0
+#define VIDEO_CC_MVS0_GDSC 1
+#define VIDEO_CC_MVS1C_GDSC 2
+#define VIDEO_CC_MVS1_GDSC 3
+
+/* VIDEO_CC resets */
+#define CVP_VIDEO_CC_INTERFACE_BCR 0
+#define CVP_VIDEO_CC_MVS0_BCR 1
+#define CVP_VIDEO_CC_MVS0C_BCR 2
+#define CVP_VIDEO_CC_MVS1_BCR 3
+#define CVP_VIDEO_CC_MVS1C_BCR 4
+#define VIDEO_CC_MVS0C_CLK_ARES 5
+#define VIDEO_CC_MVS1C_CLK_ARES 6
+
+#endif
--
2.17.1
On 9.05.2023 19:21, Taniya Das wrote:
> Add device node for video clock controller on Qualcomm SM8450 platform.
>
> Signed-off-by: Taniya Das <[email protected]>
> ---
> Changes since V3:
> - None.
>
> Changes since V2:
> - No changes.
>
> Changes since V1:
> - No changes.
>
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 595533aeafc4..00ff8efa53c7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -756,6 +756,18 @@
> "usb3_phy_wrapper_gcc_usb30_pipe_clk";
> };
>
> + videocc: clock-controller@aaf0000 {
Nodes should be sorted by unit address.
This one belongs before cci@ac15000.
> + compatible = "qcom,sm8450-videocc";
> + reg = <0 0x0aaf0000 0 0x10000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_VIDEO_AHB_CLK>;
Older SoCs used to provide a vote on XO_A for videocc ahb_clk_src,
I'd assume that's now taken care of internally?
Konrad
> + power-domains = <&rpmhpd SM8450_MMCX>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> gpi_dma2: dma-controller@800000 {
> compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
> #dma-cells = <3>;
On 09/05/2023 19:21, Taniya Das wrote:
> Add device tree bindings for the video clock controller on Qualcomm
> SM8450 platform.
>
> Signed-off-by: Taniya Das <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> Changes since V3:
> - None.
>
> Changes since V2:
> - As per Stephen's comments drop clock-names to match how newer
> qcom clk bindings are being done.
> - Change the header file name as qcom,sm8450-videocc.h to match
> latest upstream header files.
>
> Changes since V1:
> - Change the properties order to keep reg after the compatible
> property.
>
> .../bindings/clock/qcom,sm8450-videocc.yaml | 77 +++++++++++++++++++
> .../dt-bindings/clock/qcom,sm8450-videocc.h | 38 +++++++++
> 2 files changed, 115 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> new file mode 100644
> index 000000000000..58e59065bb2a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Video Clock & Reset Controller on SM8450
> +
> +maintainers:
> + - Taniya Das <[email protected]>
> +
> +description: |
> + Qualcomm video clock control module provides the clocks, resets and power
> + domains on SM8450.
> +
> + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
> +
> +properties:
> + compatible:
> + const: qcom,sm8450-videocc
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Video AHB clock from GCC
> + - description: Board XO source
Why the order is different than all other devices? Board XO is always first.
Best regards,
Krzysztof
Thanks for the review.
On 5/10/2023 12:42 PM, Krzysztof Kozlowski wrote:
> On 09/05/2023 19:21, Taniya Das wrote:
>> Add device tree bindings for the video clock controller on Qualcomm
>> SM8450 platform.
>>
>> Signed-off-by: Taniya Das <[email protected]>
>> Reviewed-by: Rob Herring <[email protected]>
>> ---
>> Changes since V3:
>> - None.
>>
>> Changes since V2:
>> - As per Stephen's comments drop clock-names to match how newer
>> qcom clk bindings are being done.
>> - Change the header file name as qcom,sm8450-videocc.h to match
>> latest upstream header files.
>>
>> Changes since V1:
>> - Change the properties order to keep reg after the compatible
>> property.
>>
>> .../bindings/clock/qcom,sm8450-videocc.yaml | 77 +++++++++++++++++++
>> .../dt-bindings/clock/qcom,sm8450-videocc.h | 38 +++++++++
>> 2 files changed, 115 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> new file mode 100644
>> index 000000000000..58e59065bb2a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
>> @@ -0,0 +1,77 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Video Clock & Reset Controller on SM8450
>> +
>> +maintainers:
>> + - Taniya Das <[email protected]>
>> +
>> +description: |
>> + Qualcomm video clock control module provides the clocks, resets and power
>> + domains on SM8450.
>> +
>> + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sm8450-videocc
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: Video AHB clock from GCC
>> + - description: Board XO source
>
> Why the order is different than all other devices? Board XO is always first.
>
>
Yes, will be fixed in the next patch set.
> Best regards,
> Krzysztof
>
--
Thanks & Regards,
Taniya Das.
Thanks for the review.
On 5/10/2023 1:47 AM, Konrad Dybcio wrote:
>
>
> On 9.05.2023 19:21, Taniya Das wrote:
>> Add device node for video clock controller on Qualcomm SM8450 platform.
>>
>> Signed-off-by: Taniya Das <[email protected]>
>> ---
>> Changes since V3:
>> - None.
>>
>> Changes since V2:
>> - No changes.
>>
>> Changes since V1:
>> - No changes.
>>
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 595533aeafc4..00ff8efa53c7 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -756,6 +756,18 @@
>> "usb3_phy_wrapper_gcc_usb30_pipe_clk";
>> };
>>
>> + videocc: clock-controller@aaf0000 {
> Nodes should be sorted by unit address.
> This one belongs before cci@ac15000.
Yes, my bad, will update in the next patchset.
>
>> + compatible = "qcom,sm8450-videocc";
>> + reg = <0 0x0aaf0000 0 0x10000>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_VIDEO_AHB_CLK>;
> Older SoCs used to provide a vote on XO_A for videocc ahb_clk_src,
> I'd assume that's now taken care of internally?
>
Yes, it is taken care internally.
> Konrad
>> + power-domains = <&rpmhpd SM8450_MMCX>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + };
>> +
>> gpi_dma2: dma-controller@800000 {
>> compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
>> #dma-cells = <3>;
--
Thanks & Regards,
Taniya Das.