The series of patches fixes various issues related to mcs
and NIX link registers.
Geetha sowjanya (4):
octeontx2-af: Fix mcs sa cam entries size
octeontx2-af: Fix mcs stats register address
octeontx2-af: Add missing mcs flr handler call
octeontx2-af: Update Tx link register range
Nithin Dabilpuram (1):
octeontx2-af: Adjust Tx credits when MCS external bypass is disabled
.../net/ethernet/marvell/octeontx2/af/mbox.h | 2 +-
.../net/ethernet/marvell/octeontx2/af/mcs.c | 16 ++++++++--
.../net/ethernet/marvell/octeontx2/af/mcs.h | 2 ++
.../ethernet/marvell/octeontx2/af/mcs_reg.h | 31 ++++++++++++++++---
.../net/ethernet/marvell/octeontx2/af/rvu.c | 3 ++
.../net/ethernet/marvell/octeontx2/af/rvu.h | 1 +
.../ethernet/marvell/octeontx2/af/rvu_nix.c | 8 +++++
.../ethernet/marvell/octeontx2/af/rvu_reg.c | 4 +--
8 files changed, 58 insertions(+), 9 deletions(-)
--
2.25.1
From: Nithin Dabilpuram <[email protected]>
When MCS external bypass is disabled, MCS returns additional
2 credits(32B) for every packet Tx'ed on LMAC. To account for
these extra credits, NIX_AF_TX_LINKX_NORM_CREDIT.CC_MCS_CNT
needs to be configured as otherwise NIX Tx credits would overflow
and will never be returned to idle state credit count
causing issues with credit control and MTU change.
This patch fixes the same by configuring CC_MCS_CNT at probe
time for MCS enabled SoC's
Fixes: bd69476e86fc ("octeontx2-af: cn10k: mcs: Install a default TCAM for normal traffic")
Signed-off-by: Nithin Dabilpuram <[email protected]>
Signed-off-by: Geetha sowjanya <[email protected]>
Signed-off-by: Sunil Goutham <[email protected]>
---
drivers/net/ethernet/marvell/octeontx2/af/mcs.c | 12 ++++++++++++
drivers/net/ethernet/marvell/octeontx2/af/mcs.h | 2 ++
drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 1 +
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 8 ++++++++
4 files changed, 23 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
index c43f19dfbd74..d6effbe46208 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
@@ -1219,6 +1219,17 @@ struct mcs *mcs_get_pdata(int mcs_id)
return NULL;
}
+bool is_mcs_bypass(int mcs_id)
+{
+ struct mcs *mcs_dev;
+
+ list_for_each_entry(mcs_dev, &mcs_list, mcs_list) {
+ if (mcs_dev->mcs_id == mcs_id)
+ return mcs_dev->bypass;
+ }
+ return true;
+}
+
void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req)
{
u64 val = 0;
@@ -1447,6 +1458,7 @@ static void mcs_set_external_bypass(struct mcs *mcs, u8 bypass)
else
val &= ~BIT_ULL(6);
mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
+ mcs->bypass = bypass;
}
static void mcs_global_cfg(struct mcs *mcs)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.h b/drivers/net/ethernet/marvell/octeontx2/af/mcs.h
index 0f89dcb76465..ccd43c3f3460 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.h
@@ -149,6 +149,7 @@ struct mcs {
u16 num_vec;
void *rvu;
u16 *tx_sa_active;
+ u8 bypass;
};
struct mcs_ops {
@@ -206,6 +207,7 @@ void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *
int mcs_alloc_ctrlpktrule(struct rsrc_bmap *rsrc, u16 *pf_map, u16 offset, u16 pcifunc);
int mcs_free_ctrlpktrule(struct mcs *mcs, struct mcs_free_ctrl_pkt_rule_req *req);
int mcs_ctrlpktrule_write(struct mcs *mcs, struct mcs_ctrl_pkt_rule_write_req *req);
+bool is_mcs_bypass(int mcs_id);
/* CN10K-B APIs */
void cn10kb_mcs_set_hw_capabilities(struct mcs *mcs);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index c4d999ef5ab4..9887edccadf7 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -345,6 +345,7 @@ struct nix_hw {
struct nix_txvlan txvlan;
struct nix_ipolicer *ipolicer;
u64 *tx_credits;
+ u64 cc_mcs_cnt;
};
/* RVU block's capabilities or functionality,
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 23c2f2ed2fb8..3d286631a011 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -12,6 +12,7 @@
#include "rvu_reg.h"
#include "rvu.h"
#include "npc.h"
+#include "mcs.h"
#include "cgx.h"
#include "lmac_common.h"
#include "rvu_npc_hash.h"
@@ -4389,6 +4390,12 @@ static void nix_link_config(struct rvu *rvu, int blkaddr,
SDP_HW_MAX_FRS << 16 | NIC_HW_MIN_FRS);
}
+ /* Get MCS external bypass status for CN10K-B */
+ if (mcs_get_blkcnt() == 1) {
+ /* Adjust for 2 credits when external bypass is disabled */
+ nix_hw->cc_mcs_cnt = is_mcs_bypass(0) ? 0 : 2;
+ }
+
/* Set credits for Tx links assuming max packet length allowed.
* This will be reconfigured based on MTU set for PF/VF.
*/
@@ -4412,6 +4419,7 @@ static void nix_link_config(struct rvu *rvu, int blkaddr,
tx_credits = (lmac_fifo_len - lmac_max_frs) / 16;
/* Enable credits and set credit pkt count to max allowed */
cfg = (tx_credits << 12) | (0x1FF << 2) | BIT_ULL(1);
+ cfg |= (nix_hw->cc_mcs_cnt << 32);
link = iter + slink;
nix_hw->tx_credits[link] = tx_credits;
--
2.25.1
If mcs resources are attached to PF/VF. These resources need
to be freed on FLR. This patch add mssing mcs flr call on PF FLR.
Fixes: bd69476e86fc ("octeontx2-af: cn10k: mcs: Install a default TCAM for normal traffic")
Signed-off-by: Geetha sowjanya <[email protected]>
---
drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index 22c395c7d040..731bb82b577c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -2631,6 +2631,9 @@ static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
rvu_npc_free_mcam_entries(rvu, pcifunc, -1);
rvu_mac_reset(rvu, pcifunc);
+ if (rvu->mcs_blk_cnt)
+ rvu_mcs_flr_handler(rvu, pcifunc);
+
mutex_unlock(&rvu->flr_lock);
}
--
2.25.1
This patch adds the miss mcs stats register
for mcs supported platforms.
Fixes: 9312150af8da ("octeontx2-af: cn10k: mcs: Support for stats collection")
Signed-off-by: Geetha sowjanya <[email protected]>
---
.../net/ethernet/marvell/octeontx2/af/mcs.c | 4 +--
.../ethernet/marvell/octeontx2/af/mcs_reg.h | 31 ++++++++++++++++---
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
index d6effbe46208..d4a4e4c837ec 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
@@ -117,7 +117,7 @@ void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id
reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYTAGGEDCTLX(id);
stats->pkt_tagged_ctl_cnt = mcs_reg_read(mcs, reg);
- reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(id);
+ reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(id);
stats->pkt_untaged_cnt = mcs_reg_read(mcs, reg);
reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(id);
@@ -215,7 +215,7 @@ void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_stats *stats,
reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCNOTVALIDX(id);
stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg);
- reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(id);
+ reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(id);
stats->pkt_unchecked_cnt = mcs_reg_read(mcs, reg);
if (mcs->hw->mcs_blks > 1) {
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h
index f3ab01fc363c..f4c6de89002c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h
@@ -810,14 +810,37 @@
offset = 0x9d8ull; \
offset; })
+#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(a) ({ \
+ u64 offset; \
+ \
+ offset = 0xee80ull; \
+ if (mcs->hw->mcs_blks > 1) \
+ offset = 0xe818ull; \
+ offset += (a) * 0x8ull; \
+ offset; })
+
+#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) ({ \
+ u64 offset; \
+ \
+ offset = 0xa680ull; \
+ if (mcs->hw->mcs_blks > 1) \
+ offset = 0xd018ull; \
+ offset += (a) * 0x8ull; \
+ offset; })
+
+#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) ({ \
+ u64 offset; \
+ \
+ offset = 0xf680ull; \
+ if (mcs->hw->mcs_blks > 1) \
+ offset = 0xe018ull; \
+ offset += (a) * 0x8ull; \
+ offset; })
+
#define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCDECRYPTEDX(a) (0xe680ull + (a) * 0x8ull)
#define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCVALIDATEX(a) (0xde80ull + (a) * 0x8ull)
-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(a) (0xa680ull + (a) * 0x8ull)
#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOTAGX(a) (0xd218 + (a) * 0x8ull)
-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) (0xd018ull + (a) * 0x8ull)
-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(a) (0xee80ull + (a) * 0x8ull)
#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(a) (0xb680ull + (a) * 0x8ull)
-#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) (0xf680ull + (a) * 0x8ull)
#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAINVALIDX(a) (0x12680ull + (a) * 0x8ull)
#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTUSINGSAERRORX(a) (0x15680ull + (a) * 0x8ull)
#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTVALIDX(a) (0x13680ull + (a) * 0x8ull)
--
2.25.1
On latest silicon versions SA cam entries increased to 256.
This patch fixes the datatype of sa_entries in mcs_hw_info
struct to u16 to hold 256 entries.
Fixes: 080bbd19c9dd ("octeontx2-af: cn10k: mcs: Add mailboxes for port related operations")
Signed-off-by: Geetha sowjanya <[email protected]>
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 6845556581c3..5df42634ceb8 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -1945,7 +1945,7 @@ struct mcs_hw_info {
u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
u8 secy_entries; /* RX/TX SECY entries per mcs block */
u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
- u8 sa_entries; /* PN table entries = SA entries */
+ u16 sa_entries; /* PN table entries = SA entries */
u64 rsvd[16];
};
--
2.25.1
On new silicons the TX channels for transmit level has increased.
This patch fixes the respective register offset range to
configure the newly added channels.
Fixes: b279bbb3314e ("octeontx2-af: NIX Tx scheduler queue config support")
Signed-off-by: Rahul Bhansali <[email protected]>
Signed-off-by: Geetha sowjanya <[email protected]>
---
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
index b3150f053291..d46ac29adb96 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
@@ -31,8 +31,8 @@ static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
{NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
{0x1200, 0x12E0} } },
{NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
- {0x1610, 0x1618}, {0x1700, 0x17B0} } },
- {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } },
+ {0x1610, 0x1618}, {0x1700, 0x17C8} } },
+ {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
{NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
};
--
2.25.1
On 23.11.2023 06:59, Geetha sowjanya wrote:
> From: Nithin Dabilpuram <[email protected]>
>
> When MCS external bypass is disabled, MCS returns additional
> 2 credits(32B) for every packet Tx'ed on LMAC. To account for
> these extra credits, NIX_AF_TX_LINKX_NORM_CREDIT.CC_MCS_CNT
> needs to be configured as otherwise NIX Tx credits would overflow
> and will never be returned to idle state credit count
> causing issues with credit control and MTU change.
>
> This patch fixes the same by configuring CC_MCS_CNT at probe
> time for MCS enabled SoC's
>
> Fixes: bd69476e86fc ("octeontx2-af: cn10k: mcs: Install a default TCAM for normal traffic")
> Signed-off-by: Nithin Dabilpuram <[email protected]>
> Signed-off-by: Geetha sowjanya <[email protected]>
> Signed-off-by: Sunil Goutham <[email protected]>
> ---
> drivers/net/ethernet/marvell/octeontx2/af/mcs.c | 12 ++++++++++++
> drivers/net/ethernet/marvell/octeontx2/af/mcs.h | 2 ++
> drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 1 +
> drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 8 ++++++++
> 4 files changed, 23 insertions(+)
>
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> index c43f19dfbd74..d6effbe46208 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> @@ -1219,6 +1219,17 @@ struct mcs *mcs_get_pdata(int mcs_id)
> return NULL;
> }
>
> +bool is_mcs_bypass(int mcs_id)
> +{
> + struct mcs *mcs_dev;
> +
> + list_for_each_entry(mcs_dev, &mcs_list, mcs_list) {
> + if (mcs_dev->mcs_id == mcs_id)
> + return mcs_dev->bypass;
> + }
> + return true;
If there is no mcs dev with the given id it means it is bypassed?
> +}
> +
> void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req)
> {
> u64 val = 0;
> @@ -1447,6 +1458,7 @@ static void mcs_set_external_bypass(struct mcs *mcs, u8 bypass)
> else
> val &= ~BIT_ULL(6);
> mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
> + mcs->bypass = bypass;
> }
>
> static void mcs_global_cfg(struct mcs *mcs)
<...>
On 23.11.2023 06:59, Geetha sowjanya wrote:
> On latest silicon versions SA cam entries increased to 256.
> This patch fixes the datatype of sa_entries in mcs_hw_info
> struct to u16 to hold 256 entries.
>
> Fixes: 080bbd19c9dd ("octeontx2-af: cn10k: mcs: Add mailboxes for port related operations")
> Signed-off-by: Geetha sowjanya <[email protected]>
> ---
Reviewed-by: Wojciech Drewek <[email protected]>
> drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
> index 6845556581c3..5df42634ceb8 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
> @@ -1945,7 +1945,7 @@ struct mcs_hw_info {
> u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
> u8 secy_entries; /* RX/TX SECY entries per mcs block */
> u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
> - u8 sa_entries; /* PN table entries = SA entries */
> + u16 sa_entries; /* PN table entries = SA entries */
> u64 rsvd[16];
> };
>
On 23.11.2023 06:59, Geetha sowjanya wrote:
> This patch adds the miss mcs stats register
> for mcs supported platforms.
>
> Fixes: 9312150af8da ("octeontx2-af: cn10k: mcs: Support for stats collection")
> Signed-off-by: Geetha sowjanya <[email protected]>
> ---
Reviewed-by: Wojciech Drewek <[email protected]>
> .../net/ethernet/marvell/octeontx2/af/mcs.c | 4 +--
> .../ethernet/marvell/octeontx2/af/mcs_reg.h | 31 ++++++++++++++++---
> 2 files changed, 29 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> index d6effbe46208..d4a4e4c837ec 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> @@ -117,7 +117,7 @@ void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id
> reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYTAGGEDCTLX(id);
> stats->pkt_tagged_ctl_cnt = mcs_reg_read(mcs, reg);
>
> - reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(id);
> + reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(id);
> stats->pkt_untaged_cnt = mcs_reg_read(mcs, reg);
>
> reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(id);
> @@ -215,7 +215,7 @@ void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_stats *stats,
> reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCNOTVALIDX(id);
> stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg);
>
> - reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(id);
> + reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(id);
> stats->pkt_unchecked_cnt = mcs_reg_read(mcs, reg);
>
> if (mcs->hw->mcs_blks > 1) {
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h
> index f3ab01fc363c..f4c6de89002c 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs_reg.h
> @@ -810,14 +810,37 @@
> offset = 0x9d8ull; \
> offset; })
>
> +#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(a) ({ \
> + u64 offset; \
> + \
> + offset = 0xee80ull; \
> + if (mcs->hw->mcs_blks > 1) \
> + offset = 0xe818ull; \
> + offset += (a) * 0x8ull; \
> + offset; })
> +
> +#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) ({ \
> + u64 offset; \
> + \
> + offset = 0xa680ull; \
> + if (mcs->hw->mcs_blks > 1) \
> + offset = 0xd018ull; \
> + offset += (a) * 0x8ull; \
> + offset; })
> +
> +#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) ({ \
> + u64 offset; \
> + \
> + offset = 0xf680ull; \
> + if (mcs->hw->mcs_blks > 1) \
> + offset = 0xe018ull; \
> + offset += (a) * 0x8ull; \
> + offset; })
> +
> #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCDECRYPTEDX(a) (0xe680ull + (a) * 0x8ull)
> #define MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCVALIDATEX(a) (0xde80ull + (a) * 0x8ull)
> -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDORNOTAGX(a) (0xa680ull + (a) * 0x8ull)
> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOTAGX(a) (0xd218 + (a) * 0x8ull)
> -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(a) (0xd018ull + (a) * 0x8ull)
> -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDOROKX(a) (0xee80ull + (a) * 0x8ull)
> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(a) (0xb680ull + (a) * 0x8ull)
> -#define MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(a) (0xf680ull + (a) * 0x8ull)
> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSAINVALIDX(a) (0x12680ull + (a) * 0x8ull)
> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTUSINGSAERRORX(a) (0x15680ull + (a) * 0x8ull)
> #define MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTVALIDX(a) (0x13680ull + (a) * 0x8ull)
On 23.11.2023 06:59, Geetha sowjanya wrote:
> On new silicons the TX channels for transmit level has increased.
Will it still work with older silicon?
> This patch fixes the respective register offset range to
> configure the newly added channels.
>
> Fixes: b279bbb3314e ("octeontx2-af: NIX Tx scheduler queue config support")
> Signed-off-by: Rahul Bhansali <[email protected]>
What Rahul's signed-off stands for?
> Signed-off-by: Geetha sowjanya <[email protected]>
> ---
> drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
> index b3150f053291..d46ac29adb96 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
> @@ -31,8 +31,8 @@ static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
> {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
> {0x1200, 0x12E0} } },
> {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
> - {0x1610, 0x1618}, {0x1700, 0x17B0} } },
> - {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } },
> + {0x1610, 0x1618}, {0x1700, 0x17C8} } },
> + {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8} } },
> {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
> };
>
On 23.11.2023 06:59, Geetha sowjanya wrote:
> If mcs resources are attached to PF/VF. These resources need
> to be freed on FLR. This patch add mssing mcs flr call on PF FLR.
>
> Fixes: bd69476e86fc ("octeontx2-af: cn10k: mcs: Install a default TCAM for normal traffic")
> Signed-off-by: Geetha sowjanya <[email protected]>
> ---
Reviewed-by: Wojciech Drewek <[email protected]>
> drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
> index 22c395c7d040..731bb82b577c 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
> @@ -2631,6 +2631,9 @@ static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
> rvu_npc_free_mcam_entries(rvu, pcifunc, -1);
> rvu_mac_reset(rvu, pcifunc);
>
> + if (rvu->mcs_blk_cnt)
> + rvu_mcs_flr_handler(rvu, pcifunc);
> +
> mutex_unlock(&rvu->flr_lock);
> }
>
> -----Original Message-----
> From: Wojciech Drewek <[email protected]>
> Sent: Thursday, November 23, 2023 4:15 PM
> To: Geethasowjanya Akula <[email protected]>; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; Sunil Kovvuri Goutham <[email protected]>;
> Subbaraya Sundeep Bhatta <[email protected]>; Hariprasad Kelam
> <[email protected]>
> Subject: [EXT] Re: [net PATCH 1/5] octeontx2-af: Adjust Tx credits when MCS
> external bypass is disabled
>
> External Email
>
> ----------------------------------------------------------------------
>
>
> On 23.11.2023 06:59, Geetha sowjanya wrote:
> > From: Nithin Dabilpuram <[email protected]>
> >
> > When MCS external bypass is disabled, MCS returns additional
> > 2 credits(32B) for every packet Tx'ed on LMAC. To account for these
> > extra credits, NIX_AF_TX_LINKX_NORM_CREDIT.CC_MCS_CNT
> > needs to be configured as otherwise NIX Tx credits would overflow and
> > will never be returned to idle state credit count causing issues with
> > credit control and MTU change.
> >
> > This patch fixes the same by configuring CC_MCS_CNT at probe time for
> > MCS enabled SoC's
> >
> > Fixes: bd69476e86fc ("octeontx2-af: cn10k: mcs: Install a default TCAM
> > for normal traffic")
> > Signed-off-by: Nithin Dabilpuram <[email protected]>
> > Signed-off-by: Geetha sowjanya <[email protected]>
> > Signed-off-by: Sunil Goutham <[email protected]>
> > ---
> > drivers/net/ethernet/marvell/octeontx2/af/mcs.c | 12 ++++++++++++
> > drivers/net/ethernet/marvell/octeontx2/af/mcs.h | 2 ++
> > drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 1 +
> > drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 8 ++++++++
> > 4 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> > b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> > index c43f19dfbd74..d6effbe46208 100644
> > --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> > +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
> > @@ -1219,6 +1219,17 @@ struct mcs *mcs_get_pdata(int mcs_id)
> > return NULL;
> > }
> >
> > +bool is_mcs_bypass(int mcs_id)
> > +{
> > + struct mcs *mcs_dev;
> > +
> > + list_for_each_entry(mcs_dev, &mcs_list, mcs_list) {
> > + if (mcs_dev->mcs_id == mcs_id)
> > + return mcs_dev->bypass;
> > + }
> > + return true;
>
> If there is no mcs dev with the given id it means it is bypassed?
Yes.
>
> > +}
> > +
> > void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req
> > *req) {
> > u64 val = 0;
> > @@ -1447,6 +1458,7 @@ static void mcs_set_external_bypass(struct mcs
> *mcs, u8 bypass)
> > else
> > val &= ~BIT_ULL(6);
> > mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
> > + mcs->bypass = bypass;
> > }
> >
> > static void mcs_global_cfg(struct mcs *mcs)
>
>
> <...>
> -----Original Message-----
> From: Wojciech Drewek <[email protected]>
> Sent: Thursday, November 23, 2023 4:28 PM
> To: Geethasowjanya Akula <[email protected]>; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; Sunil Kovvuri Goutham <[email protected]>;
> Subbaraya Sundeep Bhatta <[email protected]>; Hariprasad Kelam
> <[email protected]>
> Subject: [EXT] Re: [net PATCH 5/5] octeontx2-af: Update Tx link register range
>
> External Email
>
> ----------------------------------------------------------------------
>
>
> On 23.11.2023 06:59, Geetha sowjanya wrote:
> > On new silicons the TX channels for transmit level has increased.
>
> Will it still work with older silicon?
Yes. This registers accessed based on number of channels supported by silicon.
>
> > This patch fixes the respective register offset range to configure the
> > newly added channels.
> >
> > Fixes: b279bbb3314e ("octeontx2-af: NIX Tx scheduler queue config
> > support")
> > Signed-off-by: Rahul Bhansali <[email protected]>
>
> What Rahul's signed-off stands for?
He is the actual author. Will fix the author name in next version.
>
> > Signed-off-by: Geetha sowjanya <[email protected]>
> > ---
> > drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
> > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
> > index b3150f053291..d46ac29adb96 100644
> > --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
> > +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
> > @@ -31,8 +31,8 @@ static struct hw_reg_map
> txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
> > {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10,
> 0x0B18},
> > {0x1200, 0x12E0} } },
> > {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
> > - {0x1610, 0x1618}, {0x1700, 0x17B0} } },
> > - {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0}
> } },
> > + {0x1610, 0x1618}, {0x1700, 0x17C8} } },
> > + {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17C8}
> }
> > +},
> > {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } }, };
> >
On 23.11.2023 13:34, Geethasowjanya Akula wrote:
>
>
>> -----Original Message-----
>> From: Wojciech Drewek <[email protected]>
>> Sent: Thursday, November 23, 2023 4:15 PM
>> To: Geethasowjanya Akula <[email protected]>; [email protected];
>> [email protected]
>> Cc: [email protected]; [email protected]; [email protected];
>> [email protected]; Sunil Kovvuri Goutham <[email protected]>;
>> Subbaraya Sundeep Bhatta <[email protected]>; Hariprasad Kelam
>> <[email protected]>
>> Subject: [EXT] Re: [net PATCH 1/5] octeontx2-af: Adjust Tx credits when MCS
>> external bypass is disabled
>>
>> External Email
>>
>> ----------------------------------------------------------------------
>>
>>
>> On 23.11.2023 06:59, Geetha sowjanya wrote:
>>> From: Nithin Dabilpuram <[email protected]>
>>>
>>> When MCS external bypass is disabled, MCS returns additional
>>> 2 credits(32B) for every packet Tx'ed on LMAC. To account for these
>>> extra credits, NIX_AF_TX_LINKX_NORM_CREDIT.CC_MCS_CNT
>>> needs to be configured as otherwise NIX Tx credits would overflow and
>>> will never be returned to idle state credit count causing issues with
>>> credit control and MTU change.
>>>
>>> This patch fixes the same by configuring CC_MCS_CNT at probe time for
>>> MCS enabled SoC's
>>>
>>> Fixes: bd69476e86fc ("octeontx2-af: cn10k: mcs: Install a default TCAM
>>> for normal traffic")
>>> Signed-off-by: Nithin Dabilpuram <[email protected]>
>>> Signed-off-by: Geetha sowjanya <[email protected]>
>>> Signed-off-by: Sunil Goutham <[email protected]>
>>> ---
>>> drivers/net/ethernet/marvell/octeontx2/af/mcs.c | 12 ++++++++++++
>>> drivers/net/ethernet/marvell/octeontx2/af/mcs.h | 2 ++
>>> drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 1 +
>>> drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 8 ++++++++
>>> 4 files changed, 23 insertions(+)
>>>
>>> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
>>> b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
>>> index c43f19dfbd74..d6effbe46208 100644
>>> --- a/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
>>> +++ b/drivers/net/ethernet/marvell/octeontx2/af/mcs.c
>>> @@ -1219,6 +1219,17 @@ struct mcs *mcs_get_pdata(int mcs_id)
>>> return NULL;
>>> }
>>>
>>> +bool is_mcs_bypass(int mcs_id)
>>> +{
>>> + struct mcs *mcs_dev;
>>> +
>>> + list_for_each_entry(mcs_dev, &mcs_list, mcs_list) {
>>> + if (mcs_dev->mcs_id == mcs_id)
>>> + return mcs_dev->bypass;
>>> + }
>>> + return true;
>>
>> If there is no mcs dev with the given id it means it is bypassed?
> Yes.
Makes sense
Reviewed-by: Wojciech Drewek <[email protected]>
>>
>>> +}
>>> +
>>> void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req
>>> *req) {
>>> u64 val = 0;
>>> @@ -1447,6 +1458,7 @@ static void mcs_set_external_bypass(struct mcs
>> *mcs, u8 bypass)
>>> else
>>> val &= ~BIT_ULL(6);
>>> mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val);
>>> + mcs->bypass = bypass;
>>> }
>>>
>>> static void mcs_global_cfg(struct mcs *mcs)
>>
>>
>> <...>