2023-11-23 08:47:20

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 00/10] Enable HS-G5 support on SM8550

This series enables HS-G5 support on SM8550.

This series is rebased on below changes from Mani -
https://patchwork.kernel.org/project/linux-scsi/patch/[email protected]/
https://patchwork.kernel.org/project/linux-scsi/patch/[email protected]/

This series is tested on below HW combinations -
SM8550 MTP + UFS4.0
SM8550 QRD + UFS3.1
SM8450 MTP + UFS3.1 (for regression test)
SM8350 MTP + UFS3.1 (for regression test)

Note that during reboot test on above platforms, I occasinally hit PA (PHY)
error during the 2nd init, this is not related with this series. A fix for
this is mentioned in below patchwork -

https://patchwork.kernel.org/project/linux-scsi/patch/[email protected]/

Also note that on platforms, which have two sets of UFS PHY settings are
provided (say G4 and no-G4, G5 and no-G5). The two sets of PHY settings are
basically programming different values to different registers, mixing the
two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers. For SM8550, this series will make sure we
honor the rule. However, for old targets Mani and I will fix them in
another series in future.

v4 -> v5:
Removed two useless debug prints in patch #9

v3 -> v4:
1. Used .tbls_hs_overlay array instead of adding more tables with different names like .tbls_hs_g5

v2 -> v3:
1. Addressed comments from Andrew, Mani and Bart in patch #1
2. Added patch #2 as per request from Andrew and Mani
3. Added patch #4 to fix a common issue on old targets, it is not necessary
for this series, but put in this series only because it would be easier
to maintain and no need to rebase
4. Addressed comments from Dmitry and Mani in patches to phy-qcom-qmp-ufs.c

v1 -> v2:
1. Removed 2 changes which were exposing power info in sysfs
2. Removed 1 change which was moving data structs to phy-qcom-qmp-ufs.h
3. Added one new change (the 1st one) to clean up usage of ufs_dev_params based on comments from Mani
4. Adjusted the logic of UFS device version detection according to comments from Mani:
4.1 For HW version < 0x5, go through dual init
4.2 For HW version >= 0x5
a. If UFS device version is populated, one init is required
b. If UFS device version is not populated, go through dual init

Bao D. Nguyen (1):
scsi: ufs: ufs-qcom: Add support for UFS device version detection

Can Guo (9):
scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params
scsi: ufs: ufs-qcom: No need to set hs_rate after
ufshcd_init_host_param()
scsi: ufs: ufs-qcom: Setup host power mode during init
scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear
scsi: ufs: ufs-qcom: Allow the first init start with the maximum
supported gear
scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5
scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5
and newer
phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for
SM8550

drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 ++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 196 ++++++++++++++++++---
drivers/ufs/host/ufs-exynos.c | 7 +-
drivers/ufs/host/ufs-hisi.c | 11 +-
drivers/ufs/host/ufs-mediatek.c | 12 +-
drivers/ufs/host/ufs-qcom.c | 92 +++++++---
drivers/ufs/host/ufs-qcom.h | 5 +-
drivers/ufs/host/ufshcd-pltfrm.c | 69 ++++----
drivers/ufs/host/ufshcd-pltfrm.h | 10 +-
11 files changed, 311 insertions(+), 107 deletions(-)

--
2.7.4


2023-11-23 08:47:46

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 03/10] scsi: ufs: ufs-qcom: Setup host power mode during init

Setup host power mode and its limitations during UFS host driver init to
avoid repetitive work during every power mode change.

Acked-by: Andrew Halaney <[email protected]>
Co-developed-by: Bao D. Nguyen <[email protected]>
Signed-off-by: Bao D. Nguyen <[email protected]>
Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 21 ++++++++++++++-------
drivers/ufs/host/ufs-qcom.h | 1 +
2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index cc30ad9..cc0eb37 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
- struct ufs_host_params host_params;
+ struct ufs_host_params *host_params = &host->host_params;
int ret = 0;

if (!dev_req_params) {
@@ -908,12 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,

switch (status) {
case PRE_CHANGE:
- ufshcd_init_host_param(&host_params);
-
- /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
- host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
-
- ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev, "%s: failed to determine capabilities\n",
__func__);
@@ -1048,6 +1043,17 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
}

+static void ufs_qcom_set_host_params(struct ufs_hba *hba)
+{
+ struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ struct ufs_host_params *host_params = &host->host_params;
+
+ ufshcd_init_host_param(host_params);
+
+ /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
+ host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
+}
+
static void ufs_qcom_set_caps(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -1272,6 +1278,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)

ufs_qcom_set_caps(hba);
ufs_qcom_advertise_quirks(hba);
+ ufs_qcom_set_host_params(hba);

err = ufs_qcom_ice_init(host);
if (err)
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 82cd143..11419eb 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -238,6 +238,7 @@ struct ufs_qcom_host {

struct gpio_desc *device_reset;

+ struct ufs_host_params host_params;
u32 phy_gear;

bool esi_enabled;
--
2.7.4

2023-11-23 08:47:48

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 06/10] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5

Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.

Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 9613ad9..6756f8d 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ struct ufs_host_params *host_params = &host->host_params;
struct phy *phy = host->generic_phy;
+ enum phy_mode mode;
int ret;

+ /*
+ * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
+ * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
+ * so that the subsequent power mode change shall stick to Rate-A.
+ */
+ if (host->hw_ver.major == 0x5) {
+ if (host->phy_gear == UFS_HS_G5)
+ host_params->hs_rate = PA_HS_MODE_A;
+ else
+ host_params->hs_rate = PA_HS_MODE_B;
+ }
+
+ mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
+
/* Reset UFS Host Controller and PHY */
ret = ufs_qcom_host_reset(hba);
if (ret)
@@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
return ret;
}

- phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
+ phy_set_mode_ext(phy, mode, host->phy_gear);

/* power on phy - start serdes and phy's power and clocks */
ret = phy_power_on(phy);
--
2.7.4

2023-11-23 08:47:50

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 04/10] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear

In the dual init scenario, the initial PHY gear is set to HS-G2, and the
first Power Mode Change (PMC) is meant to find the best matching PHY gear
for the 2nd init. However, for the first PMC, if the negotiated gear (say
HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to
the negotiated gear happen, because the programmed UFS PHY settings may not
support the negotiated gear. Fix it by overwriting the negotiated gear with
the PHY gear.

Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index cc0eb37..d4edf58 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
* because, the PHY gear settings are backwards compatible and we only need to
* change the PHY gear settings while scaling to higher gears.
*/
- if (dev_req_params->gear_tx > host->phy_gear)
+ if (dev_req_params->gear_tx > host->phy_gear) {
+ u32 old_phy_gear = host->phy_gear;
+
host->phy_gear = dev_req_params->gear_tx;
+ dev_req_params->gear_tx = old_phy_gear;
+ dev_req_params->gear_rx = old_phy_gear;
+ }

/* enable the device ref clock before changing to HS mode */
if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
--
2.7.4

2023-11-23 08:48:02

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 01/10] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params

Structure ufs_dev_params is actually used in UFS host vendor drivers to
declare host specific power mode parameters, like ufs_<vendor>_params or
host_cap, which makes the code not very straightforward to read. Rename the
structure ufs_dev_params to ufs_host_params and unify the declarations in
all vendor drivers to host_params.

In addition, rename the two functions ufshcd_init_pwr_dev_param() and
ufshcd_get_pwr_dev_param() which work based on the ufs_host_params to
ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
avoid confusions.

This change does not change any functionalities or logic.

Acked-by: Andrew Halaney <[email protected]>
Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-exynos.c | 7 ++--
drivers/ufs/host/ufs-hisi.c | 11 +++----
drivers/ufs/host/ufs-mediatek.c | 12 +++----
drivers/ufs/host/ufs-qcom.c | 12 +++----
drivers/ufs/host/ufshcd-pltfrm.c | 69 ++++++++++++++++++++--------------------
drivers/ufs/host/ufshcd-pltfrm.h | 10 +++---
6 files changed, 57 insertions(+), 64 deletions(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 71bd6db..674f2f4 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -765,7 +765,7 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
{
struct exynos_ufs *ufs = ufshcd_get_variant(hba);
struct phy *generic_phy = ufs->phy;
- struct ufs_dev_params ufs_exynos_cap;
+ struct ufs_host_params host_params;
int ret;

if (!dev_req_params) {
@@ -774,10 +774,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
goto out;
}

- ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
+ ufshcd_init_host_param(&host_params);

- ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
- dev_max_params, dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
pr_err("%s: failed to determine capabilities\n", __func__);
goto out;
diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
index 0229ac0..bb0c9a7 100644
--- a/drivers/ufs/host/ufs-hisi.c
+++ b/drivers/ufs/host/ufs-hisi.c
@@ -293,9 +293,9 @@ static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
return err;
}

-static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
+static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params)
{
- ufshcd_init_pwr_dev_param(hisi_param);
+ ufshcd_init_host_param(host_params);
}

static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
@@ -365,7 +365,7 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
{
- struct ufs_dev_params ufs_hisi_cap;
+ struct ufs_host_params host_params;
int ret = 0;

if (!dev_req_params) {
@@ -377,9 +377,8 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,

switch (status) {
case PRE_CHANGE:
- ufs_hisi_set_dev_cap(&ufs_hisi_cap);
- ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
- dev_max_params, dev_req_params);
+ ufs_hisi_set_dev_cap(&host_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev,
"%s: failed to determine capabilities\n", __func__);
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index fc61790..016067d 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -996,16 +996,14 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- struct ufs_dev_params host_cap;
+ struct ufs_host_params host_params;
int ret;

- ufshcd_init_pwr_dev_param(&host_cap);
- host_cap.hs_rx_gear = UFS_HS_G5;
- host_cap.hs_tx_gear = UFS_HS_G5;
+ ufshcd_init_host_param(&host_params);
+ host_params.hs_rx_gear = UFS_HS_G5;
+ host_params.hs_tx_gear = UFS_HS_G5;

- ret = ufshcd_get_pwr_dev_param(&host_cap,
- dev_max_params,
- dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
pr_info("%s: failed to determine capabilities\n",
__func__);
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 96cb8b5..aee66a3 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
- struct ufs_dev_params ufs_qcom_cap;
+ struct ufs_host_params host_params;
int ret = 0;

if (!dev_req_params) {
@@ -908,15 +908,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,

switch (status) {
case PRE_CHANGE:
- ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
- ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
+ ufshcd_init_host_param(&host_params);
+ host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;

/* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
- ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
+ host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);

- ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
- dev_max_params,
- dev_req_params);
+ ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
if (ret) {
dev_err(hba->dev, "%s: failed to determine capabilities\n",
__func__);
diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
index da2558e..9ec11b9 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.c
+++ b/drivers/ufs/host/ufshcd-pltfrm.c
@@ -285,61 +285,60 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
}

/**
- * ufshcd_get_pwr_dev_param - get finally agreed attributes for
- * power mode change
- * @pltfrm_param: pointer to platform parameters
+ * ufshcd_negotiate_pwr_param - find power mode settings that are supported by
+ both the controller and the device
+ * @host_param: pointer to host parameters
* @dev_max: pointer to device attributes
* @agreed_pwr: returned agreed attributes
*
* Return: 0 on success, non-zero value on failure.
*/
-int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
- const struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr)
+int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
+ const struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr)
{
- int min_pltfrm_gear;
+ int min_host_gear;
int min_dev_gear;
bool is_dev_sup_hs = false;
- bool is_pltfrm_max_hs = false;
+ bool is_host_max_hs = false;

if (dev_max->pwr_rx == FAST_MODE)
is_dev_sup_hs = true;

- if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
- is_pltfrm_max_hs = true;
- min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
- pltfrm_param->hs_tx_gear);
+ if (host_param->desired_working_mode == UFS_HS_MODE) {
+ is_host_max_hs = true;
+ min_host_gear = min_t(u32, host_param->hs_rx_gear,
+ host_param->hs_tx_gear);
} else {
- min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
- pltfrm_param->pwm_tx_gear);
+ min_host_gear = min_t(u32, host_param->pwm_rx_gear,
+ host_param->pwm_tx_gear);
}

/*
- * device doesn't support HS but
- * pltfrm_param->desired_working_mode is HS,
- * thus device and pltfrm_param don't agree
+ * device doesn't support HS but host_param->desired_working_mode is HS,
+ * thus device and host_param don't agree
*/
- if (!is_dev_sup_hs && is_pltfrm_max_hs) {
+ if (!is_dev_sup_hs && is_host_max_hs) {
pr_info("%s: device doesn't support HS\n",
__func__);
return -ENOTSUPP;
- } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
+ } else if (is_dev_sup_hs && is_host_max_hs) {
/*
* since device supports HS, it supports FAST_MODE.
- * since pltfrm_param->desired_working_mode is also HS
+ * since host_param->desired_working_mode is also HS
* then final decision (FAST/FASTAUTO) is done according
* to pltfrm_params as it is the restricting factor
*/
- agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
+ agreed_pwr->pwr_rx = host_param->rx_pwr_hs;
agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
} else {
/*
- * here pltfrm_param->desired_working_mode is PWM.
+ * here host_param->desired_working_mode is PWM.
* it doesn't matter whether device supports HS or PWM,
- * in both cases pltfrm_param->desired_working_mode will
+ * in both cases host_param->desired_working_mode will
* determine the mode
*/
- agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
+ agreed_pwr->pwr_rx = host_param->rx_pwr_pwm;
agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
}

@@ -349,9 +348,9 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
* the same decision will be made for rx
*/
agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
- pltfrm_param->tx_lanes);
+ host_param->tx_lanes);
agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
- pltfrm_param->rx_lanes);
+ host_param->rx_lanes);

/* device maximum gear is the minimum between device rx and tx gears */
min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
@@ -364,26 +363,26 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
* what is the gear, as it is the one that also decided previously what
* pwr the device will be configured to.
*/
- if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
- (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
+ if ((is_dev_sup_hs && is_host_max_hs) ||
+ (!is_dev_sup_hs && !is_host_max_hs)) {
agreed_pwr->gear_rx =
- min_t(u32, min_dev_gear, min_pltfrm_gear);
+ min_t(u32, min_dev_gear, min_host_gear);
} else if (!is_dev_sup_hs) {
agreed_pwr->gear_rx = min_dev_gear;
} else {
- agreed_pwr->gear_rx = min_pltfrm_gear;
+ agreed_pwr->gear_rx = min_host_gear;
}
agreed_pwr->gear_tx = agreed_pwr->gear_rx;

- agreed_pwr->hs_rate = pltfrm_param->hs_rate;
+ agreed_pwr->hs_rate = host_param->hs_rate;

return 0;
}
-EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
+EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_param);

-void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
+void ufshcd_init_host_param(struct ufs_host_params *host_param)
{
- *dev_param = (struct ufs_dev_params){
+ *host_param = (struct ufs_host_params){
.tx_lanes = UFS_LANE_2,
.rx_lanes = UFS_LANE_2,
.hs_rx_gear = UFS_HS_G3,
@@ -398,7 +397,7 @@ void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
.desired_working_mode = UFS_HS_MODE,
};
}
-EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
+EXPORT_SYMBOL_GPL(ufshcd_init_host_param);

/**
* ufshcd_pltfrm_init - probe routine of the driver
diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h
index a86a3ad..2d4d047 100644
--- a/drivers/ufs/host/ufshcd-pltfrm.h
+++ b/drivers/ufs/host/ufshcd-pltfrm.h
@@ -10,7 +10,7 @@
#define UFS_PWM_MODE 1
#define UFS_HS_MODE 2

-struct ufs_dev_params {
+struct ufs_host_params {
u32 pwm_rx_gear; /* pwm rx gear to work in */
u32 pwm_tx_gear; /* pwm tx gear to work in */
u32 hs_rx_gear; /* hs rx gear to work in */
@@ -25,10 +25,10 @@ struct ufs_dev_params {
u32 desired_working_mode;
};

-int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param,
- const struct ufs_pa_layer_attr *dev_max,
- struct ufs_pa_layer_attr *agreed_pwr);
-void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
+int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
+ const struct ufs_pa_layer_attr *dev_max,
+ struct ufs_pa_layer_attr *agreed_pwr);
+void ufshcd_init_host_param(struct ufs_host_params *host_param);
int ufshcd_pltfrm_init(struct platform_device *pdev,
const struct ufs_hba_variant_ops *vops);
int ufshcd_populate_vreg(struct device *dev, const char *name,
--
2.7.4

2023-11-23 08:48:06

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 09/10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550

On SM8550, two sets of UFS PHY settings are provided, one set is to support
HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
settings are programming different values to different registers, mixing
the two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers.

To add HS-G5 support for SM8550, split the two sets of PHY settings into
their dedicated overlay tables, only the common parts of the two sets of
PHY settings are left in the .tbls.

Consider we are going to add even higher gear support in future, to avoid
adding more tables with different names, rename the .tbls_hs_g4 and make it
an array, a size of 2 is enough as of now.

In this case, .tbls alone is not a complete set of PHY settings, so either
tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
.tbls to become a complete set of PHY settings.

Signed-off-by: Can Guo <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++---
4 files changed, 166 insertions(+), 21 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
index c23d5e4..e563af5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
@@ -18,6 +18,7 @@
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
+#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
@@ -27,5 +28,6 @@
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
+#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220

#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8f..ef392ce 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -56,6 +56,8 @@
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
#define QSERDES_V6_COM_PLL_IVCO 0xf4
+#define QSERDES_V6_COM_CMN_IETRIM 0xfc
+#define QSERDES_V6_COM_CMN_IPTRIM 0x100
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 674f158..48f31c8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -15,8 +15,15 @@

#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
+#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
+#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
+#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
+#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
@@ -28,6 +35,8 @@
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
+#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8

#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index ad91f92..29106ec 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -41,6 +41,8 @@

#define PHY_INIT_COMPLETE_TIMEOUT 10000

+#define NUM_OVERLAY 2
+
struct qmp_phy_init_tbl {
unsigned int offset;
unsigned int val;
@@ -649,15 +651,22 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
@@ -666,19 +675,24 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
};

-static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
};

static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
};

static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),

QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
@@ -694,16 +708,45 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
};

+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
};

+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
+};
+
struct qmp_ufs_offsets {
u16 serdes;
u16 pcs;
@@ -723,6 +766,8 @@ struct qmp_phy_cfg_tbls {
int rx_num;
const struct qmp_phy_init_tbl *pcs;
int pcs_num;
+ /* Maximum supported Gear of this tbls */
+ u32 max_gear;
};

/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -730,13 +775,15 @@ struct qmp_phy_cfg {
int lanes;

const struct qmp_ufs_offsets *offsets;
+ /* Maximum supported Gear of this config */
+ u32 max_supported_gear;

/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
const struct qmp_phy_cfg_tbls tbls;
/* Additional sequence for HS Series B */
const struct qmp_phy_cfg_tbls tbls_hs_b;
- /* Additional sequence for HS G4 */
- const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for different HS Gears */
+ const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];

/* clock ids to be requested */
const char * const *clk_list;
@@ -839,6 +886,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,

.tbls = {
.serdes = msm8996_ufsphy_serdes,
@@ -864,6 +912,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,

.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -879,13 +928,14 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -898,6 +948,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,

.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -913,13 +964,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -932,6 +984,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,

.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -960,6 +1013,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,

.tbls = {
.serdes = sm6115_ufsphy_serdes,
@@ -988,6 +1042,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
.lanes = 1,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,

.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -1016,6 +1071,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,

.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1031,13 +1087,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8150_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
.rx = sm8150_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1050,6 +1107,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,

.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1065,13 +1123,14 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8250_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
.rx = sm8250_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1084,6 +1143,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,

.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1099,13 +1159,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1118,6 +1179,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,

.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1133,13 +1195,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -1152,6 +1215,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets_v6,
+ .max_supported_gear = UFS_HS_G5,

.tbls = {
.serdes = sm8550_ufsphy_serdes,
@@ -1167,6 +1231,26 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.serdes = sm8550_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
},
+ .tbls_hs_overlay[0] = {
+ .serdes = sm8550_ufsphy_g4_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
+ .tx = sm8550_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
+ .rx = sm8550_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
+ .pcs = sm8550_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
+ },
+ .tbls_hs_overlay[1] = {
+ .serdes = sm8550_ufsphy_g5_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
+ .rx = sm8550_ufsphy_g5_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
+ .pcs = sm8550_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
+ .max_gear = UFS_HS_G5,
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -1229,17 +1313,63 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
}

-static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
+static bool qmp_ufs_match_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg, int *i)
+{
+ u32 max_gear, floor_max_gear = cfg->max_supported_gear;
+ bool found = false;
+ int j;
+
+ for (j = 0; j < NUM_OVERLAY; j ++) {
+ max_gear = cfg->tbls_hs_overlay[j].max_gear;
+
+ if (max_gear == 0)
+ continue;
+
+ /* Direct matching, bail */
+ if (qmp->submode == max_gear) {
+ *i = j;
+ return true;
+ }
+
+ /* If no direct matching, the lowest gear is the best matching */
+ if (max_gear < floor_max_gear) {
+ *i = j;
+ found = true;
+ floor_max_gear = max_gear;
+ }
+ }
+
+ return found;
+}
+
+static int qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
{
+ bool apply_overlay;
+ int i;
+
+ if (qmp->submode > cfg->max_supported_gear || qmp->submode == 0) {
+ dev_err(qmp->dev, "Invalid PHY submode %u\n", qmp->submode);
+ return -EINVAL;
+ }
+
+ apply_overlay = qmp_ufs_match_gear_overlay(qmp, cfg, &i);
+
qmp_ufs_serdes_init(qmp, &cfg->tbls);
+ if (apply_overlay)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
+
if (qmp->mode == PHY_MODE_UFS_HS_B)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
+
qmp_ufs_lanes_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
+ if (apply_overlay)
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
+
qmp_ufs_pcs_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+ if (apply_overlay)
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
+
+ return 0;
}

static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -1331,7 +1461,9 @@ static int qmp_ufs_power_on(struct phy *phy)
unsigned int val;
int ret;

- qmp_ufs_init_registers(qmp, cfg);
+ ret = qmp_ufs_init_registers(qmp, cfg);
+ if (ret)
+ return ret;

ret = reset_control_deassert(qmp->ufs_reset);
if (ret)
--
2.7.4

2023-11-23 08:48:09

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 08/10] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings

The registers, which are being touched in current SM8550 UFS PHY settings,
and the values being programmed are mainly the ones working for HS-G4 mode,
meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
However, even consider HS-G4 mode only, some of them are incorrect and some
are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.

Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Can Guo <[email protected]>
---
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++-------
2 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 15bcb4b..674f158 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -10,9 +10,12 @@
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
+#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
+#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108

#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 3927eba..ad91f92 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
};

static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
};

static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),

QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
@@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
};

struct qmp_ufs_offsets {
@@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.pcs = sm8550_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8550_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
--
2.7.4

2023-11-23 08:48:34

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 10/10] scsi: ufs: ufs-qcom: Add support for UFS device version detection

From: "Bao D. Nguyen" <[email protected]>

A spare register in UFS host controller is used to indicate the UFS device
version. The spare register is populated by bootloader for now, but in
future it will be populated by HW automatically during link startup with
its best efforts in any boot stages prior to Linux.

During host driver init, read the spare register, if it is not populated
with a UFS device version, go ahead with the dual init mechanism. If a UFS
device version is in there, use the UFS device version together with host
controller's HW version to decide the proper PHY gear which should be used
to configure the UFS PHY without going through the second init.

Signed-off-by: Bao D. Nguyen <[email protected]>
Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 23 ++++++++++++++++++-----
drivers/ufs/host/ufs-qcom.h | 2 ++
2 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 7bbccf4..70bedd9 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1070,15 +1070,28 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
{
struct ufs_host_params *host_params = &host->host_params;
+ u32 val, dev_major = 0;

host->phy_gear = host_params->hs_tx_gear;

- /*
- * Power up the PHY using the minimum supported gear (UFS_HS_G2).
- * Switching to max gear will be performed during reinit if supported.
- */
- if (host->hw_ver.major < 0x5)
+ if (host->hw_ver.major < 0x5) {
+ /*
+ * Power up the PHY using the minimum supported gear (UFS_HS_G2).
+ * Switching to max gear will be performed during reinit if supported.
+ */
host->phy_gear = UFS_HS_G2;
+ } else {
+ val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG);
+ dev_major = FIELD_GET(GENMASK(7, 4), val);
+
+ /* UFS device version populated, no need to do init twice */
+ if (dev_major != 0)
+ host->hba->quirks &= ~UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
+
+ /* For UFS 3.1 and older, apply HS-G4 PHY gear to save power */
+ if (dev_major < 0x4 && dev_major > 0)
+ host->phy_gear = UFS_HS_G4;
+ }
}

static void ufs_qcom_set_host_params(struct ufs_hba *hba)
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 11419eb..d12fc5a 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -54,6 +54,8 @@ enum {
UFS_AH8_CFG = 0xFC,

REG_UFS_CFG3 = 0x271C,
+
+ REG_UFS_DEBUG_SPARE_CFG = 0x284C,
};

/* QCOM UFS host controller vendor specific debug registers */
--
2.7.4

2023-11-23 08:48:54

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 05/10] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear

During host driver init, the phy_gear is set to the minimum supported gear
(HS_G2). Then, during the first power mode change, the negotiated gear, say
HS-G4, is updated to the phy_gear variable so that in the second init the
updated phy_gear can be used to program the PHY.

But the current code only allows update the phy_gear to a higher value. If
one wants to start the first init with the maximum support gear, say HS-G4,
the phy_gear is not updated to HS-G3 if the device only supports HS-G3.

The original check added there is intend to make sure the phy_gear won't be
updated when gear is scaled down (during clock scaling). Update the check
so that one can start the first init with the maximum support gear without
breaking the original fix by checking the ufshcd_state, that is, allow
update to phy_gear only if power mode change is invoked from
ufshcd_probe_hba().

This change is a preparation patch for the next patches in the same series.

Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index d4edf58..9613ad9 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -916,16 +916,19 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
}

/*
- * Update phy_gear only when the gears are scaled to a higher value. This is
- * because, the PHY gear settings are backwards compatible and we only need to
- * change the PHY gear settings while scaling to higher gears.
+ * During UFS driver probe, always update the PHY gear to match the negotiated
+ * gear, so that, if quirk UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is enabled,
+ * the second init can program the optimal PHY settings. This allows one to start
+ * the first init with either the minimum or the maximum support gear.
*/
- if (dev_req_params->gear_tx > host->phy_gear) {
+ if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
u32 old_phy_gear = host->phy_gear;

host->phy_gear = dev_req_params->gear_tx;
- dev_req_params->gear_tx = old_phy_gear;
- dev_req_params->gear_rx = old_phy_gear;
+ if (dev_req_params->gear_tx > old_phy_gear) {
+ dev_req_params->gear_tx = old_phy_gear;
+ dev_req_params->gear_rx = old_phy_gear;
+ }
}

/* enable the device ref clock before changing to HS mode */
--
2.7.4

2023-11-23 08:53:36

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 07/10] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer

Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.

This patch is not changing any functionalities or logic but only a
preparation patch for the next patch in this series.

Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 6756f8d..7bbccf4 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -1067,6 +1067,20 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
}

+static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
+{
+ struct ufs_host_params *host_params = &host->host_params;
+
+ host->phy_gear = host_params->hs_tx_gear;
+
+ /*
+ * Power up the PHY using the minimum supported gear (UFS_HS_G2).
+ * Switching to max gear will be performed during reinit if supported.
+ */
+ if (host->hw_ver.major < 0x5)
+ host->phy_gear = UFS_HS_G2;
+}
+
static void ufs_qcom_set_host_params(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -1303,6 +1317,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
ufs_qcom_set_caps(hba);
ufs_qcom_advertise_quirks(hba);
ufs_qcom_set_host_params(hba);
+ ufs_qcom_set_phy_gear(host);

err = ufs_qcom_ice_init(host);
if (err)
@@ -1320,12 +1335,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
dev_warn(dev, "%s: failed to configure the testbus %d\n",
__func__, err);

- /*
- * Power up the PHY using the minimum supported gear (UFS_HS_G2).
- * Switching to max gear will be performed during reinit if supported.
- */
- host->phy_gear = UFS_HS_G2;
-
return 0;

out_variant_clear:
--
2.7.4

2023-11-23 08:59:21

by Can Guo

[permalink] [raw]
Subject: [PATCH v5 02/10] scsi: ufs: ufs-qcom: No need to set hs_rate after ufshcd_init_host_param()

In ufs_qcom_pwr_change_notify(), host_params.hs_rate has been set to
PA_HS_MODE_B by ufshcd_init_host_param(), hence remove the duplicated line
of work. Meanwhile, removed the macro UFS_QCOM_LIMIT_HS_RATE as it is only
used here.

Signed-off-by: Can Guo <[email protected]>
---
drivers/ufs/host/ufs-qcom.c | 1 -
drivers/ufs/host/ufs-qcom.h | 2 --
2 files changed, 3 deletions(-)

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index aee66a3..cc30ad9 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -909,7 +909,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
switch (status) {
case PRE_CHANGE:
ufshcd_init_host_param(&host_params);
- host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;

/* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 9950a00..82cd143 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -27,8 +27,6 @@
#define SLOW 1
#define FAST 2

-#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
-
/* QCOM UFS host controller vendor specific registers */
enum {
REG_UFS_SYS1CLK_1US = 0xC0,
--
2.7.4

2023-11-23 12:35:42

by Dmitry Baryshkov

[permalink] [raw]
Subject: Re: [PATCH v5 09/10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550

On Thu, 23 Nov 2023 at 10:47, Can Guo <[email protected]> wrote:
>
> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> settings are programming different values to different registers, mixing
> the two sets and/or overwriting one set with another set is definitely not
> blessed by UFS PHY designers.
>
> To add HS-G5 support for SM8550, split the two sets of PHY settings into
> their dedicated overlay tables, only the common parts of the two sets of
> PHY settings are left in the .tbls.
>
> Consider we are going to add even higher gear support in future, to avoid
> adding more tables with different names, rename the .tbls_hs_g4 and make it
> an array, a size of 2 is enough as of now.
>
> In this case, .tbls alone is not a complete set of PHY settings, so either
> tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
> .tbls to become a complete set of PHY settings.
>
> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++---
> 4 files changed, 166 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> index c23d5e4..e563af5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> @@ -18,6 +18,7 @@
> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> @@ -27,5 +28,6 @@
> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index f420f8f..ef392ce 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -56,6 +56,8 @@
> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 674f158..48f31c8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -15,8 +15,15 @@
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> @@ -28,6 +35,8 @@
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index ad91f92..29106ec 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -41,6 +41,8 @@
>
> #define PHY_INIT_COMPLETE_TIMEOUT 10000
>
> +#define NUM_OVERLAY 2
> +
> struct qmp_phy_init_tbl {
> unsigned int offset;
> unsigned int val;
> @@ -649,15 +651,22 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> @@ -666,19 +675,24 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> };
>
> -static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> @@ -694,16 +708,45 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -723,6 +766,8 @@ struct qmp_phy_cfg_tbls {
> int rx_num;
> const struct qmp_phy_init_tbl *pcs;
> int pcs_num;
> + /* Maximum supported Gear of this tbls */
> + u32 max_gear;
> };
>
> /* struct qmp_phy_cfg - per-PHY initialization config */
> @@ -730,13 +775,15 @@ struct qmp_phy_cfg {
> int lanes;
>
> const struct qmp_ufs_offsets *offsets;
> + /* Maximum supported Gear of this config */
> + u32 max_supported_gear;
>
> /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
> const struct qmp_phy_cfg_tbls tbls;
> /* Additional sequence for HS Series B */
> const struct qmp_phy_cfg_tbls tbls_hs_b;
> - /* Additional sequence for HS G4 */
> - const struct qmp_phy_cfg_tbls tbls_hs_g4;
> + /* Additional sequence for different HS Gears */
> + const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -839,6 +886,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
> .lanes = 1,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = msm8996_ufsphy_serdes,
> @@ -864,6 +912,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -879,13 +928,14 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sm8450_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> @@ -898,6 +948,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -913,13 +964,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -932,6 +984,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = sdm845_ufsphy_serdes,
> @@ -960,6 +1013,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> .lanes = 1,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = sm6115_ufsphy_serdes,
> @@ -988,6 +1042,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
> .lanes = 1,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = sdm845_ufsphy_serdes,
> @@ -1016,6 +1071,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8150_ufsphy_serdes,
> @@ -1031,13 +1087,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> .serdes = sm8150_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8150_ufsphy_hs_g4_tx,
> .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
> .rx = sm8150_ufsphy_hs_g4_rx,
> .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
> .pcs = sm8150_ufsphy_hs_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -1050,6 +1107,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8150_ufsphy_serdes,
> @@ -1065,13 +1123,14 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
> .serdes = sm8150_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8250_ufsphy_hs_g4_tx,
> .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
> .rx = sm8250_ufsphy_hs_g4_rx,
> .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
> .pcs = sm8150_ufsphy_hs_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -1084,6 +1143,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -1099,13 +1159,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -1118,6 +1179,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -1133,13 +1195,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sm8450_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> @@ -1152,6 +1215,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets_v6,
> + .max_supported_gear = UFS_HS_G5,
>
> .tbls = {
> .serdes = sm8550_ufsphy_serdes,
> @@ -1167,6 +1231,26 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .serdes = sm8550_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> },
> + .tbls_hs_overlay[0] = {
> + .serdes = sm8550_ufsphy_g4_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> + .tx = sm8550_ufsphy_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> + .rx = sm8550_ufsphy_g4_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> + .pcs = sm8550_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> + },
> + .tbls_hs_overlay[1] = {
> + .serdes = sm8550_ufsphy_g5_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> + .rx = sm8550_ufsphy_g5_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> + .pcs = sm8550_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> + .max_gear = UFS_HS_G5,
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> @@ -1229,17 +1313,63 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
> }
>
> -static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> +static bool qmp_ufs_match_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg, int *i)

You can simply return int from this function. -EINVAL would mean that
the setting was not found. Also this can make max_supported_gear
unused.

> +{
> + u32 max_gear, floor_max_gear = cfg->max_supported_gear;
> + bool found = false;
> + int j;
> +
> + for (j = 0; j < NUM_OVERLAY; j ++) {
> + max_gear = cfg->tbls_hs_overlay[j].max_gear;
> +
> + if (max_gear == 0)
> + continue;
> +
> + /* Direct matching, bail */
> + if (qmp->submode == max_gear) {
> + *i = j;
> + return true;
> + }
> +
> + /* If no direct matching, the lowest gear is the best matching */
> + if (max_gear < floor_max_gear) {
> + *i = j;
> + found = true;
> + floor_max_gear = max_gear;
> + }

We know that the table is sorted. So we can return an index of the
first setting that fits.

> + }
> +
> + return found;
> +}
> +
> +static int qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> + bool apply_overlay;
> + int i;
> +
> + if (qmp->submode > cfg->max_supported_gear || qmp->submode == 0) {
> + dev_err(qmp->dev, "Invalid PHY submode %u\n", qmp->submode);
> + return -EINVAL;
> + }
> +
> + apply_overlay = qmp_ufs_match_gear_overlay(qmp, cfg, &i);
> +
> qmp_ufs_serdes_init(qmp, &cfg->tbls);
> + if (apply_overlay)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
> +
> if (qmp->mode == PHY_MODE_UFS_HS_B)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> +
> qmp_ufs_lanes_init(qmp, &cfg->tbls);
> - if (qmp->submode == UFS_HS_G4)
> - qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
> + if (apply_overlay)
> + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
> +
> qmp_ufs_pcs_init(qmp, &cfg->tbls);
> - if (qmp->submode == UFS_HS_G4)
> - qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
> + if (apply_overlay)
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
> +
> + return 0;
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> @@ -1331,7 +1461,9 @@ static int qmp_ufs_power_on(struct phy *phy)
> unsigned int val;
> int ret;
>
> - qmp_ufs_init_registers(qmp, cfg);
> + ret = qmp_ufs_init_registers(qmp, cfg);
> + if (ret)
> + return ret;
>
> ret = reset_control_deassert(qmp->ufs_reset);
> if (ret)
> --
> 2.7.4
>
>


--
With best wishes
Dmitry

2023-11-24 01:56:55

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 09/10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550



On 11/23/2023 8:35 PM, Dmitry Baryshkov wrote:
> On Thu, 23 Nov 2023 at 10:47, Can Guo <[email protected]> wrote:
>>
>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely not
>> blessed by UFS PHY designers.
>>
>> To add HS-G5 support for SM8550, split the two sets of PHY settings into
>> their dedicated overlay tables, only the common parts of the two sets of
>> PHY settings are left in the .tbls.
>>
>> Consider we are going to add even higher gear support in future, to avoid
>> adding more tables with different names, rename the .tbls_hs_g4 and make it
>> an array, a size of 2 is enough as of now.
>>
>> In this case, .tbls alone is not a complete set of PHY settings, so either
>> tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
>> .tbls to become a complete set of PHY settings.
>>
>> Signed-off-by: Can Guo <[email protected]>
>>
>> -static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
>> +static bool qmp_ufs_match_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg, int *i)
>
> You can simply return int from this function. -EINVAL would mean that
> the setting was not found. Also this can make max_supported_gear
> unused.

I will return int in next version, but I'd like to keep the
max_support_gear, because for platforms which only .tbls is provided (no
overlay case), we need the max_supported_gear to tell whether the
requested submode is exceeding the capability provided by the PHY settings.

>
>> +{
>> + u32 max_gear, floor_max_gear = cfg->max_supported_gear;
>> + bool found = false;
>> + int j;
>> +
>> + for (j = 0; j < NUM_OVERLAY; j ++) {
>> + max_gear = cfg->tbls_hs_overlay[j].max_gear;
>> +
>> + if (max_gear == 0)
>> + continue;
>> +
>> + /* Direct matching, bail */
>> + if (qmp->submode == max_gear) {
>> + *i = j;
>> + return true;
>> + }
>> +
>> + /* If no direct matching, the lowest gear is the best matching */
>> + if (max_gear < floor_max_gear) {
>> + *i = j;
>> + found = true;
>> + floor_max_gear = max_gear;
>> + }
>
> We know that the table is sorted. So we can return an index of the
> first setting that fits.

For SM8550, it is OK, because no-G5 settings are in overlay[0] and G5
settings are in overlay[1], applying one overlay is a must.
.tbls | support nothing as it is incomplete
.tbls + .tbls_hs_overlay[0] | support G4 and lower gears
.tb.s + .tbls_hs_overlay[1] | support G5

But for previously added platforms, no. I put it this way for two reasons -

1. In case the tables are not sorted.
2. For previously added targets, whose configs support G4 and no-G4:
.tbls | support G3 and lower gears
.tbls + .tbls_hs_overlay | support G4
if we anways return an index of the first setting that fits, for these
targets, the G4 settings would always be programmed, no matter UFS
driver requests for G2/G3/G4. On these targets, as dual UFS init is
there to find the most power saving PHY settings, when UFS driver
requests for G2/G3, .tbls_hs_overlay should NOT be applied. Otherwise,
it defeats all the efforts which Mani had spent for the dual UFS init.

Thanks,
Can Guo.
>
>> + }
>> +
>> + return found;
>> +}
>> +
>> +static int qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
>> {
>> + bool apply_overlay;
>> + int i;
>> +
>> + if (qmp->submode > cfg->max_supported_gear || qmp->submode == 0) {
>> + dev_err(qmp->dev, "Invalid PHY submode %u\n", qmp->submode);
>> + return -EINVAL;
>> + }
>> +
>> + apply_overlay = qmp_ufs_match_gear_overlay(qmp, cfg, &i);
>> +
>> qmp_ufs_serdes_init(qmp, &cfg->tbls);
>> + if (apply_overlay)
>> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
>> +
>> if (qmp->mode == PHY_MODE_UFS_HS_B)
>> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
>> +
>> qmp_ufs_lanes_init(qmp, &cfg->tbls);
>> - if (qmp->submode == UFS_HS_G4)
>> - qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
>> + if (apply_overlay)
>> + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
>> +
>> qmp_ufs_pcs_init(qmp, &cfg->tbls);
>> - if (qmp->submode == UFS_HS_G4)
>> - qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
>> + if (apply_overlay)
>> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
>> +
>> + return 0;
>> }
>>
>> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
>> @@ -1331,7 +1461,9 @@ static int qmp_ufs_power_on(struct phy *phy)
>> unsigned int val;
>> int ret;
>>
>> - qmp_ufs_init_registers(qmp, cfg);
>> + ret = qmp_ufs_init_registers(qmp, cfg);
>> + if (ret)
>> + return ret;
>>
>> ret = reset_control_deassert(qmp->ufs_reset);
>> if (ret)
>> --
>> 2.7.4
>>
>>
>
>

2023-11-27 11:07:50

by Vinod Koul

[permalink] [raw]
Subject: Re: [PATCH v5 08/10] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings

On 23-11-23, 00:46, Can Guo wrote:
> The registers, which are being touched in current SM8550 UFS PHY settings,
> and the values being programmed are mainly the ones working for HS-G4 mode,
> meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
> However, even consider HS-G4 mode only, some of them are incorrect and some
> are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
> SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.

can you copy on cover so that we know the context of the series, I just
got hit with two patches out of the blue with this

>
> Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Reviewed-by: Abel Vesa <[email protected]>
> Signed-off-by: Can Guo <[email protected]>
> ---
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++-------
> 2 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 15bcb4b..674f158 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -10,9 +10,12 @@
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba..ad91f92 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> @@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> };
>
> struct qmp_ufs_offsets {
> @@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .pcs = sm8550_ufsphy_pcs,
> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> },
> + .tbls_hs_b = {
> + .serdes = sm8550_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> --
> 2.7.4

--
~Vinod

2023-11-28 01:51:06

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 08/10] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings

Hi Vinod,

On 11/27/2023 7:07 PM, Vinod Koul wrote:
> On 23-11-23, 00:46, Can Guo wrote:
>> The registers, which are being touched in current SM8550 UFS PHY settings,
>> and the values being programmed are mainly the ones working for HS-G4 mode,
>> meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
>> However, even consider HS-G4 mode only, some of them are incorrect and some
>> are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
>> SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.
>
> can you copy on cover so that we know the context of the series, I just
> got hit with two patches out of the blue with this
>

Will add you to the --to list in next version. The whole series is to
enable HS-G5 support on SM8550. FYI, the two changes to UFS PHY driver,
which you mentioned above, in the series are to 1. Rectify existing
HS-G4 PHY setting for SM8550 and 2. Add HS-G5 PHY settings for SM8550.

Thanks,
Can Guo.

>>
>> Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
>> Reviewed-by: Dmitry Baryshkov <[email protected]>
>> Reviewed-by: Abel Vesa <[email protected]>
>> Signed-off-by: Can Guo <[email protected]>
>> ---
>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++-------
>> 2 files changed, 22 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> index 15bcb4b..674f158 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
>> @@ -10,9 +10,12 @@
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
>> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
>> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
>> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>>
>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
>> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
>> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
>> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
>> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index 3927eba..ad91f92 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
>> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
>> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
>> };
>>
>> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
>> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
>> };
>>
>> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
>> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
>> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>>
>> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
>> @@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
>> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
>> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
>> };
>>
>> struct qmp_ufs_offsets {
>> @@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
>> .pcs = sm8550_ufsphy_pcs,
>> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
>> },
>> + .tbls_hs_b = {
>> + .serdes = sm8550_ufsphy_hs_b_serdes,
>> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
>> + },
>> .clk_list = sdm845_ufs_phy_clk_l,
>> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
>> .vreg_list = qmp_phy_vreg_l,
>> --
>> 2.7.4
>

2023-11-28 05:07:41

by Nitin Rawat

[permalink] [raw]
Subject: Re: [PATCH v5 03/10] scsi: ufs: ufs-qcom: Setup host power mode during init



On 11/23/2023 2:16 PM, Can Guo wrote:
> Setup host power mode and its limitations during UFS host driver init to
> avoid repetitive work during every power mode change.
>
> Acked-by: Andrew Halaney <[email protected]>
> Co-developed-by: Bao D. Nguyen <[email protected]>
> Signed-off-by: Bao D. Nguyen <[email protected]>
> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/ufs/host/ufs-qcom.c | 21 ++++++++++++++-------
> drivers/ufs/host/ufs-qcom.h | 1 +
> 2 files changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index cc30ad9..cc0eb37 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> - struct ufs_host_params host_params;
> + struct ufs_host_params *host_params = &host->host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -908,12 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufshcd_init_host_param(&host_params);
> -
> - /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> - host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> -
> - ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev, "%s: failed to determine capabilities\n",
> __func__);
> @@ -1048,6 +1043,17 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
> hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
> }
>
> +static void ufs_qcom_set_host_params(struct ufs_hba *hba)
> +{
> + struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + struct ufs_host_params *host_params = &host->host_params;
> +
> + ufshcd_init_host_param(host_params);
> +
> + /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> + host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> +}
> +
> static void ufs_qcom_set_caps(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> @@ -1272,6 +1278,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>
> ufs_qcom_set_caps(hba);
> ufs_qcom_advertise_quirks(hba);
> + ufs_qcom_set_host_params(hba);
>
> err = ufs_qcom_ice_init(host);
> if (err)
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 82cd143..11419eb 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -238,6 +238,7 @@ struct ufs_qcom_host {
>
> struct gpio_desc *device_reset;
>
> + struct ufs_host_params host_params;
> u32 phy_gear;
>
> bool esi_enabled;

Reviewed-by: Nitin Rawat <[email protected]>

2023-11-28 05:16:43

by Nitin Rawat

[permalink] [raw]
Subject: Re: [PATCH v5 06/10] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5



On 11/23/2023 2:16 PM, Can Guo wrote:
> Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
> HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
> to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
>
> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 9613ad9..6756f8d 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + struct ufs_host_params *host_params = &host->host_params;
> struct phy *phy = host->generic_phy;
> + enum phy_mode mode;
> int ret;
>
> + /*
> + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
> + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
> + * so that the subsequent power mode change shall stick to Rate-A.
> + */
> + if (host->hw_ver.major == 0x5) {
> + if (host->phy_gear == UFS_HS_G5)
> + host_params->hs_rate = PA_HS_MODE_A;
> + else
> + host_params->hs_rate = PA_HS_MODE_B;
> + }
> +
> + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
> +
> /* Reset UFS Host Controller and PHY */
> ret = ufs_qcom_host_reset(hba);
> if (ret)
> @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> return ret;
> }
>
> - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
> + phy_set_mode_ext(phy, mode, host->phy_gear);
>
> /* power on phy - start serdes and phy's power and clocks */
> ret = phy_power_on(phy);

Reviewed-by: Nitin Rawat <[email protected]>

2023-11-28 05:16:45

by Nitin Rawat

[permalink] [raw]
Subject: Re: [PATCH v5 02/10] scsi: ufs: ufs-qcom: No need to set hs_rate after ufshcd_init_host_param()



On 11/23/2023 2:16 PM, Can Guo wrote:
> In ufs_qcom_pwr_change_notify(), host_params.hs_rate has been set to
> PA_HS_MODE_B by ufshcd_init_host_param(), hence remove the duplicated line
> of work. Meanwhile, removed the macro UFS_QCOM_LIMIT_HS_RATE as it is only
> used here.
>
> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/ufs/host/ufs-qcom.c | 1 -
> drivers/ufs/host/ufs-qcom.h | 2 --
> 2 files changed, 3 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index aee66a3..cc30ad9 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -909,7 +909,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> switch (status) {
> case PRE_CHANGE:
> ufshcd_init_host_param(&host_params);
> - host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
>
> /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 9950a00..82cd143 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -27,8 +27,6 @@
> #define SLOW 1
> #define FAST 2
>
> -#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
> -
> /* QCOM UFS host controller vendor specific registers */
> enum {
> REG_UFS_SYS1CLK_1US = 0xC0,

Reviewed-by: Nitin Rawat <[email protected]>

2023-11-28 05:19:51

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 01/10] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params

On Thu, Nov 23, 2023 at 12:46:21AM -0800, Can Guo wrote:
> Structure ufs_dev_params is actually used in UFS host vendor drivers to
> declare host specific power mode parameters, like ufs_<vendor>_params or
> host_cap, which makes the code not very straightforward to read. Rename the
> structure ufs_dev_params to ufs_host_params and unify the declarations in
> all vendor drivers to host_params.
>
> In addition, rename the two functions ufshcd_init_pwr_dev_param() and
> ufshcd_get_pwr_dev_param() which work based on the ufs_host_params to
> ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
> avoid confusions.
>
> This change does not change any functionalities or logic.
>
> Acked-by: Andrew Halaney <[email protected]>
> Signed-off-by: Can Guo <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

- Mani

> ---
> drivers/ufs/host/ufs-exynos.c | 7 ++--
> drivers/ufs/host/ufs-hisi.c | 11 +++----
> drivers/ufs/host/ufs-mediatek.c | 12 +++----
> drivers/ufs/host/ufs-qcom.c | 12 +++----
> drivers/ufs/host/ufshcd-pltfrm.c | 69 ++++++++++++++++++++--------------------
> drivers/ufs/host/ufshcd-pltfrm.h | 10 +++---
> 6 files changed, 57 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index 71bd6db..674f2f4 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -765,7 +765,7 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
> {
> struct exynos_ufs *ufs = ufshcd_get_variant(hba);
> struct phy *generic_phy = ufs->phy;
> - struct ufs_dev_params ufs_exynos_cap;
> + struct ufs_host_params host_params;
> int ret;
>
> if (!dev_req_params) {
> @@ -774,10 +774,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
> goto out;
> }
>
> - ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
> + ufshcd_init_host_param(&host_params);
>
> - ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
> - dev_max_params, dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> pr_err("%s: failed to determine capabilities\n", __func__);
> goto out;
> diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
> index 0229ac0..bb0c9a7 100644
> --- a/drivers/ufs/host/ufs-hisi.c
> +++ b/drivers/ufs/host/ufs-hisi.c
> @@ -293,9 +293,9 @@ static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
> return err;
> }
>
> -static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
> +static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params)
> {
> - ufshcd_init_pwr_dev_param(hisi_param);
> + ufshcd_init_host_param(host_params);
> }
>
> static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
> @@ -365,7 +365,7 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_max_params,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> - struct ufs_dev_params ufs_hisi_cap;
> + struct ufs_host_params host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -377,9 +377,8 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufs_hisi_set_dev_cap(&ufs_hisi_cap);
> - ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
> - dev_max_params, dev_req_params);
> + ufs_hisi_set_dev_cap(&host_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev,
> "%s: failed to determine capabilities\n", __func__);
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
> index fc61790..016067d 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -996,16 +996,14 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> - struct ufs_dev_params host_cap;
> + struct ufs_host_params host_params;
> int ret;
>
> - ufshcd_init_pwr_dev_param(&host_cap);
> - host_cap.hs_rx_gear = UFS_HS_G5;
> - host_cap.hs_tx_gear = UFS_HS_G5;
> + ufshcd_init_host_param(&host_params);
> + host_params.hs_rx_gear = UFS_HS_G5;
> + host_params.hs_tx_gear = UFS_HS_G5;
>
> - ret = ufshcd_get_pwr_dev_param(&host_cap,
> - dev_max_params,
> - dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> pr_info("%s: failed to determine capabilities\n",
> __func__);
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 96cb8b5..aee66a3 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> - struct ufs_dev_params ufs_qcom_cap;
> + struct ufs_host_params host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -908,15 +908,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
> - ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
> + ufshcd_init_host_param(&host_params);
> + host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
>
> /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> - ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> + host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
>
> - ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
> - dev_max_params,
> - dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev, "%s: failed to determine capabilities\n",
> __func__);
> diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
> index da2558e..9ec11b9 100644
> --- a/drivers/ufs/host/ufshcd-pltfrm.c
> +++ b/drivers/ufs/host/ufshcd-pltfrm.c
> @@ -285,61 +285,60 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
> }
>
> /**
> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
> - * power mode change
> - * @pltfrm_param: pointer to platform parameters
> + * ufshcd_negotiate_pwr_param - find power mode settings that are supported by
> + both the controller and the device
> + * @host_param: pointer to host parameters
> * @dev_max: pointer to device attributes
> * @agreed_pwr: returned agreed attributes
> *
> * Return: 0 on success, non-zero value on failure.
> */
> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> - const struct ufs_pa_layer_attr *dev_max,
> - struct ufs_pa_layer_attr *agreed_pwr)
> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
> + const struct ufs_pa_layer_attr *dev_max,
> + struct ufs_pa_layer_attr *agreed_pwr)
> {
> - int min_pltfrm_gear;
> + int min_host_gear;
> int min_dev_gear;
> bool is_dev_sup_hs = false;
> - bool is_pltfrm_max_hs = false;
> + bool is_host_max_hs = false;
>
> if (dev_max->pwr_rx == FAST_MODE)
> is_dev_sup_hs = true;
>
> - if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
> - is_pltfrm_max_hs = true;
> - min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
> - pltfrm_param->hs_tx_gear);
> + if (host_param->desired_working_mode == UFS_HS_MODE) {
> + is_host_max_hs = true;
> + min_host_gear = min_t(u32, host_param->hs_rx_gear,
> + host_param->hs_tx_gear);
> } else {
> - min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
> - pltfrm_param->pwm_tx_gear);
> + min_host_gear = min_t(u32, host_param->pwm_rx_gear,
> + host_param->pwm_tx_gear);
> }
>
> /*
> - * device doesn't support HS but
> - * pltfrm_param->desired_working_mode is HS,
> - * thus device and pltfrm_param don't agree
> + * device doesn't support HS but host_param->desired_working_mode is HS,
> + * thus device and host_param don't agree
> */
> - if (!is_dev_sup_hs && is_pltfrm_max_hs) {
> + if (!is_dev_sup_hs && is_host_max_hs) {
> pr_info("%s: device doesn't support HS\n",
> __func__);
> return -ENOTSUPP;
> - } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
> + } else if (is_dev_sup_hs && is_host_max_hs) {
> /*
> * since device supports HS, it supports FAST_MODE.
> - * since pltfrm_param->desired_working_mode is also HS
> + * since host_param->desired_working_mode is also HS
> * then final decision (FAST/FASTAUTO) is done according
> * to pltfrm_params as it is the restricting factor
> */
> - agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
> + agreed_pwr->pwr_rx = host_param->rx_pwr_hs;
> agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
> } else {
> /*
> - * here pltfrm_param->desired_working_mode is PWM.
> + * here host_param->desired_working_mode is PWM.
> * it doesn't matter whether device supports HS or PWM,
> - * in both cases pltfrm_param->desired_working_mode will
> + * in both cases host_param->desired_working_mode will
> * determine the mode
> */
> - agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
> + agreed_pwr->pwr_rx = host_param->rx_pwr_pwm;
> agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
> }
>
> @@ -349,9 +348,9 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> * the same decision will be made for rx
> */
> agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
> - pltfrm_param->tx_lanes);
> + host_param->tx_lanes);
> agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
> - pltfrm_param->rx_lanes);
> + host_param->rx_lanes);
>
> /* device maximum gear is the minimum between device rx and tx gears */
> min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
> @@ -364,26 +363,26 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> * what is the gear, as it is the one that also decided previously what
> * pwr the device will be configured to.
> */
> - if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
> - (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
> + if ((is_dev_sup_hs && is_host_max_hs) ||
> + (!is_dev_sup_hs && !is_host_max_hs)) {
> agreed_pwr->gear_rx =
> - min_t(u32, min_dev_gear, min_pltfrm_gear);
> + min_t(u32, min_dev_gear, min_host_gear);
> } else if (!is_dev_sup_hs) {
> agreed_pwr->gear_rx = min_dev_gear;
> } else {
> - agreed_pwr->gear_rx = min_pltfrm_gear;
> + agreed_pwr->gear_rx = min_host_gear;
> }
> agreed_pwr->gear_tx = agreed_pwr->gear_rx;
>
> - agreed_pwr->hs_rate = pltfrm_param->hs_rate;
> + agreed_pwr->hs_rate = host_param->hs_rate;
>
> return 0;
> }
> -EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
> +EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_param);
>
> -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
> +void ufshcd_init_host_param(struct ufs_host_params *host_param)
> {
> - *dev_param = (struct ufs_dev_params){
> + *host_param = (struct ufs_host_params){
> .tx_lanes = UFS_LANE_2,
> .rx_lanes = UFS_LANE_2,
> .hs_rx_gear = UFS_HS_G3,
> @@ -398,7 +397,7 @@ void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
> .desired_working_mode = UFS_HS_MODE,
> };
> }
> -EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
> +EXPORT_SYMBOL_GPL(ufshcd_init_host_param);
>
> /**
> * ufshcd_pltfrm_init - probe routine of the driver
> diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h
> index a86a3ad..2d4d047 100644
> --- a/drivers/ufs/host/ufshcd-pltfrm.h
> +++ b/drivers/ufs/host/ufshcd-pltfrm.h
> @@ -10,7 +10,7 @@
> #define UFS_PWM_MODE 1
> #define UFS_HS_MODE 2
>
> -struct ufs_dev_params {
> +struct ufs_host_params {
> u32 pwm_rx_gear; /* pwm rx gear to work in */
> u32 pwm_tx_gear; /* pwm tx gear to work in */
> u32 hs_rx_gear; /* hs rx gear to work in */
> @@ -25,10 +25,10 @@ struct ufs_dev_params {
> u32 desired_working_mode;
> };
>
> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param,
> - const struct ufs_pa_layer_attr *dev_max,
> - struct ufs_pa_layer_attr *agreed_pwr);
> -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
> + const struct ufs_pa_layer_attr *dev_max,
> + struct ufs_pa_layer_attr *agreed_pwr);
> +void ufshcd_init_host_param(struct ufs_host_params *host_param);
> int ufshcd_pltfrm_init(struct platform_device *pdev,
> const struct ufs_hba_variant_ops *vops);
> int ufshcd_populate_vreg(struct device *dev, const char *name,
> --
> 2.7.4
>

--
மணிவண்ணன் சதாசிவம்

2023-11-28 05:22:47

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 02/10] scsi: ufs: ufs-qcom: No need to set hs_rate after ufshcd_init_host_param()

On Thu, Nov 23, 2023 at 12:46:22AM -0800, Can Guo wrote:
> In ufs_qcom_pwr_change_notify(), host_params.hs_rate has been set to
> PA_HS_MODE_B by ufshcd_init_host_param(), hence remove the duplicated line
> of work. Meanwhile, removed the macro UFS_QCOM_LIMIT_HS_RATE as it is only
> used here.
>
> Signed-off-by: Can Guo <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

- Mani

> ---
> drivers/ufs/host/ufs-qcom.c | 1 -
> drivers/ufs/host/ufs-qcom.h | 2 --
> 2 files changed, 3 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index aee66a3..cc30ad9 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -909,7 +909,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> switch (status) {
> case PRE_CHANGE:
> ufshcd_init_host_param(&host_params);
> - host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
>
> /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 9950a00..82cd143 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -27,8 +27,6 @@
> #define SLOW 1
> #define FAST 2
>
> -#define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
> -
> /* QCOM UFS host controller vendor specific registers */
> enum {
> REG_UFS_SYS1CLK_1US = 0xC0,
> --
> 2.7.4
>

--
மணிவண்ணன் சதாசிவம்

2023-11-28 05:24:39

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 03/10] scsi: ufs: ufs-qcom: Setup host power mode during init

On Thu, Nov 23, 2023 at 12:46:23AM -0800, Can Guo wrote:
> Setup host power mode and its limitations during UFS host driver init to
> avoid repetitive work during every power mode change.
>
> Acked-by: Andrew Halaney <[email protected]>
> Co-developed-by: Bao D. Nguyen <[email protected]>
> Signed-off-by: Bao D. Nguyen <[email protected]>
> Signed-off-by: Can Guo <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

- Mani

> ---
> drivers/ufs/host/ufs-qcom.c | 21 ++++++++++++++-------
> drivers/ufs/host/ufs-qcom.h | 1 +
> 2 files changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index cc30ad9..cc0eb37 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> - struct ufs_host_params host_params;
> + struct ufs_host_params *host_params = &host->host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -908,12 +908,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufshcd_init_host_param(&host_params);
> -
> - /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> - host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> -
> - ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev, "%s: failed to determine capabilities\n",
> __func__);
> @@ -1048,6 +1043,17 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
> hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
> }
>
> +static void ufs_qcom_set_host_params(struct ufs_hba *hba)
> +{
> + struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + struct ufs_host_params *host_params = &host->host_params;
> +
> + ufshcd_init_host_param(host_params);
> +
> + /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> + host_params->hs_tx_gear = host_params->hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> +}
> +
> static void ufs_qcom_set_caps(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> @@ -1272,6 +1278,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>
> ufs_qcom_set_caps(hba);
> ufs_qcom_advertise_quirks(hba);
> + ufs_qcom_set_host_params(hba);
>
> err = ufs_qcom_ice_init(host);
> if (err)
> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
> index 82cd143..11419eb 100644
> --- a/drivers/ufs/host/ufs-qcom.h
> +++ b/drivers/ufs/host/ufs-qcom.h
> @@ -238,6 +238,7 @@ struct ufs_qcom_host {
>
> struct gpio_desc *device_reset;
>
> + struct ufs_host_params host_params;
> u32 phy_gear;
>
> bool esi_enabled;
> --
> 2.7.4
>

--
மணிவண்ணன் சதாசிவம்

2023-11-28 05:32:06

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 01/10] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params

On Tue, Nov 28, 2023 at 10:49:36AM +0530, Manivannan Sadhasivam wrote:
> On Thu, Nov 23, 2023 at 12:46:21AM -0800, Can Guo wrote:
> > Structure ufs_dev_params is actually used in UFS host vendor drivers to
> > declare host specific power mode parameters, like ufs_<vendor>_params or
> > host_cap, which makes the code not very straightforward to read. Rename the
> > structure ufs_dev_params to ufs_host_params and unify the declarations in
> > all vendor drivers to host_params.
> >
> > In addition, rename the two functions ufshcd_init_pwr_dev_param() and
> > ufshcd_get_pwr_dev_param() which work based on the ufs_host_params to
> > ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
> > avoid confusions.
> >
> > This change does not change any functionalities or logic.
> >
> > Acked-by: Andrew Halaney <[email protected]>
> > Signed-off-by: Can Guo <[email protected]>
>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
>
> - Mani
>
> > ---
> > drivers/ufs/host/ufs-exynos.c | 7 ++--
> > drivers/ufs/host/ufs-hisi.c | 11 +++----
> > drivers/ufs/host/ufs-mediatek.c | 12 +++----
> > drivers/ufs/host/ufs-qcom.c | 12 +++----
> > drivers/ufs/host/ufshcd-pltfrm.c | 69 ++++++++++++++++++++--------------------
> > drivers/ufs/host/ufshcd-pltfrm.h | 10 +++---
> > 6 files changed, 57 insertions(+), 64 deletions(-)
> >

[...]

> > diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h
> > index a86a3ad..2d4d047 100644
> > --- a/drivers/ufs/host/ufshcd-pltfrm.h
> > +++ b/drivers/ufs/host/ufshcd-pltfrm.h
> > @@ -10,7 +10,7 @@
> > #define UFS_PWM_MODE 1
> > #define UFS_HS_MODE 2
> >
> > -struct ufs_dev_params {
> > +struct ufs_host_params {
> > u32 pwm_rx_gear; /* pwm rx gear to work in */
> > u32 pwm_tx_gear; /* pwm tx gear to work in */
> > u32 hs_rx_gear; /* hs rx gear to work in */
> > @@ -25,10 +25,10 @@ struct ufs_dev_params {
> > u32 desired_working_mode;
> > };
> >
> > -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param,
> > - const struct ufs_pa_layer_attr *dev_max,
> > - struct ufs_pa_layer_attr *agreed_pwr);
> > -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
> > +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
> > + const struct ufs_pa_layer_attr *dev_max,
> > + struct ufs_pa_layer_attr *agreed_pwr);
> > +void ufshcd_init_host_param(struct ufs_host_params *host_param);

Noticed this after giving my R-b tag. Could you please rename the functions to:

int ufshcd_negotiate_pwr_params(const struct ufs_host_params *host_params,...
void ufshcd_init_host_params(struct ufs_host_params *host_params);

Not a big deal, but since the argument passed to both functions are 'params',
it'd be good if the function definition also use the same plural form.

- Mani

--
மணிவண்ணன் சதாசிவம்

2023-11-28 05:32:45

by Nitin Rawat

[permalink] [raw]
Subject: Re: [PATCH v5 01/10] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params



On 11/23/2023 2:16 PM, Can Guo wrote:
> Structure ufs_dev_params is actually used in UFS host vendor drivers to
> declare host specific power mode parameters, like ufs_<vendor>_params or
> host_cap, which makes the code not very straightforward to read. Rename the
> structure ufs_dev_params to ufs_host_params and unify the declarations in
> all vendor drivers to host_params.
>
> In addition, rename the two functions ufshcd_init_pwr_dev_param() and
> ufshcd_get_pwr_dev_param() which work based on the ufs_host_params to
> ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
> avoid confusions.
>
> This change does not change any functionalities or logic.
>
> Acked-by: Andrew Halaney <[email protected]>
> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/ufs/host/ufs-exynos.c | 7 ++--
> drivers/ufs/host/ufs-hisi.c | 11 +++----
> drivers/ufs/host/ufs-mediatek.c | 12 +++----
> drivers/ufs/host/ufs-qcom.c | 12 +++----
> drivers/ufs/host/ufshcd-pltfrm.c | 69 ++++++++++++++++++++--------------------
> drivers/ufs/host/ufshcd-pltfrm.h | 10 +++---
> 6 files changed, 57 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
> index 71bd6db..674f2f4 100644
> --- a/drivers/ufs/host/ufs-exynos.c
> +++ b/drivers/ufs/host/ufs-exynos.c
> @@ -765,7 +765,7 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
> {
> struct exynos_ufs *ufs = ufshcd_get_variant(hba);
> struct phy *generic_phy = ufs->phy;
> - struct ufs_dev_params ufs_exynos_cap;
> + struct ufs_host_params host_params;
> int ret;
>
> if (!dev_req_params) {
> @@ -774,10 +774,9 @@ static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
> goto out;
> }
>
> - ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
> + ufshcd_init_host_param(&host_params);
>
> - ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
> - dev_max_params, dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> pr_err("%s: failed to determine capabilities\n", __func__);
> goto out;
> diff --git a/drivers/ufs/host/ufs-hisi.c b/drivers/ufs/host/ufs-hisi.c
> index 0229ac0..bb0c9a7 100644
> --- a/drivers/ufs/host/ufs-hisi.c
> +++ b/drivers/ufs/host/ufs-hisi.c
> @@ -293,9 +293,9 @@ static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
> return err;
> }
>
> -static void ufs_hisi_set_dev_cap(struct ufs_dev_params *hisi_param)
> +static void ufs_hisi_set_dev_cap(struct ufs_host_params *host_params)
> {
> - ufshcd_init_pwr_dev_param(hisi_param);
> + ufshcd_init_host_param(host_params);
> }
>
> static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
> @@ -365,7 +365,7 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_max_params,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> - struct ufs_dev_params ufs_hisi_cap;
> + struct ufs_host_params host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -377,9 +377,8 @@ static int ufs_hisi_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufs_hisi_set_dev_cap(&ufs_hisi_cap);
> - ret = ufshcd_get_pwr_dev_param(&ufs_hisi_cap,
> - dev_max_params, dev_req_params);
> + ufs_hisi_set_dev_cap(&host_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev,
> "%s: failed to determine capabilities\n", __func__);
> diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
> index fc61790..016067d 100644
> --- a/drivers/ufs/host/ufs-mediatek.c
> +++ b/drivers/ufs/host/ufs-mediatek.c
> @@ -996,16 +996,14 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> - struct ufs_dev_params host_cap;
> + struct ufs_host_params host_params;
> int ret;
>
> - ufshcd_init_pwr_dev_param(&host_cap);
> - host_cap.hs_rx_gear = UFS_HS_G5;
> - host_cap.hs_tx_gear = UFS_HS_G5;
> + ufshcd_init_host_param(&host_params);
> + host_params.hs_rx_gear = UFS_HS_G5;
> + host_params.hs_tx_gear = UFS_HS_G5;
>
> - ret = ufshcd_get_pwr_dev_param(&host_cap,
> - dev_max_params,
> - dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> pr_info("%s: failed to determine capabilities\n",
> __func__);
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 96cb8b5..aee66a3 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -898,7 +898,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> struct ufs_pa_layer_attr *dev_req_params)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> - struct ufs_dev_params ufs_qcom_cap;
> + struct ufs_host_params host_params;
> int ret = 0;
>
> if (!dev_req_params) {
> @@ -908,15 +908,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>
> switch (status) {
> case PRE_CHANGE:
> - ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
> - ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
> + ufshcd_init_host_param(&host_params);
> + host_params.hs_rate = UFS_QCOM_LIMIT_HS_RATE;
>
> /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */
> - ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
> + host_params.hs_tx_gear = host_params.hs_rx_gear = ufs_qcom_get_hs_gear(hba);
>
> - ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap,
> - dev_max_params,
> - dev_req_params);
> + ret = ufshcd_negotiate_pwr_param(&host_params, dev_max_params, dev_req_params);
> if (ret) {
> dev_err(hba->dev, "%s: failed to determine capabilities\n",
> __func__);
> diff --git a/drivers/ufs/host/ufshcd-pltfrm.c b/drivers/ufs/host/ufshcd-pltfrm.c
> index da2558e..9ec11b9 100644
> --- a/drivers/ufs/host/ufshcd-pltfrm.c
> +++ b/drivers/ufs/host/ufshcd-pltfrm.c
> @@ -285,61 +285,60 @@ static int ufshcd_parse_operating_points(struct ufs_hba *hba)
> }
>
> /**
> - * ufshcd_get_pwr_dev_param - get finally agreed attributes for
> - * power mode change
> - * @pltfrm_param: pointer to platform parameters
> + * ufshcd_negotiate_pwr_param - find power mode settings that are supported by
> + both the controller and the device
> + * @host_param: pointer to host parameters
> * @dev_max: pointer to device attributes
> * @agreed_pwr: returned agreed attributes
> *
> * Return: 0 on success, non-zero value on failure.
> */
> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> - const struct ufs_pa_layer_attr *dev_max,
> - struct ufs_pa_layer_attr *agreed_pwr)
> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
> + const struct ufs_pa_layer_attr *dev_max,
> + struct ufs_pa_layer_attr *agreed_pwr)
> {
> - int min_pltfrm_gear;
> + int min_host_gear;
> int min_dev_gear;
> bool is_dev_sup_hs = false;
> - bool is_pltfrm_max_hs = false;
> + bool is_host_max_hs = false;
>
> if (dev_max->pwr_rx == FAST_MODE)
> is_dev_sup_hs = true;
>
> - if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
> - is_pltfrm_max_hs = true;
> - min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
> - pltfrm_param->hs_tx_gear);
> + if (host_param->desired_working_mode == UFS_HS_MODE) {
> + is_host_max_hs = true;
> + min_host_gear = min_t(u32, host_param->hs_rx_gear,
> + host_param->hs_tx_gear);
> } else {
> - min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
> - pltfrm_param->pwm_tx_gear);
> + min_host_gear = min_t(u32, host_param->pwm_rx_gear,
> + host_param->pwm_tx_gear);
> }
>
> /*
> - * device doesn't support HS but
> - * pltfrm_param->desired_working_mode is HS,
> - * thus device and pltfrm_param don't agree
> + * device doesn't support HS but host_param->desired_working_mode is HS,
> + * thus device and host_param don't agree
> */
> - if (!is_dev_sup_hs && is_pltfrm_max_hs) {
> + if (!is_dev_sup_hs && is_host_max_hs) {
> pr_info("%s: device doesn't support HS\n",
> __func__);
> return -ENOTSUPP;
> - } else if (is_dev_sup_hs && is_pltfrm_max_hs) {
> + } else if (is_dev_sup_hs && is_host_max_hs) {
> /*
> * since device supports HS, it supports FAST_MODE.
> - * since pltfrm_param->desired_working_mode is also HS
> + * since host_param->desired_working_mode is also HS
> * then final decision (FAST/FASTAUTO) is done according
> * to pltfrm_params as it is the restricting factor
> */
> - agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
> + agreed_pwr->pwr_rx = host_param->rx_pwr_hs;
> agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
> } else {
> /*
> - * here pltfrm_param->desired_working_mode is PWM.
> + * here host_param->desired_working_mode is PWM.
> * it doesn't matter whether device supports HS or PWM,
> - * in both cases pltfrm_param->desired_working_mode will
> + * in both cases host_param->desired_working_mode will
> * determine the mode
> */
> - agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
> + agreed_pwr->pwr_rx = host_param->rx_pwr_pwm;
> agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
> }
>
> @@ -349,9 +348,9 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> * the same decision will be made for rx
> */
> agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
> - pltfrm_param->tx_lanes);
> + host_param->tx_lanes);
> agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
> - pltfrm_param->rx_lanes);
> + host_param->rx_lanes);
>
> /* device maximum gear is the minimum between device rx and tx gears */
> min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
> @@ -364,26 +363,26 @@ int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *pltfrm_param,
> * what is the gear, as it is the one that also decided previously what
> * pwr the device will be configured to.
> */
> - if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
> - (!is_dev_sup_hs && !is_pltfrm_max_hs)) {
> + if ((is_dev_sup_hs && is_host_max_hs) ||
> + (!is_dev_sup_hs && !is_host_max_hs)) {
> agreed_pwr->gear_rx =
> - min_t(u32, min_dev_gear, min_pltfrm_gear);
> + min_t(u32, min_dev_gear, min_host_gear);
> } else if (!is_dev_sup_hs) {
> agreed_pwr->gear_rx = min_dev_gear;
> } else {
> - agreed_pwr->gear_rx = min_pltfrm_gear;
> + agreed_pwr->gear_rx = min_host_gear;
> }
> agreed_pwr->gear_tx = agreed_pwr->gear_rx;
>
> - agreed_pwr->hs_rate = pltfrm_param->hs_rate;
> + agreed_pwr->hs_rate = host_param->hs_rate;
>
> return 0;
> }
> -EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
> +EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_param);
>
> -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
> +void ufshcd_init_host_param(struct ufs_host_params *host_param)
> {
> - *dev_param = (struct ufs_dev_params){
> + *host_param = (struct ufs_host_params){
> .tx_lanes = UFS_LANE_2,
> .rx_lanes = UFS_LANE_2,
> .hs_rx_gear = UFS_HS_G3,
> @@ -398,7 +397,7 @@ void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
> .desired_working_mode = UFS_HS_MODE,
> };
> }
> -EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
> +EXPORT_SYMBOL_GPL(ufshcd_init_host_param);
>
> /**
> * ufshcd_pltfrm_init - probe routine of the driver
> diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h
> index a86a3ad..2d4d047 100644
> --- a/drivers/ufs/host/ufshcd-pltfrm.h
> +++ b/drivers/ufs/host/ufshcd-pltfrm.h
> @@ -10,7 +10,7 @@
> #define UFS_PWM_MODE 1
> #define UFS_HS_MODE 2
>
> -struct ufs_dev_params {
> +struct ufs_host_params {
> u32 pwm_rx_gear; /* pwm rx gear to work in */
> u32 pwm_tx_gear; /* pwm tx gear to work in */
> u32 hs_rx_gear; /* hs rx gear to work in */
> @@ -25,10 +25,10 @@ struct ufs_dev_params {
> u32 desired_working_mode;
> };
>
> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param,
> - const struct ufs_pa_layer_attr *dev_max,
> - struct ufs_pa_layer_attr *agreed_pwr);
> -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
> + const struct ufs_pa_layer_attr *dev_max,
> + struct ufs_pa_layer_attr *agreed_pwr);
> +void ufshcd_init_host_param(struct ufs_host_params *host_param);
> int ufshcd_pltfrm_init(struct platform_device *pdev,
> const struct ufs_hba_variant_ops *vops);
> int ufshcd_populate_vreg(struct device *dev, const char *name,

Reviewed-by: Nitin Rawat <[email protected]>

2023-11-28 05:46:20

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 04/10] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear

On Thu, Nov 23, 2023 at 12:46:24AM -0800, Can Guo wrote:
> In the dual init scenario, the initial PHY gear is set to HS-G2, and the
> first Power Mode Change (PMC) is meant to find the best matching PHY gear
> for the 2nd init. However, for the first PMC, if the negotiated gear (say
> HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to
> the negotiated gear happen, because the programmed UFS PHY settings may not
> support the negotiated gear. Fix it by overwriting the negotiated gear with
> the PHY gear.
>

I don't quite understand this patch. If the phy_gear is G2 initially and the
negotiated gear is G4, then as per this change,

phy_gear = G4;
negotiated gear = G2;

Could you please explain how this make sense?

- Mani

> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/ufs/host/ufs-qcom.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index cc0eb37..d4edf58 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> * because, the PHY gear settings are backwards compatible and we only need to
> * change the PHY gear settings while scaling to higher gears.
> */
> - if (dev_req_params->gear_tx > host->phy_gear)
> + if (dev_req_params->gear_tx > host->phy_gear) {
> + u32 old_phy_gear = host->phy_gear;
> +
> host->phy_gear = dev_req_params->gear_tx;
> + dev_req_params->gear_tx = old_phy_gear;
> + dev_req_params->gear_rx = old_phy_gear;
> + }
>
> /* enable the device ref clock before changing to HS mode */
> if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
> --
> 2.7.4
>

--
மணிவண்ணன் சதாசிவம்

2023-11-28 05:55:43

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 06/10] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5

On Thu, Nov 23, 2023 at 12:46:26AM -0800, Can Guo wrote:
> Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
> HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
> to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
>
> Signed-off-by: Can Guo <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

One question below...

> ---
> drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 9613ad9..6756f8d 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> + struct ufs_host_params *host_params = &host->host_params;
> struct phy *phy = host->generic_phy;
> + enum phy_mode mode;
> int ret;
>
> + /*
> + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
> + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
> + * so that the subsequent power mode change shall stick to Rate-A.
> + */
> + if (host->hw_ver.major == 0x5) {
> + if (host->phy_gear == UFS_HS_G5)
> + host_params->hs_rate = PA_HS_MODE_A;
> + else
> + host_params->hs_rate = PA_HS_MODE_B;

Is this 'else' part really needed? Since there wouldn't be any 2nd init, I think
we can skip that.

- Mani

> + }
> +
> + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
> +
> /* Reset UFS Host Controller and PHY */
> ret = ufs_qcom_host_reset(hba);
> if (ret)
> @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> return ret;
> }
>
> - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
> + phy_set_mode_ext(phy, mode, host->phy_gear);
>
> /* power on phy - start serdes and phy's power and clocks */
> ret = phy_power_on(phy);
> --
> 2.7.4
>

--
மணிவண்ணன் சதாசிவம்

2023-11-28 06:01:16

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 07/10] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer

On Thu, Nov 23, 2023 at 12:46:27AM -0800, Can Guo wrote:
> Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
>

MAX_GEAR will be used for hosts with hw_ver.major >= 4

> This patch is not changing any functionalities or logic but only a
> preparation patch for the next patch in this series.
>
> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++------
> 1 file changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> index 6756f8d..7bbccf4 100644
> --- a/drivers/ufs/host/ufs-qcom.c
> +++ b/drivers/ufs/host/ufs-qcom.c
> @@ -1067,6 +1067,20 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
> hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
> }
>
> +static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
> +{
> + struct ufs_host_params *host_params = &host->host_params;
> +
> + host->phy_gear = host_params->hs_tx_gear;
> +
> + /*
> + * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> + * Switching to max gear will be performed during reinit if supported.

You need to reword this comment too.

> + */
> + if (host->hw_ver.major < 0x5)

As I mentioned above, MAX_GEAR will be used if hw_ver.major is >=4 in
ufs_qcom_get_hs_gear(). So this check should be (< 0x4).

- Mani

> + host->phy_gear = UFS_HS_G2;
> +}
> +
> static void ufs_qcom_set_host_params(struct ufs_hba *hba)
> {
> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> @@ -1303,6 +1317,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> ufs_qcom_set_caps(hba);
> ufs_qcom_advertise_quirks(hba);
> ufs_qcom_set_host_params(hba);
> + ufs_qcom_set_phy_gear(host);
>
> err = ufs_qcom_ice_init(host);
> if (err)
> @@ -1320,12 +1335,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> dev_warn(dev, "%s: failed to configure the testbus %d\n",
> __func__, err);
>
> - /*
> - * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> - * Switching to max gear will be performed during reinit if supported.
> - */
> - host->phy_gear = UFS_HS_G2;
> -
> return 0;
>
> out_variant_clear:
> --
> 2.7.4
>

--
மணிவண்ணன் சதாசிவம்

2023-11-28 06:03:29

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 08/10] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings

On Thu, Nov 23, 2023 at 12:46:28AM -0800, Can Guo wrote:
> The registers, which are being touched in current SM8550 UFS PHY settings,
> and the values being programmed are mainly the ones working for HS-G4 mode,
> meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
> However, even consider HS-G4 mode only, some of them are incorrect and some
> are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
> SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.
>
> Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Reviewed-by: Abel Vesa <[email protected]>
> Signed-off-by: Can Guo <[email protected]>

Reviewed-by: Manivannan Sadhasivam <[email protected]>

- Mani

> ---
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++-------
> 2 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 15bcb4b..674f158 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -10,9 +10,12 @@
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
> #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
> +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
> +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 3927eba..ad91f92 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> @@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> };
>
> struct qmp_ufs_offsets {
> @@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .pcs = sm8550_ufsphy_pcs,
> .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
> },
> + .tbls_hs_b = {
> + .serdes = sm8550_ufsphy_hs_b_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> --
> 2.7.4
>

--
மணிவண்ணன் சதாசிவம்

2023-11-28 06:48:15

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 09/10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550

On Thu, Nov 23, 2023 at 12:46:29AM -0800, Can Guo wrote:
> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> settings are programming different values to different registers, mixing
> the two sets and/or overwriting one set with another set is definitely not
> blessed by UFS PHY designers.
>
> To add HS-G5 support for SM8550, split the two sets of PHY settings into
> their dedicated overlay tables, only the common parts of the two sets of
> PHY settings are left in the .tbls.
>
> Consider we are going to add even higher gear support in future, to avoid
> adding more tables with different names, rename the .tbls_hs_g4 and make it
> an array, a size of 2 is enough as of now.
>
> In this case, .tbls alone is not a complete set of PHY settings, so either
> tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
> .tbls to become a complete set of PHY settings.
>

Thanks for the update! This really helps in minimizing the changes for future
gears.

> Signed-off-by: Can Guo <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++---
> 4 files changed, 166 insertions(+), 21 deletions(-)
>
>

[...]

> -static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> +static bool qmp_ufs_match_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg, int *i)
> +{
> + u32 max_gear, floor_max_gear = cfg->max_supported_gear;
> + bool found = false;
> + int j;
> +
> + for (j = 0; j < NUM_OVERLAY; j ++) {
> + max_gear = cfg->tbls_hs_overlay[j].max_gear;
> +
> + if (max_gear == 0)

Is this condition possible for hs_overlay tables?

> + continue;
> +
> + /* Direct matching, bail */
> + if (qmp->submode == max_gear) {
> + *i = j;
> + return true;
> + }
> +
> + /* If no direct matching, the lowest gear is the best matching */
> + if (max_gear < floor_max_gear) {

Can you start the loop from max? If looks odd to set the matching params in the
first iteration itself and then checking the next one.

> + *i = j;
> + found = true;
> + floor_max_gear = max_gear;
> + }
> + }
> +
> + return found;
> +}
> +
> +static int qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> + bool apply_overlay;
> + int i;
> +
> + if (qmp->submode > cfg->max_supported_gear || qmp->submode == 0) {
> + dev_err(qmp->dev, "Invalid PHY submode %u\n", qmp->submode);
> + return -EINVAL;
> + }

This check should be moved to qmp_ufs_set_mode().

Rest LGTM.

- Mani

--
மணிவண்ணன் சதாசிவம்

2023-11-28 07:48:39

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 06/10] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5

Hi Mani,

On 11/28/2023 1:55 PM, Manivannan Sadhasivam wrote:
> On Thu, Nov 23, 2023 at 12:46:26AM -0800, Can Guo wrote:
>> Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
>> HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
>> to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
>>
>> Signed-off-by: Can Guo <[email protected]>
>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
>
> One question below...
>
>> ---
>> drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index 9613ad9..6756f8d 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
>> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>> {
>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>> + struct ufs_host_params *host_params = &host->host_params;
>> struct phy *phy = host->generic_phy;
>> + enum phy_mode mode;
>> int ret;
>>
>> + /*
>> + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
>> + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
>> + * so that the subsequent power mode change shall stick to Rate-A.
>> + */
>> + if (host->hw_ver.major == 0x5) {
>> + if (host->phy_gear == UFS_HS_G5)
>> + host_params->hs_rate = PA_HS_MODE_A;
>> + else
>> + host_params->hs_rate = PA_HS_MODE_B;
>
> Is this 'else' part really needed? Since there wouldn't be any 2nd init, I think
> we can skip that.

We need it because, even there is only one init, if a UFS3.1 device is
attached, phy_gear is given as UFS_HS_G4 in ufs_qcom_set_phy_gear(),
hence we need to put the UFS at HS-G4 Rate B, not Rate A.

Thanks,
Can Guo.

>
> - Mani
>
>> + }
>> +
>> + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
>> +
>> /* Reset UFS Host Controller and PHY */
>> ret = ufs_qcom_host_reset(hba);
>> if (ret)
>> @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>> return ret;
>> }
>>
>> - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
>> + phy_set_mode_ext(phy, mode, host->phy_gear);
>>
>> /* power on phy - start serdes and phy's power and clocks */
>> ret = phy_power_on(phy);
>> --
>> 2.7.4
>>
>

2023-11-28 07:50:40

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 01/10] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params



On 11/28/2023 1:31 PM, Manivannan Sadhasivam wrote:
> On Tue, Nov 28, 2023 at 10:49:36AM +0530, Manivannan Sadhasivam wrote:
>> On Thu, Nov 23, 2023 at 12:46:21AM -0800, Can Guo wrote:
>>> Structure ufs_dev_params is actually used in UFS host vendor drivers to
>>> declare host specific power mode parameters, like ufs_<vendor>_params or
>>> host_cap, which makes the code not very straightforward to read. Rename the
>>> structure ufs_dev_params to ufs_host_params and unify the declarations in
>>> all vendor drivers to host_params.
>>>
>>> In addition, rename the two functions ufshcd_init_pwr_dev_param() and
>>> ufshcd_get_pwr_dev_param() which work based on the ufs_host_params to
>>> ufshcd_init_host_param() and ufshcd_negotiate_pwr_param() respectively to
>>> avoid confusions.
>>>
>>> This change does not change any functionalities or logic.
>>>
>>> Acked-by: Andrew Halaney <[email protected]>
>>> Signed-off-by: Can Guo <[email protected]>
>>
>> Reviewed-by: Manivannan Sadhasivam <[email protected]>
>>
>> - Mani
>>
>>> ---
>>> drivers/ufs/host/ufs-exynos.c | 7 ++--
>>> drivers/ufs/host/ufs-hisi.c | 11 +++----
>>> drivers/ufs/host/ufs-mediatek.c | 12 +++----
>>> drivers/ufs/host/ufs-qcom.c | 12 +++----
>>> drivers/ufs/host/ufshcd-pltfrm.c | 69 ++++++++++++++++++++--------------------
>>> drivers/ufs/host/ufshcd-pltfrm.h | 10 +++---
>>> 6 files changed, 57 insertions(+), 64 deletions(-)
>>>
>
> [...]
>
>>> diff --git a/drivers/ufs/host/ufshcd-pltfrm.h b/drivers/ufs/host/ufshcd-pltfrm.h
>>> index a86a3ad..2d4d047 100644
>>> --- a/drivers/ufs/host/ufshcd-pltfrm.h
>>> +++ b/drivers/ufs/host/ufshcd-pltfrm.h
>>> @@ -10,7 +10,7 @@
>>> #define UFS_PWM_MODE 1
>>> #define UFS_HS_MODE 2
>>>
>>> -struct ufs_dev_params {
>>> +struct ufs_host_params {
>>> u32 pwm_rx_gear; /* pwm rx gear to work in */
>>> u32 pwm_tx_gear; /* pwm tx gear to work in */
>>> u32 hs_rx_gear; /* hs rx gear to work in */
>>> @@ -25,10 +25,10 @@ struct ufs_dev_params {
>>> u32 desired_working_mode;
>>> };
>>>
>>> -int ufshcd_get_pwr_dev_param(const struct ufs_dev_params *dev_param,
>>> - const struct ufs_pa_layer_attr *dev_max,
>>> - struct ufs_pa_layer_attr *agreed_pwr);
>>> -void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param);
>>> +int ufshcd_negotiate_pwr_param(const struct ufs_host_params *host_param,
>>> + const struct ufs_pa_layer_attr *dev_max,
>>> + struct ufs_pa_layer_attr *agreed_pwr);
>>> +void ufshcd_init_host_param(struct ufs_host_params *host_param);
>
> Noticed this after giving my R-b tag. Could you please rename the functions to:
>
> int ufshcd_negotiate_pwr_params(const struct ufs_host_params *host_params,...
> void ufshcd_init_host_params(struct ufs_host_params *host_params);
>
> Not a big deal, but since the argument passed to both functions are 'params',
> it'd be good if the function definition also use the same plural form.
>

No worries, will do in next version.

Thanks,
Can Guo.

> - Mani
>

2023-11-28 07:59:22

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 07/10] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer

Hi Mani,

On 11/28/2023 2:00 PM, Manivannan Sadhasivam wrote:
> On Thu, Nov 23, 2023 at 12:46:27AM -0800, Can Guo wrote:
>> Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
>>
>
> MAX_GEAR will be used for hosts with hw_ver.major >= 4

I put it > 5 because I am not intent to touch any old targets which has
proven working fine with starting with PHY gear HS_G2. If I put it >= 4,
there would be many targets impacted by this change. I need to go back
and test those platforms (HW ver == 4).

Thanks,
Can Guo.

>
>> This patch is not changing any functionalities or logic but only a
>> preparation patch for the next patch in this series.
>>
>> Signed-off-by: Can Guo <[email protected]>
>> ---
>> drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++------
>> 1 file changed, 15 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index 6756f8d..7bbccf4 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -1067,6 +1067,20 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
>> hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
>> }
>>
>> +static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
>> +{
>> + struct ufs_host_params *host_params = &host->host_params;
>> +
>> + host->phy_gear = host_params->hs_tx_gear;
>> +
>> + /*
>> + * Power up the PHY using the minimum supported gear (UFS_HS_G2).
>> + * Switching to max gear will be performed during reinit if supported.
>
> You need to reword this comment too.
>
>> + */
>> + if (host->hw_ver.major < 0x5)
>
> As I mentioned above, MAX_GEAR will be used if hw_ver.major is >=4 in
> ufs_qcom_get_hs_gear(). So this check should be (< 0x4).
>
> - Mani
>
>> + host->phy_gear = UFS_HS_G2;
>> +}
>> +
>> static void ufs_qcom_set_host_params(struct ufs_hba *hba)
>> {
>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>> @@ -1303,6 +1317,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>> ufs_qcom_set_caps(hba);
>> ufs_qcom_advertise_quirks(hba);
>> ufs_qcom_set_host_params(hba);
>> + ufs_qcom_set_phy_gear(host);
>>
>> err = ufs_qcom_ice_init(host);
>> if (err)
>> @@ -1320,12 +1335,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>> dev_warn(dev, "%s: failed to configure the testbus %d\n",
>> __func__, err);
>>
>> - /*
>> - * Power up the PHY using the minimum supported gear (UFS_HS_G2).
>> - * Switching to max gear will be performed during reinit if supported.
>> - */
>> - host->phy_gear = UFS_HS_G2;
>> -
>> return 0;
>>
>> out_variant_clear:
>> --
>> 2.7.4
>>
>

2023-11-28 08:07:41

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 04/10] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear

Hi Mani,

On 11/28/2023 1:45 PM, Manivannan Sadhasivam wrote:
> On Thu, Nov 23, 2023 at 12:46:24AM -0800, Can Guo wrote:
>> In the dual init scenario, the initial PHY gear is set to HS-G2, and the
>> first Power Mode Change (PMC) is meant to find the best matching PHY gear
>> for the 2nd init. However, for the first PMC, if the negotiated gear (say
>> HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to
>> the negotiated gear happen, because the programmed UFS PHY settings may not
>> support the negotiated gear. Fix it by overwriting the negotiated gear with
>> the PHY gear.
>>
>
> I don't quite understand this patch. If the phy_gear is G2 initially and the
> negotiated gear is G4, then as per this change,
>
> phy_gear = G4;
> negotiated gear = G2;
>
> Could you please explain how this make sense?

phy_gear was G2 (in the beginning) and just now changed to G4, but the
PHY settings programmed in the beginning can only support no-G4 (not
G4). Without this change, as the negotiated gear is G4, the power mode
change is going to put UFS at HS-G4 mode, but the PHY settings
programmed is no-G4. This change is to limit the negotiated gear to
HS-G2 for the 1st init. In the 2nd init, as the new PHY gear is G4, G4
PHY settings would be programmed, it'd be safe to put the UFS at HS-G4 mode.

Thanks,
Can Guo.
>
> - Mani
>
>> Signed-off-by: Can Guo <[email protected]>
>> ---
>> drivers/ufs/host/ufs-qcom.c | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index cc0eb37..d4edf58 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>> * because, the PHY gear settings are backwards compatible and we only need to
>> * change the PHY gear settings while scaling to higher gears.
>> */
>> - if (dev_req_params->gear_tx > host->phy_gear)
>> + if (dev_req_params->gear_tx > host->phy_gear) {
>> + u32 old_phy_gear = host->phy_gear;
>> +
>> host->phy_gear = dev_req_params->gear_tx;
>> + dev_req_params->gear_tx = old_phy_gear;
>> + dev_req_params->gear_rx = old_phy_gear;
>> + }
>>
>> /* enable the device ref clock before changing to HS mode */
>> if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
>> --
>> 2.7.4
>>
>

2023-11-28 09:01:33

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 09/10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550



On 11/28/2023 2:47 PM, Manivannan Sadhasivam wrote:
> On Thu, Nov 23, 2023 at 12:46:29AM -0800, Can Guo wrote:
>> On SM8550, two sets of UFS PHY settings are provided, one set is to support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely not
>> blessed by UFS PHY designers.
>>
>> To add HS-G5 support for SM8550, split the two sets of PHY settings into
>> their dedicated overlay tables, only the common parts of the two sets of
>> PHY settings are left in the .tbls.
>>
>> Consider we are going to add even higher gear support in future, to avoid
>> adding more tables with different names, rename the .tbls_hs_g4 and make it
>> an array, a size of 2 is enough as of now.
>>
>> In this case, .tbls alone is not a complete set of PHY settings, so either
>> tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
>> .tbls to become a complete set of PHY settings.
>>
>
> Thanks for the update! This really helps in minimizing the changes for future
> gears.
>
>> Signed-off-by: Can Guo <[email protected]>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
>> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++---
>> 4 files changed, 166 insertions(+), 21 deletions(-)
>>
>>
>
> [...]
>
>> -static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
>> +static bool qmp_ufs_match_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg, int *i)
>> +{
>> + u32 max_gear, floor_max_gear = cfg->max_supported_gear;
>> + bool found = false;
>> + int j;
>> +
>> + for (j = 0; j < NUM_OVERLAY; j ++) {
>> + max_gear = cfg->tbls_hs_overlay[j].max_gear;
>> +
>> + if (max_gear == 0)
>
> Is this condition possible for hs_overlay tables?

Yes, now there are 2 overlays for SM8550, but only one overlay for the
rest targets. For those who has only one overlay, this check fits them.

>
>> + continue;
>> +
>> + /* Direct matching, bail */
>> + if (qmp->submode == max_gear) {
>> + *i = j;
>> + return true;
>> + }
>> +
>> + /* If no direct matching, the lowest gear is the best matching */
>> + if (max_gear < floor_max_gear) {
>
> Can you start the loop from max? If looks odd to set the matching params in the
> first iteration itself and then checking the next one.

OK, will start from j = NUM_VERLAY - 1; in next version. When I wrote
the code, I was not expecting the max is always in the last overlay,
they can come in any orders.

>
>> + *i = j;
>> + found = true;
>> + floor_max_gear = max_gear;
>> + }
>> + }
>> +
>> + return found;
>> +}
>> +
>> +static int qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
>> {
>> + bool apply_overlay;
>> + int i;
>> +
>> + if (qmp->submode > cfg->max_supported_gear || qmp->submode == 0) {
>> + dev_err(qmp->dev, "Invalid PHY submode %u\n", qmp->submode);
>> + return -EINVAL;
>> + }
>
> This check should be moved to qmp_ufs_set_mode().

OK.

Thanks,
Can Guo.

>
> Rest LGTM.
>
> - Mani
>

2023-11-28 09:59:39

by Neil Armstrong

[permalink] [raw]
Subject: Re: [PATCH v5 09/10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550

Hi,

On 23/11/2023 09:46, Can Guo wrote:
> On SM8550, two sets of UFS PHY settings are provided, one set is to support
> HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
> settings are programming different values to different registers, mixing
> the two sets and/or overwriting one set with another set is definitely not
> blessed by UFS PHY designers.
>
> To add HS-G5 support for SM8550, split the two sets of PHY settings into
> their dedicated overlay tables, only the common parts of the two sets of
> PHY settings are left in the .tbls.
>
> Consider we are going to add even higher gear support in future, to avoid
> adding more tables with different names, rename the .tbls_hs_g4 and make it
> an array, a size of 2 is enough as of now.
>
> In this case, .tbls alone is not a complete set of PHY settings, so either
> tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
> .tbls to become a complete set of PHY settings.
>
> Signed-off-by: Can Guo <[email protected]>

Since Vinod has already merged SM8650 UFS PHY support, I'm afraid this
serie will break UFS if the SM8650 UFS tables aren't updated aswell.

Could you confirm if this will be the case ?

Thanks,
Neil


> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
> drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
> .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 174 ++++++++++++++++++---
> 4 files changed, 166 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> index c23d5e4..e563af5 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
> @@ -18,6 +18,7 @@
> #define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
> #define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
> #define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
> +#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
> #define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
> #define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
> #define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
> @@ -27,5 +28,6 @@
> #define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
> #define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
> #define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
> +#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> index f420f8f..ef392ce 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
> @@ -56,6 +56,8 @@
> #define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
> #define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
> #define QSERDES_V6_COM_PLL_IVCO 0xf4
> +#define QSERDES_V6_COM_CMN_IETRIM 0xfc
> +#define QSERDES_V6_COM_CMN_IPTRIM 0x100
> #define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
> #define QSERDES_V6_COM_RESETSM_CNTRL 0x118
> #define QSERDES_V6_COM_LOCK_CMP_EN 0x120
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> index 674f158..48f31c8 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
> @@ -15,8 +15,15 @@
>
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
> #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
> +#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
> #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
> +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
> +#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
> +#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
> #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
> +#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
> +#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
> #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
> @@ -28,6 +35,8 @@
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
> #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
> +#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
> #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
> +#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
>
> #endif
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index ad91f92..29106ec 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -41,6 +41,8 @@
>
> #define PHY_INIT_COMPLETE_TIMEOUT 10000
>
> +#define NUM_OVERLAY 2
> +
> struct qmp_phy_init_tbl {
> unsigned int offset;
> unsigned int val;
> @@ -649,15 +651,22 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
> @@ -666,19 +675,24 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
> QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
> };
>
> -static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
> - QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
> };
>
> static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
> - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
>
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
> @@ -694,16 +708,45 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
> QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
> + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
> +};
> +
> static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
> - QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
> +};
> +
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
> QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
> };
>
> +static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
> + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
> +};
> +
> struct qmp_ufs_offsets {
> u16 serdes;
> u16 pcs;
> @@ -723,6 +766,8 @@ struct qmp_phy_cfg_tbls {
> int rx_num;
> const struct qmp_phy_init_tbl *pcs;
> int pcs_num;
> + /* Maximum supported Gear of this tbls */
> + u32 max_gear;
> };
>
> /* struct qmp_phy_cfg - per-PHY initialization config */
> @@ -730,13 +775,15 @@ struct qmp_phy_cfg {
> int lanes;
>
> const struct qmp_ufs_offsets *offsets;
> + /* Maximum supported Gear of this config */
> + u32 max_supported_gear;
>
> /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
> const struct qmp_phy_cfg_tbls tbls;
> /* Additional sequence for HS Series B */
> const struct qmp_phy_cfg_tbls tbls_hs_b;
> - /* Additional sequence for HS G4 */
> - const struct qmp_phy_cfg_tbls tbls_hs_g4;
> + /* Additional sequence for different HS Gears */
> + const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
>
> /* clock ids to be requested */
> const char * const *clk_list;
> @@ -839,6 +886,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
> .lanes = 1,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = msm8996_ufsphy_serdes,
> @@ -864,6 +912,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -879,13 +928,14 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sm8450_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> @@ -898,6 +948,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -913,13 +964,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -932,6 +984,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = sdm845_ufsphy_serdes,
> @@ -960,6 +1013,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
> .lanes = 1,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = sm6115_ufsphy_serdes,
> @@ -988,6 +1042,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
> .lanes = 1,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G3,
>
> .tbls = {
> .serdes = sdm845_ufsphy_serdes,
> @@ -1016,6 +1071,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8150_ufsphy_serdes,
> @@ -1031,13 +1087,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
> .serdes = sm8150_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8150_ufsphy_hs_g4_tx,
> .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
> .rx = sm8150_ufsphy_hs_g4_rx,
> .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
> .pcs = sm8150_ufsphy_hs_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -1050,6 +1107,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8150_ufsphy_serdes,
> @@ -1065,13 +1123,14 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
> .serdes = sm8150_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8250_ufsphy_hs_g4_tx,
> .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
> .rx = sm8250_ufsphy_hs_g4_rx,
> .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
> .pcs = sm8150_ufsphy_hs_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -1084,6 +1143,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -1099,13 +1159,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> @@ -1118,6 +1179,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets,
> + .max_supported_gear = UFS_HS_G4,
>
> .tbls = {
> .serdes = sm8350_ufsphy_serdes,
> @@ -1133,13 +1195,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
> .serdes = sm8350_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
> },
> - .tbls_hs_g4 = {
> + .tbls_hs_overlay[0] = {
> .tx = sm8350_ufsphy_g4_tx,
> .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
> .rx = sm8350_ufsphy_g4_rx,
> .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
> .pcs = sm8350_ufsphy_g4_pcs,
> .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> },
> .clk_list = sm8450_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
> @@ -1152,6 +1215,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .lanes = 2,
>
> .offsets = &qmp_ufs_offsets_v6,
> + .max_supported_gear = UFS_HS_G5,
>
> .tbls = {
> .serdes = sm8550_ufsphy_serdes,
> @@ -1167,6 +1231,26 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
> .serdes = sm8550_ufsphy_hs_b_serdes,
> .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
> },
> + .tbls_hs_overlay[0] = {
> + .serdes = sm8550_ufsphy_g4_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
> + .tx = sm8550_ufsphy_g4_tx,
> + .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
> + .rx = sm8550_ufsphy_g4_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
> + .pcs = sm8550_ufsphy_g4_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
> + .max_gear = UFS_HS_G4,
> + },
> + .tbls_hs_overlay[1] = {
> + .serdes = sm8550_ufsphy_g5_serdes,
> + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
> + .rx = sm8550_ufsphy_g5_rx,
> + .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
> + .pcs = sm8550_ufsphy_g5_pcs,
> + .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
> + .max_gear = UFS_HS_G5,
> + },
> .clk_list = sdm845_ufs_phy_clk_l,
> .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
> .vreg_list = qmp_phy_vreg_l,
> @@ -1229,17 +1313,63 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
> qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
> }
>
> -static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> +static bool qmp_ufs_match_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg, int *i)
> +{
> + u32 max_gear, floor_max_gear = cfg->max_supported_gear;
> + bool found = false;
> + int j;
> +
> + for (j = 0; j < NUM_OVERLAY; j ++) {
> + max_gear = cfg->tbls_hs_overlay[j].max_gear;
> +
> + if (max_gear == 0)
> + continue;
> +
> + /* Direct matching, bail */
> + if (qmp->submode == max_gear) {
> + *i = j;
> + return true;
> + }
> +
> + /* If no direct matching, the lowest gear is the best matching */
> + if (max_gear < floor_max_gear) {
> + *i = j;
> + found = true;
> + floor_max_gear = max_gear;
> + }
> + }
> +
> + return found;
> +}
> +
> +static int qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
> {
> + bool apply_overlay;
> + int i;
> +
> + if (qmp->submode > cfg->max_supported_gear || qmp->submode == 0) {
> + dev_err(qmp->dev, "Invalid PHY submode %u\n", qmp->submode);
> + return -EINVAL;
> + }
> +
> + apply_overlay = qmp_ufs_match_gear_overlay(qmp, cfg, &i);
> +
> qmp_ufs_serdes_init(qmp, &cfg->tbls);
> + if (apply_overlay)
> + qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
> +
> if (qmp->mode == PHY_MODE_UFS_HS_B)
> qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
> +
> qmp_ufs_lanes_init(qmp, &cfg->tbls);
> - if (qmp->submode == UFS_HS_G4)
> - qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
> + if (apply_overlay)
> + qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
> +
> qmp_ufs_pcs_init(qmp, &cfg->tbls);
> - if (qmp->submode == UFS_HS_G4)
> - qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
> + if (apply_overlay)
> + qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
> +
> + return 0;
> }
>
> static int qmp_ufs_com_init(struct qmp_ufs *qmp)
> @@ -1331,7 +1461,9 @@ static int qmp_ufs_power_on(struct phy *phy)
> unsigned int val;
> int ret;
>
> - qmp_ufs_init_registers(qmp, cfg);
> + ret = qmp_ufs_init_registers(qmp, cfg);
> + if (ret)
> + return ret;
>
> ret = reset_control_deassert(qmp->ufs_reset);
> if (ret)

2023-11-28 10:04:42

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 09/10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550

Hi Neil,

On 11/28/2023 5:59 PM, [email protected] wrote:
> Hi,
>
> On 23/11/2023 09:46, Can Guo wrote:
>> On SM8550, two sets of UFS PHY settings are provided, one set is to
>> support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets
>> of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely
>> not
>> blessed by UFS PHY designers.
>>
>> To add HS-G5 support for SM8550, split the two sets of PHY settings into
>> their dedicated overlay tables, only the common parts of the two sets of
>> PHY settings are left in the .tbls.
>>
>> Consider we are going to add even higher gear support in future, to avoid
>> adding more tables with different names, rename the .tbls_hs_g4 and
>> make it
>> an array, a size of 2 is enough as of now.
>>
>> In this case, .tbls alone is not a complete set of PHY settings, so
>> either
>> tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
>> .tbls to become a complete set of PHY settings.
>>
>> Signed-off-by: Can Guo <[email protected]>
>
> Since Vinod has already merged SM8650 UFS PHY support, I'm afraid this
> serie will break UFS if the SM8650 UFS tables aren't updated aswell.
>
> Could you confirm if this will be the case ?

Because this change modifies data struct, it would be caught during
compiliation stage even if this change applies cleanly, hence it won't
break UFS.

Thanks,
Can Guo.

>
> Thanks,
> Neil
>
>

2023-11-28 10:52:59

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 04/10] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear

On Tue, Nov 28, 2023 at 04:05:59PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/28/2023 1:45 PM, Manivannan Sadhasivam wrote:
> > On Thu, Nov 23, 2023 at 12:46:24AM -0800, Can Guo wrote:
> > > In the dual init scenario, the initial PHY gear is set to HS-G2, and the
> > > first Power Mode Change (PMC) is meant to find the best matching PHY gear
> > > for the 2nd init. However, for the first PMC, if the negotiated gear (say
> > > HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to
> > > the negotiated gear happen, because the programmed UFS PHY settings may not
> > > support the negotiated gear. Fix it by overwriting the negotiated gear with
> > > the PHY gear.
> > >
> >
> > I don't quite understand this patch. If the phy_gear is G2 initially and the
> > negotiated gear is G4, then as per this change,
> >
> > phy_gear = G4;
> > negotiated gear = G2;
> >
> > Could you please explain how this make sense?
>
> phy_gear was G2 (in the beginning) and just now changed to G4, but the PHY
> settings programmed in the beginning can only support no-G4 (not G4).
> Without this change, as the negotiated gear is G4, the power mode change is
> going to put UFS at HS-G4 mode, but the PHY settings programmed is no-G4.

But we are going to reinit the PHY anyway, isn't it?

> This change is to limit the negotiated gear to HS-G2 for the 1st init. In
> the 2nd init, as the new PHY gear is G4, G4 PHY settings would be
> programmed, it'd be safe to put the UFS at HS-G4 mode.
>

Why do we need to limit it since we already have the logic in place to set
whatever gear mode applicable for 1st init?

- Mani

> Thanks,
> Can Guo.
> >
> > - Mani
> >
> > > Signed-off-by: Can Guo <[email protected]>
> > > ---
> > > drivers/ufs/host/ufs-qcom.c | 7 ++++++-
> > > 1 file changed, 6 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > > index cc0eb37..d4edf58 100644
> > > --- a/drivers/ufs/host/ufs-qcom.c
> > > +++ b/drivers/ufs/host/ufs-qcom.c
> > > @@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> > > * because, the PHY gear settings are backwards compatible and we only need to
> > > * change the PHY gear settings while scaling to higher gears.
> > > */
> > > - if (dev_req_params->gear_tx > host->phy_gear)
> > > + if (dev_req_params->gear_tx > host->phy_gear) {
> > > + u32 old_phy_gear = host->phy_gear;
> > > +
> > > host->phy_gear = dev_req_params->gear_tx;
> > > + dev_req_params->gear_tx = old_phy_gear;
> > > + dev_req_params->gear_rx = old_phy_gear;
> > > + }
> > > /* enable the device ref clock before changing to HS mode */
> > > if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
> > > --
> > > 2.7.4
> > >
> >

--
மணிவண்ணன் சதாசிவம்

2023-11-28 10:55:23

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 06/10] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5

On Tue, Nov 28, 2023 at 03:48:02PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/28/2023 1:55 PM, Manivannan Sadhasivam wrote:
> > On Thu, Nov 23, 2023 at 12:46:26AM -0800, Can Guo wrote:
> > > Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
> > > HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
> > > to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
> > >
> > > Signed-off-by: Can Guo <[email protected]>
> >
> > Reviewed-by: Manivannan Sadhasivam <[email protected]>
> >
> > One question below...
> >
> > > ---
> > > drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
> > > 1 file changed, 17 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > > index 9613ad9..6756f8d 100644
> > > --- a/drivers/ufs/host/ufs-qcom.c
> > > +++ b/drivers/ufs/host/ufs-qcom.c
> > > @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
> > > static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> > > {
> > > struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> > > + struct ufs_host_params *host_params = &host->host_params;
> > > struct phy *phy = host->generic_phy;
> > > + enum phy_mode mode;
> > > int ret;
> > > + /*
> > > + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
> > > + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
> > > + * so that the subsequent power mode change shall stick to Rate-A.
> > > + */
> > > + if (host->hw_ver.major == 0x5) {
> > > + if (host->phy_gear == UFS_HS_G5)
> > > + host_params->hs_rate = PA_HS_MODE_A;
> > > + else
> > > + host_params->hs_rate = PA_HS_MODE_B;
> >
> > Is this 'else' part really needed? Since there wouldn't be any 2nd init, I think
> > we can skip that.
>
> We need it because, even there is only one init, if a UFS3.1 device is
> attached, phy_gear is given as UFS_HS_G4 in ufs_qcom_set_phy_gear(), hence
> we need to put the UFS at HS-G4 Rate B, not Rate A.
>

But the default hs_rate is PA_HS_MODE_B only and the else condition would be not
needed for the 1st init.

- Mani

> Thanks,
> Can Guo.
>
> >
> > - Mani
> >
> > > + }
> > > +
> > > + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
> > > +
> > > /* Reset UFS Host Controller and PHY */
> > > ret = ufs_qcom_host_reset(hba);
> > > if (ret)
> > > @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> > > return ret;
> > > }
> > > - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
> > > + phy_set_mode_ext(phy, mode, host->phy_gear);
> > > /* power on phy - start serdes and phy's power and clocks */
> > > ret = phy_power_on(phy);
> > > --
> > > 2.7.4
> > >
> >

--
மணிவண்ணன் சதாசிவம்

2023-11-28 10:59:25

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 07/10] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer

On Tue, Nov 28, 2023 at 03:58:42PM +0800, Can Guo wrote:
> Hi Mani,
>
> On 11/28/2023 2:00 PM, Manivannan Sadhasivam wrote:
> > On Thu, Nov 23, 2023 at 12:46:27AM -0800, Can Guo wrote:
> > > Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
> > >
> >
> > MAX_GEAR will be used for hosts with hw_ver.major >= 4
>
> I put it > 5 because I am not intent to touch any old targets which has
> proven working fine with starting with PHY gear HS_G2. If I put it >= 4,
> there would be many targets impacted by this change. I need to go back and
> test those platforms (HW ver == 4).
>

This assumption will make the code hard to maintain. I think if you happen to
test it on atleast a couple of old targets it should be good since I do not see
how others can fail.

- Mani

> Thanks,
> Can Guo.
>
> >
> > > This patch is not changing any functionalities or logic but only a
> > > preparation patch for the next patch in this series.
> > >
> > > Signed-off-by: Can Guo <[email protected]>
> > > ---
> > > drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++------
> > > 1 file changed, 15 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > > index 6756f8d..7bbccf4 100644
> > > --- a/drivers/ufs/host/ufs-qcom.c
> > > +++ b/drivers/ufs/host/ufs-qcom.c
> > > @@ -1067,6 +1067,20 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
> > > hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
> > > }
> > > +static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
> > > +{
> > > + struct ufs_host_params *host_params = &host->host_params;
> > > +
> > > + host->phy_gear = host_params->hs_tx_gear;
> > > +
> > > + /*
> > > + * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> > > + * Switching to max gear will be performed during reinit if supported.
> >
> > You need to reword this comment too.
> >
> > > + */
> > > + if (host->hw_ver.major < 0x5)
> >
> > As I mentioned above, MAX_GEAR will be used if hw_ver.major is >=4 in
> > ufs_qcom_get_hs_gear(). So this check should be (< 0x4).
> >
> > - Mani
> >
> > > + host->phy_gear = UFS_HS_G2;
> > > +}
> > > +
> > > static void ufs_qcom_set_host_params(struct ufs_hba *hba)
> > > {
> > > struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> > > @@ -1303,6 +1317,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> > > ufs_qcom_set_caps(hba);
> > > ufs_qcom_advertise_quirks(hba);
> > > ufs_qcom_set_host_params(hba);
> > > + ufs_qcom_set_phy_gear(host);
> > > err = ufs_qcom_ice_init(host);
> > > if (err)
> > > @@ -1320,12 +1335,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> > > dev_warn(dev, "%s: failed to configure the testbus %d\n",
> > > __func__, err);
> > > - /*
> > > - * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> > > - * Switching to max gear will be performed during reinit if supported.
> > > - */
> > > - host->phy_gear = UFS_HS_G2;
> > > -
> > > return 0;
> > > out_variant_clear:
> > > --
> > > 2.7.4
> > >
> >

--
மணிவண்ணன் சதாசிவம்

2023-11-28 11:01:19

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 06/10] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5



On 11/28/2023 6:55 PM, Manivannan Sadhasivam wrote:
> On Tue, Nov 28, 2023 at 03:48:02PM +0800, Can Guo wrote:
>> Hi Mani,
>>
>> On 11/28/2023 1:55 PM, Manivannan Sadhasivam wrote:
>>> On Thu, Nov 23, 2023 at 12:46:26AM -0800, Can Guo wrote:
>>>> Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
>>>> HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
>>>> to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
>>>>
>>>> Signed-off-by: Can Guo <[email protected]>
>>>
>>> Reviewed-by: Manivannan Sadhasivam <[email protected]>
>>>
>>> One question below...
>>>
>>>> ---
>>>> drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
>>>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>>>> index 9613ad9..6756f8d 100644
>>>> --- a/drivers/ufs/host/ufs-qcom.c
>>>> +++ b/drivers/ufs/host/ufs-qcom.c
>>>> @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
>>>> static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>>>> {
>>>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>>>> + struct ufs_host_params *host_params = &host->host_params;
>>>> struct phy *phy = host->generic_phy;
>>>> + enum phy_mode mode;
>>>> int ret;
>>>> + /*
>>>> + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
>>>> + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
>>>> + * so that the subsequent power mode change shall stick to Rate-A.
>>>> + */
>>>> + if (host->hw_ver.major == 0x5) {
>>>> + if (host->phy_gear == UFS_HS_G5)
>>>> + host_params->hs_rate = PA_HS_MODE_A;
>>>> + else
>>>> + host_params->hs_rate = PA_HS_MODE_B;
>>>
>>> Is this 'else' part really needed? Since there wouldn't be any 2nd init, I think
>>> we can skip that.
>>
>> We need it because, even there is only one init, if a UFS3.1 device is
>> attached, phy_gear is given as UFS_HS_G4 in ufs_qcom_set_phy_gear(), hence
>> we need to put the UFS at HS-G4 Rate B, not Rate A.
>>
>
> But the default hs_rate is PA_HS_MODE_B only and the else condition would be not
> needed for the 1st init.

You are right, but still we need this in case the UFS device version is
not populated, meaning dual init can also happen to SM8550. We need to
apply the right hs_rate in case the 2nd init asks for HS_G4.

Thanks,
Can Guo.

>
> - Mani
>
>> Thanks,
>> Can Guo.
>>
>>>
>>> - Mani
>>>
>>>> + }
>>>> +
>>>> + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
>>>> +
>>>> /* Reset UFS Host Controller and PHY */
>>>> ret = ufs_qcom_host_reset(hba);
>>>> if (ret)
>>>> @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
>>>> return ret;
>>>> }
>>>> - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
>>>> + phy_set_mode_ext(phy, mode, host->phy_gear);
>>>> /* power on phy - start serdes and phy's power and clocks */
>>>> ret = phy_power_on(phy);
>>>> --
>>>> 2.7.4
>>>>
>>>
>

2023-11-28 11:02:21

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 07/10] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer



On 11/28/2023 6:59 PM, Manivannan Sadhasivam wrote:
> On Tue, Nov 28, 2023 at 03:58:42PM +0800, Can Guo wrote:
>> Hi Mani,
>>
>> On 11/28/2023 2:00 PM, Manivannan Sadhasivam wrote:
>>> On Thu, Nov 23, 2023 at 12:46:27AM -0800, Can Guo wrote:
>>>> Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
>>>>
>>>
>>> MAX_GEAR will be used for hosts with hw_ver.major >= 4
>>
>> I put it > 5 because I am not intent to touch any old targets which has
>> proven working fine with starting with PHY gear HS_G2. If I put it >= 4,
>> there would be many targets impacted by this change. I need to go back and
>> test those platforms (HW ver == 4).
>>
>
> This assumption will make the code hard to maintain. I think if you happen to
> test it on atleast a couple of old targets it should be good since I do not see
> how others can fail.

Point taken. I will put it >= 4 in next version and test it on platforms
like SM8350 and SM8450.

Thanks,
Can Guo.

>
> - Mani
>
>> Thanks,
>> Can Guo.
>>
>>>
>>>> This patch is not changing any functionalities or logic but only a
>>>> preparation patch for the next patch in this series.
>>>>
>>>> Signed-off-by: Can Guo <[email protected]>
>>>> ---
>>>> drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++------
>>>> 1 file changed, 15 insertions(+), 6 deletions(-)
>>>>
>>>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>>>> index 6756f8d..7bbccf4 100644
>>>> --- a/drivers/ufs/host/ufs-qcom.c
>>>> +++ b/drivers/ufs/host/ufs-qcom.c
>>>> @@ -1067,6 +1067,20 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
>>>> hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
>>>> }
>>>> +static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
>>>> +{
>>>> + struct ufs_host_params *host_params = &host->host_params;
>>>> +
>>>> + host->phy_gear = host_params->hs_tx_gear;
>>>> +
>>>> + /*
>>>> + * Power up the PHY using the minimum supported gear (UFS_HS_G2).
>>>> + * Switching to max gear will be performed during reinit if supported.
>>>
>>> You need to reword this comment too.
>>>
>>>> + */
>>>> + if (host->hw_ver.major < 0x5)
>>>
>>> As I mentioned above, MAX_GEAR will be used if hw_ver.major is >=4 in
>>> ufs_qcom_get_hs_gear(). So this check should be (< 0x4).
>>>
>>> - Mani
>>>
>>>> + host->phy_gear = UFS_HS_G2;
>>>> +}
>>>> +
>>>> static void ufs_qcom_set_host_params(struct ufs_hba *hba)
>>>> {
>>>> struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>>>> @@ -1303,6 +1317,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>>>> ufs_qcom_set_caps(hba);
>>>> ufs_qcom_advertise_quirks(hba);
>>>> ufs_qcom_set_host_params(hba);
>>>> + ufs_qcom_set_phy_gear(host);
>>>> err = ufs_qcom_ice_init(host);
>>>> if (err)
>>>> @@ -1320,12 +1335,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
>>>> dev_warn(dev, "%s: failed to configure the testbus %d\n",
>>>> __func__, err);
>>>> - /*
>>>> - * Power up the PHY using the minimum supported gear (UFS_HS_G2).
>>>> - * Switching to max gear will be performed during reinit if supported.
>>>> - */
>>>> - host->phy_gear = UFS_HS_G2;
>>>> -
>>>> return 0;
>>>> out_variant_clear:
>>>> --
>>>> 2.7.4
>>>>
>>>
>

2023-11-28 11:04:38

by Can Guo

[permalink] [raw]
Subject: Re: [PATCH v5 04/10] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear



On 11/28/2023 6:52 PM, Manivannan Sadhasivam wrote:
> On Tue, Nov 28, 2023 at 04:05:59PM +0800, Can Guo wrote:
>> Hi Mani,
>>
>> On 11/28/2023 1:45 PM, Manivannan Sadhasivam wrote:
>>> On Thu, Nov 23, 2023 at 12:46:24AM -0800, Can Guo wrote:
>>>> In the dual init scenario, the initial PHY gear is set to HS-G2, and the
>>>> first Power Mode Change (PMC) is meant to find the best matching PHY gear
>>>> for the 2nd init. However, for the first PMC, if the negotiated gear (say
>>>> HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to
>>>> the negotiated gear happen, because the programmed UFS PHY settings may not
>>>> support the negotiated gear. Fix it by overwriting the negotiated gear with
>>>> the PHY gear.
>>>>
>>>
>>> I don't quite understand this patch. If the phy_gear is G2 initially and the
>>> negotiated gear is G4, then as per this change,
>>>
>>> phy_gear = G4;
>>> negotiated gear = G2;
>>>
>>> Could you please explain how this make sense?
>>
>> phy_gear was G2 (in the beginning) and just now changed to G4, but the PHY
>> settings programmed in the beginning can only support no-G4 (not G4).
>> Without this change, as the negotiated gear is G4, the power mode change is
>> going to put UFS at HS-G4 mode, but the PHY settings programmed is no-G4.
>
> But we are going to reinit the PHY anyway, isn't it?

We are power mode changing to HS-G4 with no-G4 PHY settings programmed,
the power mode change operation, in the 1st init, may immediately cause
UIC errors and lead to probe fail. We are not seeing issues as of now,
maybe because the amount of HW used for testing is not large enough.

This change is not really related to this specific series, I can remove
it in next version.

Thanks,
Can Guo.

>
>> This change is to limit the negotiated gear to HS-G2 for the 1st init. In
>> the 2nd init, as the new PHY gear is G4, G4 PHY settings would be
>> programmed, it'd be safe to put the UFS at HS-G4 mode.
>>
>
> Why do we need to limit it since we already have the logic in place to set
> whatever gear mode applicable for 1st init?
>
> - Mani
>
>> Thanks,
>> Can Guo.
>>>
>>> - Mani
>>>
>>>> Signed-off-by: Can Guo <[email protected]>
>>>> ---
>>>> drivers/ufs/host/ufs-qcom.c | 7 ++++++-
>>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>>>> index cc0eb37..d4edf58 100644
>>>> --- a/drivers/ufs/host/ufs-qcom.c
>>>> +++ b/drivers/ufs/host/ufs-qcom.c
>>>> @@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
>>>> * because, the PHY gear settings are backwards compatible and we only need to
>>>> * change the PHY gear settings while scaling to higher gears.
>>>> */
>>>> - if (dev_req_params->gear_tx > host->phy_gear)
>>>> + if (dev_req_params->gear_tx > host->phy_gear) {
>>>> + u32 old_phy_gear = host->phy_gear;
>>>> +
>>>> host->phy_gear = dev_req_params->gear_tx;
>>>> + dev_req_params->gear_tx = old_phy_gear;
>>>> + dev_req_params->gear_rx = old_phy_gear;
>>>> + }
>>>> /* enable the device ref clock before changing to HS mode */
>>>> if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
>>>> --
>>>> 2.7.4
>>>>
>>>
>

2023-11-28 11:21:37

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 04/10] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear

On Tue, Nov 28, 2023 at 07:03:41PM +0800, Can Guo wrote:
>
>
> On 11/28/2023 6:52 PM, Manivannan Sadhasivam wrote:
> > On Tue, Nov 28, 2023 at 04:05:59PM +0800, Can Guo wrote:
> > > Hi Mani,
> > >
> > > On 11/28/2023 1:45 PM, Manivannan Sadhasivam wrote:
> > > > On Thu, Nov 23, 2023 at 12:46:24AM -0800, Can Guo wrote:
> > > > > In the dual init scenario, the initial PHY gear is set to HS-G2, and the
> > > > > first Power Mode Change (PMC) is meant to find the best matching PHY gear
> > > > > for the 2nd init. However, for the first PMC, if the negotiated gear (say
> > > > > HS-G4) is higher than the initial PHY gear, we cannot go ahead let PMC to
> > > > > the negotiated gear happen, because the programmed UFS PHY settings may not
> > > > > support the negotiated gear. Fix it by overwriting the negotiated gear with
> > > > > the PHY gear.
> > > > >
> > > >
> > > > I don't quite understand this patch. If the phy_gear is G2 initially and the
> > > > negotiated gear is G4, then as per this change,
> > > >
> > > > phy_gear = G4;
> > > > negotiated gear = G2;
> > > >
> > > > Could you please explain how this make sense?
> > >
> > > phy_gear was G2 (in the beginning) and just now changed to G4, but the PHY
> > > settings programmed in the beginning can only support no-G4 (not G4).
> > > Without this change, as the negotiated gear is G4, the power mode change is
> > > going to put UFS at HS-G4 mode, but the PHY settings programmed is no-G4.
> >
> > But we are going to reinit the PHY anyway, isn't it?
>
> We are power mode changing to HS-G4 with no-G4 PHY settings programmed, the
> power mode change operation, in the 1st init, may immediately cause UIC
> errors and lead to probe fail. We are not seeing issues as of now, maybe
> because the amount of HW used for testing is not large enough.
>

I'm not sure what you are saying is what happening. Because, if we use the
incompatible gear setting, we should immediately see the UIC error.

> This change is not really related to this specific series, I can remove it
> in next version.
>

Please do so. This needs to be reviewed separately.

- Mani

> Thanks,
> Can Guo.
>
> >
> > > This change is to limit the negotiated gear to HS-G2 for the 1st init. In
> > > the 2nd init, as the new PHY gear is G4, G4 PHY settings would be
> > > programmed, it'd be safe to put the UFS at HS-G4 mode.
> > >
> >
> > Why do we need to limit it since we already have the logic in place to set
> > whatever gear mode applicable for 1st init?
> >
> > - Mani
> >
> > > Thanks,
> > > Can Guo.
> > > >
> > > > - Mani
> > > >
> > > > > Signed-off-by: Can Guo <[email protected]>
> > > > > ---
> > > > > drivers/ufs/host/ufs-qcom.c | 7 ++++++-
> > > > > 1 file changed, 6 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > > > > index cc0eb37..d4edf58 100644
> > > > > --- a/drivers/ufs/host/ufs-qcom.c
> > > > > +++ b/drivers/ufs/host/ufs-qcom.c
> > > > > @@ -920,8 +920,13 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
> > > > > * because, the PHY gear settings are backwards compatible and we only need to
> > > > > * change the PHY gear settings while scaling to higher gears.
> > > > > */
> > > > > - if (dev_req_params->gear_tx > host->phy_gear)
> > > > > + if (dev_req_params->gear_tx > host->phy_gear) {
> > > > > + u32 old_phy_gear = host->phy_gear;
> > > > > +
> > > > > host->phy_gear = dev_req_params->gear_tx;
> > > > > + dev_req_params->gear_tx = old_phy_gear;
> > > > > + dev_req_params->gear_rx = old_phy_gear;
> > > > > + }
> > > > > /* enable the device ref clock before changing to HS mode */
> > > > > if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
> > > > > --
> > > > > 2.7.4
> > > > >
> > > >
> >

--
மணிவண்ணன் சதாசிவம்

2023-11-28 11:23:10

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 07/10] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer

On Tue, Nov 28, 2023 at 07:01:27PM +0800, Can Guo wrote:
>
>
> On 11/28/2023 6:59 PM, Manivannan Sadhasivam wrote:
> > On Tue, Nov 28, 2023 at 03:58:42PM +0800, Can Guo wrote:
> > > Hi Mani,
> > >
> > > On 11/28/2023 2:00 PM, Manivannan Sadhasivam wrote:
> > > > On Thu, Nov 23, 2023 at 12:46:27AM -0800, Can Guo wrote:
> > > > > Set the initial PHY gear to max HS gear for hosts with HW ver 5 and newer.
> > > > >
> > > >
> > > > MAX_GEAR will be used for hosts with hw_ver.major >= 4
> > >
> > > I put it > 5 because I am not intent to touch any old targets which has
> > > proven working fine with starting with PHY gear HS_G2. If I put it >= 4,
> > > there would be many targets impacted by this change. I need to go back and
> > > test those platforms (HW ver == 4).
> > >
> >
> > This assumption will make the code hard to maintain. I think if you happen to
> > test it on atleast a couple of old targets it should be good since I do not see
> > how others can fail.
>
> Point taken. I will put it >= 4 in next version and test it on platforms
> like SM8350 and SM8450.
>

Appreciated, thanks!

- Mani

> Thanks,
> Can Guo.
>
> >
> > - Mani
> >
> > > Thanks,
> > > Can Guo.
> > >
> > > >
> > > > > This patch is not changing any functionalities or logic but only a
> > > > > preparation patch for the next patch in this series.
> > > > >
> > > > > Signed-off-by: Can Guo <[email protected]>
> > > > > ---
> > > > > drivers/ufs/host/ufs-qcom.c | 21 +++++++++++++++------
> > > > > 1 file changed, 15 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > > > > index 6756f8d..7bbccf4 100644
> > > > > --- a/drivers/ufs/host/ufs-qcom.c
> > > > > +++ b/drivers/ufs/host/ufs-qcom.c
> > > > > @@ -1067,6 +1067,20 @@ static void ufs_qcom_advertise_quirks(struct ufs_hba *hba)
> > > > > hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH;
> > > > > }
> > > > > +static void ufs_qcom_set_phy_gear(struct ufs_qcom_host *host)
> > > > > +{
> > > > > + struct ufs_host_params *host_params = &host->host_params;
> > > > > +
> > > > > + host->phy_gear = host_params->hs_tx_gear;
> > > > > +
> > > > > + /*
> > > > > + * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> > > > > + * Switching to max gear will be performed during reinit if supported.
> > > >
> > > > You need to reword this comment too.
> > > >
> > > > > + */
> > > > > + if (host->hw_ver.major < 0x5)
> > > >
> > > > As I mentioned above, MAX_GEAR will be used if hw_ver.major is >=4 in
> > > > ufs_qcom_get_hs_gear(). So this check should be (< 0x4).
> > > >
> > > > - Mani
> > > >
> > > > > + host->phy_gear = UFS_HS_G2;
> > > > > +}
> > > > > +
> > > > > static void ufs_qcom_set_host_params(struct ufs_hba *hba)
> > > > > {
> > > > > struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> > > > > @@ -1303,6 +1317,7 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> > > > > ufs_qcom_set_caps(hba);
> > > > > ufs_qcom_advertise_quirks(hba);
> > > > > ufs_qcom_set_host_params(hba);
> > > > > + ufs_qcom_set_phy_gear(host);
> > > > > err = ufs_qcom_ice_init(host);
> > > > > if (err)
> > > > > @@ -1320,12 +1335,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
> > > > > dev_warn(dev, "%s: failed to configure the testbus %d\n",
> > > > > __func__, err);
> > > > > - /*
> > > > > - * Power up the PHY using the minimum supported gear (UFS_HS_G2).
> > > > > - * Switching to max gear will be performed during reinit if supported.
> > > > > - */
> > > > > - host->phy_gear = UFS_HS_G2;
> > > > > -
> > > > > return 0;
> > > > > out_variant_clear:
> > > > > --
> > > > > 2.7.4
> > > > >
> > > >
> >

--
மணிவண்ணன் சதாசிவம்

2023-11-28 11:24:47

by Manivannan Sadhasivam

[permalink] [raw]
Subject: Re: [PATCH v5 06/10] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5

On Tue, Nov 28, 2023 at 06:59:39PM +0800, Can Guo wrote:
>
>
> On 11/28/2023 6:55 PM, Manivannan Sadhasivam wrote:
> > On Tue, Nov 28, 2023 at 03:48:02PM +0800, Can Guo wrote:
> > > Hi Mani,
> > >
> > > On 11/28/2023 1:55 PM, Manivannan Sadhasivam wrote:
> > > > On Thu, Nov 23, 2023 at 12:46:26AM -0800, Can Guo wrote:
> > > > > Qcom UFS hosts, with HW ver 5, can only support up to HS-G5 Rate-A due to
> > > > > HW limitations. If the HS-G5 PHY gear is used, update host_params->hs_rate
> > > > > to Rate-A, so that the subsequent power mode changes shall stick to Rate-A.
> > > > >
> > > > > Signed-off-by: Can Guo <[email protected]>
> > > >
> > > > Reviewed-by: Manivannan Sadhasivam <[email protected]>
> > > >
> > > > One question below...
> > > >
> > > > > ---
> > > > > drivers/ufs/host/ufs-qcom.c | 18 +++++++++++++++++-
> > > > > 1 file changed, 17 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
> > > > > index 9613ad9..6756f8d 100644
> > > > > --- a/drivers/ufs/host/ufs-qcom.c
> > > > > +++ b/drivers/ufs/host/ufs-qcom.c
> > > > > @@ -442,9 +442,25 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
> > > > > static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> > > > > {
> > > > > struct ufs_qcom_host *host = ufshcd_get_variant(hba);
> > > > > + struct ufs_host_params *host_params = &host->host_params;
> > > > > struct phy *phy = host->generic_phy;
> > > > > + enum phy_mode mode;
> > > > > int ret;
> > > > > + /*
> > > > > + * HW ver 5 can only support up to HS-G5 Rate-A due to HW limitations.
> > > > > + * If the HS-G5 PHY gear is used, update host_params->hs_rate to Rate-A,
> > > > > + * so that the subsequent power mode change shall stick to Rate-A.
> > > > > + */
> > > > > + if (host->hw_ver.major == 0x5) {
> > > > > + if (host->phy_gear == UFS_HS_G5)
> > > > > + host_params->hs_rate = PA_HS_MODE_A;
> > > > > + else
> > > > > + host_params->hs_rate = PA_HS_MODE_B;
> > > >
> > > > Is this 'else' part really needed? Since there wouldn't be any 2nd init, I think
> > > > we can skip that.
> > >
> > > We need it because, even there is only one init, if a UFS3.1 device is
> > > attached, phy_gear is given as UFS_HS_G4 in ufs_qcom_set_phy_gear(), hence
> > > we need to put the UFS at HS-G4 Rate B, not Rate A.
> > >
> >
> > But the default hs_rate is PA_HS_MODE_B only and the else condition would be not
> > needed for the 1st init.
>
> You are right, but still we need this in case the UFS device version is not
> populated, meaning dual init can also happen to SM8550. We need to apply the
> right hs_rate in case the 2nd init asks for HS_G4.
>

Hmm, yeah I missed that corner case. This is fine.

- Mani

> Thanks,
> Can Guo.
>
> >
> > - Mani
> >
> > > Thanks,
> > > Can Guo.
> > >
> > > >
> > > > - Mani
> > > >
> > > > > + }
> > > > > +
> > > > > + mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A;
> > > > > +
> > > > > /* Reset UFS Host Controller and PHY */
> > > > > ret = ufs_qcom_host_reset(hba);
> > > > > if (ret)
> > > > > @@ -459,7 +475,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
> > > > > return ret;
> > > > > }
> > > > > - phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->phy_gear);
> > > > > + phy_set_mode_ext(phy, mode, host->phy_gear);
> > > > > /* power on phy - start serdes and phy's power and clocks */
> > > > > ret = phy_power_on(phy);
> > > > > --
> > > > > 2.7.4
> > > > >
> > > >
> >

--
மணிவண்ணன் சதாசிவம்