LinuxLists.cc - [PATCH 00/13]Update the icicle kit device tree

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Subject: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts

From: Ivan Griffin <[email protected]>

Provide named identifiers for device tree for RISC-V interrupts.

Licensed under GPL and MIT, as this file may be useful to any OS that
uses device tree.

Signed-off-by: Ivan Griffin <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
.../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h

diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
new file mode 100644
index 000000000000..e1c32f6090ac
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/riscv-hart.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2021 Microchip Technology Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
+
+#define HART_INT_U_SOFT 0
+#define HART_INT_S_SOFT 1
+#define HART_INT_M_SOFT 3
+#define HART_INT_U_TIMER 4
+#define HART_INT_S_TIMER 5
+#define HART_INT_M_TIMER 7
+#define HART_INT_U_EXT 8
+#define HART_INT_S_EXT 9
+#define HART_INT_M_EXT 11
+
+#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
--
2.33.1

2021-11-08 15:07:03

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Subject: [PATCH 02/13] dt-bindings: interrupt-controller: add defines for mpfs-plic

From: Ivan Griffin <[email protected]>

Add device tree bindings for the Microchip Polarfire Soc interrupt
controller

Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Ivan Griffin <[email protected]>
---
.../microchip,mpfs-plic.h | 199 ++++++++++++++++++
1 file changed, 199 insertions(+)
create mode 100644 include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h

diff --git a/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h
new file mode 100644
index 000000000000..81c8cd02abd8
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2021 Microchip Technology Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
+
+#define PLIC_INT_INVALID 0
+#define PLIC_INT_L2_METADATA_CORR 1
+#define PLIC_INT_L2_METADAT_UNCORR 2
+#define PLIC_INT_L2_DATA_CORR 3
+#define PLIC_INT_L2_DATA_UNCORR 4
+#define PLIC_INT_DMA_CH0_DONE 5
+#define PLIC_INT_DMA_CH0_ERR 6
+#define PLIC_INT_DMA_CH1_DONE 7
+#define PLIC_INT_DMA_CH1_ERR 8
+#define PLIC_INT_DMA_CH2_DONE 9
+#define PLIC_INT_DMA_CH2_ERR 10
+#define PLIC_INT_DMA_CH3_DONE 11
+#define PLIC_INT_DMA_CH3_ERR 12
+
+#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13
+#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14
+#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15
+#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16
+#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17
+#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18
+#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19
+#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20
+#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21
+#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22
+#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23
+#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24
+#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25
+#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26
+#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27
+#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28
+#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29
+#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30
+#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31
+#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32
+#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33
+#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34
+#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35
+#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36
+#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37
+#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38
+#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39
+#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40
+#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41
+#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42
+#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43
+#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44
+#define PLIC_INT_GPIO1_BIT18 45
+#define PLIC_INT_GPIO1_BIT19 46
+#define PLIC_INT_GPIO1_BIT20 47
+#define PLIC_INT_GPIO1_BIT21 48
+#define PLIC_INT_GPIO1_BIT22 49
+#define PLIC_INT_GPIO1_BIT23 50
+#define PLIC_INT_GPIO0_NON_DIRECT 51
+#define PLIC_INT_GPIO1_NON_DIRECT 52
+#define PLIC_INT_GPIO2_NON_DIRECT 53
+#define PLIC_INT_SPI0 54
+#define PLIC_INT_SPI1 55
+#define PLIC_INT_CAN0 56
+#define PLIC_INT_CAN1 57
+#define PLIC_INT_I2C0_MAIN 58
+#define PLIC_INT_I2C0_ALERT 59
+#define PLIC_INT_I2C0_SUS 60
+#define PLIC_INT_I2C1_MAIN 61
+#define PLIC_INT_I2C1_ALERT 62
+#define PLIC_INT_I2C1_SUS 63
+#define PLIC_INT_MAC0_INT 64
+#define PLIC_INT_MAC0_QUEUE1 65
+#define PLIC_INT_MAC0_QUEUE2 66
+#define PLIC_INT_MAC0_QUEUE3 67
+#define PLIC_INT_MAC0_EMAC 68
+#define PLIC_INT_MAC0_MMSL 69
+#define PLIC_INT_MAC1_INT 70
+#define PLIC_INT_MAC1_QUEUE1 71
+#define PLIC_INT_MAC1_QUEUE2 72
+#define PLIC_INT_MAC1_QUEUE3 73
+#define PLIC_INT_MAC1_EMAC 74
+#define PLIC_INT_MAC1_MMSL 75
+#define PLIC_INT_DDRC_TRAIN 76
+#define PLIC_INT_SCB_INTERRUPT 77
+#define PLIC_INT_ECC_ERROR 78
+#define PLIC_INT_ECC_CORRECT 79
+#define PLIC_INT_RTC_WAKEUP 80
+#define PLIC_INT_RTC_MATCH 81
+#define PLIC_INT_TIMER1 82
+#define PLIC_INT_TIMER2 83
+#define PLIC_INT_ENVM 84
+#define PLIC_INT_QSPI 85
+#define PLIC_INT_USB_DMA 86
+#define PLIC_INT_USB_MC 87
+#define PLIC_INT_MMC_MAIN 88
+#define PLIC_INT_MMC_WAKEUP 89
+#define PLIC_INT_MMUART0 90
+#define PLIC_INT_MMUART1 91
+#define PLIC_INT_MMUART2 92
+#define PLIC_INT_MMUART3 93
+#define PLIC_INT_MMUART4 94
+#define PLIC_INT_G5C_DEVRST 95
+#define PLIC_INT_G5C_MESSAGE 96
+#define PLIC_INT_USOC_VC_INTERRUPT 97
+#define PLIC_INT_USOC_SMB_INTERRUPT 98
+#define PLIC_INT_E51_0_MAINTENACE 99
+#define PLIC_INT_WDOG0_MRVP 100
+#define PLIC_INT_WDOG1_MRVP 101
+#define PLIC_INT_WDOG2_MRVP 102
+#define PLIC_INT_WDOG3_MRVP 103
+#define PLIC_INT_WDOG4_MRVP 104
+#define PLIC_INT_WDOG0_TOUT 105
+#define PLIC_INT_WDOG1_TOUT 106
+#define PLIC_INT_WDOG2_TOUT 107
+#define PLIC_INT_WDOG3_TOUT 108
+#define PLIC_INT_WDOG4_TOUT 109
+#define PLIC_INT_G5C_MSS_SPI 110
+#define PLIC_INT_VOLT_TEMP_ALARM 111
+#define PLIC_INT_ATHENA_COMPLETE 112
+#define PLIC_INT_ATHENA_ALARM 113
+#define PLIC_INT_ATHENA_BUS_ERROR 114
+#define PLIC_INT_USOC_AXIC_US 115
+#define PLIC_INT_USOC_AXIC_DS 116
+#define PLIC_INT_SPARE 117
+
+#define PLIC_INT_FABRIC_F2H_0 118
+#define PLIC_INT_FABRIC_F2H_1 119
+#define PLIC_INT_FABRIC_F2H_2 120
+#define PLIC_INT_FABRIC_F2H_3 121
+#define PLIC_INT_FABRIC_F2H_4 122
+#define PLIC_INT_FABRIC_F2H_5 123
+#define PLIC_INT_FABRIC_F2H_6 124
+#define PLIC_INT_FABRIC_F2H_7 125
+#define PLIC_INT_FABRIC_F2H_8 126
+#define PLIC_INT_FABRIC_F2H_9 127
+#define PLIC_INT_FABRIC_F2H_10 128
+#define PLIC_INT_FABRIC_F2H_11 129
+#define PLIC_INT_FABRIC_F2H_12 130
+#define PLIC_INT_FABRIC_F2H_13 131
+#define PLIC_INT_FABRIC_F2H_14 132
+#define PLIC_INT_FABRIC_F2H_15 133
+#define PLIC_INT_FABRIC_F2H_16 134
+#define PLIC_INT_FABRIC_F2H_17 135
+#define PLIC_INT_FABRIC_F2H_18 136
+#define PLIC_INT_FABRIC_F2H_19 137
+#define PLIC_INT_FABRIC_F2H_20 138
+#define PLIC_INT_FABRIC_F2H_21 139
+#define PLIC_INT_FABRIC_F2H_22 140
+#define PLIC_INT_FABRIC_F2H_23 141
+#define PLIC_INT_FABRIC_F2H_24 142
+#define PLIC_INT_FABRIC_F2H_25 143
+#define PLIC_INT_FABRIC_F2H_26 144
+#define PLIC_INT_FABRIC_F2H_27 145
+#define PLIC_INT_FABRIC_F2H_28 146
+#define PLIC_INT_FABRIC_F2H_29 147
+#define PLIC_INT_FABRIC_F2H_30 148
+#define PLIC_INT_FABRIC_F2H_31 149
+#define PLIC_INT_FABRIC_F2H_32 150
+#define PLIC_INT_FABRIC_F2H_33 151
+#define PLIC_INT_FABRIC_F2H_34 152
+#define PLIC_INT_FABRIC_F2H_35 153
+#define PLIC_INT_FABRIC_F2H_36 154
+#define PLIC_INT_FABRIC_F2H_37 155
+#define PLIC_INT_FABRIC_F2H_38 156
+#define PLIC_INT_FABRIC_F2H_39 157
+#define PLIC_INT_FABRIC_F2H_40 158
+#define PLIC_INT_FABRIC_F2H_41 159
+#define PLIC_INT_FABRIC_F2H_42 160
+#define PLIC_INT_FABRIC_F2H_43 161
+#define PLIC_INT_FABRIC_F2H_44 162
+#define PLIC_INT_FABRIC_F2H_45 163
+#define PLIC_INT_FABRIC_F2H_46 164
+#define PLIC_INT_FABRIC_F2H_47 165
+#define PLIC_INT_FABRIC_F2H_48 166
+#define PLIC_INT_FABRIC_F2H_49 167
+#define PLIC_INT_FABRIC_F2H_50 168
+#define PLIC_INT_FABRIC_F2H_51 169
+#define PLIC_INT_FABRIC_F2H_52 170
+#define PLIC_INT_FABRIC_F2H_53 171
+#define PLIC_INT_FABRIC_F2H_54 172
+#define PLIC_INT_FABRIC_F2H_55 173
+#define PLIC_INT_FABRIC_F2H_56 174
+#define PLIC_INT_FABRIC_F2H_57 175
+#define PLIC_INT_FABRIC_F2H_58 176
+#define PLIC_INT_FABRIC_F2H_59 177
+#define PLIC_INT_FABRIC_F2H_60 178
+#define PLIC_INT_FABRIC_F2H_61 179
+#define PLIC_INT_FABRIC_F2H_62 180
+#define PLIC_INT_FABRIC_F2H_63 181
+#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182
+#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183
+#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184
+#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185
+#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186
+
+#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */
--
2.33.1

2021-11-08 15:07:38

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Subject: [PATCH 03/13] dt-bindings: soc/microchip: update sys ctrlr compat string

From: Conor Dooley <[email protected]>

Update 'compatible' strings for system controller drivers to the
approved Microchip name.

Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/mailbox/microchip,polarfire-soc-mailbox.yaml | 4 +++-
.../soc/microchip/microchip,polarfire-soc-sys-controller.yaml | 4 +++-
drivers/mailbox/mailbox-mpfs.c | 1 +
3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
index bbb173ea483c..b08c8a158eea 100644
--- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
@@ -11,7 +11,9 @@ maintainers:

properties:
compatible:
- const: microchip,polarfire-soc-mailbox
+ enum:
+ - microchip,polarfire-soc-mailbox
+ - microchip,mpfs-mailbox

reg:
items:
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
index 2cd3bc6bd8d6..d6c953cd154b 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
@@ -19,7 +19,9 @@ properties:
maxItems: 1

compatible:
- const: microchip,polarfire-soc-sys-controller
+ enum:
+ - microchip,polarfire-soc-sys-controller
+ - microchip,mpfs-sys-controller

required:
- compatible
diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index 0d6e2231a2c7..9d5e558a6ee6 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -233,6 +233,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev)

static const struct of_device_id mpfs_mbox_of_match[] = {
{.compatible = "microchip,polarfire-soc-mailbox", },
+ {.compatible = "microchip,mpfs-mailbox", },
{},
};
MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
--
2.33.1

2021-11-08 15:07:46

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Subject: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

From: Conor Dooley <[email protected]>

Add mpfs-soc to clear undocumented binding warning

Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 3f981e897126..1ff7a5224bbc 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -21,6 +21,7 @@ properties:
- enum:
- microchip,mpfs-icicle-kit
- const: microchip,mpfs
+ - const: microchip,mpfs-soc

additionalProperties: true

--
2.33.1

2021-11-08 15:07:52

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Subject: [PATCH 05/13] dt-bindings: i2c: add bindings for microchip mpfs i2c

From: Conor Dooley <[email protected]>

Add device tree bindings for the i2c controller on
the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Daire McNamara <[email protected]>
---
.../bindings/i2c/microchip,mpfs-i2c.yaml | 74 +++++++++++++++++++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml

diff --git a/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
new file mode 100644
index 000000000000..bc4ea4498d35
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/microchip,mpfs-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS I2C Controller Device Tree Bindings
+
+maintainers:
+ - Daire McNamara <[email protected]>
+
+description: |
+ This I2C controller is found on the Microchip PolarFire SoC.
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: Phandle of the clock feeding the I2C controller.
+ minItems: 1
+
+ clock-frequency:
+ description: |
+ Desired I2C bus clock frequency in Hz. As only Standard and Fast
+ modes are supported, possible values are 100000 and 400000.
+ enum: [100000, 400000]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0 0x2010a000 0 0x1000>;
+ interrupts = <58>;
+ clock-frequency = <100000>;
+ clocks = <&clkcfg CLK_I2C0>;
+ };
+ };
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0 0x2010b000 0 0x1000>;
+ interrupts = <61>;
+ clock-frequency = <100000>;
+ clocks = <&clkcfg CLK_I2C1>;
+ };
+ };
+...
--
2.33.1

2021-11-08 15:07:56

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Subject: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

From: Conor Dooley <[email protected]>

Add device tree bindings for the hardware rng device accessed via
the system services on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml

diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
new file mode 100644
index 000000000000..e8ecb3538a86
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip MPFS random number generator
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+properties:
+ compatible:
+ const: microchip,polarfire-soc-rng
+
+ syscontroller:
+ maxItems: 1
+ description: name of the system controller device node
+
+required:
+ - compatible
+ - "syscontroller"
+
+additionalProperties: false
+
+examples:
+ - |
+ hwrandom: hwrandom {
+ compatible = "microchip,polarfire-soc-rng";
+ syscontroller = <&syscontroller>;
+ };
--
2.33.1

2021-11-08 15:08:03

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Subject: [PATCH 08/13] dt-bindings: soc/microchip: add bindings for mpfs system services

From: Conor Dooley <[email protected]>

Add device tree bindings for the services provided by the system
controller directly on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
---
.../microchip,mpfs-generic-service.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml

diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
new file mode 100644
index 000000000000..f89d3a74c059
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-generic-service.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip MPFS system services
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+properties:
+ compatible:
+ const: microchip,mpfs-generic-service
+
+ syscontroller:
+ maxItems: 1
+ description: name of the system controller device node
+
+required:
+ - compatible
+ - "syscontroller"
+
+additionalProperties: false
+
+examples:
+ - |
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ syscontroller = <&syscontroller>;
+ };
--
2.33.1

2021-11-08 15:08:09

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Subject: [PATCH 07/13] dt-bindings: rtc: add bindings for microchip mpfs rtc

From: Conor Dooley <[email protected]>

Add device tree bindings for the real time clock on
the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Daire McNamara <[email protected]>
---
.../bindings/rtc/microchip,mfps-rtc.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
new file mode 100644
index 000000000000..c82b3e7351e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+ - $ref: "rtc.yaml#"
+
+maintainers:
+ - Daire McNamara <[email protected]>
+ - Lewis Hanly <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ prescaler:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rtc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0 0x20124000 0 0x1000>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ interrupts = <80>;
+ };
+ };
+...
--
2.33.1

2021-11-08 15:08:21

[permalink] [raw]

Subject: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio

From: Conor Dooley <[email protected]>

Add device tree bindings for the gpio controller on
the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml

diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 000000000000..067019ddc1f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+description: |
+ This GPIO controller is found on the Microchip PolarFire SoC.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,mpfs-gpio
+ - microsemi,ms-pf-mss-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ ngpios:
+ description:
+ The number of GPIOs available.
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - "#gpio-cells"
+ - gpio-controller
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+ };
+...
--
2.33.1

2021-11-08 15:08:54

[permalink] [raw]

Subject: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

From: Conor Dooley <[email protected]>

Add device tree bindings for the {q,}spi controller on
the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml

diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
new file mode 100644
index 000000000000..efed145ad029
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+description: |
+ This {Q,}SPI controller is found on the Microchip PolarFire SoC.
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-spi
+ - microsemi,ms-pf-mss-spi
+ - microchip,mpfs-qspi
+ - microsemi,ms-pf-mss-qspi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ num-cs:
+ description: |
+ Number of chip selects used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 8
+ default: 8
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_SPI0>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_SPI0>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
+ };
+ };
+...
--
2.33.1

2021-11-08 15:09:00

[permalink] [raw]

Subject: [PATCH 11/13] dt-bindings: usb: add bindings for microchip mpfs musb

From: Conor Dooley <[email protected]>

Add device tree bindings for the usb controller on
the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <[email protected]>
---
.../bindings/usb/microchip,mpfs-usb-host.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml

diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
new file mode 100644
index 000000000000..b867f49e7d70
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/microchip,mpfs-usb-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS USB Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <[email protected]>
+
+description: |
+ This USB controller is found on the Microchip PolarFire SoC.
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-usb-host
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ minItems: 2
+ items:
+ - const: dma
+ - const: mc
+
+ clocks:
+ maxItems: 1
+
+ dr_mode:
+ enum:
+ - host
+ - otg
+ - peripheral
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - dr_mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-usb-host";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
+ interrupt-names = "dma","mc";
+ dr_mode = "host";
+ status = "disabled";
+ };
+ };
+
+...
--
2.33.1

2021-11-08 15:09:07

[permalink] [raw]

Subject: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

From: Conor Dooley <[email protected]>

Update the device tree for the icicle kit by splitting it into a third part,
which contains peripherals in the fpga fabric, add new peripherals
(spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory
map which have been changed.

Signed-off-by: Conor Dooley <[email protected]>
---
.../dts/microchip/microchip-mpfs-fabric.dtsi | 21 ++
.../microchip/microchip-mpfs-icicle-kit.dts | 159 +++++++--
.../boot/dts/microchip/microchip-mpfs.dtsi | 333 ++++++++++++++----
3 files changed, 428 insertions(+), 85 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi

diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
new file mode 100644
index 000000000000..8fa3356494f1
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+ fpgadma: fpgadma@60020000 {
+ compatible = "microchip,mpfs-fpga-dma-uio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x60020000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_FABRIC_F2H_2>;
+ status = "okay";
+ };
+
+ fpgalsram: fpga_lsram@61000000 {
+ compatible = "generic-uio";
+ reg = <0x0 0x61000000 0x0 0x0001000
+ 0x14 0x00000000 0x0 0x00010000>;
+ status = "okay";
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index fc1e5869df1b..4212129fcdf1 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */

/dts-v1/;

@@ -13,72 +13,187 @@ / {
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";

aliases {
- ethernet0 = &emac1;
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
+ mmuart0 = &mmuart0;
+ mmuart1 = &mmuart1;
+ mmuart2 = &mmuart2;
+ mmuart3 = &mmuart3;
+ mmuart4 = &mmuart4;
};

chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "mmuart1:115200n8";
};

cpus {
timebase-frequency = <RTCCLK_FREQ>;
};

- memory@80000000 {
+ ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
- clocks = <&clkcfg 26>;
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
+ clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x40000000>;
+ clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
};
};

-&serial0 {
+&mmuart1 {
status = "okay";
};

-&serial1 {
+&mmuart2 {
status = "okay";
};

-&serial2 {
+&mmuart3 {
status = "okay";
};

-&serial3 {
+&mmuart4 {
status = "okay";
};

&mmc {
status = "okay";
-
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
+ cap-mmc-highspeed;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};

-&emac0 {
+&spi0 {
+ status = "okay";
+ spidev@0 {
+ compatible = "spidev";
+ reg = <0>; /* CS 0 */
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ pac193x: pac193x@10 {
+ compatible = "microchip,pac1934";
+ reg = <0x10>;
+ samp-rate = <64>;
+ status = "okay";
+ ch0: channel0 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDDREG";
+ channel_enabled;
+ };
+ ch1: channel1 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDDA25";
+ channel_enabled;
+ };
+ ch2: channel2 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDD25";
+ channel_enabled;
+ };
+ ch3: channel3 {
+ uohms-shunt-res = <10000>;
+ rail-name = "VDDA_REG";
+ channel_enabled;
+ };
+ };
+};
+
+&mac0 {
+ status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy0>;
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x01>;
- };
};

-&emac1 {
+&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
- ti,fifo-depth = <0x01>;
+ ti,fifo-depth = <0x1>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x1>;
};
};
+
+&gpio2 {
+ interrupts = <PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c9f6d205d2ba..805e07f0169e 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -1,7 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */

-/dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
+#include "dt-bindings/interrupt-controller/riscv-hart.h"
+#include "microchip-mpfs-fabric.dtsi"

/ {
#address-cells = <2>;
@@ -16,8 +19,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;

- cpu@0 {
- clock-frequency = <0>;
+ cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -25,6 +27,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg CLK_CPU>;
status = "disabled";

cpu0_intc: interrupt-controller {
@@ -34,8 +37,7 @@ cpu0_intc: interrupt-controller {
};
};

- cpu@1 {
- clock-frequency = <0>;
+ cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -51,6 +53,7 @@ cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";

@@ -61,8 +64,7 @@ cpu1_intc: interrupt-controller {
};
};

- cpu@2 {
- clock-frequency = <0>;
+ cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -78,6 +80,7 @@ cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";

@@ -88,8 +91,7 @@ cpu2_intc: interrupt-controller {
};
};

- cpu@3 {
- clock-frequency = <0>;
+ cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -105,6 +107,7 @@ cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";

@@ -115,8 +118,7 @@ cpu3_intc: interrupt-controller {
};
};

- cpu@4 {
- clock-frequency = <0>;
+ cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -132,8 +134,10 @@ cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
+
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
@@ -145,49 +149,55 @@ cpu4_intc: interrupt-controller {
soc {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "simple-bus";
+ compatible = "microchip,mpfs-soc", "simple-bus";
ranges;

- cache-controller@2010000 {
+ cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_L2_METADATA_CORR
+ PLIC_INT_L2_METADAT_UNCORR
+ PLIC_INT_L2_DATA_CORR>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
- interrupt-parent = <&plic>;
- interrupts = <1 2 3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
};

- clint@2000000 {
+ clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7
- &cpu2_intc 3 &cpu2_intc 7
- &cpu3_intc 3 &cpu3_intc 7
- &cpu4_intc 3 &cpu4_intc 7>;
+ interrupts-extended =
+ <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
+ &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
+ &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
+ &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
+ &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
};

plic: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
+ compatible = "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
+ #interrupt-cells = <1>;
riscv,ndev = <186>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11
- &cpu1_intc 11 &cpu1_intc 9
- &cpu2_intc 11 &cpu2_intc 9
- &cpu3_intc 11 &cpu3_intc 9
- &cpu4_intc 11 &cpu4_intc 9>;
+ interrupts-extended = <&cpu0_intc HART_INT_M_EXT
+ &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
+ &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
+ &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
+ &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
};

- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
+ pdma: pdma@3000000 {
+ compatible = "microchip,mpfs-pdma-uio";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
+ PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
+ PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
+ PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
#dma-cells = <1>;
};

@@ -205,7 +215,7 @@ clkcfg: clkcfg@20002000 {
clocks = <&refclk>;
#clock-cells = <1>;
clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
- "mac0", "mac1", "mmc", "timer", /* 4-7 */
+ "mac0", "mac1", "mmc", "timer", /* 4-7 */
"mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
"mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
"i2c1", "can0", "can1", "usb", /* 16-19 */
@@ -214,90 +224,287 @@ clkcfg: clkcfg@20002000 {
"fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
};

- serial0: serial@20000000 {
+ mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
+ clocks = <&clkcfg CLK_MMUART0>;
interrupt-parent = <&plic>;
- interrupts = <90>;
+ interrupts = <PLIC_INT_MMUART0>;
current-speed = <115200>;
- clocks = <&clkcfg 8>;
- status = "disabled";
+ status = "disabled"; /* Reserved for the HSS */
};

- serial1: serial@20100000 {
+ mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
+ clocks = <&clkcfg CLK_MMUART1>;
interrupt-parent = <&plic>;
- interrupts = <91>;
+ interrupts = <PLIC_INT_MMUART1>;
current-speed = <115200>;
- clocks = <&clkcfg 9>;
status = "disabled";
};

- serial2: serial@20102000 {
+ mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
+ clocks = <&clkcfg CLK_MMUART2>;
interrupt-parent = <&plic>;
- interrupts = <92>;
+ interrupts = <PLIC_INT_MMUART2>;
current-speed = <115200>;
- clocks = <&clkcfg 10>;
status = "disabled";
};

- serial3: serial@20104000 {
+ mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
+ clocks = <&clkcfg CLK_MMUART3>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MMUART3>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ mmuart4: serial@20106000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20106000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&clkcfg CLK_MMUART4>;
interrupt-parent = <&plic>;
- interrupts = <93>;
+ interrupts = <PLIC_INT_MMUART4>;
current-speed = <115200>;
- clocks = <&clkcfg 11>;
status = "disabled";
};

- /* Common node entry for emmc/sd */
- mmc: mmc@20008000 {
+ mmc: mmc@20008000 { /* Common node entry for emmc/sd */
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_MMC>;
interrupt-parent = <&plic>;
- interrupts = <88 89>;
- clocks = <&clkcfg 6>;
+ interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>;
max-frequency = <200000000>;
status = "disabled";
};

- emac0: ethernet@20110000 {
- compatible = "cdns,macb";
- reg = <0x0 0x20110000 0x0 0x2000>;
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_SPI0>;
interrupt-parent = <&plic>;
- interrupts = <64 65 66 67>;
- local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 4>, <&clkcfg 2>;
- clock-names = "pclk", "hclk";
+ interrupts = <PLIC_INT_SPI0>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_SPI1>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_SPI1>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ qspi: qspi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_QSPI>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_QSPI>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_I2C0>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_I2C0_MAIN>;
+ clock-frequency = <100000>;
status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c";
#address-cells = <1>;
#size-cells = <0>;
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_I2C1>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_I2C1_MAIN>;
+ clock-frequency = <100000>;
+ status = "disabled";
};

- emac1: ethernet@20112000 {
+ mac0: ethernet@20110000 {
compatible = "cdns,macb";
- reg = <0x0 0x20112000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20110000 0x0 0x2000>;
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
+ clock-names = "pclk", "hclk";
interrupt-parent = <&plic>;
- interrupts = <70 71 72 73>;
- local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 5>, <&clkcfg 2>;
+ interrupts = <PLIC_INT_MAC0_INT
+ PLIC_INT_MAC0_QUEUE1
+ PLIC_INT_MAC0_QUEUE2
+ PLIC_INT_MAC0_QUEUE3
+ PLIC_INT_MAC0_EMAC
+ PLIC_INT_MAC0_MMSL>;
+ mac-address = [56 34 12 00 FC 01];
status = "disabled";
+ };
+
+ mac1: ethernet@20112000 {
+ compatible = "cdns,macb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20112000 0x0 0x2000>;
+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_MAC1_INT
+ PLIC_INT_MAC1_QUEUE1
+ PLIC_INT_MAC1_QUEUE2
+ PLIC_INT_MAC1_QUEUE3
+ PLIC_INT_MAC1_EMAC
+ PLIC_INT_MAC1_MMSL>;
+ mac-address = [56 34 12 00 FC 02];
+ status = "disabled";
+ };
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_GPIO0>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_GPIO1>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
#address-cells = <1>;
#size-cells = <0>;
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
+ status = "disabled";
};

+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-usb-host";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ reg-names = "mc","control";
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
+ interrupt-names = "dma","mc";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_G5C_MESSAGE>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_FABRIC_F2H_1>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ mchp,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ mboxes = <&mbox 0>;
+ };
+
+ hwrandom: hwrandom {
+ compatible = "microchip,mpfs-rng";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscontroller = <&syscontroller>;
+ };
+
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscontroller = <&syscontroller>;
+ };
};
};
--
2.33.1

2021-11-08 15:09:11

[permalink] [raw]

Subject: [PATCH 13/13] MAINTAINERS: update riscv/microchip entry

From: Conor Dooley <[email protected]>

Update the riscv/microchip entry by adding the microchip dts
directory and myself as maintainer

Signed-off-by: Conor Dooley <[email protected]>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ca6d6fde85cf..a0000ddd02fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16077,8 +16077,10 @@ K: riscv

RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
M: Lewis Hanly <[email protected]>
+M: Conor Dooley <[email protected]>
L: [email protected]
S: Supported
+F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.33.1

2021-11-08 21:09:41

[permalink] [raw]

Subject: Re: [PATCH 03/13] dt-bindings: soc/microchip: update sys ctrlr compat string

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Update 'compatible' strings for system controller drivers to the
> approved Microchip name.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/mailbox/microchip,polarfire-soc-mailbox.yaml | 4 +++-
> .../soc/microchip/microchip,polarfire-soc-sys-controller.yaml | 4 +++-
> drivers/mailbox/mailbox-mpfs.c | 1 +
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> index bbb173ea483c..b08c8a158eea 100644
> --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> @@ -11,7 +11,9 @@ maintainers:
>
> properties:
> compatible:
> - const: microchip,polarfire-soc-mailbox
> + enum:
> + - microchip,polarfire-soc-mailbox
> + - microchip,mpfs-mailbox
>
> reg:
> items:
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> index 2cd3bc6bd8d6..d6c953cd154b 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> @@ -19,7 +19,9 @@ properties:
> maxItems: 1
>
> compatible:
> - const: microchip,polarfire-soc-sys-controller
> + enum:
> + - microchip,polarfire-soc-sys-controller
> + - microchip,mpfs-sys-controller
>
> required:
> - compatible
> diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
> index 0d6e2231a2c7..9d5e558a6ee6 100644
> --- a/drivers/mailbox/mailbox-mpfs.c
> +++ b/drivers/mailbox/mailbox-mpfs.c
> @@ -233,6 +233,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev)
>
> static const struct of_device_id mpfs_mbox_of_match[] = {
> {.compatible = "microchip,polarfire-soc-mailbox", },
> + {.compatible = "microchip,mpfs-mailbox", },
> {},
> };
> MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);

Please split the bindings from the code.

Best regards,
Krzysztof

2021-11-08 21:10:52

[permalink] [raw]

Subject: Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add mpfs-soc to clear undocumented binding warning

What warnings? There is no such compatible used.

>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
> index 3f981e897126..1ff7a5224bbc 100644
> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> @@ -21,6 +21,7 @@ properties:
> - enum:
> - microchip,mpfs-icicle-kit
> - const: microchip,mpfs
> + - const: microchip,mpfs-soc
>
> additionalProperties: true
>
>

Best regards,
Krzysztof

2021-11-08 21:13:19

[permalink] [raw]

Subject: Re: [PATCH 05/13] dt-bindings: i2c: add bindings for microchip mpfs i2c

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the i2c controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>
> ---
> .../bindings/i2c/microchip,mpfs-i2c.yaml | 74 +++++++++++++++++++
> 1 file changed, 74 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
>
> diff --git a/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
> new file mode 100644
> index 000000000000..bc4ea4498d35
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i2c/microchip,mpfs-i2c.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS I2C Controller Device Tree Bindings
> +
> +maintainers:
> + - Daire McNamara <[email protected]>
> +
> +description: |
> + This I2C controller is found on the Microchip PolarFire SoC.
> +
> +allOf:
> + - $ref: /schemas/i2c/i2c-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + description: Phandle of the clock feeding the I2C controller.

Skip such descriptions here and in other patches - they do not introduce
any meaningful information.

> + minItems: 1

Define instead exact number of clocks or maxItems... but why would they
be variable?

> +
> + clock-frequency:
> + description: |
> + Desired I2C bus clock frequency in Hz. As only Standard and Fast
> + modes are supported, possible values are 100000 and 400000.
> + enum: [100000, 400000]
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/microchip,mpfs-clock.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + i2c@2010a000 {
> + compatible = "microchip,mpfs-i2c";
> + reg = <0 0x2010a000 0 0x1000>;
> + interrupts = <58>;
> + clock-frequency = <100000>;
> + clocks = <&clkcfg CLK_I2C0>;
> + };
> + };
> + - |
> + #include <dt-bindings/clock/microchip,mpfs-clock.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + i2c@2010b000 {
> + compatible = "microchip,mpfs-i2c";
> + reg = <0 0x2010b000 0 0x1000>;
> + interrupts = <61>;
> + clock-frequency = <100000>;
> + clocks = <&clkcfg CLK_I2C1>;

This is the same example as above, just with changed numbers. Skip it.

> + };
> + };
> +...
>

Best regards,
Krzysztof

2021-11-08 21:17:08

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the hardware rng device accessed via
> the system services on the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>
> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> new file mode 100644
> index 000000000000..e8ecb3538a86
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> @@ -0,0 +1,31 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Microchip MPFS random number generator
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +properties:
> + compatible:
> + const: microchip,polarfire-soc-rng
> +
> + syscontroller:
> + maxItems: 1
> + description: name of the system controller device node

There are several issues with this:
1. You need to describe the type.
2. Description is not helpful (just copying the name of property) and
actually misleading because you do not put there the name of device node.
3. What is it? Looks like syscon (or sometimes called sysreg). If yes,
please use existing syscon bindings.

> +
> +required:
> + - compatible
> + - "syscontroller"

No need for quotes.

> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + hwrandom: hwrandom {
> + compatible = "microchip,polarfire-soc-rng";
> + syscontroller = <&syscontroller>;
> + };
>

Best regards,
Krzysztof

2021-11-08 21:20:31

[permalink] [raw]

Subject: Re: [PATCH 07/13] dt-bindings: rtc: add bindings for microchip mpfs rtc

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>
> ---
> .../bindings/rtc/microchip,mfps-rtc.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>
> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> new file mode 100644
> index 000000000000..c82b3e7351e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
> +
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
> +
> +allOf:
> + - $ref: "rtc.yaml#"

No need for quotes.

> +
> +maintainers:
> + - Daire McNamara <[email protected]>
> + - Lewis Hanly <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-rtc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + prescaler:
> + maxItems: 1

You need to describe the type and add description. This does not look
like standard property, so it needs vendor prefix.

> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: rtc
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/microchip,mpfs-clock.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;

Add a blank line before new node. The same in previous examples.

> + rtc@20124000 {
> + compatible = "microchip,mpfs-rtc";
> + reg = <0 0x20124000 0 0x1000>;
> + clocks = <&clkcfg CLK_RTC>;
> + clock-names = "rtc";
> + interrupts = <80>;
> + };
> + };
> +...
>

Best regards,
Krzysztof

2021-11-08 21:20:58

[permalink] [raw]

Subject: Re: [PATCH 08/13] dt-bindings: soc/microchip: add bindings for mpfs system services

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the services provided by the system
> controller directly on the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../microchip,mpfs-generic-service.yaml | 31 +++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
> new file mode 100644
> index 000000000000..f89d3a74c059
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
> @@ -0,0 +1,31 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-generic-service.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Microchip MPFS system services
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +properties:
> + compatible:
> + const: microchip,mpfs-generic-service
> +
> + syscontroller:
> + maxItems: 1
> + description: name of the system controller device node

Same comment as for rng patch.

> +
> +required:
> + - compatible
> + - "syscontroller"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + sysserv: sysserv {
> + compatible = "microchip,mpfs-generic-service";
> + syscontroller = <&syscontroller>;
> + };
>

Best regards,
Krzysztof

2021-11-08 21:23:18

[permalink] [raw]

Subject: Re: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the gpio controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++
> 1 file changed, 108 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>
> diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> new file mode 100644
> index 000000000000..067019ddc1f7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS GPIO Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + This GPIO controller is found on the Microchip PolarFire SoC.

If "Microchip MPFS" means "Microchip PolarFire SoC", then this is
duplicating the title. Similarly to your previous patches. Skip it then,
there is no point to have descriptions which are obvious or duplicating
existing information.

> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - microchip,mpfs-gpio
> + - microsemi,ms-pf-mss-gpio
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description:
> + Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
> + minItems: 1
> + maxItems: 32
> +
> + interrupt-controller: true
> +
> + clocks:
> + maxItems: 1
> +
> + "#gpio-cells":
> + const: 2
> +
> + ngpios:
> + description:
> + The number of GPIOs available.
> + minimum: 1
> + maximum: 32
> + default: 32
> +
> + gpio-controller: true
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - "#interrupt-cells"
> + - "#gpio-cells"
> + - gpio-controller
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + gpio2: gpio@20122000 {
> + compatible = "microchip,mpfs-gpio";
> + reg = <0x0 0x20122000 0x0 0x1000>;
> + clocks = <&clkcfg CLK_GPIO2>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";

Skip status=disabled.

> + };
> + };
> +...
>

Best regards,
Krzysztof

2021-11-08 21:24:48

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the {q,}spi controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> new file mode 100644
> index 000000000000..efed145ad029
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + This {Q,}SPI controller is found on the Microchip PolarFire SoC.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"

No need for quotes.

> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-spi
> + - microsemi,ms-pf-mss-spi
> + - microchip,mpfs-qspi
> + - microsemi,ms-pf-mss-qspi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-names:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 2

This does not match clock-names. Describe clocks instead. Are you really
sure your hardware can have an optional second clock?

> +
> + num-cs:
> + description: |
> + Number of chip selects used.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 1
> + maximum: 8
> + default: 8
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + spi0: spi@20108000 {
> + compatible = "microchip,mpfs-spi";
> + reg = <0x0 0x20108000 0x0 0x1000>;
> + clocks = <&clkcfg CLK_SPI0>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_SPI0>;
> + spi-max-frequency = <25000000>;
> + num-cs = <8>;
> + status = "disabled";
> + };
> + };
> +...
>

Best regards,
Krzysztof

2021-11-08 21:27:59

[permalink] [raw]

Subject: Re: [PATCH 11/13] dt-bindings: usb: add bindings for microchip mpfs musb

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the usb controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/usb/microchip,mpfs-usb-host.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
> new file mode 100644
> index 000000000000..b867f49e7d70
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/microchip,mpfs-usb-host.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS USB Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + This USB controller is found on the Microchip PolarFire SoC.
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-usb-host
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + minItems: 2

minItems should not be needed because you define all expected items below.

> + items:
> + - const: dma
> + - const: mc
> +
> + clocks:
> + maxItems: 1
> +
> + dr_mode:
> + enum:
> + - host
> + - otg
> + - peripheral
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - dr_mode
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + usb: usb@20201000 {
> + compatible = "microchip,mpfs-usb-host";
> + reg = <0x0 0x20201000 0x0 0x1000>;
> + clocks = <&clkcfg CLK_USB>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
> + interrupt-names = "dma","mc";
> + dr_mode = "host";
> + status = "disabled";

Skip disabled in example.

> + };
> + };
> +
> +...
>

Best regards,
Krzysztof

2021-11-08 21:40:19

[permalink] [raw]

Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

On 08/11/2021 16:05, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Update the device tree for the icicle kit by splitting it into a third part,
> which contains peripherals in the fpga fabric, add new peripherals
> (spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory
> map which have been changed.

This should be multiple commits because you mix up refactoring (split)
and adding new features. The patch is really, really difficult to
review. I gave up in the middle.

>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../dts/microchip/microchip-mpfs-fabric.dtsi | 21 ++
> .../microchip/microchip-mpfs-icicle-kit.dts | 159 +++++++--
> .../boot/dts/microchip/microchip-mpfs.dtsi | 333 ++++++++++++++----
> 3 files changed, 428 insertions(+), 85 deletions(-)
> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> new file mode 100644
> index 000000000000..8fa3356494f1
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> +
> +/ {
> + fpgadma: fpgadma@60020000 {
> + compatible = "microchip,mpfs-fpga-dma-uio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x60020000 0x0 0x1000>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_FABRIC_F2H_2>;
> + status = "okay";
> + };
> +
> + fpgalsram: fpga_lsram@61000000 {

Node names go with hyphen, but actually you should not need it, because
the name should be generic, e.g. "uio".

However there is no such compatible and checkpatch should complain about it.

> + compatible = "generic-uio";
> + reg = <0x0 0x61000000 0x0 0x0001000
> + 0x14 0x00000000 0x0 0x00010000>;
> + status = "okay";
> + };
> +};
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> index fc1e5869df1b..4212129fcdf1 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> -/* Copyright (c) 2020 Microchip Technology Inc */
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>
> /dts-v1/;
>
> @@ -13,72 +13,187 @@ / {
> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
>
> aliases {
> - ethernet0 = &emac1;
> - serial0 = &serial0;
> - serial1 = &serial1;
> - serial2 = &serial2;
> - serial3 = &serial3;> + mmuart0 = &mmuart0;
> + mmuart1 = &mmuart1;
> + mmuart2 = &mmuart2;
> + mmuart3 = &mmuart3;
> + mmuart4 = &mmuart4;

Why? Commit msg does not explain it.

> };
>
> chosen {
> - stdout-path = "serial0:115200n8";
> + stdout-path = "mmuart1:115200n8";
> };
>
> cpus {
> timebase-frequency = <RTCCLK_FREQ>;
> };
>
> - memory@80000000 {
> + ddrc_cache_lo: memory@80000000 {
> device_type = "memory";
> - reg = <0x0 0x80000000 0x0 0x40000000>;
> - clocks = <&clkcfg 26>;
> + reg = <0x0 0x80000000 0x0 0x2e000000>;
> + clocks = <&clkcfg CLK_DDRC>;
> + status = "okay";
> + };
> +
> + ddrc_cache_hi: memory@1000000000 {
> + device_type = "memory";
> + reg = <0x10 0x0 0x0 0x40000000>;
> + clocks = <&clkcfg CLK_DDRC>;
> + status = "okay";
> };
> };
>
> -&serial0 {
> +&mmuart1 {
> status = "okay";
> };
>
> -&serial1 {
> +&mmuart2 {
> status = "okay";
> };
>
> -&serial2 {
> +&mmuart3 {
> status = "okay";
> };
>
> -&serial3 {
> +&mmuart4 {
> status = "okay";
> };
>
> &mmc {
> status = "okay";
> -
> bus-width = <4>;
> disable-wp;
> cap-sd-highspeed;
> + cap-mmc-highspeed;
> card-detect-delay = <200>;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> sd-uhs-sdr12;
> sd-uhs-sdr25;
> sd-uhs-sdr50;
> sd-uhs-sdr104;
> };
>
> -&emac0 {
> +&spi0 {
> + status = "okay";
> + spidev@0 {
> + compatible = "spidev";

1. There is no such compatible,
2. You should have big fat warning when booting, so such DT cannot be
accepted.

> + reg = <0>; /* CS 0 */
> + spi-max-frequency = <10000000>;
> + status = "okay";
> + };
> +};
> +
> +&spi1 {
> + status = "okay";
> +};
> +
> +&qspi {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +};
> +
> +&i2c1 {
> + status = "okay";
> + pac193x: pac193x@10 {

Generic node name. Looks like compatible is not documented, so first
bindings.

> + compatible = "microchip,pac1934";
> + reg = <0x10>;
> + samp-rate = <64>;
> + status = "okay";
> + ch0: channel0 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDDREG";
> + channel_enabled;
> + };
> + ch1: channel1 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDDA25";
> + channel_enabled;
> + };
> + ch2: channel2 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDD25";
> + channel_enabled;
> + };
> + ch3: channel3 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDDA_REG";
> + channel_enabled;
> + };
> + };
> +};
> +
> +&mac0 {
> + status = "okay";
> phy-mode = "sgmii";
> phy-handle = <&phy0>;
> - phy0: ethernet-phy@8 {
> - reg = <8>;
> - ti,fifo-depth = <0x01>;
> - };
> };
>
> -&emac1 {
> +&mac1 {

I gave up here, it's not easy to find what is effect of refactoring,
what is a new node.

Best regards,
Krzysztof

2021-11-09 04:06:38

[permalink] [raw]

Subject: Re: [PATCH 05/13] dt-bindings: i2c: add bindings for microchip mpfs i2c

On Mon, 08 Nov 2021 15:05:46 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the i2c controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>
> ---
> .../bindings/i2c/microchip,mpfs-i2c.yaml | 74 +++++++++++++++++++
> 1 file changed, 74 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include <dt-bindings/clock/microchip,mpfs-clock.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1441: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1552366

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

2021-11-09 04:06:43

[permalink] [raw]

Subject: Re: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio

On Mon, 08 Nov 2021 15:05:50 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the gpio controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++
> 1 file changed, 108 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1441: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1552384

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

2021-11-09 04:06:47

[permalink] [raw]

Subject: Re: [PATCH 11/13] dt-bindings: usb: add bindings for microchip mpfs musb

On Mon, 08 Nov 2021 15:05:52 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the usb controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/usb/microchip,mpfs-usb-host.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml: properties:interrupt-names: 'oneOf' conditional failed, one must be fixed:
[{'const': 'dma'}, {'const': 'mc'}] is too long
[{'const': 'dma'}, {'const': 'mc'}] is too short
False schema does not allow 2
1 was expected
hint: "minItems" is only needed if less than the "items" list length
from schema $id: http://devicetree.org/meta-schemas/items.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml: ignoring, error in schema: properties: interrupt-names
warning: no schema found in file: ./Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1441: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1552389

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

2021-11-09 04:06:47

[permalink] [raw]

Subject: Re: [PATCH 07/13] dt-bindings: rtc: add bindings for microchip mpfs rtc

On Mon, 08 Nov 2021 15:05:48 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>
> ---
> .../bindings/rtc/microchip,mfps-rtc.yaml | 61 +++++++++++++++++++
> 1 file changed, 61 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include <dt-bindings/clock/microchip,mpfs-clock.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1441: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1552374

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

2021-11-09 04:06:59

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On Mon, 08 Nov 2021 15:05:51 +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the {q,}spi controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1441: dt_binding_check] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1552385

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

2021-11-09 08:35:18

[permalink] [raw]

Subject: Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

Hi Conor,

On Mon, Nov 8, 2021 at 4:06 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Add mpfs-soc to clear undocumented binding warning
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
> index 3f981e897126..1ff7a5224bbc 100644
> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> @@ -21,6 +21,7 @@ properties:
> - enum:
> - microchip,mpfs-icicle-kit
> - const: microchip,mpfs
> + - const: microchip,mpfs-soc

Doesn't the "s" in "mpfs" already stand for "soc"?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 08:37:39

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

Hi Conor,

On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the hardware rng device accessed via
> the system services on the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>

Thanks for your patch!

> ---
> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>
> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> new file mode 100644
> index 000000000000..e8ecb3538a86
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> @@ -0,0 +1,31 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Microchip MPFS random number generator
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +properties:
> + compatible:
> + const: microchip,polarfire-soc-rng

"microchip,mpfs-rng", for consistency with other bindings?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 08:39:51

[permalink] [raw]

Subject: Re: [PATCH 07/13] dt-bindings: rtc: add bindings for microchip mpfs rtc

Hi Conor,

On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Daire McNamara <[email protected]>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
> @@ -0,0 +1,61 @@

> +examples:
> + - |
> + #include <dt-bindings/clock/microchip,mpfs-clock.h>
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;

Examples are indeed built with #{address,size}-cells = <1>.
However, there is no need to override this. Just drop the zeros in
the reg property below.

> + rtc@20124000 {
> + compatible = "microchip,mpfs-rtc";
> + reg = <0 0x20124000 0 0x1000>;
> + clocks = <&clkcfg CLK_RTC>;
> + clock-names = "rtc";
> + interrupts = <80>;
> + };
> + };
> +...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 08:41:30

[permalink] [raw]

Subject: Re: [PATCH 03/13] dt-bindings: soc/microchip: update sys ctrlr compat string

Hi Conor,

On Mon, Nov 8, 2021 at 4:06 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Update 'compatible' strings for system controller drivers to the
> approved Microchip name.
>
> Signed-off-by: Conor Dooley <[email protected]>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> @@ -11,7 +11,9 @@ maintainers:
>
> properties:
> compatible:
> - const: microchip,polarfire-soc-mailbox
> + enum:
> + - microchip,polarfire-soc-mailbox
> + - microchip,mpfs-mailbox

Is there any point in keeping the old compatible value?
Are there any real users? Most of the MPFS upstream DT is still in flux.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 08:43:26

[permalink] [raw]

Subject: Re: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio

Hi Conor,

On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the gpio controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS GPIO Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + This GPIO controller is found on the Microchip PolarFire SoC.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - microchip,mpfs-gpio
> + - microsemi,ms-pf-mss-gpio

What's the difference between these two?
If there is a difference, please add a comment "# <explanation>"
to each entry.
If there is no difference, please drop the second one.

> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description:
> + Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
> + minItems: 1
> + maxItems: 32
> +
> + interrupt-controller: true
> +
> + clocks:
> + maxItems: 1
> +
> + "#gpio-cells":
> + const: 2
> +
> + ngpios:
> + description:
> + The number of GPIOs available.
> + minimum: 1
> + maximum: 32
> + default: 32
> +
> + gpio-controller: true
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - "#interrupt-cells"
> + - "#gpio-cells"
> + - gpio-controller
> + - clocks

Any specific reason interrupt-controller is not required?

> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;

Just drop these two...

> + gpio2: gpio@20122000 {
> + compatible = "microchip,mpfs-gpio";
> + reg = <0x0 0x20122000 0x0 0x1000>;

... and the zeros here.

> + clocks = <&clkcfg CLK_GPIO2>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";

Please drop this.

> + };
> + };

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 08:46:02

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

Hi Conor,

On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the {q,}spi controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + This {Q,}SPI controller is found on the Microchip PolarFire SoC.
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-spi
> + - microsemi,ms-pf-mss-spi
> + - microchip,mpfs-qspi
> + - microsemi,ms-pf-mss-qspi

Same comment as before: what are the ms-pf-mss entries?

> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;

Please drop these two...

> + spi0: spi@20108000 {
> + compatible = "microchip,mpfs-spi";
> + reg = <0x0 0x20108000 0x0 0x1000>;

... and the zeros here.

> + clocks = <&clkcfg CLK_SPI0>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_SPI0>;
> + spi-max-frequency = <25000000>;
> + num-cs = <8>;
> + status = "disabled";

Please drop this.

> + };
> + };
> +...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 08:56:47

[permalink] [raw]

Subject: Re: [PATCH 11/13] dt-bindings: usb: add bindings for microchip mpfs musb

Hi Conor,

On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Add device tree bindings for the usb controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <[email protected]>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/microchip,mpfs-usb-host.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip MPFS USB Controller Device Tree Bindings
> +
> +maintainers:
> + - Conor Dooley <[email protected]>
> +
> +description: |
> + This USB controller is found on the Microchip PolarFire SoC.
> +
> +properties:
> + compatible:
> + enum:
> + - microchip,mpfs-usb-host

"microchip-mpfs-usb", given the dr_mode property below indicates this
controller is not limited to host mode?

> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + minItems: 2
> + items:
> + - const: dma
> + - const: mc
> +
> + clocks:
> + maxItems: 1
> +
> + dr_mode:
> + enum:
> + - host
> + - otg
> + - peripheral
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - dr_mode
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include "dt-bindings/clock/microchip,mpfs-clock.h"
> + #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;

Please drop these two...

> + usb: usb@20201000 {
> + compatible = "microchip,mpfs-usb-host";
> + reg = <0x0 0x20201000 0x0 0x1000>;

... and the zeros here.

> + clocks = <&clkcfg CLK_USB>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;

Please group by angular brackets:

<PLIC_INT_USB_DMA>, <PLIC_INT_USB_MC>.

> + interrupt-names = "dma","mc";
> + dr_mode = "host";
> + status = "disabled";

Please drop this.

> + };
> + };
> +
> +...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 09:05:08

[permalink] [raw]

Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

Hi Conor,

On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> From: Conor Dooley <[email protected]>
>
> Update the device tree for the icicle kit by splitting it into a third part,
> which contains peripherals in the fpga fabric, add new peripherals
> (spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory
> map which have been changed.
>
> Signed-off-by: Conor Dooley <[email protected]>

Thanks for your patch!

Please split it into logical separated parts.

> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> @@ -0,0 +1,21 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> +
> +/ {
> + fpgadma: fpgadma@60020000 {
> + compatible = "microchip,mpfs-fpga-dma-uio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x60020000 0x0 0x1000>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_FABRIC_F2H_2>;
> + status = "okay";
> + };
> +
> + fpgalsram: fpga_lsram@61000000 {
> + compatible = "generic-uio";
> + reg = <0x0 0x61000000 0x0 0x0001000
> + 0x14 0x00000000 0x0 0x00010000>;

Please group by angular brackets, to increase readability, and support
automatic validation:

<0x0 0x61000000 0x0 0x0001000>, <0x14 0x00000000 0x0 0x00010000>

> + status = "okay";
> + };

Do we really want UIO nodes in upstream DT?

> +};
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> index fc1e5869df1b..4212129fcdf1 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> @@ -1,5 +1,5 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> -/* Copyright (c) 2020 Microchip Technology Inc */
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>
> /dts-v1/;
>
> @@ -13,72 +13,187 @@ / {
> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
>
> aliases {
> - ethernet0 = &emac1;
> - serial0 = &serial0;
> - serial1 = &serial1;
> - serial2 = &serial2;
> - serial3 = &serial3;
> + mmuart0 = &mmuart0;
> + mmuart1 = &mmuart1;
> + mmuart2 = &mmuart2;
> + mmuart3 = &mmuart3;
> + mmuart4 = &mmuart4;

Why? SerialN is the standard alias name.

> };

>
> -&emac0 {
> +&spi0 {
> + status = "okay";
> + spidev@0 {
> + compatible = "spidev";

Please don't use "spidev", but a proper compatible value describing
what is really connected. If you want to use it with spidev (which
is software policy, not hardware description), add that compatible
value to drivers/spi/spidev.c:spidev_dt_ids[], or use driver_override
in sysfs at runtime.

> + reg = <0>; /* CS 0 */
> + spi-max-frequency = <10000000>;
> + status = "okay";
> + };
> +};
> +
> +&spi1 {
> + status = "okay";

No slave devices specified?

> +};
> +
> +&qspi {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +};
> +
> +&i2c1 {
> + status = "okay";
> + pac193x: pac193x@10 {

adc@, I guess?

> + compatible = "microchip,pac1934";
> + reg = <0x10>;
> + samp-rate = <64>;
> + status = "okay";
> + ch0: channel0 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDDREG";
> + channel_enabled;
> + };
> + ch1: channel1 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDDA25";
> + channel_enabled;
> + };
> + ch2: channel2 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDD25";
> + channel_enabled;
> + };
> + ch3: channel3 {
> + uohms-shunt-res = <10000>;
> + rail-name = "VDDA_REG";
> + channel_enabled;
> + };
> + };
> +};

> +&gpio2 {
> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT
> + PLIC_INT_GPIO2_NON_DIRECT>;

Why override interrupts in the board .dts file?
Doesn't this belong in the SoC .dtsi file?
Please group using angular brackets.

> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

> @@ -145,49 +149,55 @@ cpu4_intc: interrupt-controller {
> soc {
> #address-cells = <2>;
> #size-cells = <2>;
> - compatible = "simple-bus";
> + compatible = "microchip,mpfs-soc", "simple-bus";
> ranges;
>
> - cache-controller@2010000 {
> + cctrllr: cache-controller@2010000 {
> compatible = "sifive,fu540-c000-ccache", "cache";
> + reg = <0x0 0x2010000 0x0 0x1000>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_L2_METADATA_CORR
> + PLIC_INT_L2_METADAT_UNCORR
> + PLIC_INT_L2_DATA_CORR>;

Please group using angular brackets.

> cache-block-size = <64>;
> cache-level = <2>;
> cache-sets = <1024>;
> cache-size = <2097152>;
> cache-unified;
> - interrupt-parent = <&plic>;
> - interrupts = <1 2 3>;
> - reg = <0x0 0x2010000 0x0 0x1000>;
> };
>
> - clint@2000000 {
> + clint: clint@2000000 {
> compatible = "sifive,fu540-c000-clint", "sifive,clint0";
> reg = <0x0 0x2000000 0x0 0xC000>;
> - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> - &cpu1_intc 3 &cpu1_intc 7
> - &cpu2_intc 3 &cpu2_intc 7
> - &cpu3_intc 3 &cpu3_intc 7
> - &cpu4_intc 3 &cpu4_intc 7>;
> + interrupts-extended =
> + <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
> + &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
> + &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
> + &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
> + &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;

Please group using angular brackets.

> };
>
> plic: interrupt-controller@c000000 {
> - #interrupt-cells = <1>;
> - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
> + compatible = "sifive,plic-1.0.0";

Why drop the first one again?

> reg = <0x0 0xc000000 0x0 0x4000000>;
> + #interrupt-cells = <1>;
> riscv,ndev = <186>;
> interrupt-controller;
> - interrupts-extended = <&cpu0_intc 11
> - &cpu1_intc 11 &cpu1_intc 9
> - &cpu2_intc 11 &cpu2_intc 9
> - &cpu3_intc 11 &cpu3_intc 9
> - &cpu4_intc 11 &cpu4_intc 9>;
> + interrupts-extended = <&cpu0_intc HART_INT_M_EXT
> + &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
> + &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
> + &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
> + &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
> };
>
> - dma@3000000 {
> - compatible = "sifive,fu540-c000-pdma";
> + pdma: pdma@3000000 {
> + compatible = "microchip,mpfs-pdma-uio";
> reg = <0x0 0x3000000 0x0 0x8000>;
> interrupt-parent = <&plic>;
> - interrupts = <23 24 25 26 27 28 29 30>;
> + interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
> + PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
> + PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
> + PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;

Please group using angular brackets.

> #dma-cells = <1>;
> };
>
> @@ -205,7 +215,7 @@ clkcfg: clkcfg@20002000 {
> clocks = <&refclk>;
> #clock-cells = <1>;
> clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
> - "mac0", "mac1", "mmc", "timer", /* 4-7 */
> + "mac0", "mac1", "mmc", "timer", /* 4-7 */
> "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
> "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
> "i2c1", "can0", "can1", "usb", /* 16-19 */

No need for clock-output-names at all.

>
> - emac1: ethernet@20112000 {
> + mac0: ethernet@20110000 {
> compatible = "cdns,macb";
> - reg = <0x0 0x20112000 0x0 0x2000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x20110000 0x0 0x2000>;
> + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
> + clock-names = "pclk", "hclk";
> interrupt-parent = <&plic>;
> - interrupts = <70 71 72 73>;
> - local-mac-address = [00 00 00 00 00 00];
> - clocks = <&clkcfg 5>, <&clkcfg 2>;
> + interrupts = <PLIC_INT_MAC0_INT
> + PLIC_INT_MAC0_QUEUE1
> + PLIC_INT_MAC0_QUEUE2
> + PLIC_INT_MAC0_QUEUE3
> + PLIC_INT_MAC0_EMAC
> + PLIC_INT_MAC0_MMSL>;

Please group using angular brackets.

> + mac-address = [56 34 12 00 FC 01];

Please drop this.

> status = "disabled";
> + };
>
> + rtc: rtc@20124000 {
> + compatible = "microchip,mpfs-rtc";
> #address-cells = <1>;
> #size-cells = <0>;
> + reg = <0x0 0x20124000 0x0 0x1000>;
> + clocks = <&clkcfg CLK_RTC>;
> + clock-names = "rtc";
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;

Please group using angular brackets.

> + status = "disabled";
> };
>
> + usb: usb@20201000 {
> + compatible = "microchip,mpfs-usb-host";
> + reg = <0x0 0x20201000 0x0 0x1000>;
> + reg-names = "mc","control";
> + clocks = <&clkcfg CLK_USB>;
> + interrupt-parent = <&plic>;
> + interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;

Please group using angular brackets.

> + interrupt-names = "dma","mc";
> + dr_mode = "host";
> + status = "disabled";
> + };
> +

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 10:56:37

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 09/11/2021 08:45, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - microchip,mpfs-spi
>> + - microsemi,ms-pf-mss-spi
>> + - microchip,mpfs-qspi
>> + - microsemi,ms-pf-mss-qspi
>
> Same comment as before: what are the ms-pf-mss entries?
>

i think i will just drop the microsemi bindings, on reflection i dont
think theyre relevant to this version of the device tree.

2021-11-09 11:55:17

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On 09/11/2021 08:37, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Add device tree bindings for the hardware rng device accessed via
>> the system services on the Microchip PolarFire SoC.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>
> Thanks for your patch!
>
>> ---
>> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>> new file mode 100644
>> index 000000000000..e8ecb3538a86
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>> @@ -0,0 +1,31 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Microchip MPFS random number generator
>> +
>> +maintainers:
>> + - Conor Dooley <[email protected]>
>> +
>> +properties:
>> + compatible:
>> + const: microchip,polarfire-soc-rng
>
> "microchip,mpfs-rng", for consistency with other bindings?
correct, dropped the wrong one while cleaning up since this doesnt match
the device tree.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>

2021-11-09 12:08:25

[permalink] [raw]

Subject: Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

On 09/11/2021 08:34, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Mon, Nov 8, 2021 at 4:06 PM <[email protected]> wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Add mpfs-soc to clear undocumented binding warning
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> Documentation/devicetree/bindings/riscv/microchip.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
>> index 3f981e897126..1ff7a5224bbc 100644
>> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
>> @@ -21,6 +21,7 @@ properties:
>> - enum:
>> - microchip,mpfs-icicle-kit
>> - const: microchip,mpfs
>> + - const: microchip,mpfs-soc
>
> Doesn't the "s" in "mpfs" already stand for "soc"?
not wrong, but using mpf-soc would be confusing since "mpf" is the part
name for the non soc fpga. is it fine to just reuse "mpfs" for the dtsi
overall compatible and for the soc subsection?
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>

2021-11-09 12:16:35

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 09/11/2021 04:06, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, 08 Nov 2021 15:05:51 +0000, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Add device tree bindings for the {q,}spi controller on
>> the Microchip PolarFire SoC.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
>> 1 file changed, 72 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>>
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
> 19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
Rob,
Should I drop the header from the example or is there a way for me
specify the dependent patch to pass this check?
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
> make[1]: *** [scripts/Makefile.lib:385: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dt.yaml] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1441: dt_binding_check] Error 2
>
> doc reference errors (make refcheckdocs):
>
> See https://patchwork.ozlabs.org/patch/1552385
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
>

2021-11-09 12:53:39

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 09/11/2021 13:16, [email protected] wrote:
> On 09/11/2021 04:06, Rob Herring wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Mon, 08 Nov 2021 15:05:51 +0000, [email protected] wrote:
>>> From: Conor Dooley <[email protected]>
>>>
>>> Add device tree bindings for the {q,}spi controller on
>>> the Microchip PolarFire SoC.
>>>
>>> Signed-off-by: Conor Dooley <[email protected]>
>>> ---
>>> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
>>> 1 file changed, 72 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>>>
>>
>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>
>> yamllint warnings/errors:
>>
>> dtschema/dtc warnings/errors:
>> Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
>> 19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
> Rob,
> Should I drop the header from the example or is there a way for me
> specify the dependent patch to pass this check?

The error has to be fixed, although not necessarily by dropping the
header, but by posting it. How this can pass on your system? There is no
such file added in this patchset.

Best regards,
Krzysztof

2021-11-09 12:54:46

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On 08/11/2021 21:16, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 08/11/2021 16:05, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Add device tree bindings for the hardware rng device accessed via
>> the system services on the Microchip PolarFire SoC.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>> new file mode 100644
>> index 000000000000..e8ecb3538a86
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>> @@ -0,0 +1,31 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Microchip MPFS random number generator
>> +
>> +maintainers:
>> + - Conor Dooley <[email protected]>
>> +
>> +properties:
>> + compatible:
>> + const: microchip,polarfire-soc-rng
>> +
>> + syscontroller:
>> + maxItems: 1
>> + description: name of the system controller device node
>
> There are several issues with this:
> 1. You need to describe the type.
> 2. Description is not helpful (just copying the name of property) and
> actually misleading because you do not put there the name of device node.
> 3. What is it? Looks like syscon (or sometimes called sysreg). If yes,
> please use existing syscon bindings.
1 & 2 - Correct, it is bad & I'll write a better description for it.
3 - Its a system controller implemented as a mailbox. The syscontroller
is the mailbox client, which the rng and generic drivers both use.
>
>> +
>> +required:
>> + - compatible
>> + - "syscontroller"
>
> No need for quotes.
>
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + hwrandom: hwrandom {
>> + compatible = "microchip,polarfire-soc-rng";
>> + syscontroller = <&syscontroller>;
>> + };
>>
>
>
> Best regards,
> Krzysztof
>

2021-11-09 12:57:01

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On 09/11/2021 13:54, [email protected] wrote:
> On 08/11/2021 21:16, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 08/11/2021 16:05, [email protected] wrote:
>>> From: Conor Dooley <[email protected]>
>>>
>>> Add device tree bindings for the hardware rng device accessed via
>>> the system services on the Microchip PolarFire SoC.
>>>
>>> Signed-off-by: Conor Dooley <[email protected]>
>>> ---
>>> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>> new file mode 100644
>>> index 000000000000..e8ecb3538a86
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>> @@ -0,0 +1,31 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>> +
>>> +title: Microchip MPFS random number generator
>>> +
>>> +maintainers:
>>> + - Conor Dooley <[email protected]>
>>> +
>>> +properties:
>>> + compatible:
>>> + const: microchip,polarfire-soc-rng
>>> +
>>> + syscontroller:
>>> + maxItems: 1
>>> + description: name of the system controller device node
>>
>> There are several issues with this:
>> 1. You need to describe the type.
>> 2. Description is not helpful (just copying the name of property) and
>> actually misleading because you do not put there the name of device node.
>> 3. What is it? Looks like syscon (or sometimes called sysreg). If yes,
>> please use existing syscon bindings.
> 1 & 2 - Correct, it is bad & I'll write a better description for it.
> 3 - Its a system controller implemented as a mailbox. The syscontroller
> is the mailbox client, which the rng and generic drivers both use.

I understood that pointed device node is a mailbox, not this node. But
here, what is it here? How do you use it here?

Best regards,
Krzysztof

2021-11-09 12:58:27

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 09/11/2021 12:53, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 09/11/2021 13:16, [email protected] wrote:
>> On 09/11/2021 04:06, Rob Herring wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Mon, 08 Nov 2021 15:05:51 +0000, [email protected] wrote:
>>>> From: Conor Dooley <[email protected]>
>>>>
>>>> Add device tree bindings for the {q,}spi controller on
>>>> the Microchip PolarFire SoC.
>>>>
>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>> ---
>>>> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
>>>> 1 file changed, 72 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>>>>
>>>
>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>
>>> yamllint warnings/errors:
>>>
>>> dtschema/dtc warnings/errors:
>>> Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
>>> 19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
>> Rob,
>> Should I drop the header from the example or is there a way for me
>> specify the dependent patch to pass this check?
>
> The error has to be fixed, although not necessarily by dropping the
> header, but by posting it. How this can pass on your system? There is no
> such file added in this patchset.
I linked the patch adding the clock as a dependency in the cover letter
[1], which is why I was wondering if there was a better way to do so
that would get picked up by the checker bot.

[1]
https://lore.kernel.org/linux-clk/[email protected]/
>
> Best regards,
> Krzysztof
>

2021-11-09 13:04:31

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 09/11/2021 13:58, [email protected] wrote:
> On 09/11/2021 12:53, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 09/11/2021 13:16, [email protected] wrote:
>>> On 09/11/2021 04:06, Rob Herring wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On Mon, 08 Nov 2021 15:05:51 +0000, [email protected] wrote:
>>>>> From: Conor Dooley <[email protected]>
>>>>>
>>>>> Add device tree bindings for the {q,}spi controller on
>>>>> the Microchip PolarFire SoC.
>>>>>
>>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>>> ---
>>>>> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
>>>>> 1 file changed, 72 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>>>>>
>>>>
>>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>>
>>>> yamllint warnings/errors:
>>>>
>>>> dtschema/dtc warnings/errors:
>>>> Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
>>>> 19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
>>> Rob,
>>> Should I drop the header from the example or is there a way for me
>>> specify the dependent patch to pass this check?
>>
>> The error has to be fixed, although not necessarily by dropping the
>> header, but by posting it. How this can pass on your system? There is no
>> such file added in this patchset.
> I linked the patch adding the clock as a dependency in the cover letter
> [1], which is why I was wondering if there was a better way to do so
> that would get picked up by the checker bot.

It's not only about the bot, but dependency when applied. If you did not
warn clk maintainer that clock bindings should go via Rob's tree or
should be provided as a tag, the patches here cannot be applied in this
cycle.

Best regards,
Krzysztof

2021-11-09 13:05:05

[permalink] [raw]

Subject: Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

Hi Conor,

On Tue, Nov 9, 2021 at 1:08 PM <[email protected]> wrote:
> On 09/11/2021 08:34, Geert Uytterhoeven wrote:
> > On Mon, Nov 8, 2021 at 4:06 PM <[email protected]> wrote:
> >> From: Conor Dooley <[email protected]>
> >>
> >> Add mpfs-soc to clear undocumented binding warning
> >>
> >> Signed-off-by: Conor Dooley <[email protected]>

> >> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
> >> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> >> @@ -21,6 +21,7 @@ properties:
> >> - enum:
> >> - microchip,mpfs-icicle-kit
> >> - const: microchip,mpfs
> >> + - const: microchip,mpfs-soc
> >
> > Doesn't the "s" in "mpfs" already stand for "soc"?
> not wrong, but using mpf-soc would be confusing since "mpf" is the part
> name for the non soc fpga. is it fine to just reuse "mpfs" for the dtsi
> overall compatible and for the soc subsection?

I really meant: what is the difference between "microchip,mpfs" and
"microchip,mpfs-soc"? Can't you just use the former?

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-09 13:20:50

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 09/11/2021 13:04, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 09/11/2021 13:58, [email protected] wrote:
>> On 09/11/2021 12:53, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 09/11/2021 13:16, [email protected] wrote:
>>>> On 09/11/2021 04:06, Rob Herring wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On Mon, 08 Nov 2021 15:05:51 +0000, [email protected] wrote:
>>>>>> From: Conor Dooley <[email protected]>
>>>>>>
>>>>>> Add device tree bindings for the {q,}spi controller on
>>>>>> the Microchip PolarFire SoC.
>>>>>>
>>>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>>>> ---
>>>>>> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
>>>>>> 1 file changed, 72 insertions(+)
>>>>>> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>>>>>>
>>>>>
>>>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>>>
>>>>> yamllint warnings/errors:
>>>>>
>>>>> dtschema/dtc warnings/errors:
>>>>> Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
>>>>> 19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
>>>> Rob,
>>>> Should I drop the header from the example or is there a way for me
>>>> specify the dependent patch to pass this check?
>>>
>>> The error has to be fixed, although not necessarily by dropping the
>>> header, but by posting it. How this can pass on your system? There is no
>>> such file added in this patchset.
>> I linked the patch adding the clock as a dependency in the cover letter
>> [1], which is why I was wondering if there was a better way to do so
>> that would get picked up by the checker bot.
>
> It's not only about the bot, but dependency when applied. If you did not
> warn clk maintainer that clock bindings should go via Rob's tree or
> should be provided as a tag, the patches here cannot be applied in this
> cycle.
It was not my (our) intention to send the clock patches via rob's tree.
And since this is my first time trying to upstream wholescale changes to
a device tree I honestly didn't expect this series to get accepted in
this cycle anyway.
>
> Best regards,
> Krzysztof
>

2021-11-09 13:36:14

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On 09/11/2021 12:56, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 09/11/2021 13:54, [email protected] wrote:
>> On 08/11/2021 21:16, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 08/11/2021 16:05, [email protected] wrote:
>>>> From: Conor Dooley <[email protected]>
>>>>
>>>> Add device tree bindings for the hardware rng device accessed via
>>>> the system services on the Microchip PolarFire SoC.
>>>>
>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>> ---
>>>> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
>>>> 1 file changed, 31 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>> new file mode 100644
>>>> index 000000000000..e8ecb3538a86
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>> @@ -0,0 +1,31 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>>> +
>>>> +title: Microchip MPFS random number generator
>>>> +
>>>> +maintainers:
>>>> + - Conor Dooley <[email protected]>
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + const: microchip,polarfire-soc-rng
>>>> +
>>>> + syscontroller:
>>>> + maxItems: 1
>>>> + description: name of the system controller device node
>>>
>>> There are several issues with this:
>>> 1. You need to describe the type.
>>> 2. Description is not helpful (just copying the name of property) and
>>> actually misleading because you do not put there the name of device node.
>>> 3. What is it? Looks like syscon (or sometimes called sysreg). If yes,
>>> please use existing syscon bindings.
>> 1 & 2 - Correct, it is bad & I'll write a better description for it.
>> 3 - Its a system controller implemented as a mailbox. The syscontroller
>> is the mailbox client, which the rng and generic drivers both use.
>
> I understood that pointed device node is a mailbox, not this node. But
> here, what is it here? How do you use it here?
The system controller is the means of access to the random number
generator. The phandle to the sys controller is provided here so that
the rng driver can locate the mailbox client through which it requests
random numbers.

I'm not quite sure that I am answering the question you are asking though.
>
> Best regards,
> Krzysztof
>

2021-11-09 15:21:02

[permalink] [raw]

Subject: Re: [PATCH 03/13] dt-bindings: soc/microchip: update sys ctrlr compat string

On 09/11/2021 08:33, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Mon, Nov 8, 2021 at 4:06 PM <[email protected]> wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Update 'compatible' strings for system controller drivers to the
>> approved Microchip name.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>
> Thanks for your patch!
>
>> --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
>> +++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
>> @@ -11,7 +11,9 @@ maintainers:
>>
>> properties:
>> compatible:
>> - const: microchip,polarfire-soc-mailbox
>> + enum:
>> + - microchip,polarfire-soc-mailbox
>> + - microchip,mpfs-mailbox
>
> Is there any point in keeping the old compatible value?
> Are there any real users? Most of the MPFS upstream DT is still in flux.
yeah, true. and now is as good a time as any to just outright change it.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>

2021-11-10 07:43:31

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On 09/11/2021 14:36, [email protected] wrote:
> On 09/11/2021 12:56, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 09/11/2021 13:54, [email protected] wrote:
>>> On 08/11/2021 21:16, Krzysztof Kozlowski wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 08/11/2021 16:05, [email protected] wrote:
>>>>> From: Conor Dooley <[email protected]>
>>>>>
>>>>> Add device tree bindings for the hardware rng device accessed via
>>>>> the system services on the Microchip PolarFire SoC.
>>>>>
>>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>>> ---
>>>>> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
>>>>> 1 file changed, 31 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..e8ecb3538a86
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>> @@ -0,0 +1,31 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>>>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>>>> +
>>>>> +title: Microchip MPFS random number generator
>>>>> +
>>>>> +maintainers:
>>>>> + - Conor Dooley <[email protected]>
>>>>> +
>>>>> +properties:
>>>>> + compatible:
>>>>> + const: microchip,polarfire-soc-rng
>>>>> +
>>>>> + syscontroller:
>>>>> + maxItems: 1
>>>>> + description: name of the system controller device node
>>>>
>>>> There are several issues with this:
>>>> 1. You need to describe the type.
>>>> 2. Description is not helpful (just copying the name of property) and
>>>> actually misleading because you do not put there the name of device node.
>>>> 3. What is it? Looks like syscon (or sometimes called sysreg). If yes,
>>>> please use existing syscon bindings.
>>> 1 & 2 - Correct, it is bad & I'll write a better description for it.
>>> 3 - Its a system controller implemented as a mailbox. The syscontroller
>>> is the mailbox client, which the rng and generic drivers both use.
>>
>> I understood that pointed device node is a mailbox, not this node. But
>> here, what is it here? How do you use it here?
> The system controller is the means of access to the random number
> generator. The phandle to the sys controller is provided here so that
> the rng driver can locate the mailbox client through which it requests
> random numbers.

I am asking this to understand whether there is a generic or existing
property which should be used instead.

If I understand correctly, the rng driver needs a mailbox client? If it
is mailbox client, then there is a property: "mboxes". Use this one
(look for existing bindings, e.g.
Documentation/devicetree/bindings/firmware/arm,scmi.yaml).

Best regards,
Krzysztof

2021-11-10 07:45:21

[permalink] [raw]

Subject: Re: [PATCH 10/13] dt-bindings: spi: add bindings for microchip mpfs spi

On 09/11/2021 14:20, [email protected] wrote:
> On 09/11/2021 13:04, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 09/11/2021 13:58, [email protected] wrote:
>>> On 09/11/2021 12:53, Krzysztof Kozlowski wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 09/11/2021 13:16, [email protected] wrote:
>>>>> On 09/11/2021 04:06, Rob Herring wrote:
>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>
>>>>>> On Mon, 08 Nov 2021 15:05:51 +0000, [email protected] wrote:
>>>>>>> From: Conor Dooley <[email protected]>
>>>>>>>
>>>>>>> Add device tree bindings for the {q,}spi controller on
>>>>>>> the Microchip PolarFire SoC.
>>>>>>>
>>>>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>>>>> ---
>>>>>>> .../bindings/spi/microchip,mpfs-spi.yaml | 72 +++++++++++++++++++
>>>>>>> 1 file changed, 72 insertions(+)
>>>>>>> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>>>>>>>
>>>>>>
>>>>>> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
>>>>>> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>>>>>>
>>>>>> yamllint warnings/errors:
>>>>>>
>>>>>> dtschema/dtc warnings/errors:
>>>>>> Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
>>>>>> 19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
>>>>> Rob,
>>>>> Should I drop the header from the example or is there a way for me
>>>>> specify the dependent patch to pass this check?
>>>>
>>>> The error has to be fixed, although not necessarily by dropping the
>>>> header, but by posting it. How this can pass on your system? There is no
>>>> such file added in this patchset.
>>> I linked the patch adding the clock as a dependency in the cover letter
>>> [1], which is why I was wondering if there was a better way to do so
>>> that would get picked up by the checker bot.
>>
>> It's not only about the bot, but dependency when applied. If you did not
>> warn clk maintainer that clock bindings should go via Rob's tree or
>> should be provided as a tag, the patches here cannot be applied in this
>> cycle.
> It was not my (our) intention to send the clock patches via rob's tree.
> And since this is my first time trying to upstream wholescale changes to
> a device tree I honestly didn't expect this series to get accepted in
> this cycle anyway.

OK :)

Assuming your new bindings pass db_binding_check with
DT_CHECKER_FLAGS=-m (on top of clock patch), I propose to keep the
header here.

Another idea would be to submit without the header and use raw IDs
(numbers) and convert it later. I prefer the first- base on clock patches.

Best regards,
Krzysztof

2021-11-10 09:46:36

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Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On 10/11/2021 07:43, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 09/11/2021 14:36, [email protected] wrote:
>> On 09/11/2021 12:56, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 09/11/2021 13:54, [email protected] wrote:
>>>> On 08/11/2021 21:16, Krzysztof Kozlowski wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On 08/11/2021 16:05, [email protected] wrote:
>>>>>> From: Conor Dooley <[email protected]>
>>>>>>
>>>>>> Add device tree bindings for the hardware rng device accessed via
>>>>>> the system services on the Microchip PolarFire SoC.
>>>>>>
>>>>>> Signed-off-by: Conor Dooley <[email protected]>
>>>>>> ---
>>>>>> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
>>>>>> 1 file changed, 31 insertions(+)
>>>>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>>> new file mode 100644
>>>>>> index 000000000000..e8ecb3538a86
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
>>>>>> @@ -0,0 +1,31 @@
>>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>>> +%YAML 1.2
>>>>>> +---
>>>>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
>>>>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>>>>> +
>>>>>> +title: Microchip MPFS random number generator
>>>>>> +
>>>>>> +maintainers:
>>>>>> + - Conor Dooley <[email protected]>
>>>>>> +
>>>>>> +properties:
>>>>>> + compatible:
>>>>>> + const: microchip,polarfire-soc-rng
>>>>>> +
>>>>>> + syscontroller:
>>>>>> + maxItems: 1
>>>>>> + description: name of the system controller device node
>>>>>
>>>>> There are several issues with this:
>>>>> 1. You need to describe the type.
>>>>> 2. Description is not helpful (just copying the name of property) and
>>>>> actually misleading because you do not put there the name of device node.
>>>>> 3. What is it? Looks like syscon (or sometimes called sysreg). If yes,
>>>>> please use existing syscon bindings.
>>>> 1 & 2 - Correct, it is bad & I'll write a better description for it.
>>>> 3 - Its a system controller implemented as a mailbox. The syscontroller
>>>> is the mailbox client, which the rng and generic drivers both use.
>>>
>>> I understood that pointed device node is a mailbox, not this node. But
>>> here, what is it here? How do you use it here?
>> The system controller is the means of access to the random number
>> generator. The phandle to the sys controller is provided here so that
>> the rng driver can locate the mailbox client through which it requests
>> random numbers.
>
> I am asking this to understand whether there is a generic or existing
> property which should be used instead.
>
> If I understand correctly, the rng driver needs a mailbox client?
Correct, it needs one. Binding for that is here:
Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> If it is a mailbox client, then there is a property: "mboxes". Use this one
> (look for existing bindings, e.g.
> Documentation/devicetree/bindings/firmware/arm,scmi.yaml).
>
>
> Best regards,
> Krzysztof
>

2021-11-10 12:07:21

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Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

On 08/11/2021 21:40, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 08/11/2021 16:05, [email protected] wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Update the device tree for the icicle kit by splitting it into a third part,
>> which contains peripherals in the fpga fabric, add new peripherals
>> (spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory
>> map which have been changed.
>
> This should be multiple commits because you mix up refactoring (split)
> and adding new features. The patch is really, really difficult to
> review. I gave up in the middle.
>
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> .../dts/microchip/microchip-mpfs-fabric.dtsi | 21 ++
>> .../microchip/microchip-mpfs-icicle-kit.dts | 159 +++++++--
>> .../boot/dts/microchip/microchip-mpfs.dtsi | 333 ++++++++++++++----
>> 3 files changed, 428 insertions(+), 85 deletions(-)
>> create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>> new file mode 100644
>> index 000000000000..8fa3356494f1
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>> @@ -0,0 +1,21 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>> +
>> +/ {
>> + fpgadma: fpgadma@60020000 {
>> + compatible = "microchip,mpfs-fpga-dma-uio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x0 0x60020000 0x0 0x1000>;
>> + interrupt-parent = <&plic>;
>> + interrupts = <PLIC_INT_FABRIC_F2H_2>;
>> + status = "okay";
>> + };
>> +
>> + fpgalsram: fpga_lsram@61000000 {
>
> Node names go with hyphen, but actually you should not need it, because
> the name should be generic, e.g. "uio".
sure, will change it to uio.
>
> However there is no such compatible and checkpatch should complain about it.
yeah, this and the pac1934 i didnt send bindings for - erroneously
thought i might not have to do so. ill get a binding sorted out for both
of these.
>
>> + compatible = "generic-uio";
>> + reg = <0x0 0x61000000 0x0 0x0001000
>> + 0x14 0x00000000 0x0 0x00010000>;
>> + status = "okay";
>> + };
>> +};
>> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> index fc1e5869df1b..4212129fcdf1 100644
>> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> @@ -1,5 +1,5 @@
>> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> -/* Copyright (c) 2020 Microchip Technology Inc */
>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>>
>> /dts-v1/;
>>
>> @@ -13,72 +13,187 @@ / {
>> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
>>
>> aliases {
>> - ethernet0 = &emac1;
>> - serial0 = &serial0;
>> - serial1 = &serial1;
>> - serial2 = &serial2;
>> - serial3 = &serial3;> + mmuart0 = &mmuart0;
>> + mmuart1 = &mmuart1;
>> + mmuart2 = &mmuart2;
>> + mmuart3 = &mmuart3;
>> + mmuart4 = &mmuart4;
>
> Why? Commit msg does not explain it.
changed to match all of our documentation
>
>> };
>>
>> chosen {
>> - stdout-path = "serial0:115200n8";
>> + stdout-path = "mmuart1:115200n8";
>> };
>>
>> cpus {
>> timebase-frequency = <RTCCLK_FREQ>;
>> };
>>
>> - memory@80000000 {
>> + ddrc_cache_lo: memory@80000000 {
>> device_type = "memory";
>> - reg = <0x0 0x80000000 0x0 0x40000000>;
>> - clocks = <&clkcfg 26>;
>> + reg = <0x0 0x80000000 0x0 0x2e000000>;
>> + clocks = <&clkcfg CLK_DDRC>;
>> + status = "okay";
>> + };
>> +
>> + ddrc_cache_hi: memory@1000000000 {
>> + device_type = "memory";
>> + reg = <0x10 0x0 0x0 0x40000000>;
>> + clocks = <&clkcfg CLK_DDRC>;
>> + status = "okay";
>> };
>> };
>>
>> -&serial0 {
>> +&mmuart1 {
>> status = "okay";
>> };
>>
>> -&serial1 {
>> +&mmuart2 {
>> status = "okay";
>> };
>>
>> -&serial2 {
>> +&mmuart3 {
>> status = "okay";
>> };
>>
>> -&serial3 {
>> +&mmuart4 {
>> status = "okay";
>> };
>>
>> &mmc {
>> status = "okay";
>> -
>> bus-width = <4>;
>> disable-wp;
>> cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> card-detect-delay = <200>;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> sd-uhs-sdr12;
>> sd-uhs-sdr25;
>> sd-uhs-sdr50;
>> sd-uhs-sdr104;
>> };
>>
>> -&emac0 {
>> +&spi0 {
>> + status = "okay";
>> + spidev@0 {
>> + compatible = "spidev";
>
> 1. There is no such compatible,
> 2. You should have big fat warning when booting, so such DT cannot be
> accepted.
this one was an oversight from me, that compatible has never been
"spidev" on its own in our internal stuff and i mustve accidentally
dropped a vendor string while making these patches.
>
>> + reg = <0>; /* CS 0 */
>> + spi-max-frequency = <10000000>;
>> + status = "okay";
>> + };
>> +};
>> +
>> +&spi1 {
>> + status = "okay";
>> +};
>> +
>> +&qspi {
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + pac193x: pac193x@10 {
>
> Generic node name. Looks like compatible is not documented, so first
> bindings.
>
as above
>
>> + compatible = "microchip,pac1934";
>> + reg = <0x10>;
>> + samp-rate = <64>;
>> + status = "okay";
>> + ch0: channel0 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDDREG";
>> + channel_enabled;
>> + };
>> + ch1: channel1 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDDA25";
>> + channel_enabled;
>> + };
>> + ch2: channel2 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDD25";
>> + channel_enabled;
>> + };
>> + ch3: channel3 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDDA_REG";
>> + channel_enabled;
>> + };
>> + };
>> +};
>> +
>> +&mac0 {
>> + status = "okay";
>> phy-mode = "sgmii";
>> phy-handle = <&phy0>;
>> - phy0: ethernet-phy@8 {
>> - reg = <8>;
>> - ti,fifo-depth = <0x01>;
>> - };
>> };
>>
>> -&emac1 {
>> +&mac1 {
>
> I gave up here, it's not easy to find what is effect of refactoring,
> what is a new node.
yeah, ill split it into several patches - probably one for the
splitting, one for the new defines, one for the changes to existing
nodes and one for node additions.
>
> Best regards,
> Krzysztof
>

2021-11-10 14:20:13

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Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

On 09/11/2021 09:04, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
>> From: Conor Dooley <[email protected]>
>>
>> Update the device tree for the icicle kit by splitting it into a third part,
>> which contains peripherals in the fpga fabric, add new peripherals
>> (spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory
>> map which have been changed.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>
> Thanks for your patch!
>
> Please split it into logical separated parts.
yeah, ive split it into several patches - one for the splitting into 3,
one for the new defines, one for the changes to existing nodes and one
for node additions.

>
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
>> @@ -0,0 +1,21 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>> +
>> +/ {
>> + fpgadma: fpgadma@60020000 {
>> + compatible = "microchip,mpfs-fpga-dma-uio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x0 0x60020000 0x0 0x1000>;
>> + interrupt-parent = <&plic>;
>> + interrupts = <PLIC_INT_FABRIC_F2H_2>;
>> + status = "okay";
>> + };
>> +
>> + fpgalsram: fpga_lsram@61000000 {
>> + compatible = "generic-uio";
>> + reg = <0x0 0x61000000 0x0 0x0001000
>> + 0x14 0x00000000 0x0 0x00010000>;
>
> Please group by angular brackets, to increase readability, and support
> automatic validation:
>
> <0x0 0x61000000 0x0 0x0001000>, <0x14 0x00000000 0x0 0x00010000>
>
>> + status = "okay";
>> + };
>
> Do we really want UIO nodes in upstream DT?
As I said in the replies to another patch this is my first time doing
any upstreaming of a device tree, i didnt realise that this would be a
problem.
>
>> +};
>> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> index fc1e5869df1b..4212129fcdf1 100644
>> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
>> @@ -1,5 +1,5 @@
>> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> -/* Copyright (c) 2020 Microchip Technology Inc */
>> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
>>
>> /dts-v1/;
>>
>> @@ -13,72 +13,187 @@ / {
>> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
>>
>> aliases {
>> - ethernet0 = &emac1;
>> - serial0 = &serial0;
>> - serial1 = &serial1;
>> - serial2 = &serial2;
>> - serial3 = &serial3;
>> + mmuart0 = &mmuart0;
>> + mmuart1 = &mmuart1;
>> + mmuart2 = &mmuart2;
>> + mmuart3 = &mmuart3;
>> + mmuart4 = &mmuart4;
>
> Why? SerialN is the standard alias name.
we changed the label to mmuart to match the microchip documentation.
would it make more sense to call mmuart but alias it to serial?
ie serial0 = &mmuart0;
>
>> };
>
>>
>> -&emac0 {
>> +&spi0 {
>> + status = "okay";
>> + spidev@0 {
>> + compatible = "spidev";
>
> Please don't use "spidev", but a proper compatible value describing
> what is really connected. If you want to use it with spidev (which
> is software policy, not hardware description), add that compatible
> value to drivers/spi/spidev.c:spidev_dt_ids[], or use driver_override
> in sysfs at runtime.
as i said to Krzysztof - this one was an oversight from me, that
compatible has never been "spidev" on its own in our internal tree and
i mustve accidentally omitted the vendor string while making these patches.

Either way, after talking some more we decided that this entry is not
appropriate anyway and i will drop it.
>
>> + reg = <0>; /* CS 0 */
>> + spi-max-frequency = <10000000>;
>> + status = "okay";
>> + };
>> +};
>> +
>> +&spi1 {
>> + status = "okay";
>
> No slave devices specified?
no, but its exposed
>
>> +};
>> +
>> +&qspi {
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + pac193x: pac193x@10 {
>
> adc@, I guess?
sure
>
>> + compatible = "microchip,pac1934";
>> + reg = <0x10>;
>> + samp-rate = <64>;
>> + status = "okay";
>> + ch0: channel0 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDDREG";
>> + channel_enabled;
>> + };
>> + ch1: channel1 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDDA25";
>> + channel_enabled;
>> + };
>> + ch2: channel2 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDD25";
>> + channel_enabled;
>> + };
>> + ch3: channel3 {
>> + uohms-shunt-res = <10000>;
>> + rail-name = "VDDA_REG";
>> + channel_enabled;
>> + };
>> + };
>> +};
>
>> +&gpio2 {
>> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT
>> + PLIC_INT_GPIO2_NON_DIRECT>;
>
> Why override interrupts in the board .dts file?
> Doesn't this belong in the SoC .dtsi file?
The interrupt setup for the gpio isnt fixed, there is an option to
either connect the individual gpio interrupts to the plic *or* they can
be connected to a per gpio controller common interrupt, and it is up to
the driver to read a register to determine which interrupt triggered the
common/NON_DIRECT interrupt. This decision is made by a write to a
system register in application code, which to us didn't seem like it
belonged in the soc .dtsi.

Using the common interrupt for GPIO2 is the default on the
polarfire-soc, there are only 38 per gpio line interrupts available of
which 14 are connected to gpio0 and 24 to gpio1.

> Please group using angular brackets.
>
>> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>
>> @@ -145,49 +149,55 @@ cpu4_intc: interrupt-controller {
>> soc {
>> #address-cells = <2>;
>> #size-cells = <2>;
>> - compatible = "simple-bus";
>> + compatible = "microchip,mpfs-soc", "simple-bus";
>> ranges;
>>
>> - cache-controller@2010000 {
>> + cctrllr: cache-controller@2010000 {
>> compatible = "sifive,fu540-c000-ccache", "cache";
>> + reg = <0x0 0x2010000 0x0 0x1000>;
>> + interrupt-parent = <&plic>;
>> + interrupts = <PLIC_INT_L2_METADATA_CORR
>> + PLIC_INT_L2_METADAT_UNCORR
>> + PLIC_INT_L2_DATA_CORR>;
>
> Please group using angular brackets.
>
>> cache-block-size = <64>;
>> cache-level = <2>;
>> cache-sets = <1024>;
>> cache-size = <2097152>;
>> cache-unified;
>> - interrupt-parent = <&plic>;
>> - interrupts = <1 2 3>;
>> - reg = <0x0 0x2010000 0x0 0x1000>;
>> };
>>
>> - clint@2000000 {
>> + clint: clint@2000000 {
>> compatible = "sifive,fu540-c000-clint", "sifive,clint0";
>> reg = <0x0 0x2000000 0x0 0xC000>;
>> - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
>> - &cpu1_intc 3 &cpu1_intc 7
>> - &cpu2_intc 3 &cpu2_intc 7
>> - &cpu3_intc 3 &cpu3_intc 7
>> - &cpu4_intc 3 &cpu4_intc 7>;
>> + interrupts-extended =
>> + <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER
>> + &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER
>> + &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER
>> + &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER
>> + &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>;
>
> Please group using angular brackets.
>
>> };
>>
>> plic: interrupt-controller@c000000 {
>> - #interrupt-cells = <1>;
>> - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
>> + compatible = "sifive,plic-1.0.0";
>
> Why drop the first one again?
we felt it didnt make sense to have something that specifically
references the fu540 in the device tree for this board.
>
>> reg = <0x0 0xc000000 0x0 0x4000000>;
>> + #interrupt-cells = <1>;
>> riscv,ndev = <186>;
>> interrupt-controller;
>> - interrupts-extended = <&cpu0_intc 11
>> - &cpu1_intc 11 &cpu1_intc 9
>> - &cpu2_intc 11 &cpu2_intc 9
>> - &cpu3_intc 11 &cpu3_intc 9
>> - &cpu4_intc 11 &cpu4_intc 9>;
>> + interrupts-extended = <&cpu0_intc HART_INT_M_EXT
>> + &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT
>> + &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT
>> + &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT
>> + &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>;
>> };
>>
>> - dma@3000000 {
>> - compatible = "sifive,fu540-c000-pdma";
>> + pdma: pdma@3000000 {
>> + compatible = "microchip,mpfs-pdma-uio";
>> reg = <0x0 0x3000000 0x0 0x8000>;
>> interrupt-parent = <&plic>;
>> - interrupts = <23 24 25 26 27 28 29 30>;
>> + interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR
>> + PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR
>> + PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR
>> + PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>;
>
> Please group using angular brackets.
>
>> #dma-cells = <1>;
>> };
>>
>> @@ -205,7 +215,7 @@ clkcfg: clkcfg@20002000 {
>> clocks = <&refclk>;
>> #clock-cells = <1>;
>> clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
>> - "mac0", "mac1", "mmc", "timer", /* 4-7 */
>> + "mac0", "mac1", "mmc", "timer", /* 4-7 */
>> "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
>> "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
>> "i2c1", "can0", "can1", "usb", /* 16-19 */
>
> No need for clock-output-names at all.
>
>>
>> - emac1: ethernet@20112000 {
>> + mac0: ethernet@20110000 {
>> compatible = "cdns,macb";
>> - reg = <0x0 0x20112000 0x0 0x2000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x0 0x20110000 0x0 0x2000>;
>> + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
>> + clock-names = "pclk", "hclk";
>> interrupt-parent = <&plic>;
>> - interrupts = <70 71 72 73>;
>> - local-mac-address = [00 00 00 00 00 00];
>> - clocks = <&clkcfg 5>, <&clkcfg 2>;
>> + interrupts = <PLIC_INT_MAC0_INT
>> + PLIC_INT_MAC0_QUEUE1
>> + PLIC_INT_MAC0_QUEUE2
>> + PLIC_INT_MAC0_QUEUE3
>> + PLIC_INT_MAC0_EMAC
>> + PLIC_INT_MAC0_MMSL>;
>
> Please group using angular brackets.
>
>> + mac-address = [56 34 12 00 FC 01];
>
> Please drop this.
Is the problem here having mac-address instead of local-, having either
at all or that we have populated it rather than just filling with 0s?
We set it in u-boot anyway, so I think dropping entirely is okay.
>
>> status = "disabled";
>> + };
>>
>> + rtc: rtc@20124000 {
>> + compatible = "microchip,mpfs-rtc";
>> #address-cells = <1>;
>> #size-cells = <0>;
>> + reg = <0x0 0x20124000 0x0 0x1000>;
>> + clocks = <&clkcfg CLK_RTC>;
>> + clock-names = "rtc";
>> + interrupt-parent = <&plic>;
>> + interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>;
>
> Please group using angular brackets.
>
>> + status = "disabled";
>> };
>>
>> + usb: usb@20201000 {
>> + compatible = "microchip,mpfs-usb-host";
>> + reg = <0x0 0x20201000 0x0 0x1000>;
>> + reg-names = "mc","control";
>> + clocks = <&clkcfg CLK_USB>;
>> + interrupt-parent = <&plic>;
>> + interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>;
>
> Please group using angular brackets.
>
>> + interrupt-names = "dma","mc";
>> + dr_mode = "host";
>> + status = "disabled";
>> + };
>> +
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>

2021-11-10 14:58:49

[permalink] [raw]

Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

Hi Conor,

On Wed, Nov 10, 2021 at 3:20 PM <[email protected]> wrote:
> On 09/11/2021 09:04, Geert Uytterhoeven wrote:
> > On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> >> From: Conor Dooley <[email protected]>
> >>
> >> Update the device tree for the icicle kit by splitting it into a third part,
> >> which contains peripherals in the fpga fabric, add new peripherals
> >> (spi, qspi, gpio, rtc, pcie, system services, i2c), update parts of the memory
> >> map which have been changed.
> >>
> >> Signed-off-by: Conor Dooley <[email protected]>

> As I said in the replies to another patch this is my first time doing
> any upstreaming of a device tree, i didnt realise that this would be a
> problem.

No problem, we're here to help you ;-)

> >> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> >> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> >> @@ -1,5 +1,5 @@
> >> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> -/* Copyright (c) 2020 Microchip Technology Inc */
> >> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> >>
> >> /dts-v1/;
> >>
> >> @@ -13,72 +13,187 @@ / {
> >> compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
> >>
> >> aliases {
> >> - ethernet0 = &emac1;
> >> - serial0 = &serial0;
> >> - serial1 = &serial1;
> >> - serial2 = &serial2;
> >> - serial3 = &serial3;
> >> + mmuart0 = &mmuart0;
> >> + mmuart1 = &mmuart1;
> >> + mmuart2 = &mmuart2;
> >> + mmuart3 = &mmuart3;
> >> + mmuart4 = &mmuart4;
> >
> > Why? SerialN is the standard alias name.
> we changed the label to mmuart to match the microchip documentation.

The serialN aliases are standardized, so you cannot change them.

> would it make more sense to call mmuart but alias it to serial?
> ie serial0 = &mmuart0;

You can change the labels, so that's OK.

> >> +&spi1 {
> >> + status = "okay";
> >
> > No slave devices specified?
> no, but its exposed

But without specifying slave devices first you cannot use the
controller anyway? While I2C supports instantiating slaves from
userspace by writing to the new_device file in sysfs, SPI doesn't
have that feature.

> >> +&gpio2 {
> >> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT
> >> + PLIC_INT_GPIO2_NON_DIRECT>;
> >
> > Why override interrupts in the board .dts file?
> > Doesn't this belong in the SoC .dtsi file?
> The interrupt setup for the gpio isnt fixed, there is an option to
> either connect the individual gpio interrupts to the plic *or* they can
> be connected to a per gpio controller common interrupt, and it is up to
> the driver to read a register to determine which interrupt triggered the
> common/NON_DIRECT interrupt. This decision is made by a write to a
> system register in application code, which to us didn't seem like it
> belonged in the soc .dtsi.

So it is software policy? Then it doesn't belong in the board DTS either.

> Using the common interrupt for GPIO2 is the default on the
> polarfire-soc, there are only 38 per gpio line interrupts available of
> which 14 are connected to gpio0 and 24 to gpio1.

> >> plic: interrupt-controller@c000000 {
> >> - #interrupt-cells = <1>;
> >> - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
> >> + compatible = "sifive,plic-1.0.0";
> >
> > Why drop the first one again?
> we felt it didnt make sense to have something that specifically
> references the fu540 in the device tree for this board.

That would be a revert of commit 73d3c44115514616 ("riscv: dts:
microchip: add missing compatibles for clint and plic"), which you
supplied an R-b tag for?

Is this the same plic as in the FU540 SoC? Or do we need a new
microchip,mpfs-plic compatible value?

> >> - emac1: ethernet@20112000 {
> >> + mac0: ethernet@20110000 {
> >> compatible = "cdns,macb";
> >> - reg = <0x0 0x20112000 0x0 0x2000>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + reg = <0x0 0x20110000 0x0 0x2000>;
> >> + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
> >> + clock-names = "pclk", "hclk";
> >> interrupt-parent = <&plic>;
> >> - interrupts = <70 71 72 73>;
> >> - local-mac-address = [00 00 00 00 00 00];
> >> - clocks = <&clkcfg 5>, <&clkcfg 2>;
> >> + interrupts = <PLIC_INT_MAC0_INT
> >> + PLIC_INT_MAC0_QUEUE1
> >> + PLIC_INT_MAC0_QUEUE2
> >> + PLIC_INT_MAC0_QUEUE3
> >> + PLIC_INT_MAC0_EMAC
> >> + PLIC_INT_MAC0_MMSL>;
> >
> > Please group using angular brackets.
> >
> >> + mac-address = [56 34 12 00 FC 01];
> >
> > Please drop this.
> Is the problem here having mac-address instead of local-, having either
> at all or that we have populated it rather than just filling with 0s?

MAC addresses are supposed to be unique.

> We set it in u-boot anyway, so I think dropping entirely is okay.

Exactly.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-10 15:07:23

[permalink] [raw]

Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

On 10/11/2021 14:58, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
>>>> plic: interrupt-controller@c000000 {
>>>> - #interrupt-cells = <1>;
>>>> - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
>>>> + compatible = "sifive,plic-1.0.0";
>>>
>>> Why drop the first one again?
>> we felt it didnt make sense to have something that specifically
>> references the fu540 in the device tree for this board.
>
> That would be a revert of commit 73d3c44115514616 ("riscv: dts:
> microchip: add missing compatibles for clint and plic"), which you
> supplied an R-b tag for?
>
> Is this the same plic as in the FU540 SoC? Or do we need a new
> microchip,mpfs-plic compatible value?
>
yeah, ignore that. i confused this change (which is an accidental
clobber) with another sifive compatible that was dropped for not being
relevant. hardly makes sense to drop this one when i kept it for the
clint and cache controller!

>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>

2021-11-15 15:40:48

[permalink] [raw]

Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

On 10/11/2021 14:58, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Wed, Nov 10, 2021 at 3:20 PM <[email protected]> wrote:
>> On 09/11/2021 09:04, Geert Uytterhoeven wrote:
>>> On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
>>>> From: Conor Dooley <[email protected]>
>>>>
>>>> +&gpio2 {
>>>> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT
>>>> + PLIC_INT_GPIO2_NON_DIRECT>;
>>>
>>> Why override interrupts in the board .dts file?
>>> Doesn't this belong in the SoC .dtsi file?
>> The interrupt setup for the gpio isnt fixed, there is an option to
>> either connect the individual gpio interrupts to the plic *or* they can
>> be connected to a per gpio controller common interrupt, and it is up to
>> the driver to read a register to determine which interrupt triggered the
>> common/NON_DIRECT interrupt. This decision is made by a write to a
>> system register in application code, which to us didn't seem like it
>> belonged in the soc .dtsi.
>
> So it is software policy? Then it doesn't belong in the board DTS either.
The write (if was to be done) would be done by the bootloader, based on
the bitstream written to the FPGA, before even u-boot is started. By
application I meant the bootloader (or some other bare metal
application), not a program running in userspace in case that's what you
interpreted. Am I incorrect in thinking that if it is set up by the
bootloader that Linux can take it for granted?
>
>> Using the common interrupt for GPIO2 is the default on the
>> polarfire-soc, there are only 38 per gpio line interrupts available of
>> which 14 are connected to gpio0 and 24 to gpio1.
>
>
> Exactly.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>

2021-11-15 16:19:24

[permalink] [raw]

Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

Hi Conor,

On Mon, Nov 15, 2021 at 4:39 PM <[email protected]> wrote:
> On 10/11/2021 14:58, Geert Uytterhoeven wrote:
> > On Wed, Nov 10, 2021 at 3:20 PM <[email protected]> wrote:
> >> On 09/11/2021 09:04, Geert Uytterhoeven wrote:
> >>> On Mon, Nov 8, 2021 at 4:07 PM <[email protected]> wrote:
> >>>> From: Conor Dooley <[email protected]>
> >>>>
> >>>> +&gpio2 {
> >>>> + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT
> >>>> + PLIC_INT_GPIO2_NON_DIRECT>;
> >>>
> >>> Why override interrupts in the board .dts file?
> >>> Doesn't this belong in the SoC .dtsi file?
> >> The interrupt setup for the gpio isnt fixed, there is an option to
> >> either connect the individual gpio interrupts to the plic *or* they can
> >> be connected to a per gpio controller common interrupt, and it is up to
> >> the driver to read a register to determine which interrupt triggered the
> >> common/NON_DIRECT interrupt. This decision is made by a write to a
> >> system register in application code, which to us didn't seem like it
> >> belonged in the soc .dtsi.
> >
> > So it is software policy? Then it doesn't belong in the board DTS either.
>
> The write (if was to be done) would be done by the bootloader, based on
> the bitstream written to the FPGA, before even u-boot is started. By
> application I meant the bootloader (or some other bare metal
> application), not a program running in userspace in case that's what you
> interpreted. Am I incorrect in thinking that if it is set up by the
> bootloader that Linux can take it for granted?

If it is to be provided by the boot loader, the boot loader should fill
in the interrupts property, just like it already does (or should do, if it
doesn't) for /memory and chosen/bootargs.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2021-11-17 12:18:07

by Daire McNamara

[permalink] [raw]

Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit device tree

On Mon, 2021-11-15 at 17:17 +0100, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> Hi Conor,
>
> On Mon, Nov 15, 2021 at 4:39 PM <[email protected]> wrote:
> > On 10/11/2021 14:58, Geert Uytterhoeven wrote:
> > > On Wed, Nov 10, 2021 at 3:20 PM <[email protected]>
> > > wrote:
> > > > On 09/11/2021 09:04, Geert Uytterhoeven wrote:
> > > > > On Mon, Nov 8, 2021 at 4:07 PM <[email protected]>
> > > > > wrote:
> > > > > > From: Conor Dooley <[email protected]>
> > > > > >
> > > > > > +&gpio2 {
> > > > > > + interrupts = <PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT
> > > > > > + PLIC_INT_GPIO2_NON_DIRECT>;
> > > > >
> > > > > Why override interrupts in the board .dts file?
> > > > > Doesn't this belong in the SoC .dtsi file?
> > > > The interrupt setup for the gpio isnt fixed, there is an option
> > > > to
> > > > either connect the individual gpio interrupts to the plic *or*
> > > > they can
> > > > be connected to a per gpio controller common interrupt, and it
> > > > is up to
> > > > the driver to read a register to determine which interrupt
> > > > triggered the
> > > > common/NON_DIRECT interrupt. This decision is made by a write
> > > > to a
> > > > system register in application code, which to us didn't seem
> > > > like it
> > > > belonged in the soc .dtsi.
> > >
> > > So it is software policy? Then it doesn't belong in the board DTS
> > > either.
> >
> > The write (if was to be done) would be done by the bootloader,
> > based on
> > the bitstream written to the FPGA, before even u-boot is started.
> > By
> > application I meant the bootloader (or some other bare metal
> > application), not a program running in userspace in case that's
> > what you
> > interpreted. Am I incorrect in thinking that if it is set up by the
> > bootloader that Linux can take it for granted?
>
> If it is to be provided by the boot loader, the boot loader should
> fill
> in the interrupts property, just like it already does (or should do,
> if it
> doesn't) for /memory and chosen/bootargs.
Whether a given GPIO is routed via a bank where it has its own
interrupt line or via a bank where it shares an interrupt line is an
SoC capability. A particular routing is instantiated by a particular
board (e.g. Icicle). A custom bootloader feels like complete overkill
for this job.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
> [email protected]
>
> In personal conversations with technical people, I call myself a
> hacker. But
> when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds

2021-11-23 11:08:17

by Heiko Stübner

[permalink] [raw]

Subject: Re: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts

Am Montag, 8. November 2021, 16:05:42 CET schrieb [email protected]:
> From: Ivan Griffin <[email protected]>
>
> Provide named identifiers for device tree for RISC-V interrupts.
>
> Licensed under GPL and MIT, as this file may be useful to any OS that
> uses device tree.
>
> Signed-off-by: Ivan Griffin <[email protected]>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
>
> diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
> new file mode 100644
> index 000000000000..e1c32f6090ac
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +
> +#define HART_INT_U_SOFT 0
> +#define HART_INT_S_SOFT 1
> +#define HART_INT_M_SOFT 3
> +#define HART_INT_U_TIMER 4
> +#define HART_INT_S_TIMER 5
> +#define HART_INT_M_TIMER 7
> +#define HART_INT_U_EXT 8
> +#define HART_INT_S_EXT 9
> +#define HART_INT_M_EXT 11

(1) From checking clic doc [0] I see an additional
12 CLIC software interrupt
defined.

(2) The doc states that the ordering is a recommendation and
"not mandatory in all incarnations of the CLIC"
Is that clarified somewhere else that this more than recommended?

Thanks
Heiko

[0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc

> +
> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
>

2021-11-23 11:17:36

by Heiko Stübner

[permalink] [raw]

Subject: Re: [PATCH 02/13] dt-bindings: interrupt-controller: add defines for mpfs-plic

Hi,

Am Montag, 8. November 2021, 16:05:43 CET schrieb [email protected]:
> From: Ivan Griffin <[email protected]>
>
> Add device tree bindings for the Microchip Polarfire Soc interrupt
> controller
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Ivan Griffin <[email protected]>
> ---
> .../microchip,mpfs-plic.h | 199 ++++++++++++++++++
> 1 file changed, 199 insertions(+)
> create mode 100644 include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h
>
> diff --git a/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h
> new file mode 100644
> index 000000000000..81c8cd02abd8
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h
> @@ -0,0 +1,199 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
> +
> +#define PLIC_INT_INVALID 0
> +#define PLIC_INT_L2_METADATA_CORR 1
> +#define PLIC_INT_L2_METADAT_UNCORR 2
> +#define PLIC_INT_L2_DATA_CORR 3
> +#define PLIC_INT_L2_DATA_UNCORR 4
> +#define PLIC_INT_DMA_CH0_DONE 5
> +#define PLIC_INT_DMA_CH0_ERR 6
> +#define PLIC_INT_DMA_CH1_DONE 7
> +#define PLIC_INT_DMA_CH1_ERR 8
> +#define PLIC_INT_DMA_CH2_DONE 9
> +#define PLIC_INT_DMA_CH2_ERR 10
> +#define PLIC_INT_DMA_CH3_DONE 11
> +#define PLIC_INT_DMA_CH3_ERR 12
> +
> +#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13
> +#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14
> +#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15
> +#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16
> +#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17
> +#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18
> +#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19
> +#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20
> +#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21
> +#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22
> +#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23
> +#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24
> +#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25
> +#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26
> +#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27
> +#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28
> +#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29
> +#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30
> +#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31
> +#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32
> +#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33
> +#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34
> +#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35
> +#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36
> +#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37
> +#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38
> +#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39
> +#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40
> +#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41
> +#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42
> +#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43
> +#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44
> +#define PLIC_INT_GPIO1_BIT18 45
> +#define PLIC_INT_GPIO1_BIT19 46
> +#define PLIC_INT_GPIO1_BIT20 47
> +#define PLIC_INT_GPIO1_BIT21 48
> +#define PLIC_INT_GPIO1_BIT22 49
> +#define PLIC_INT_GPIO1_BIT23 50
> +#define PLIC_INT_GPIO0_NON_DIRECT 51
> +#define PLIC_INT_GPIO1_NON_DIRECT 52
> +#define PLIC_INT_GPIO2_NON_DIRECT 53
> +#define PLIC_INT_SPI0 54
> +#define PLIC_INT_SPI1 55
> +#define PLIC_INT_CAN0 56
> +#define PLIC_INT_CAN1 57
> +#define PLIC_INT_I2C0_MAIN 58
> +#define PLIC_INT_I2C0_ALERT 59
> +#define PLIC_INT_I2C0_SUS 60
> +#define PLIC_INT_I2C1_MAIN 61
> +#define PLIC_INT_I2C1_ALERT 62
> +#define PLIC_INT_I2C1_SUS 63
> +#define PLIC_INT_MAC0_INT 64
> +#define PLIC_INT_MAC0_QUEUE1 65
> +#define PLIC_INT_MAC0_QUEUE2 66
> +#define PLIC_INT_MAC0_QUEUE3 67
> +#define PLIC_INT_MAC0_EMAC 68
> +#define PLIC_INT_MAC0_MMSL 69
> +#define PLIC_INT_MAC1_INT 70
> +#define PLIC_INT_MAC1_QUEUE1 71
> +#define PLIC_INT_MAC1_QUEUE2 72
> +#define PLIC_INT_MAC1_QUEUE3 73
> +#define PLIC_INT_MAC1_EMAC 74
> +#define PLIC_INT_MAC1_MMSL 75
> +#define PLIC_INT_DDRC_TRAIN 76
> +#define PLIC_INT_SCB_INTERRUPT 77
> +#define PLIC_INT_ECC_ERROR 78
> +#define PLIC_INT_ECC_CORRECT 79
> +#define PLIC_INT_RTC_WAKEUP 80
> +#define PLIC_INT_RTC_MATCH 81
> +#define PLIC_INT_TIMER1 82
> +#define PLIC_INT_TIMER2 83
> +#define PLIC_INT_ENVM 84
> +#define PLIC_INT_QSPI 85
> +#define PLIC_INT_USB_DMA 86
> +#define PLIC_INT_USB_MC 87
> +#define PLIC_INT_MMC_MAIN 88
> +#define PLIC_INT_MMC_WAKEUP 89
> +#define PLIC_INT_MMUART0 90
> +#define PLIC_INT_MMUART1 91
> +#define PLIC_INT_MMUART2 92
> +#define PLIC_INT_MMUART3 93
> +#define PLIC_INT_MMUART4 94
> +#define PLIC_INT_G5C_DEVRST 95
> +#define PLIC_INT_G5C_MESSAGE 96
> +#define PLIC_INT_USOC_VC_INTERRUPT 97
> +#define PLIC_INT_USOC_SMB_INTERRUPT 98
> +#define PLIC_INT_E51_0_MAINTENACE 99
> +#define PLIC_INT_WDOG0_MRVP 100
> +#define PLIC_INT_WDOG1_MRVP 101
> +#define PLIC_INT_WDOG2_MRVP 102
> +#define PLIC_INT_WDOG3_MRVP 103
> +#define PLIC_INT_WDOG4_MRVP 104
> +#define PLIC_INT_WDOG0_TOUT 105
> +#define PLIC_INT_WDOG1_TOUT 106
> +#define PLIC_INT_WDOG2_TOUT 107
> +#define PLIC_INT_WDOG3_TOUT 108
> +#define PLIC_INT_WDOG4_TOUT 109
> +#define PLIC_INT_G5C_MSS_SPI 110
> +#define PLIC_INT_VOLT_TEMP_ALARM 111
> +#define PLIC_INT_ATHENA_COMPLETE 112
> +#define PLIC_INT_ATHENA_ALARM 113
> +#define PLIC_INT_ATHENA_BUS_ERROR 114
> +#define PLIC_INT_USOC_AXIC_US 115
> +#define PLIC_INT_USOC_AXIC_DS 116
> +#define PLIC_INT_SPARE 117
> +
> +#define PLIC_INT_FABRIC_F2H_0 118
> +#define PLIC_INT_FABRIC_F2H_1 119
> +#define PLIC_INT_FABRIC_F2H_2 120
> +#define PLIC_INT_FABRIC_F2H_3 121
> +#define PLIC_INT_FABRIC_F2H_4 122
> +#define PLIC_INT_FABRIC_F2H_5 123
> +#define PLIC_INT_FABRIC_F2H_6 124
> +#define PLIC_INT_FABRIC_F2H_7 125
> +#define PLIC_INT_FABRIC_F2H_8 126
> +#define PLIC_INT_FABRIC_F2H_9 127
> +#define PLIC_INT_FABRIC_F2H_10 128
> +#define PLIC_INT_FABRIC_F2H_11 129
> +#define PLIC_INT_FABRIC_F2H_12 130
> +#define PLIC_INT_FABRIC_F2H_13 131
> +#define PLIC_INT_FABRIC_F2H_14 132
> +#define PLIC_INT_FABRIC_F2H_15 133
> +#define PLIC_INT_FABRIC_F2H_16 134
> +#define PLIC_INT_FABRIC_F2H_17 135
> +#define PLIC_INT_FABRIC_F2H_18 136
> +#define PLIC_INT_FABRIC_F2H_19 137
> +#define PLIC_INT_FABRIC_F2H_20 138
> +#define PLIC_INT_FABRIC_F2H_21 139
> +#define PLIC_INT_FABRIC_F2H_22 140
> +#define PLIC_INT_FABRIC_F2H_23 141
> +#define PLIC_INT_FABRIC_F2H_24 142
> +#define PLIC_INT_FABRIC_F2H_25 143
> +#define PLIC_INT_FABRIC_F2H_26 144
> +#define PLIC_INT_FABRIC_F2H_27 145
> +#define PLIC_INT_FABRIC_F2H_28 146
> +#define PLIC_INT_FABRIC_F2H_29 147
> +#define PLIC_INT_FABRIC_F2H_30 148
> +#define PLIC_INT_FABRIC_F2H_31 149
> +#define PLIC_INT_FABRIC_F2H_32 150
> +#define PLIC_INT_FABRIC_F2H_33 151
> +#define PLIC_INT_FABRIC_F2H_34 152
> +#define PLIC_INT_FABRIC_F2H_35 153
> +#define PLIC_INT_FABRIC_F2H_36 154
> +#define PLIC_INT_FABRIC_F2H_37 155
> +#define PLIC_INT_FABRIC_F2H_38 156
> +#define PLIC_INT_FABRIC_F2H_39 157
> +#define PLIC_INT_FABRIC_F2H_40 158
> +#define PLIC_INT_FABRIC_F2H_41 159
> +#define PLIC_INT_FABRIC_F2H_42 160
> +#define PLIC_INT_FABRIC_F2H_43 161
> +#define PLIC_INT_FABRIC_F2H_44 162
> +#define PLIC_INT_FABRIC_F2H_45 163
> +#define PLIC_INT_FABRIC_F2H_46 164
> +#define PLIC_INT_FABRIC_F2H_47 165
> +#define PLIC_INT_FABRIC_F2H_48 166
> +#define PLIC_INT_FABRIC_F2H_49 167
> +#define PLIC_INT_FABRIC_F2H_50 168
> +#define PLIC_INT_FABRIC_F2H_51 169
> +#define PLIC_INT_FABRIC_F2H_52 170
> +#define PLIC_INT_FABRIC_F2H_53 171
> +#define PLIC_INT_FABRIC_F2H_54 172
> +#define PLIC_INT_FABRIC_F2H_55 173
> +#define PLIC_INT_FABRIC_F2H_56 174
> +#define PLIC_INT_FABRIC_F2H_57 175
> +#define PLIC_INT_FABRIC_F2H_58 176
> +#define PLIC_INT_FABRIC_F2H_59 177
> +#define PLIC_INT_FABRIC_F2H_60 178
> +#define PLIC_INT_FABRIC_F2H_61 179
> +#define PLIC_INT_FABRIC_F2H_62 180
> +#define PLIC_INT_FABRIC_F2H_63 181
> +#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182
> +#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183
> +#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184
> +#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185
> +#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186

Some thoughts I had while reading the patch:

(1) Are these constants really helpful?
- the PLIC is part of the soc, so most references will be handled in
the core soc dtsi - and only once - and no board devicetree will
likely need to handle them at all
- named constants are helpful if they make the number clearer
but PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2
or PLIC_INT_FABRIC_F2H_47 (and friends) probably do not really
provide any additional value to someone reading the devicetree source

(2) If they should stay, they probably need a different prefix as they're
pretty specific to the plic on the polarfire soc, so maybe
MPFS_PLIC_* ?

Heiko

> +
> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */
>

2021-11-23 11:24:25

by Heiko Stübner

[permalink] [raw]

Subject: Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

Am Dienstag, 9. November 2021, 14:04:45 CET schrieb Geert Uytterhoeven:
> Hi Conor,
>
> On Tue, Nov 9, 2021 at 1:08 PM <[email protected]> wrote:
> > On 09/11/2021 08:34, Geert Uytterhoeven wrote:
> > > On Mon, Nov 8, 2021 at 4:06 PM <[email protected]> wrote:
> > >> From: Conor Dooley <[email protected]>
> > >>
> > >> Add mpfs-soc to clear undocumented binding warning
> > >>
> > >> Signed-off-by: Conor Dooley <[email protected]>
>
> > >> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
> > >> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> > >> @@ -21,6 +21,7 @@ properties:
> > >> - enum:
> > >> - microchip,mpfs-icicle-kit
> > >> - const: microchip,mpfs
> > >> + - const: microchip,mpfs-soc
> > >
> > > Doesn't the "s" in "mpfs" already stand for "soc"?
> > not wrong, but using mpf-soc would be confusing since "mpf" is the part
> > name for the non soc fpga. is it fine to just reuse "mpfs" for the dtsi
> > overall compatible and for the soc subsection?
>
> I really meant: what is the difference between "microchip,mpfs" and
> "microchip,mpfs-soc"? Can't you just use the former?

definitly agreed :-)

Having the board named as
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"
sounds the most sensible.

As Conor wrote, "mpfs" is the name of the soc itself - with mpf being
the fpga part, so that would follow what boards in other parts of the
kernel do.

Heiko

2021-11-23 11:35:58

by Anup Patel

[permalink] [raw]

Subject: Re: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts

On Tue, Nov 23, 2021 at 4:38 PM Heiko Stübner <[email protected]> wrote:
>
> Am Montag, 8. November 2021, 16:05:42 CET schrieb [email protected]:
> > From: Ivan Griffin <[email protected]>
> >
> > Provide named identifiers for device tree for RISC-V interrupts.
> >
> > Licensed under GPL and MIT, as this file may be useful to any OS that
> > uses device tree.
> >
> > Signed-off-by: Ivan Griffin <[email protected]>
> > Signed-off-by: Conor Dooley <[email protected]>
> > ---
> > .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
> >
> > diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
> > new file mode 100644
> > index 000000000000..e1c32f6090ac
> > --- /dev/null
> > +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> > +/*
> > + * Copyright (C) 2021 Microchip Technology Inc. All rights reserved.
> > + */
> > +
> > +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> > +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> > +
> > +#define HART_INT_U_SOFT 0
> > +#define HART_INT_S_SOFT 1
> > +#define HART_INT_M_SOFT 3
> > +#define HART_INT_U_TIMER 4
> > +#define HART_INT_S_TIMER 5
> > +#define HART_INT_M_TIMER 7
> > +#define HART_INT_U_EXT 8
> > +#define HART_INT_S_EXT 9
> > +#define HART_INT_M_EXT 11
>
> (1) From checking clic doc [0] I see an additional
> 12 CLIC software interrupt
> defined.

Local IRQ #12 is for S-mode guest external interrupts as-per
the ratified H-extension specification.

I guess CLIC spec needs to be updated.

Regards,
Anup

>
> (2) The doc states that the ordering is a recommendation and
> "not mandatory in all incarnations of the CLIC"
> Is that clarified somewhere else that this more than recommended?
>
> Thanks
> Heiko
>
>
> [0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc
>
> > +
> > +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
> >
>
>
>
>

2021-11-29 19:58:26

[permalink] [raw]

Subject: Re: [PATCH 02/13] dt-bindings: interrupt-controller: add defines for mpfs-plic

On Mon, Nov 08, 2021 at 03:05:43PM +0000, [email protected] wrote:
> From: Ivan Griffin <[email protected]>
>
> Add device tree bindings for the Microchip Polarfire Soc interrupt
> controller
>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Ivan Griffin <[email protected]>
> ---
> .../microchip,mpfs-plic.h | 199 ++++++++++++++++++
> 1 file changed, 199 insertions(+)
> create mode 100644 include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h

Notice how there are not SoC interrupt defines in this directory. That's
because we don't do defines for them. The 'rule' is only defines for
made up numbers which are not in a reference manual.

Rob

2021-11-29 19:59:45

[permalink] [raw]

Subject: Re: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts

On Mon, 08 Nov 2021 15:05:42 +0000, [email protected] wrote:
> From: Ivan Griffin <[email protected]>
>
> Provide named identifiers for device tree for RISC-V interrupts.
>
> Licensed under GPL and MIT, as this file may be useful to any OS that
> uses device tree.
>
> Signed-off-by: Ivan Griffin <[email protected]>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../interrupt-controller/riscv-hart.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
>

Acked-by: Rob Herring <[email protected]>

2021-11-29 20:05:34

[permalink] [raw]

Subject: Re: [PATCH 03/13] dt-bindings: soc/microchip: update sys ctrlr compat string

On Mon, Nov 08, 2021 at 03:05:44PM +0000, [email protected] wrote:
> From: Conor Dooley <[email protected]>
>
> Update 'compatible' strings for system controller drivers to the
> approved Microchip name.

Why do I care what Microchip approved? You all picked identifiers
(that's all it is) and now get to live with them.

>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../bindings/mailbox/microchip,polarfire-soc-mailbox.yaml | 4 +++-
> .../soc/microchip/microchip,polarfire-soc-sys-controller.yaml | 4 +++-
> drivers/mailbox/mailbox-mpfs.c | 1 +
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> index bbb173ea483c..b08c8a158eea 100644
> --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> @@ -11,7 +11,9 @@ maintainers:
>
> properties:
> compatible:
> - const: microchip,polarfire-soc-mailbox
> + enum:
> + - microchip,polarfire-soc-mailbox
> + - microchip,mpfs-mailbox
>
> reg:
> items:
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> index 2cd3bc6bd8d6..d6c953cd154b 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> @@ -19,7 +19,9 @@ properties:
> maxItems: 1
>
> compatible:
> - const: microchip,polarfire-soc-sys-controller
> + enum:
> + - microchip,polarfire-soc-sys-controller
> + - microchip,mpfs-sys-controller
>
> required:
> - compatible
> diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
> index 0d6e2231a2c7..9d5e558a6ee6 100644
> --- a/drivers/mailbox/mailbox-mpfs.c
> +++ b/drivers/mailbox/mailbox-mpfs.c
> @@ -233,6 +233,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev)
>
> static const struct of_device_id mpfs_mbox_of_match[] = {
> {.compatible = "microchip,polarfire-soc-mailbox", },
> + {.compatible = "microchip,mpfs-mailbox", },
> {},
> };
> MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
> --
> 2.33.1
>
>

2021-11-29 20:11:04

[permalink] [raw]

Subject: Re: [PATCH 06/13] dt-bindings: rng: add bindings for microchip mpfs rng

On Wed, Nov 10, 2021 at 09:46:23AM +0000, [email protected] wrote:
> On 10/11/2021 07:43, Krzysztof Kozlowski wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 09/11/2021 14:36, [email protected] wrote:
> >> On 09/11/2021 12:56, Krzysztof Kozlowski wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> On 09/11/2021 13:54, [email protected] wrote:
> >>>> On 08/11/2021 21:16, Krzysztof Kozlowski wrote:
> >>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>>>
> >>>>> On 08/11/2021 16:05, [email protected] wrote:
> >>>>>> From: Conor Dooley <[email protected]>
> >>>>>>
> >>>>>> Add device tree bindings for the hardware rng device accessed via
> >>>>>> the system services on the Microchip PolarFire SoC.
> >>>>>>
> >>>>>> Signed-off-by: Conor Dooley <[email protected]>
> >>>>>> ---
> >>>>>> .../bindings/rng/microchip,mpfs-rng.yaml | 31 +++++++++++++++++++
> >>>>>> 1 file changed, 31 insertions(+)
> >>>>>> create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> >>>>>> new file mode 100644
> >>>>>> index 000000000000..e8ecb3538a86
> >>>>>> --- /dev/null
> >>>>>> +++ b/Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
> >>>>>> @@ -0,0 +1,31 @@
> >>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >>>>>> +%YAML 1.2
> >>>>>> +---
> >>>>>> +$id: "http://devicetree.org/schemas/rng/microchip,mpfs-rng.yaml#"
> >>>>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> >>>>>> +
> >>>>>> +title: Microchip MPFS random number generator
> >>>>>> +
> >>>>>> +maintainers:
> >>>>>> + - Conor Dooley <[email protected]>
> >>>>>> +
> >>>>>> +properties:
> >>>>>> + compatible:
> >>>>>> + const: microchip,polarfire-soc-rng
> >>>>>> +
> >>>>>> + syscontroller:
> >>>>>> + maxItems: 1
> >>>>>> + description: name of the system controller device node
> >>>>>
> >>>>> There are several issues with this:
> >>>>> 1. You need to describe the type.
> >>>>> 2. Description is not helpful (just copying the name of property) and
> >>>>> actually misleading because you do not put there the name of device node.
> >>>>> 3. What is it? Looks like syscon (or sometimes called sysreg). If yes,
> >>>>> please use existing syscon bindings.
> >>>> 1 & 2 - Correct, it is bad & I'll write a better description for it.
> >>>> 3 - Its a system controller implemented as a mailbox. The syscontroller
> >>>> is the mailbox client, which the rng and generic drivers both use.
> >>>
> >>> I understood that pointed device node is a mailbox, not this node. But
> >>> here, what is it here? How do you use it here?
> >> The system controller is the means of access to the random number
> >> generator. The phandle to the sys controller is provided here so that
> >> the rng driver can locate the mailbox client through which it requests
> >> random numbers.
> >
> > I am asking this to understand whether there is a generic or existing
> > property which should be used instead.
> >
> > If I understand correctly, the rng driver needs a mailbox client?
> Correct, it needs one. Binding for that is here:
> Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml

The rng node and others should be a child of the sys controller node.

Rob

2021-11-30 08:16:08

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Subject: Re: [PATCH 02/13] dt-bindings: interrupt-controller: add defines for mpfs-plic

On 29/11/2021 19:56, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Nov 08, 2021 at 03:05:43PM +0000, [email protected] wrote:
>> From: Ivan Griffin <[email protected]>
>>
>> Add device tree bindings for the Microchip Polarfire Soc interrupt
>> controller
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> Signed-off-by: Ivan Griffin <[email protected]>
>> ---
>> .../microchip,mpfs-plic.h | 199 ++++++++++++++++++
>> 1 file changed, 199 insertions(+)
>> create mode 100644 include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h
>
> Notice how there are not SoC interrupt defines in this directory. That's
> because we don't do defines for them. The 'rule' is only defines for
> made up numbers which are not in a reference manual.
Oh fair enough, I will drop these changes for V2 so. Thanks.
>
> Rob
>

2021-11-30 08:35:44