Hi!
A representative from SiLabs writes: "All the currently published versions
of the Si5351 (v1.0) and AN619 (v0.6) do not include the “Si5351A/C only”
disclaimer. Based on this and our current understanding, I see no issue
performing a PLLB reset for ‘B’ type devices.". Hence, it should not be
any issues always performing the PLL reset.
Changes in v2:
- Output disabling and power down removed in order to prevent
breaking systems requiring always-enabled clocks
- Cosmetic changes
Jacob
Jacob Siverskog (1):
clk: si5351: Add PLL soft reset
drivers/clk/clk-si5351.c | 6 ++++++
1 file changed, 6 insertions(+)
--
2.6.3
This is according to figure 12 ("I2C Programming Procedure") in
"Si5351A/B/C Data Sheet"
(https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf).
Without the PLL soft reset, we were unable to get three outputs
working at the same time.
According to Silicon Labs support, performing PLL soft reset will only
be noticeable if the PLL parameters have been changed.
Signed-off-by: Jacob Siverskog <[email protected]>
Signed-off-by: Jens Rudberg <[email protected]>
---
drivers/clk/clk-si5351.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index e346b22..984c058 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1091,6 +1091,12 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
SI5351_CLK_POWERDOWN, 0);
+ /* do a pll soft reset on both plls, needed in some cases to get all
+ * outputs running
+ */
+ si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
+ SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
+
dev_dbg(&hwdata->drvdata->client->dev,
"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
__func__, clk_hw_get_name(hw), (1 << rdiv),
--
2.6.3
On 20.11.2015 18:22, Jacob Siverskog wrote:
> This is according to figure 12 ("I2C Programming Procedure") in
> "Si5351A/B/C Data Sheet"
> (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf).
>
> Without the PLL soft reset, we were unable to get three outputs
> working at the same time.
>
> According to Silicon Labs support, performing PLL soft reset will only
> be noticeable if the PLL parameters have been changed.
>
> Signed-off-by: Jacob Siverskog <[email protected]>
> Signed-off-by: Jens Rudberg <[email protected]>
> ---
> drivers/clk/clk-si5351.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
> index e346b22..984c058 100644
> --- a/drivers/clk/clk-si5351.c
> +++ b/drivers/clk/clk-si5351.c
> @@ -1091,6 +1091,12 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
> si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
> SI5351_CLK_POWERDOWN, 0);
>
> + /* do a pll soft reset on both plls, needed in some cases to get all
> + * outputs running
> + */
Common convention for multi-line comments usually is:
/*
* Do a PLL soft reset on both PLLs required to get
* all outputs running.
*/
After you fixed the style issue, you can add my
Acked-by: Sebastian Hesselbarth <[email protected]>
Thanks!
> + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
> + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
> +
> dev_dbg(&hwdata->drvdata->client->dev,
> "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
> __func__, clk_hw_get_name(hw), (1 << rdiv),
>
Hi!
Changes in v3:
- Fix multiline comment style
Changes in v2:
- Output disabling and power down removed in order to prevent
breaking systems requiring always-enabled clocks
- Cosmetic changes
Jacob
Jacob Siverskog (1):
clk: si5351: Add PLL soft reset
drivers/clk/clk-si5351.c | 7 +++++++
1 file changed, 7 insertions(+)
--
2.6.3
This is according to figure 12 ("I2C Programming Procedure") in
"Si5351A/B/C Data Sheet"
(https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf).
Without the PLL soft reset, we were unable to get three outputs
working at the same time.
According to Silicon Labs support, performing PLL soft reset will only
be noticeable if the PLL parameters have been changed.
Signed-off-by: Jacob Siverskog <[email protected]>
Signed-off-by: Jens Rudberg <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
---
drivers/clk/clk-si5351.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index e346b22..850316a 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -1091,6 +1091,13 @@ static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
SI5351_CLK_POWERDOWN, 0);
+ /*
+ * Do a pll soft reset on both plls, needed in some cases to get
+ * all outputs running.
+ */
+ si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
+ SI5351_PLL_RESET_A | SI5351_PLL_RESET_B);
+
dev_dbg(&hwdata->drvdata->client->dev,
"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
__func__, clk_hw_get_name(hw), (1 << rdiv),
--
2.6.3
On 11/20, Jacob Siverskog wrote:
> This is according to figure 12 ("I2C Programming Procedure") in
> "Si5351A/B/C Data Sheet"
> (https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf).
>
> Without the PLL soft reset, we were unable to get three outputs
> working at the same time.
>
> According to Silicon Labs support, performing PLL soft reset will only
> be noticeable if the PLL parameters have been changed.
>
> Signed-off-by: Jacob Siverskog <[email protected]>
> Signed-off-by: Jens Rudberg <[email protected]>
> Acked-by: Sebastian Hesselbarth <[email protected]>
> ---
Applied to clk-next
--
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