From: Bartosz Golaszewski <[email protected]>
Add the GPU and PCIe IOMMUs for sa8775p platforms as well as the required
GPU clock controller driver.
Bartosz Golaszewski (6):
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
arm64: defconfig: enable the SA8775P GPUCC driver
dt-bindings: iommu: arm,smmu: enable clocks for sa8775p
arm64: dts: qcom: sa8775p: add the pcie smmu node
arm64: dts: qcom: sa8775p: add the GPU clock controller node
arm64: dts: qcom: sa8775p: add the GPU IOMMU node
Shazad Hussain (1):
clk: qcom: add the GPUCC driver for sa8775p
.../bindings/clock/qcom,sa8775p-gpucc.yaml | 61 ++
.../devicetree/bindings/iommu/arm,smmu.yaml | 1 -
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 115 ++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sa8775p.c | 633 ++++++++++++++++++
.../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 ++
8 files changed, 869 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml
create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c
create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
The KGSL iommu will require the clocks property to be set. Enable it for
sa8775p in the bindings.
Cc: Will Deacon <[email protected]>
Cc: Robin Murphy <[email protected]>
Cc: Joerg Roedel <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 807cb511fe18..74d5164ed1e8 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -375,7 +375,6 @@ allOf:
- nvidia,smmu-500
- qcom,qcm2290-smmu-500
- qcom,qdu1000-smmu-500
- - qcom,sa8775p-smmu-500
- qcom,sc7180-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add the PCIe SMMU node for sa8775p platforms.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 2343df7e0ea4..9ab630c7d81b 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
};
+ pcie_smmu: iommu@15200000 {
+ compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15200000 0x0 0x800000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+
+ interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add the GPUCC node for sa8775p platforms.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9ab630c7d81b..4c45ad1cc7ff 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -591,6 +591,18 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sa8775p-gpucc";
+ reg = <0x0 0x03d90000 0x0 0xa000>;
+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
--
2.37.2
From: Shazad Hussain <[email protected]>
Add the clock driver for the Qualcomm Graphics Clock control module.
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Signed-off-by: Shazad Hussain <[email protected]>
[Bartosz: make ready for upstream]
Co-authored-by: Bartosz Golaszewski <[email protected]>
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sa8775p.c | 633 +++++++++++++++++++++++++++++++
3 files changed, 642 insertions(+)
create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 449bc8314d21..5e1919738aeb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -437,6 +437,14 @@ config SA_GCC_8775P
Say Y if you want to use peripheral devices such as UART, SPI,
I2C, USB, UFS, SDCC, etc.
+config SA_GPUCC_8775P
+ tristate "SA8775P Graphics clock controller"
+ select SA_GCC_8775P
+ help
+ Support for the graphics clock controller on SA8775P devices.
+ Say Y if you want to support graphics controller devices and
+ functionality such as 3D graphics.
+
config SC_GCC_7180
tristate "SC7180 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index c1adb427d1ef..525e0172a1ef 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o
+obj-$(CONFIG_SA_GPUCC_8775P) += gpucc-sa8775p.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
new file mode 100644
index 000000000000..46d73bd0199b
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -0,0 +1,633 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "reset.h"
+#include "gdsc.h"
+
+/* Need to match the order of clocks in DT binding */
+enum {
+ DT_IFACE,
+ DT_BI_TCXO,
+ DT_GCC_GPU_GPLL0_CLK_SRC,
+ DT_GCC_GPU_GPLL0_DIV_CLK_SRC,
+};
+
+enum {
+ P_BI_TCXO,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL0_OUT_MAIN_DIV,
+ P_GPU_CC_PLL0_OUT_MAIN,
+ P_GPU_CC_PLL1_OUT_MAIN,
+};
+
+static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO };
+
+static const struct pll_vco lucid_evo_vco[] = {
+ { 249600000, 2020000000, 0 },
+};
+
+/* 810MHz configuration */
+static struct alpha_pll_config gpu_cc_pll0_config = {
+ .l = 0x2a,
+ .alpha = 0x3000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x32aa299c,
+ .user_ctl_val = 0x00000001,
+ .user_ctl_hi_val = 0x00400805,
+};
+
+static struct clk_alpha_pll gpu_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = lucid_evo_vco,
+ .num_vco = ARRAY_SIZE(lucid_evo_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_pll0",
+ .parent_data = &parent_data_tcxo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+/* 1000MHz configuration */
+static struct alpha_pll_config gpu_cc_pll1_config = {
+ .l = 0x34,
+ .alpha = 0x1555,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x00182261,
+ .config_ctl_hi1_val = 0x32aa299c,
+ .user_ctl_val = 0x00000001,
+ .user_ctl_hi_val = 0x00400805,
+};
+
+static struct clk_alpha_pll gpu_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = lucid_evo_vco,
+ .num_vco = ARRAY_SIZE(lucid_evo_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_pll1",
+ .parent_data = &parent_data_tcxo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_lucid_evo_ops,
+ },
+ },
+};
+
+static const struct parent_map gpu_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_MAIN_DIV, 6 },
+};
+
+static const struct clk_parent_data gpu_cc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+ { .index = DT_GCC_GPU_GPLL0_CLK_SRC },
+ { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
+};
+
+static const struct parent_map gpu_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPU_CC_PLL0_OUT_MAIN, 1 },
+ { P_GPU_CC_PLL1_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_MAIN_DIV, 6 },
+};
+
+static const struct clk_parent_data gpu_cc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpu_cc_pll0.clkr.hw },
+ { .hw = &gpu_cc_pll1.clkr.hw },
+ { .index = DT_GCC_GPU_GPLL0_CLK_SRC },
+ { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
+};
+
+static const struct parent_map gpu_cc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_GPU_CC_PLL1_OUT_MAIN, 3 },
+ { P_GPLL0_OUT_MAIN, 5 },
+ { P_GPLL0_OUT_MAIN_DIV, 6 },
+};
+
+static const struct clk_parent_data gpu_cc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &gpu_cc_pll1.clkr.hw },
+ { .index = DT_GCC_GPU_GPLL0_CLK_SRC },
+ { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC },
+};
+
+static const struct parent_map gpu_cc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data gpu_cc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+};
+
+static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
+ F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gpu_cc_ff_clk_src = {
+ .cmd_rcgr = 0x9474,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gpu_cc_parent_map_0,
+ .freq_tbl = ftbl_gpu_cc_ff_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_ff_clk_src",
+ .parent_data = gpu_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
+ F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gpu_cc_gmu_clk_src = {
+ .cmd_rcgr = 0x9318,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gpu_cc_parent_map_1,
+ .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_gmu_clk_src",
+ .parent_data = gpu_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
+ F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gpu_cc_hub_clk_src = {
+ .cmd_rcgr = 0x93ec,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gpu_cc_parent_map_2,
+ .freq_tbl = ftbl_gpu_cc_hub_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_hub_clk_src",
+ .parent_data = gpu_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gpu_cc_xo_clk_src = {
+ .cmd_rcgr = 0x9010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gpu_cc_parent_map_3,
+ .freq_tbl = ftbl_gpu_cc_xo_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_xo_clk_src",
+ .parent_data = gpu_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div gpu_cc_demet_div_clk_src = {
+ .reg = 0x9054,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpu_cc_demet_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
+ .reg = 0x9430,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpu_cc_hub_ahb_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
+ .reg = 0x942c,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gpu_cc_hub_cx_int_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch gpu_cc_ahb_clk = {
+ .halt_reg = 0x911c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x911c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cb_clk = {
+ .halt_reg = 0x93a4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x93a4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_cb_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_crc_ahb_clk = {
+ .halt_reg = 0x9120,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9120,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_crc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_ff_clk = {
+ .halt_reg = 0x914c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x914c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_cx_ff_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_ff_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_gmu_clk = {
+ .halt_reg = 0x913c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x913c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_cx_gmu_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_gmu_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
+ .halt_reg = 0x9130,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9130,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_cx_snoc_dvm_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cxo_aon_clk = {
+ .halt_reg = 0x9004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_cxo_aon_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_cxo_clk = {
+ .halt_reg = 0x9144,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9144,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_cxo_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_demet_clk = {
+ .halt_reg = 0x900c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x900c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_demet_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_demet_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
+ .halt_reg = 0x7000,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x7000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_hub_aon_clk = {
+ .halt_reg = 0x93e8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x93e8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_hub_aon_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_hub_cx_int_clk = {
+ .halt_reg = 0x9148,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9148,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_hub_cx_int_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_aon_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_memnoc_gfx_clk = {
+ .halt_reg = 0x9150,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9150,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_memnoc_gfx_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gpu_cc_sleep_clk = {
+ .halt_reg = 0x9134,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x9134,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpu_cc_sleep_clk",
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
+ [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
+ [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
+ [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+ [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
+ [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
+ [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
+ [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
+ [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
+ [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr,
+ [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
+ [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
+ [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+ [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
+ [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
+ [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
+ [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
+ [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
+ [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
+ [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr,
+ [GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
+ [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
+ [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
+ [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr,
+};
+
+static struct gdsc cx_gdsc = {
+ .gdscr = 0x9108,
+ .gds_hw_ctrl = 0x953c,
+ .pd = {
+ .name = "cx_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON,
+};
+
+static struct gdsc gx_gdsc = {
+ .gdscr = 0x905c,
+ .pd = {
+ .name = "gx_gdsc",
+ .power_on = gdsc_gx_do_nothing_enable,
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = AON_RESET | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc *gpu_cc_sa8775p_gdscs[] = {
+ [GPU_CC_CX_GDSC] = &cx_gdsc,
+ [GPU_CC_GX_GDSC] = &gx_gdsc,
+};
+
+static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = {
+ [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 },
+ [GPUCC_GPU_CC_CB_BCR] = { 0x93a0 },
+ [GPUCC_GPU_CC_CX_BCR] = { 0x9104 },
+ [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 },
+ [GPUCC_GPU_CC_FF_BCR] = { 0x9470 },
+ [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 },
+ [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 },
+ [GPUCC_GPU_CC_GX_BCR] = { 0x9058 },
+ [GPUCC_GPU_CC_XO_BCR] = { 0x9000 },
+};
+
+static const struct regmap_config gpu_cc_sa8775p_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x9988,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gpu_cc_sa8775p_desc = {
+ .config = &gpu_cc_sa8775p_regmap_config,
+ .clks = gpu_cc_sa8775p_clocks,
+ .num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks),
+ .resets = gpu_cc_sa8775p_resets,
+ .num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets),
+ .gdscs = gpu_cc_sa8775p_gdscs,
+ .num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs),
+};
+
+static const struct of_device_id gpu_cc_sa8775p_match_table[] = {
+ { .compatible = "qcom,sa8775p-gpucc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table);
+
+static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
+ clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
+
+ /*
+ * Keep the clocks always-ON
+ * GPU_CC_CB_CLK
+ */
+ regmap_update_bits(regmap, 0x93a4, BIT(0), BIT(0));
+
+ return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap);
+}
+
+static struct platform_driver gpu_cc_sa8775p_driver = {
+ .probe = gpu_cc_sa8775p_probe,
+ .driver = {
+ .name = "gpu_cc-sa8775p",
+ .of_match_table = gpu_cc_sa8775p_match_table,
+ },
+};
+
+static int __init gpu_cc_sa8775p_init(void)
+{
+ return platform_driver_register(&gpu_cc_sa8775p_driver);
+}
+subsys_initcall(gpu_cc_sa8775p_init);
+
+static void __exit gpu_cc_sa8775p_exit(void)
+{
+ platform_driver_unregister(&gpu_cc_sa8775p_driver);
+}
+module_exit(gpu_cc_sa8775p_exit);
+
+MODULE_DESCRIPTION("SA8775P GPUCC driver");
+MODULE_LICENSE("GPL");
--
2.37.2
Quoting Bartosz Golaszewski (2023-03-28 12:36:27)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 449bc8314d21..5e1919738aeb 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -437,6 +437,14 @@ config SA_GCC_8775P
> Say Y if you want to use peripheral devices such as UART, SPI,
> I2C, USB, UFS, SDCC, etc.
>
> +config SA_GPUCC_8775P
> + tristate "SA8775P Graphics clock controller"
> + select SA_GCC_8775P
Should select QCOM_GDSC as well.
> + help
> + Support for the graphics clock controller on SA8775P devices.
> + Say Y if you want to support graphics controller devices and
> + functionality such as 3D graphics.
> +
> config SC_GCC_7180
> tristate "SC7180 Global Clock Controller"
> select QCOM_GDSC
> diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
> new file mode 100644
> index 000000000000..46d73bd0199b
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-sa8775p.c
> @@ -0,0 +1,633 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023, Linaro Limited
> + */
> +
> +#include <linux/clk.h>
Is this include used? If not, remove it as this is a clk provider and
not a clk consumer.
On 28/03/2023 21:36, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> The KGSL iommu will require the clocks property to be set. Enable it for
> sa8775p in the bindings.
>
> Cc: Will Deacon <[email protected]>
> Cc: Robin Murphy <[email protected]>
> Cc: Joerg Roedel <[email protected]>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index 807cb511fe18..74d5164ed1e8 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -375,7 +375,6 @@ allOf:
> - nvidia,smmu-500
> - qcom,qcm2290-smmu-500
> - qcom,qdu1000-smmu-500
> - - qcom,sa8775p-smmu-500
Then you need to describe them, like other variants are doing.
Best regards,
Krzysztof
On 28.03.2023 21:36, Bartosz Golaszewski wrote:
> From: Shazad Hussain <[email protected]>
>
> Add the clock driver for the Qualcomm Graphics Clock control module.
>
> Cc: Stephen Boyd <[email protected]>
> Cc: Michael Turquette <[email protected]>
> Signed-off-by: Shazad Hussain <[email protected]>
> [Bartosz: make ready for upstream]
> Co-authored-by: Bartosz Golaszewski <[email protected]>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
[...]
> +/* Need to match the order of clocks in DT binding */
> +enum {
> + DT_IFACE,
I think it's never used?
[...]
> +static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> +
> + regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
> + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
> +
> + /*
> + * Keep the clocks always-ON
> + * GPU_CC_CB_CLK
> + */
> + regmap_update_bits(regmap, 0x93a4, BIT(0), BIT(0));
You set it as CRITICAL, this should be unnecessary now.
Konrad
> +
> + return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap);
> +}
> +
> +static struct platform_driver gpu_cc_sa8775p_driver = {
> + .probe = gpu_cc_sa8775p_probe,
> + .driver = {
> + .name = "gpu_cc-sa8775p",
> + .of_match_table = gpu_cc_sa8775p_match_table,
> + },
> +};
> +
> +static int __init gpu_cc_sa8775p_init(void)
> +{
> + return platform_driver_register(&gpu_cc_sa8775p_driver);
> +}
> +subsys_initcall(gpu_cc_sa8775p_init);
> +
> +static void __exit gpu_cc_sa8775p_exit(void)
> +{
> + platform_driver_unregister(&gpu_cc_sa8775p_driver);
> +}
> +module_exit(gpu_cc_sa8775p_exit);
> +
> +MODULE_DESCRIPTION("SA8775P GPUCC driver");
> +MODULE_LICENSE("GPL");
On 28.03.2023 21:36, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the GPUCC node for sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 9ab630c7d81b..4c45ad1cc7ff 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -591,6 +591,18 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + gpucc: clock-controller@3d90000 {
> + compatible = "qcom,sa8775p-gpucc";
> + reg = <0x0 0x03d90000 0x0 0xa000>;
> + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
Without the first clock, as pointed out in the clk review:
Reviewed-by: Konrad Dybcio <[email protected]>
(that also makes it compatible with the generic gpucc bindings!)
Konrad
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sa8775p-pdc", "qcom,pdc";
> reg = <0x0 0x0b220000 0x0 0x30000>,
On 28.03.2023 21:36, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the PCIe SMMU node for sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 2343df7e0ea4..9ab630c7d81b 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
> <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pcie_smmu: iommu@15200000 {
> + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x15200000 0x0 0x800000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> +
> + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
That's a lot of interrupts!
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> intc: interrupt-controller@17a00000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
On Tue, Mar 28, 2023 at 09:36:29PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> The KGSL iommu will require the clocks property to be set. Enable it for
Isn't KGSL the name for QCom's adreno vendor driver? What does that have
to do with bindings?
> sa8775p in the bindings.
>
> Cc: Will Deacon <[email protected]>
> Cc: Robin Murphy <[email protected]>
> Cc: Joerg Roedel <[email protected]>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index 807cb511fe18..74d5164ed1e8 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -375,7 +375,6 @@ allOf:
> - nvidia,smmu-500
> - qcom,qcm2290-smmu-500
> - qcom,qdu1000-smmu-500
> - - qcom,sa8775p-smmu-500
> - qcom,sc7180-smmu-500
> - qcom,sc8180x-smmu-500
> - qcom,sc8280xp-smmu-500
> --
> 2.37.2
>
On 3.04.2023 22:41, Rob Herring wrote:
> On Tue, Mar 28, 2023 at 09:36:29PM +0200, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <[email protected]>
>>
>> The KGSL iommu will require the clocks property to be set. Enable it for
>
> Isn't KGSL the name for QCom's adreno vendor driver? What does that have
> to do with bindings?
It's called "KGSL SMMU" (as opposed to the other "APPS SMMU" (Application
Processor SubSystem) in some places in Qualcommland
Konrad
>
>> sa8775p in the bindings.
>>
>> Cc: Will Deacon <[email protected]>
>> Cc: Robin Murphy <[email protected]>
>> Cc: Joerg Roedel <[email protected]>
>> Signed-off-by: Bartosz Golaszewski <[email protected]>
>> ---
>> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> index 807cb511fe18..74d5164ed1e8 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> @@ -375,7 +375,6 @@ allOf:
>> - nvidia,smmu-500
>> - qcom,qcm2290-smmu-500
>> - qcom,qdu1000-smmu-500
>> - - qcom,sa8775p-smmu-500
>> - qcom,sc7180-smmu-500
>> - qcom,sc8180x-smmu-500
>> - qcom,sc8280xp-smmu-500
>> --
>> 2.37.2
>>
On Wed, Mar 29, 2023 at 4:15 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Bartosz Golaszewski (2023-03-28 12:36:27)
> > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> > index 449bc8314d21..5e1919738aeb 100644
> > --- a/drivers/clk/qcom/Kconfig
> > +++ b/drivers/clk/qcom/Kconfig
> > @@ -437,6 +437,14 @@ config SA_GCC_8775P
> > Say Y if you want to use peripheral devices such as UART, SPI,
> > I2C, USB, UFS, SDCC, etc.
> >
> > +config SA_GPUCC_8775P
> > + tristate "SA8775P Graphics clock controller"
> > + select SA_GCC_8775P
>
> Should select QCOM_GDSC as well.
>
Why if it's already selected indirectly by SA_GCC_8775P? Other GPUCCs
in here don't select it either.
Bart
> > + help
> > + Support for the graphics clock controller on SA8775P devices.
> > + Say Y if you want to support graphics controller devices and
> > + functionality such as 3D graphics.
> > +
> > config SC_GCC_7180
> > tristate "SC7180 Global Clock Controller"
> > select QCOM_GDSC
> > diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
> > new file mode 100644
> > index 000000000000..46d73bd0199b
> > --- /dev/null
> > +++ b/drivers/clk/qcom/gpucc-sa8775p.c
> > @@ -0,0 +1,633 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
> > + * Copyright (c) 2023, Linaro Limited
> > + */
> > +
> > +#include <linux/clk.h>
>
> Is this include used? If not, remove it as this is a clk provider and
> not a clk consumer.
Quoting Bartosz Golaszewski (2023-04-06 04:20:33)
> On Wed, Mar 29, 2023 at 4:15 AM Stephen Boyd <[email protected]> wrote:
> >
> > Quoting Bartosz Golaszewski (2023-03-28 12:36:27)
> > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> > > index 449bc8314d21..5e1919738aeb 100644
> > > --- a/drivers/clk/qcom/Kconfig
> > > +++ b/drivers/clk/qcom/Kconfig
> > > @@ -437,6 +437,14 @@ config SA_GCC_8775P
> > > Say Y if you want to use peripheral devices such as UART, SPI,
> > > I2C, USB, UFS, SDCC, etc.
> > >
> > > +config SA_GPUCC_8775P
> > > + tristate "SA8775P Graphics clock controller"
> > > + select SA_GCC_8775P
> >
> > Should select QCOM_GDSC as well.
> >
>
> Why if it's already selected indirectly by SA_GCC_8775P? Other GPUCCs
> in here don't select it either.
For completeness.