Add cm40 subsystem.
Add cm40_lpuart and lpurt1 for 8dxl evk boards.
Signed-off-by: Frank Li <[email protected]>
---
Alice Guo (1):
arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
Dong Aisheng (1):
arm64: dts: imx8: add cm40 subsystem dtsi
Frank Li (2):
arm64: dts: imx8dxl: update cm40 irq number informaiton
dts: arm64: imx8dxl-evk: add lpuart1 and cm40 uart
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 92 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 50 ++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 13 ++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
4 files changed, 156 insertions(+)
---
base-commit: 62a517a071e93c650cc847ce300b04a94b0cb7f2
change-id: 20240228-m4_lpuart-30791c032f2a
Best regards,
--
Frank Li <[email protected]>
Update cm40 irq number for imx8dxl chip.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index 9d49c75a26222..b9d137d69f5a7 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -243,3 +243,14 @@ xtal24m: clock-xtal24m {
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"
+
+&cm40_intmux {
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.34.1
From: Alice Guo <[email protected]>
Adding lpuart device in cm40 subsystem.
Signed-off-by: Alice Guo <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
index b1d626862ddf8..ecca5ada224b7 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -64,4 +64,29 @@ cm40_intmux: intmux@37400000 {
power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
status = "disabled";
};
+
+ cm40_lpuart: serial@37220000 {
+ compatible = "fsl,imx8qxp-lpuart";
+ reg = <0x37220000 0x1000>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&cm40_intmux>;
+ clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>;
+ clock-names = "ipg", "baud";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ status = "disabled";
+ };
+
+ cm40_uart_lpcg: clock-controller@37620000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37620000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
+ clock-output-names = "cm40_lpcg_uart_clk",
+ "cm40_lpcg_uart_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_UART>;
+ };
};
--
2.34.1
Add lpuart1 and cm40 uart.
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 50 +++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 2123d431e0613..b45b0c99fe204 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -16,6 +16,8 @@ aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial6 = &cm40_lpuart;
};
chosen {
@@ -51,6 +53,24 @@ linux,cma {
};
};
+ modem_reset: modem-reset {
+ compatible = "gpio-reset";
+ reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2000>;
+ reset-post-delay-ms = <40>;
+ #reset-cells = <0>;
+ };
+
+ m2_uart1_sel: fixedregulator@101 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "m2_uart1_sel";
+ gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
mux3_en: regulator-0 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@@ -354,6 +374,27 @@ &flexcan3 {
status = "okay";
};
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ resets = <&modem_reset>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&cm40_intmux {
+ status = "disabled";
+};
+
+&cm40_lpuart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cm40_lpuart>;
+ status = "disabled";
+};
+
&lsio_gpio4 {
status = "okay";
};
@@ -595,6 +636,15 @@ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
From: Dong Aisheng <[email protected]>
Add cm40 subsystem dtsi.
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
3 files changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
new file mode 100644
index 0000000000000..b1d626862ddf8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Dong Aisheng <[email protected]>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+cm40_subsys: bus@34000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x34000000 0x0 0x34000000 0x4000000>;
+
+ cm40_ipg_clk: clock-cm40-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <132000000>;
+ clock-output-names = "cm40_ipg_clk";
+ };
+
+ cm40_i2c: i2c@37230000 {
+ compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x37230000 0x1000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&cm40_intmux>;
+ clocks = <&cm40_i2c_lpcg 0>,
+ <&cm40_i2c_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ status = "disabled";
+ };
+
+ cm40_i2c_lpcg: clock-controller@37630000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x37630000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
+ <&cm40_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "cm40_lpcg_i2c_clk",
+ "cm40_lpcg_i2c_ipg_clk";
+ power-domains = <&pd IMX_SC_R_M4_0_I2C>;
+ };
+
+ cm40_intmux: intmux@37400000 {
+ compatible = "fsl,imx-intmux";
+ reg = <0x37400000 0x1000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ clocks = <&cm40_ipg_clk>;
+ clock-names = "ipg";
+ power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
index a0674c5c55766..9d49c75a26222 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
+#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
};
/* sorted in register address */
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 10e16d84c0c3b..c49fb1282ae65 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -316,6 +316,7 @@ map0 {
/* sorted in register address */
#include "imx8-ss-img.dtsi"
+ #include "imx8-ss-cm40.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
--
2.34.1
On Wed, Feb 28, 2024 at 4:55 PM Frank Li <[email protected]> wrote:
>
> From: Alice Guo <[email protected]>
>
> Adding lpuart device in cm40 subsystem.
Don't start a commit log with "Adding". Use "Add" instead.
On Wed, Feb 28, 2024 at 4:55 PM Frank Li <[email protected]> wrote:
> + modem_reset: modem-reset {
> + compatible = "gpio-reset";
I don't see this compatible documented.
> + reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>;
> + reset-delay-us = <2000>;
> + reset-post-delay-ms = <40>;
> + #reset-cells = <0>;
> + };
> +
> + m2_uart1_sel: fixedregulator@101 {
Why is this @101 here? You should remove it.
Passing a unit address without a corresponding reg entry triggers a
dt-schema warning.
We want less warnings dt-schema warnings, not more :-)
Hi Frank,
thanks for the patch.
Am Mittwoch, 28. Februar 2024, 20:54:57 CET schrieb Frank Li:
> From: Dong Aisheng <[email protected]>
>
> Add cm40 subsystem dtsi.
>
> Signed-off-by: Dong Aisheng <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 67 +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
> 3 files changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> new file mode 100644
> index 0000000000000..b1d626862ddf8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 NXP
> + * Dong Aisheng <[email protected]>
> + */
> +
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +cm40_subsys: bus@34000000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x34000000 0x0 0x34000000 0x4000000>;
You should set interrupt-parent = <&cm40_intmux> here already.
So you can skip it for all subsequent nodes, but the cm40_intmux itself.
> +
> + cm40_ipg_clk: clock-cm40-ipg {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <132000000>;
> + clock-output-names = "cm40_ipg_clk";
> + };
> +
> + cm40_i2c: i2c@37230000 {
> + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> + reg = <0x37230000 0x1000>;
> + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&cm40_intmux>;
I personally prefer the parent to be stated first.
> + clocks = <&cm40_i2c_lpcg 0>,
> + <&cm40_i2c_lpcg 1>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_M4_0_I2C>;
> + status = "disabled";
> + };
> +
> + cm40_i2c_lpcg: clock-controller@37630000 {
Please sort the nodes by bus address.
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x37630000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
> + <&cm40_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "cm40_lpcg_i2c_clk",
> + "cm40_lpcg_i2c_ipg_clk";
> + power-domains = <&pd IMX_SC_R_M4_0_I2C>;
> + };
> +
> + cm40_intmux: intmux@37400000 {
> + compatible = "fsl,imx-intmux";
> + reg = <0x37400000 0x1000>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <2>;
> + clocks = <&cm40_ipg_clk>;
> + clock-names = "ipg";
> + power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
> + status = "disabled";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> index a0674c5c55766..9d49c75a26222 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> @@ -5,6 +5,7 @@
>
> #include <dt-bindings/clock/imx8-clock.h>
> #include <dt-bindings/dma/fsl-edma.h>
> +#include <dt-bindings/clock/imx8-lpcg.h>
> #include <dt-bindings/firmware/imx/rsrc.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -231,6 +232,7 @@ xtal24m: clock-xtal24m {
> };
>
> /* sorted in register address */
> + #include "imx8-ss-cm40.dtsi"
> #include "imx8-ss-adma.dtsi"
> #include "imx8-ss-conn.dtsi"
> #include "imx8-ss-ddr.dtsi"
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 10e16d84c0c3b..c49fb1282ae65 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -316,6 +316,7 @@ map0 {
>
> /* sorted in register address */
> #include "imx8-ss-img.dtsi"
> + #include "imx8-ss-cm40.dtsi"
cm40 subsystem is bus@34000000, so IMHO it should go below vpu subsystem,
which is vpu@2c000000.
Best regards,
Alexander
> #include "imx8-ss-vpu.dtsi"
> #include "imx8-ss-gpu0.dtsi"
> #include "imx8-ss-adma.dtsi"
>
>
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
Hi Frank,
thanks for the patch.
Am Mittwoch, 28. Februar 2024, 20:54:58 CET schrieb Frank Li:
> From: Alice Guo <[email protected]>
>
> Adding lpuart device in cm40 subsystem.
>
> Signed-off-by: Alice Guo <[email protected]>
> Reviewed-by: Peng Fan <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> index b1d626862ddf8..ecca5ada224b7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi
> @@ -64,4 +64,29 @@ cm40_intmux: intmux@37400000 {
> power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
> status = "disabled";
> };
> +
> + cm40_lpuart: serial@37220000 {
> + compatible = "fsl,imx8qxp-lpuart";
> + reg = <0x37220000 0x1000>;
> + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&cm40_intmux>;
With interrupt-parent set in Patch 1 for the whole subsystem, this line
is not needed anymore.
Best regards,
Alexander
> + clocks = <&cm40_uart_lpcg 1>, <&cm40_uart_lpcg 0>;
> + clock-names = "ipg", "baud";
> + assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_M4_0_UART>;
> + status = "disabled";
> + };
> +
> + cm40_uart_lpcg: clock-controller@37620000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x37620000 0x1000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
> + <&cm40_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
> + clock-output-names = "cm40_lpcg_uart_clk",
> + "cm40_lpcg_uart_ipg_clk";
> + power-domains = <&pd IMX_SC_R_M4_0_UART>;
> + };
> };
>
>
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
On Wed, 28 Feb 2024 14:54:56 -0500, Frank Li wrote:
> Add cm40 subsystem.
> Add cm40_lpuart and lpurt1 for 8dxl evk boards.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> Alice Guo (1):
> arm64: dts: imx8dxl: add lpuart device in cm40 subsystem
>
> Dong Aisheng (1):
> arm64: dts: imx8: add cm40 subsystem dtsi
>
> Frank Li (2):
> arm64: dts: imx8dxl: update cm40 irq number informaiton
> dts: arm64: imx8dxl-evk: add lpuart1 and cm40 uart
>
> arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi | 92 +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 50 ++++++++++++++
> arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 13 ++++
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 +
> 4 files changed, 156 insertions(+)
> ---
> base-commit: 62a517a071e93c650cc847ce300b04a94b0cb7f2
> change-id: 20240228-m4_lpuart-30791c032f2a
>
> Best regards,
> --
> Frank Li <[email protected]>
>
>
>
My bot found new DT warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y freescale/imx8dxl-evk.dtb' for [email protected]:
arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb: /: fixedregulator@101: 'anyOf' conditional failed, one must be fixed:
'reg' is a required property
'ranges' is a required property
from schema $id: http://devicetree.org/schemas/root-node.yaml#
arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb: bus@34000000: clock-cm40-ipg: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[132000000]], 'clock-output-names': ['cm40_ipg_clk'], 'phandle': [[15]]} should not be valid under {'type': 'object'}
from schema $id: http://devicetree.org/schemas/simple-bus.yaml#
arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb: intmux@37400000: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/interrupt-controller/fsl,intmux.yaml#
arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb: serial@5a070000: Unevaluated properties are not allowed ('resets' was unexpected)
from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb: /modem-reset: failed to match any schema with compatible: ['gpio-reset']