Hello everyone,
The v5 series is a significantly cleaned up version from v4,
started by Ezequiel Garcia's suggestion of splitting out the
regmap infrastructure from the drivers (thank you!).
Turns out no changes are required to the existing drivers and
the bridge can transparently take care of the layout logic,
so there's no need to expose the regmap via plat_data anymore.
Starting from this version I also opted to add per-patch
changelogs. All review comments up to now have been addressed.
Tested on IMX6DL.
Adrian Ratiu (5):
drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
drm: bridge: synopsis: add dsi v1.01 support
drm: imx: Add i.MX 6 MIPI DSI host platform driver
dt-bindings: display: add i.MX6 MIPI DSI host controller doc
.../display/imx/fsl,mipi-dsi-imx6.yaml | 134 ++++
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 683 +++++++++++++-----
drivers/gpu/drm/imx/Kconfig | 7 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
5 files changed, 1049 insertions(+), 175 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
--
2.26.0
This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.
Cc: Rob Herring <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: [email protected]
Signed-off-by: Sjoerd Simons <[email protected]>
Signed-off-by: Martyn Welch <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
Changes since v4:
- Fixed yaml binding to pass `make dt_binding_check dtbs_check`
and addressed received binding feedback (Rob)
Changes since v3:
- Added commit message (Neil)
- Converted to yaml format (Neil)
- Minor dt node + driver fixes (Rob)
- Added small panel example to the host controller binding
Changes since v2:
- Fixed commit tags (Emil)
---
.../display/imx/fsl,mipi-dsi-imx6.yaml | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index 000000000000..59146df11510
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+ - Adrian Ratiu <[email protected]>
+
+description: |
+ The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+ IP block with a companion PHY IP.
+
+ These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+ Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+ the following device-specific properties.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx6q-mipi-dsi
+ - const: snps,dw-mipi-dsi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Module Clock
+ - description: DSI bus clock
+
+ clock-names:
+ items:
+ - const: ref
+ - const: pclk
+
+ fsl,gpr:
+ description: Phandle to the iomuxc-gpr region containing the multiplexer control register.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ ports:
+ type: object
+ description: |
+ A node containing DSI input & output port nodes with endpoint
+ definitions as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+ properties:
+ port@0:
+ type: object
+ description:
+ DSI input port node, connected to the ltdc rgb output port.
+
+ port@1:
+ type: object
+ description:
+ DSI output port node, connected to a panel or a bridge input port"
+
+patternProperties:
+ "^panel@[0-3]$":
+ type: object
+ description: |
+ A node containing the panel or bridge description as documented in
+ Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
+ properties:
+ port:
+ type: object
+ description:
+ Panel or bridge port node, connected to the DSI output port (port@1)
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi: dsi@21e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e0000 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+ <&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "pclk";
+
+ ports {
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "sharp,ls032b3sx01";
+ reg = <0>;
+ reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
+ ports {
+ port@0 {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+ };
+
+...
--
2.26.0
This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
controller which is embedded in i.MX 6 SoCs.
Based on following patches, but updated/extended to work with existing
support found in the kernel:
- drm: imx: Support Synopsys DesignWare MIPI DSI host controller
Signed-off-by: Liu Ying <[email protected]>
- ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
Signed-off-by: Liu Ying <[email protected]>
Cc: Fabio Estevam <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Signed-off-by: Sjoerd Simons <[email protected]>
Signed-off-by: Martyn Welch <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
Changes since v4:
- Split off driver-specific configuration of phy timings due
to new upstream API.
- Move regmap infrastructure logic to separate commit (Ezequiel)
- Move dsi v1.01 layout addition to a separate commit (Ezequiel)
- Minor warnings and driver name fixes
Changes since v3:
- Renamed platform driver to reflect it's i.MX6 only. (Fabio)
Changes since v2:
- Fixed commit tags. (Emil)
Changes since v1:
- Moved register definitions & regmap initialization into bridge
module. Platform drivers get the regmap via plat_data after
calling the bridge probe. (Emil)
---
drivers/gpu/drm/imx/Kconfig | 7 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 +++++++++++++++++++++++++
3 files changed, 407 insertions(+)
create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 207bf7409dfb..b49e70e7f0fd 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -39,3 +39,10 @@ config DRM_IMX_HDMI
depends on DRM_IMX
help
Choose this if you want to use HDMI on i.MX6.
+
+config DRM_IMX6_MIPI_DSI
+ tristate "Freescale i.MX6 DRM MIPI DSI"
+ select DRM_DW_MIPI_DSI
+ depends on DRM_IMX
+ help
+ Choose this if you want to use MIPI DSI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 21cdcc2faabc..9a7843c59347 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
+obj-$(CONFIG_DRM_IMX6_MIPI_DSI) += dw_mipi_dsi-imx6.o
diff --git a/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
new file mode 100644
index 000000000000..56b17d8670a2
--- /dev/null
+++ b/drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * i.MX6 drm driver - MIPI DSI Host Controller
+ *
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/videodev2.h>
+#include <drm/bridge/dw_mipi_dsi.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+
+#include "imx-drm.h"
+
+#define DSI_PWR_UP 0x04
+#define RESET 0
+#define POWERUP BIT(0)
+
+#define DSI_PHY_IF_CTRL 0x5c
+#define PHY_IF_CTRL_RESET 0x0
+
+#define DSI_PHY_TST_CTRL0 0x64
+#define PHY_TESTCLK BIT(1)
+#define PHY_UNTESTCLK 0
+#define PHY_TESTCLR BIT(0)
+#define PHY_UNTESTCLR 0
+
+#define DSI_PHY_TST_CTRL1 0x68
+#define PHY_TESTEN BIT(16)
+#define PHY_UNTESTEN 0
+#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
+#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
+
+struct imx_mipi_dsi {
+ struct drm_encoder encoder;
+ struct device *dev;
+ struct regmap *mux_sel;
+ struct dw_mipi_dsi *mipi_dsi;
+ struct clk *pllref_clk;
+
+ void __iomem *base;
+ unsigned int lane_mbps;
+};
+
+struct dphy_pll_testdin_map {
+ unsigned int max_mbps;
+ u8 testdin;
+};
+
+/* The table is based on 27MHz DPHY pll reference clock. */
+static const struct dphy_pll_testdin_map dptdin_map[] = {
+ {160, 0x04}, {180, 0x24}, {200, 0x44}, {210, 0x06},
+ {240, 0x26}, {250, 0x46}, {270, 0x08}, {300, 0x28},
+ {330, 0x48}, {360, 0x2a}, {400, 0x4a}, {450, 0x0c},
+ {500, 0x2c}, {550, 0x0e}, {600, 0x2e}, {650, 0x10},
+ {700, 0x30}, {750, 0x12}, {800, 0x32}, {850, 0x14},
+ {900, 0x34}, {950, 0x54}, {1000, 0x74}
+};
+
+static inline struct imx_mipi_dsi *enc_to_dsi(struct drm_encoder *enc)
+{
+ return container_of(enc, struct imx_mipi_dsi, encoder);
+}
+
+static void imx_mipi_dsi_set_ipu_di_mux(struct imx_mipi_dsi *dsi, int ipu_di)
+{
+ regmap_update_bits(dsi->mux_sel, IOMUXC_GPR3,
+ IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
+ ipu_di << IMX6Q_GPR3_MIPI_MUX_CTL_SHIFT);
+}
+
+static const struct drm_encoder_funcs imx_mipi_dsi_encoder_funcs = {
+ .destroy = imx_drm_encoder_destroy,
+};
+
+static bool imx_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adj_mode)
+{
+ return true;
+}
+
+static int imx_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn)
+{
+ struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
+
+ /* The following values are taken from dw_hdmi_imx_atomic_check */
+ imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ imx_crtc_state->di_hsync_pin = 2;
+ imx_crtc_state->di_vsync_pin = 3;
+
+ return 0;
+}
+
+static void imx_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
+{
+ struct imx_mipi_dsi *dsi = enc_to_dsi(encoder);
+ int mux = drm_of_encoder_active_port_id(dsi->dev->of_node, encoder);
+
+ imx_mipi_dsi_set_ipu_di_mux(dsi, mux);
+}
+
+static void imx_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
+{
+}
+
+static const struct drm_encoder_helper_funcs imx_mipi_dsi_encoder_helpers = {
+ .mode_fixup = imx_mipi_dsi_encoder_mode_fixup,
+ .commit = imx_mipi_dsi_encoder_commit,
+ .disable = imx_mipi_dsi_encoder_disable,
+ .atomic_check = imx_mipi_dsi_encoder_atomic_check,
+};
+
+static int imx_mipi_dsi_register(struct drm_device *drm,
+ struct imx_mipi_dsi *dsi)
+{
+ int ret;
+
+ ret = imx_drm_encoder_parse_of(drm, &dsi->encoder, dsi->dev->of_node);
+ if (ret)
+ return ret;
+
+ drm_encoder_helper_add(&dsi->encoder,
+ &imx_mipi_dsi_encoder_helpers);
+ drm_encoder_init(drm, &dsi->encoder, &imx_mipi_dsi_encoder_funcs,
+ DRM_MODE_ENCODER_DSI, NULL);
+ return 0;
+}
+
+static enum drm_mode_status imx_mipi_dsi_mode_valid(void *priv_data,
+ const struct drm_display_mode *mode)
+{
+ /*
+ * The VID_PKT_SIZE field in the DSI_VID_PKT_CFG
+ * register is 11-bit.
+ */
+ if (mode->hdisplay > 0x7ff)
+ return MODE_BAD_HVALUE;
+
+ /*
+ * The V_ACTIVE_LINES field in the DSI_VTIMING_CFG
+ * register is 11-bit.
+ */
+ if (mode->vdisplay > 0x7ff)
+ return MODE_BAD_VVALUE;
+
+ return MODE_OK;
+}
+
+
+static unsigned int max_mbps_to_testdin(unsigned int max_mbps)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(dptdin_map); i++)
+ if (dptdin_map[i].max_mbps == max_mbps)
+ return dptdin_map[i].testdin;
+
+ return -EINVAL;
+}
+
+static inline void dsi_write(struct imx_mipi_dsi *dsi, u32 reg, u32 val)
+{
+ writel(val, dsi->base + reg);
+}
+
+static int imx_mipi_dsi_phy_init(void *priv_data)
+{
+ struct imx_mipi_dsi *dsi = priv_data;
+ int testdin;
+
+ testdin = max_mbps_to_testdin(dsi->lane_mbps);
+ if (testdin < 0) {
+ dev_err(dsi->dev,
+ "failed to get testdin for %dmbps lane clock\n",
+ dsi->lane_mbps);
+ return testdin;
+ }
+
+ dsi_write(dsi, DSI_PHY_IF_CTRL, PHY_IF_CTRL_RESET);
+ dsi_write(dsi, DSI_PWR_UP, POWERUP);
+
+ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
+ dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
+ PHY_TESTDIN(0x44));
+ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
+ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
+ dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
+ PHY_TESTDIN(testdin));
+ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
+ dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
+
+ return 0;
+}
+
+static int imx_mipi_dsi_get_lane_mbps(void *priv_data,
+ const struct drm_display_mode *mode,
+ unsigned long mode_flags, u32 lanes,
+ u32 format, unsigned int *lane_mbps)
+{
+ struct imx_mipi_dsi *dsi = priv_data;
+ int bpp;
+ unsigned int i, target_mbps, mpclk;
+ unsigned long pllref;
+
+ bpp = mipi_dsi_pixel_format_to_bpp(format);
+ if (bpp < 0) {
+ dev_err(dsi->dev, "failed to get bpp for pixel format %d\n",
+ format);
+ return bpp;
+ }
+
+ pllref = clk_get_rate(dsi->pllref_clk);
+ if (pllref != 27000000)
+ dev_warn(dsi->dev, "expect 27MHz DPHY pll reference clock\n");
+
+ mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC);
+ if (mpclk) {
+ /* take 1/0.7 blanking overhead into consideration */
+ target_mbps = (mpclk * (bpp / lanes) * 10) / 7;
+ } else {
+ dev_dbg(dsi->dev, "use default 1Gbps DPHY pll clock\n");
+ target_mbps = 1000;
+ }
+
+ dev_dbg(dsi->dev, "target DPHY pll clock frequency is %uMbps\n",
+ target_mbps);
+
+ for (i = 0; i < ARRAY_SIZE(dptdin_map); i++) {
+ if (target_mbps < dptdin_map[i].max_mbps) {
+ *lane_mbps = dptdin_map[i].max_mbps;
+ dsi->lane_mbps = *lane_mbps;
+ dev_dbg(dsi->dev,
+ "real DPHY pll clock frequency is %uMbps\n",
+ *lane_mbps);
+ return 0;
+ }
+ }
+
+ dev_err(dsi->dev, "DPHY clock frequency %uMbps is out of range\n",
+ target_mbps);
+
+ return -EINVAL;
+}
+
+static int
+dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
+ struct dw_mipi_dsi_dphy_timing *timing)
+{
+ timing->clk_hs2lp = 0x40;
+ timing->clk_lp2hs = 0x40;
+ timing->data_hs2lp = 0x40;
+ timing->data_lp2hs = 0x40;
+
+ return 0;
+}
+
+static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_imx6_phy_ops = {
+ .init = imx_mipi_dsi_phy_init,
+ .get_lane_mbps = imx_mipi_dsi_get_lane_mbps,
+ .get_timing = dw_mipi_dsi_phy_get_timing,
+};
+
+static struct dw_mipi_dsi_plat_data imx6q_mipi_dsi_drv_data = {
+ .max_data_lanes = 2,
+ .mode_valid = imx_mipi_dsi_mode_valid,
+ .phy_ops = &dw_mipi_dsi_imx6_phy_ops,
+};
+
+static const struct of_device_id imx_dsi_dt_ids[] = {
+ {
+ .compatible = "fsl,imx6q-mipi-dsi",
+ .data = &imx6q_mipi_dsi_drv_data,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imx_dsi_dt_ids);
+
+static int imx_mipi_dsi_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
+ struct drm_device *drm = data;
+ int ret;
+
+ ret = imx_mipi_dsi_register(drm, dsi);
+ if (ret)
+ return ret;
+
+ ret = dw_mipi_dsi_bind(dsi->mipi_dsi, &dsi->encoder);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void imx_mipi_dsi_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct imx_mipi_dsi *dsi = dev_get_drvdata(dev);
+
+ return dw_mipi_dsi_unbind(dsi->mipi_dsi);
+}
+
+static const struct component_ops imx_mipi_dsi_ops = {
+ .bind = imx_mipi_dsi_bind,
+ .unbind = imx_mipi_dsi_unbind,
+};
+
+static int imx_mipi_dsi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *of_id = of_match_device(imx_dsi_dt_ids, dev);
+ struct dw_mipi_dsi_plat_data *pdata = (struct dw_mipi_dsi_plat_data*) of_id->data;
+ struct imx_mipi_dsi *dsi;
+ struct resource *res;
+ int ret;
+
+ dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
+ if (!dsi)
+ return -ENOMEM;
+
+ dsi->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dsi->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(dsi->base)) {
+ DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
+ return PTR_ERR(dsi->base);
+ }
+
+ dsi->pllref_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(dsi->pllref_clk)) {
+ ret = PTR_ERR(dsi->pllref_clk);
+ dev_dbg(dev, "%s: Unable to get pll reference clock: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dsi->pllref_clk);
+ if (ret) {
+ dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
+ return ret;
+ }
+
+ dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
+ if (IS_ERR(dsi->mux_sel)) {
+ ret = PTR_ERR(dsi->mux_sel);
+ dev_err(dev, "%s: Failed to get GPR regmap: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ dev_set_drvdata(dev, dsi);
+
+ imx6q_mipi_dsi_drv_data.base = dsi->base;
+ imx6q_mipi_dsi_drv_data.priv_data = dsi;
+
+ dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata);
+ if (IS_ERR(dsi->mipi_dsi)) {
+ ret = PTR_ERR(dsi->mipi_dsi);
+ dev_dbg(dev, "%s: Unable to probe DW DSI host device: %d\n",
+ __func__, ret);
+ return -ENODEV;
+ }
+
+ return component_add(&pdev->dev, &imx_mipi_dsi_ops);
+}
+
+static int imx_mipi_dsi_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &imx_mipi_dsi_ops);
+ return 0;
+}
+
+static struct platform_driver imx_mipi_dsi_driver = {
+ .probe = imx_mipi_dsi_probe,
+ .remove = imx_mipi_dsi_remove,
+ .driver = {
+ .of_match_table = imx_dsi_dt_ids,
+ .name = "dw-mipi-dsi-imx6",
+ },
+};
+module_platform_driver(imx_mipi_dsi_driver);
+
+MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver");
+MODULE_AUTHOR("Liu Ying <[email protected]>");
+MODULE_LICENSE("GPL");
--
2.26.0
The Synopsis MIPI DSI v1.01 host controller is quite widely used
on platforms like i.mx6 and is not very different from the other
versions like the 1.31/1.30 used on rockchip/stm. The protocols
appear to be the same, only the register layout is different and
the newer versions have new features symbolized by new registers
so adding support for it is just a matter of defining the new
layout and adding a couple of dsi version checks.
Signed-off-by: Adrian Ratiu <[email protected]>
---
New in v5.
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +++++++++++++++++-
1 file changed, 119 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5b78ff925af0..fb9dbc4fd0f5 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -32,6 +32,7 @@
#define HWVER_131 0x31333100 /* IP version 1.31 */
#define HWVER_130 0x31333000 /* IP version 1.30 */
+#define HWVER_101 0x31303000 /* IP version 1.01 */
#define DSI_VERSION 0x00
#define VERSION GENMASK(31, 8)
@@ -100,6 +101,25 @@
#define DSI_EDPI_CMD_SIZE 0x64
#define DSI_CMD_MODE_CFG 0x68
+
+#define DSI_DPI_CFG 0x0c
+#define DSI_TMR_LINE_CFG 0x28
+#define DSI_VTIMING_CFG 0x2c
+#define DSI_PHY_TMR_CFG_V101 0x30
+#define DSI_PHY_IF_CFG_V101 0x58
+#define DSI_PHY_IF_CTRL 0x5c
+#define DSI_PHY_RSTZ_V101 0x54
+#define DSI_PHY_STATUS_V101 0x60
+#define DSI_PHY_TST_CTRL0_V101 0x64
+#define DSI_GEN_HDR_V101 0x34
+#define DSI_GEN_PLD_DATA_V101 0x38
+#define DSI_CMD_MODE_CFG_V101 0x24
+#define DSI_CMD_PKT_STATUS_V101 0x3c
+#define DSI_VID_PKT_CFG 0x20
+#define DSI_VID_MODE_CFG_V101 0x1c
+#define DSI_TO_CNT_CFG_V101 0x40
+#define DSI_PCKHDL_CFG_V101 0x18
+
#define MAX_RD_PKT_SIZE_LP BIT(24)
#define DCS_LW_TX_LP BIT(19)
#define DCS_SR_0P_TX_LP BIT(18)
@@ -127,6 +147,33 @@
GEN_SW_1P_TX_LP | \
GEN_SW_0P_TX_LP)
+#define EN_TEAR_FX_V101 BIT(14)
+#define DCS_LW_TX_LP_V101 BIT(12)
+#define GEN_LW_TX_LP_V101 BIT(11)
+#define MAX_RD_PKT_SIZE_LP_V101 BIT(10)
+#define DCS_SW_2P_TX_LP_V101 BIT(9)
+#define DCS_SW_1P_TX_LP_V101 BIT(8)
+#define DCS_SW_0P_TX_LP_V101 BIT(7)
+#define GEN_SR_2P_TX_LP_V101 BIT(6)
+#define GEN_SR_1P_TX_LP_V101 BIT(5)
+#define GEN_SR_0P_TX_LP_V101 BIT(4)
+#define GEN_SW_2P_TX_LP_V101 BIT(3)
+#define GEN_SW_1P_TX_LP_V101 BIT(2)
+#define GEN_SW_0P_TX_LP_V101 BIT(1)
+
+#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
+ GEN_LW_TX_LP_V101 | \
+ MAX_RD_PKT_SIZE_LP_V101 | \
+ DCS_SW_2P_TX_LP_V101 | \
+ DCS_SW_1P_TX_LP_V101 | \
+ DCS_SW_0P_TX_LP_V101 | \
+ GEN_SR_2P_TX_LP_V101 | \
+ GEN_SR_1P_TX_LP_V101 | \
+ GEN_SR_0P_TX_LP_V101 | \
+ GEN_SW_2P_TX_LP_V101 | \
+ GEN_SW_1P_TX_LP_V101 | \
+ GEN_SW_0P_TX_LP_V101)
+
#define DSI_GEN_HDR 0x6c
#define DSI_GEN_PLD_DATA 0x70
@@ -165,6 +212,11 @@
#define DSI_INT_MSK0 0xc4
#define DSI_INT_MSK1 0xc8
+#define DSI_ERROR_ST0_V101 0x44
+#define DSI_ERROR_ST1_V101 0x48
+#define DSI_ERROR_MSK0_V101 0x4c
+#define DSI_ERROR_MSK1_V101 0x50
+
#define DSI_PHY_TMR_RD_CFG 0xf4
#define PHY_STATUS_TIMEOUT_US 10000
@@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
};
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
+ .cfg_dpi_vid = REG_FIELD(DSI_DPI_CFG, 0, 1),
+ .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
+ .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10),
+ .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6),
+ .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG, 7, 7),
+ .cfg_cmd_mode_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 0, 0),
+ .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 1, 12),
+ .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
+ .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
+ .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
+ .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
+ .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
+ .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_CFG, 0, 10),
+ .cfg_vid_hsa_time = REG_FIELD(DSI_TMR_LINE_CFG, 0, 8),
+ .cfg_vid_hbp_time = REG_FIELD(DSI_TMR_LINE_CFG, 9, 17),
+ .cfg_vid_hline_time = REG_FIELD(DSI_TMR_LINE_CFG, 18, 31),
+ .cfg_vid_vsa_time = REG_FIELD(DSI_VTIMING_CFG, 0, 3),
+ .cfg_vid_vbp_time = REG_FIELD(DSI_VTIMING_CFG, 4, 9),
+ .cfg_vid_vfp_time = REG_FIELD(DSI_VTIMING_CFG, 10, 15),
+ .cfg_vid_vactive_time = REG_FIELD(DSI_VTIMING_CFG, 16, 26),
+ .cfg_phy_txrequestclkhs = REG_FIELD(DSI_PHY_IF_CTRL, 0, 0),
+ .cfg_phy_bta_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 0, 11),
+ .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 12, 19),
+ .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 20, 27),
+ .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0_V101, 0, 0),
+ .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ_V101, 0, 0),
+ .cfg_phy_unrstz = REG_FIELD(DSI_PHY_RSTZ_V101, 1, 1),
+ .cfg_phy_enableclk = REG_FIELD(DSI_PHY_RSTZ_V101, 2, 2),
+ .cfg_phy_nlanes = REG_FIELD(DSI_PHY_IF_CFG_V101, 0, 1),
+ .cfg_phy_stop_wait_time = REG_FIELD(DSI_PHY_IF_CFG_V101, 2, 9),
+ .cfg_phy_status = REG_FIELD(DSI_PHY_STATUS_V101, 0, 0),
+ .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG_V101, 0, 4),
+ .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 0, 15),
+ .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 16, 31),
+ .cfg_int_stat0 = REG_FIELD(DSI_ERROR_ST0_V101, 0, 20),
+ .cfg_int_stat1 = REG_FIELD(DSI_ERROR_ST1_V101, 0, 17),
+ .cfg_int_mask0 = REG_FIELD(DSI_ERROR_MSK0_V101, 0, 20),
+ .cfg_int_mask1 = REG_FIELD(DSI_ERROR_MSK1_V101, 0, 17),
+ .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR_V101, 0, 31),
+ .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA_V101, 0, 31),
+};
+
/*
* Check if either a link to a master or slave is present
*/
@@ -466,6 +561,9 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
case HWVER_131:
cmd_mode_lp = CMD_MODE_ALL_LP;
break;
+ case HWVER_101:
+ cmd_mode_lp = CMD_MODE_ALL_LP_V101;
+ break;
}
if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
@@ -644,7 +742,7 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
#ifdef CONFIG_DEBUG_FS
- if (dsi->vpg) {
+ if (dsi->hw_version > HWVER_101 && dsi->vpg) {
regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_en, 1);
regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_horiz,
dsi->vpg_horizontal ? 1 : 0);
@@ -662,9 +760,15 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
dw_mipi_dsi_video_mode_config(dsi);
+ if (dsi->hw_version == HWVER_101)
+ regmap_field_write(dsi->field_vid_mode_en, 1);
+
regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
} else {
regmap_field_write(dsi->field_cmd_mode_en, 1);
+
+ if (dsi->hw_version == HWVER_101)
+ regmap_field_write(dsi->field_vid_mode_en, 0);
}
regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
@@ -857,9 +961,13 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
- regmap_field_write(dsi->field_phy_max_rd_time, 10000);
- regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
- regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
+ if (dsi->hw_version > HWVER_101) {
+ regmap_field_write(dsi->field_phy_max_rd_time, 10000);
+ regmap_field_write(dsi->field_phy_clkhs2lp_time,
+ timing.clk_hs2lp);
+ regmap_field_write(dsi->field_phy_clklp2hs_time,
+ timing.clk_lp2hs);
+ }
}
static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -880,7 +988,8 @@ static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
regmap_field_write(dsi->field_phy_unrstz, 0);
regmap_field_write(dsi->field_phy_unshutdownz, 0);
- regmap_field_write(dsi->field_phy_forcepll, 0);
+ if (dsi->hw_version > HWVER_101)
+ regmap_field_write(dsi->field_phy_forcepll, 0);
regmap_field_write(dsi->field_phy_testclr, 0);
regmap_field_write(dsi->field_phy_testclr, 1);
@@ -896,7 +1005,8 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
regmap_field_write(dsi->field_phy_unrstz, 1);
regmap_field_write(dsi->field_phy_unshutdownz, 1);
- regmap_field_write(dsi->field_phy_forcepll, 1);
+ if (dsi->hw_version > HWVER_101)
+ regmap_field_write(dsi->field_phy_forcepll, 1);
ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
val, val & PHY_LOCK,
@@ -1131,6 +1241,9 @@ static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
case HWVER_131:
variant = &dw_mipi_dsi_v130_v131_layout;
break;
+ case HWVER_101:
+ variant = &dw_mipi_dsi_v101_layout;
+ break;
default:
DRM_ERROR("Unrecognized DSI host controller HW revision\n");
return -ENODEV;
--
2.26.0
In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.
The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.
Signed-off-by: Adrian Ratiu <[email protected]>
---
New in v5.
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 ++++++++++--------
1 file changed, 117 insertions(+), 91 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7b..6d9e2f21c9cc 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
#include <linux/reset.h>
#include <video/mipi_display.h>
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
struct drm_bridge *panel_bridge;
struct device *dev;
void __iomem *base;
+ struct regmap *regs;
struct clk *pclk;
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
u32 lanes;
u32 format;
unsigned long mode_flags;
+ u32 hw_version;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
};
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .name = "dw-mipi-dsi",
+};
+
/*
* Check if either a link to a master or slave is present
*/
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
}
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
- writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
- return readl(dsi->base + reg);
-}
-
static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
@@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
- dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
- dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+ regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+ regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
}
static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
{
int ret;
- u32 val, mask;
+ u32 val = 0, mask;
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_CMD_FULL), 1000,
- CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_CMD_FULL), 1000,
+ CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
- dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+ regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, (val & mask) == mask,
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, (val & mask) == mask,
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
const u8 *tx_buf = packet->payload;
int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
__le32 word;
- u32 val;
+ u32 val = 0;
while (len) {
if (len < pld_data_bytes) {
word = 0;
memcpy(&word, tx_buf, len);
- dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+ regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+ le32_to_cpu(word));
len = 0;
} else {
memcpy(&word, tx_buf, pld_data_bytes);
- dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+ regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+ le32_to_cpu(word));
tx_buf += pld_data_bytes;
len -= pld_data_bytes;
}
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_W_FULL), 1000,
- CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_PLD_W_FULL),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev,
"failed to get available write payload FIFO\n");
@@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
{
int i, j, ret, len = msg->rx_len;
u8 *buf = msg->rx_buf;
- u32 val;
+ u32 val = 0;
/* Wait end of the read operation */
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_RD_CMD_BUSY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_RD_CMD_BUSY),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Timeout during read operation\n");
return ret;
@@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
for (i = 0; i < len; i += 4) {
/* Read fifo must not be empty before all bytes are read */
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_R_EMPTY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_PLD_R_EMPTY),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Read payload FIFO is empty\n");
return ret;
}
- val = dsi_read(dsi, DSI_GEN_PLD_DATA);
+ regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
for (j = 0; j < 4 && j + i < len; j++)
buf[i + j] = val >> (8 * j);
}
@@ -536,29 +538,29 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
}
#endif /* CONFIG_DEBUG_FS */
- dsi_write(dsi, DSI_VID_MODE_CFG, val);
+ regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
}
static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
unsigned long mode_flags)
{
- dsi_write(dsi, DSI_PWR_UP, RESET);
+ regmap_write(dsi->regs, DSI_PWR_UP, RESET);
if (mode_flags & MIPI_DSI_MODE_VIDEO) {
- dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+ regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
dw_mipi_dsi_video_mode_config(dsi);
- dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+ regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
} else {
- dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
}
- dsi_write(dsi, DSI_PWR_UP, POWERUP);
+ regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
}
static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
{
- dsi_write(dsi, DSI_PWR_UP, RESET);
- dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
+ regmap_write(dsi->regs, DSI_PWR_UP, RESET);
+ regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
}
static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
*/
u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
- dsi_write(dsi, DSI_PWR_UP, RESET);
+ regmap_write(dsi->regs, DSI_PWR_UP, RESET);
/*
* TODO dw drv improvements
* timeout clock division should be computed with the
* high speed transmission counter timeout and byte lane...
*/
- dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
+ regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
TX_ESC_CLK_DIVISION(esc_clk_division));
}
@@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
val |= HSYNC_ACTIVE_LOW;
- dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
- dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
- dsi_write(dsi, DSI_DPI_CFG_POL, val);
+ regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
+ regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
+ regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
/*
* TODO dw drv improvements
* largest packet sizes during hfp or during vsa/vpb/vfp
* should be computed according to byte lane, lane number and only
* if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
*/
- dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
+ regmap_write(dsi->regs, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
| INVACT_LPCMD_TIME(4));
}
static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
{
- dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
+ regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
}
static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
@@ -638,7 +640,7 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
* non-burst video modes, see dw_mipi_dsi_video_mode_config()...
*/
- dsi_write(dsi, DSI_VID_PKT_SIZE,
+ regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
dw_mipi_is_dual_mode(dsi) ?
VID_PKT_SIZE(mode->hdisplay / 2) :
VID_PKT_SIZE(mode->hdisplay));
@@ -651,14 +653,15 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
* compute high speed transmission counter timeout according
* to the timeout clock division (TO_CLK_DIVISION) and byte lane...
*/
- dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+ regmap_write(dsi->regs, DSI_TO_CNT_CFG,
+ HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
/*
* TODO dw drv improvements
* the Bus-Turn-Around Timeout Counter should be computed
* according to byte lane...
*/
- dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
- dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
+ regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
}
/* Get lane byte clock cycles. */
@@ -692,13 +695,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
* computations below may be improved...
*/
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
- dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
+ regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
- dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
+ regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
- dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
+ regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
}
static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
@@ -711,10 +714,10 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
vfp = mode->vsync_start - mode->vdisplay;
vbp = mode->vtotal - mode->vsync_end;
- dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
- dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
- dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
- dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
+ regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
+ regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
+ regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
+ regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
}
static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
@@ -737,23 +740,25 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
* DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
*/
- hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+ regmap_read(dsi->regs, DSI_VERSION, &hw_version);
+ hw_version &= VERSION;
if (hw_version >= HWVER_131) {
- dsi_write(dsi, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
- PHY_LP2HS_TIME_V131(timing.data_lp2hs));
- dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
+ regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
+ PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
+ PHY_LP2HS_TIME_V131(timing.data_lp2hs));
+ regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
+ MAX_RD_TIME_V131(10000));
} else {
- dsi_write(dsi, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME(timing.data_hs2lp) |
- PHY_LP2HS_TIME(timing.data_lp2hs) |
- MAX_RD_TIME(10000));
+ regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
+ PHY_HS2LP_TIME(timing.data_hs2lp) |
+ PHY_LP2HS_TIME(timing.data_lp2hs) |
+ MAX_RD_TIME(10000));
}
- dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
- PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
- PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
+ regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
+ PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
+ PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
}
static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -763,46 +768,49 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
* stop wait time should be the maximum between host dsi
* and panel stop wait times
*/
- dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
- N_LANES(dsi->lanes));
+ regmap_write(dsi->regs, DSI_PHY_IF_CFG,
+ PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
}
static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
{
/* Clear PHY state */
- dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
- | PHY_RSTZ | PHY_SHUTDOWNZ);
- dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
- dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
- dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
+ | PHY_RSTZ | PHY_SHUTDOWNZ);
+ regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
+ regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
}
static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
{
- u32 val;
+ u32 val = 0;
int ret;
- dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
- PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+ regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
+ PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
- ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
- val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
+ val, val & PHY_LOCK,
+ 1000, PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
- ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
- val, val & PHY_STOP_STATE_CLK_LANE, 1000,
- PHY_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
+ val, val & PHY_STOP_STATE_CLK_LANE, 1000,
+ PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
}
static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
{
- dsi_read(dsi, DSI_INT_ST0);
- dsi_read(dsi, DSI_INT_ST1);
- dsi_write(dsi, DSI_INT_MSK0, 0);
- dsi_write(dsi, DSI_INT_MSK1, 0);
+ u32 val;
+
+ regmap_read(dsi->regs, DSI_INT_ST0, &val);
+ regmap_read(dsi->regs, DSI_INT_ST1, &val);
+ regmap_write(dsi->regs, DSI_INT_MSK0, 0);
+ regmap_write(dsi->regs, DSI_INT_MSK1, 0);
}
static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
@@ -989,6 +997,14 @@ static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
#endif /* CONFIG_DEBUG_FS */
+static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
+{
+ regmap_read(dsi->regs, DSI_VERSION, &dsi->hw_version);
+ dsi->hw_version &= VERSION;
+ if (!dsi->hw_version)
+ dev_err(dsi->dev, "Failed to read DSI hw version register\n");
+}
+
static struct dw_mipi_dsi *
__dw_mipi_dsi_probe(struct platform_device *pdev,
const struct dw_mipi_dsi_plat_data *plat_data)
@@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
dsi->base = plat_data->base;
}
+ dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
+ &dw_mipi_dsi_regmap_cfg);
+ if (IS_ERR(dsi->regs)) {
+ ret = PTR_ERR(dsi->regs);
+ DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
+ return ERR_PTR(ret);
+ }
+
dsi->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(dsi->pclk)) {
ret = PTR_ERR(dsi->pclk);
@@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
clk_disable_unprepare(dsi->pclk);
}
+ dw_mipi_dsi_get_hw_version(dsi);
+
dw_mipi_dsi_debugfs_init(dsi);
pm_runtime_enable(dev);
--
2.26.0
Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.
The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.
The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.
The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.
Suggested-by: Boris Brezillon <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
Changes since v4:
- Move regmap infrastructure logic to a separate commit (Ezequiel)
- Consolidate field infrastructure in this commit (Ezequiel)
- Move the dsi v1.01 layout logic to a separate commit (Ezequiel)
Changes since v2:
- Added const declarations to dw_mipi_dsi structs (Emil)
- Fixed commit tags (Emil)
Changes since v1:
- Moved register definitions & regmap initialization into bridge
module. Platform drivers get the regmap via plat_data after calling
the bridge probe (Emil).
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 510 ++++++++++++------
1 file changed, 352 insertions(+), 158 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6d9e2f21c9cc..5b78ff925af0 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
#include <drm/drm_probe_helper.h>
#define HWVER_131 0x31333100 /* IP version 1.31 */
+#define HWVER_130 0x31333000 /* IP version 1.30 */
#define DSI_VERSION 0x00
#define VERSION GENMASK(31, 8)
@@ -47,7 +48,6 @@
#define DPI_VCID(vcid) ((vcid) & 0x3)
#define DSI_DPI_COLOR_CODING 0x10
-#define LOOSELY18_EN BIT(8)
#define DPI_COLOR_CODING_16BIT_1 0x0
#define DPI_COLOR_CODING_16BIT_2 0x1
#define DPI_COLOR_CODING_16BIT_3 0x2
@@ -56,11 +56,6 @@
#define DPI_COLOR_CODING_24BIT 0x5
#define DSI_DPI_CFG_POL 0x14
-#define COLORM_ACTIVE_LOW BIT(4)
-#define SHUTD_ACTIVE_LOW BIT(3)
-#define HSYNC_ACTIVE_LOW BIT(2)
-#define VSYNC_ACTIVE_LOW BIT(1)
-#define DATAEN_ACTIVE_LOW BIT(0)
#define DSI_DPI_LP_CMD_TIM 0x18
#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
#define DSI_GEN_VCID 0x30
#define DSI_MODE_CFG 0x34
-#define ENABLE_VIDEO_MODE 0
-#define ENABLE_CMD_MODE BIT(0)
#define DSI_VID_MODE_CFG 0x38
-#define ENABLE_LOW_POWER (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK (0x3f << 8)
+#define ENABLE_LOW_POWER 0x3f
+
#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
#define VID_MODE_TYPE_BURST 0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLE BIT(16)
-#define VID_MODE_VPG_HORIZONTAL BIT(24)
#define DSI_VID_PKT_SIZE 0x3c
-#define VID_PKT_SIZE(p) ((p) & 0x3fff)
#define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
#define DSI_VID_NULL_SIZE 0x44
-#define VID_NULL_SIZE(b) ((b) & 0x1fff)
#define DSI_VID_HSA_TIME 0x48
#define DSI_VID_HBP_TIME 0x4c
@@ -125,7 +112,6 @@
#define GEN_SW_2P_TX_LP BIT(10)
#define GEN_SW_1P_TX_LP BIT(9)
#define GEN_SW_0P_TX_LP BIT(8)
-#define ACK_RQST_EN BIT(1)
#define TEAR_FX_EN BIT(0)
#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
@@ -154,8 +140,6 @@
#define GEN_CMD_EMPTY BIT(0)
#define DSI_TO_CNT_CFG 0x78
-#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
-#define LPRX_TO_CNT(p) ((p) & 0xffff)
#define DSI_HS_RD_TO_CNT 0x7c
#define DSI_LP_RD_TO_CNT 0x80
@@ -164,52 +148,17 @@
#define DSI_BTA_TO_CNT 0x8c
#define DSI_LPCLK_CTRL 0x94
-#define AUTO_CLKLANE_CTRL BIT(1)
-#define PHY_TXREQUESTCLKHS BIT(0)
-
#define DSI_PHY_TMR_LPCLK_CFG 0x98
-#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
-#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
-
#define DSI_PHY_TMR_CFG 0x9c
-#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
-#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
-#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
-#define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
-#define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
-
#define DSI_PHY_RSTZ 0xa0
-#define PHY_DISFORCEPLL 0
-#define PHY_ENFORCEPLL BIT(3)
-#define PHY_DISABLECLK 0
-#define PHY_ENABLECLK BIT(2)
-#define PHY_RSTZ 0
-#define PHY_UNRSTZ BIT(1)
-#define PHY_SHUTDOWNZ 0
-#define PHY_UNSHUTDOWNZ BIT(0)
-
#define DSI_PHY_IF_CFG 0xa4
-#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
-#define N_LANES(n) (((n) - 1) & 0x3)
-
-#define DSI_PHY_ULPS_CTRL 0xa8
-#define DSI_PHY_TX_TRIGGERS 0xac
#define DSI_PHY_STATUS 0xb0
#define PHY_STOP_STATE_CLK_LANE BIT(2)
#define PHY_LOCK BIT(0)
#define DSI_PHY_TST_CTRL0 0xb4
-#define PHY_TESTCLK BIT(1)
-#define PHY_UNTESTCLK 0
-#define PHY_TESTCLR BIT(0)
-#define PHY_UNTESTCLR 0
-
#define DSI_PHY_TST_CTRL1 0xb8
-#define PHY_TESTEN BIT(16)
-#define PHY_UNTESTEN 0
-#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
-#define PHY_TESTDIN(n) ((n) & 0xff)
#define DSI_INT_ST0 0xbc
#define DSI_INT_ST1 0xc0
@@ -217,7 +166,6 @@
#define DSI_INT_MSK1 0xc8
#define DSI_PHY_TMR_RD_CFG 0xf4
-#define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
#define PHY_STATUS_TIMEOUT_US 10000
#define CMD_PKT_STATUS_TIMEOUT_US 20000
@@ -250,6 +198,53 @@ struct dw_mipi_dsi {
struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
const struct dw_mipi_dsi_plat_data *plat_data;
+
+ struct regmap_field *field_dpi_18loosely_en;
+ struct regmap_field *field_dpi_color_coding;
+ struct regmap_field *field_dpi_vid;
+ struct regmap_field *field_dpi_vsync_active_low;
+ struct regmap_field *field_dpi_hsync_active_low;
+ struct regmap_field *field_cmd_mode_ack_rqst_en;
+ struct regmap_field *field_cmd_mode_all_lp_en;
+ struct regmap_field *field_cmd_mode_en;
+ struct regmap_field *field_cmd_pkt_status;
+ struct regmap_field *field_vid_mode_en;
+ struct regmap_field *field_vid_mode_type;
+ struct regmap_field *field_vid_mode_low_power;
+ struct regmap_field *field_vid_mode_vpg_en;
+ struct regmap_field *field_vid_mode_vpg_horiz;
+ struct regmap_field *field_vid_pkt_size;
+ struct regmap_field *field_vid_hsa_time;
+ struct regmap_field *field_vid_hbp_time;
+ struct regmap_field *field_vid_hline_time;
+ struct regmap_field *field_vid_vsa_time;
+ struct regmap_field *field_vid_vbp_time;
+ struct regmap_field *field_vid_vfp_time;
+ struct regmap_field *field_vid_vactive_time;
+ struct regmap_field *field_phy_txrequestclkhs;
+ struct regmap_field *field_phy_bta_time;
+ struct regmap_field *field_phy_max_rd_time;
+ struct regmap_field *field_phy_lp2hs_time;
+ struct regmap_field *field_phy_hs2lp_time;
+ struct regmap_field *field_phy_clklp2hs_time;
+ struct regmap_field *field_phy_clkhs2lp_time;
+ struct regmap_field *field_phy_testclr;
+ struct regmap_field *field_phy_unshutdownz;
+ struct regmap_field *field_phy_unrstz;
+ struct regmap_field *field_phy_enableclk;
+ struct regmap_field *field_phy_forcepll;
+ struct regmap_field *field_phy_nlanes;
+ struct regmap_field *field_phy_stop_wait_time;
+ struct regmap_field *field_phy_status;
+ struct regmap_field *field_pckhdl_cfg;
+ struct regmap_field *field_hstx_timeout_counter;
+ struct regmap_field *field_lprx_timeout_counter;
+ struct regmap_field *field_int_stat0;
+ struct regmap_field *field_int_stat1;
+ struct regmap_field *field_int_mask0;
+ struct regmap_field *field_int_mask1;
+ struct regmap_field *field_gen_hdr;
+ struct regmap_field *field_gen_payload;
};
static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
@@ -259,6 +254,111 @@ static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
.name = "dw-mipi-dsi",
};
+struct dw_mipi_dsi_variant {
+ /* Regmap field configs for DSI adapter */
+ struct reg_field cfg_dpi_18loosely_en;
+ struct reg_field cfg_dpi_color_coding;
+ struct reg_field cfg_dpi_vid;
+ struct reg_field cfg_dpi_vsync_active_low;
+ struct reg_field cfg_dpi_hsync_active_low;
+ struct reg_field cfg_cmd_mode_en;
+ struct reg_field cfg_cmd_mode_ack_rqst_en;
+ struct reg_field cfg_cmd_mode_all_lp_en;
+ struct reg_field cfg_cmd_pkt_status;
+ struct reg_field cfg_vid_mode_en;
+ struct reg_field cfg_vid_mode_type;
+ struct reg_field cfg_vid_mode_low_power;
+ struct reg_field cfg_vid_mode_vpg_en;
+ struct reg_field cfg_vid_mode_vpg_horiz;
+ struct reg_field cfg_vid_pkt_size;
+ struct reg_field cfg_vid_hsa_time;
+ struct reg_field cfg_vid_hbp_time;
+ struct reg_field cfg_vid_hline_time;
+ struct reg_field cfg_vid_vsa_time;
+ struct reg_field cfg_vid_vbp_time;
+ struct reg_field cfg_vid_vfp_time;
+ struct reg_field cfg_vid_vactive_time;
+ struct reg_field cfg_phy_txrequestclkhs;
+ struct reg_field cfg_phy_bta_time;
+ struct reg_field cfg_phy_max_rd_time;
+ struct reg_field cfg_phy_lp2hs_time;
+ struct reg_field cfg_phy_hs2lp_time;
+ struct reg_field cfg_phy_max_rd_time_v131;
+ struct reg_field cfg_phy_lp2hs_time_v131;
+ struct reg_field cfg_phy_hs2lp_time_v131;
+ struct reg_field cfg_phy_clklp2hs_time;
+ struct reg_field cfg_phy_clkhs2lp_time;
+ struct reg_field cfg_phy_testclr;
+ struct reg_field cfg_phy_unshutdownz;
+ struct reg_field cfg_phy_unrstz;
+ struct reg_field cfg_phy_enableclk;
+ struct reg_field cfg_phy_forcepll;
+ struct reg_field cfg_phy_nlanes;
+ struct reg_field cfg_phy_stop_wait_time;
+ struct reg_field cfg_phy_status;
+ struct reg_field cfg_pckhdl_cfg;
+ struct reg_field cfg_hstx_timeout_counter;
+ struct reg_field cfg_lprx_timeout_counter;
+ struct reg_field cfg_int_stat0;
+ struct reg_field cfg_int_stat1;
+ struct reg_field cfg_int_mask0;
+ struct reg_field cfg_int_mask1;
+ struct reg_field cfg_gen_hdr;
+ struct reg_field cfg_gen_payload;
+};
+
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
+ .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
+ .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
+ .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 2),
+ .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
+ .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
+ .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
+ .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG, 8, 24),
+ .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
+ .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
+ .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
+ .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
+ .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
+ .cfg_vid_mode_vpg_en = REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
+ .cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
+ .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
+ .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
+ .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
+ .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
+ .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
+ .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
+ .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
+ .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+ .cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
+ .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
+ .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+ .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
+ .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
+ .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
+ .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+ .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+ .cfg_phy_clklp2hs_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
+ .cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
+ .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
+ .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ, 0, 0),
+ .cfg_phy_unrstz = REG_FIELD(DSI_PHY_RSTZ, 1, 1),
+ .cfg_phy_enableclk = REG_FIELD(DSI_PHY_RSTZ, 2, 2),
+ .cfg_phy_forcepll = REG_FIELD(DSI_PHY_RSTZ, 3, 3),
+ .cfg_phy_nlanes = REG_FIELD(DSI_PHY_IF_CFG, 0, 1),
+ .cfg_phy_stop_wait_time = REG_FIELD(DSI_PHY_IF_CFG, 8, 15),
+ .cfg_phy_status = REG_FIELD(DSI_PHY_STATUS, 0, 0),
+ .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
+ .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
+ .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
+ .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 31),
+ .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 31),
+ .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 31),
+ .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 31),
+ .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 31),
+ .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
+};
+
/*
* Check if either a link to a master or slave is present
*/
@@ -359,15 +459,22 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
const struct mipi_dsi_msg *msg)
{
bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
- u32 val = 0;
+ u32 cmd_mode_lp = 0;
+
+ switch (dsi->hw_version) {
+ case HWVER_130:
+ case HWVER_131:
+ cmd_mode_lp = CMD_MODE_ALL_LP;
+ break;
+ }
if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
- val |= ACK_RQST_EN;
+ regmap_field_write(dsi->field_cmd_mode_ack_rqst_en, 1);
+
if (lpm)
- val |= CMD_MODE_ALL_LP;
+ regmap_field_write(dsi->field_cmd_mode_all_lp_en, cmd_mode_lp);
- regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
- regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
+ regmap_field_write(dsi->field_phy_txrequestclkhs, lpm ? 0 : 1);
}
static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
@@ -375,18 +482,18 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
int ret;
u32 val = 0, mask;
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_CMD_FULL), 1000,
- CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val, !(val & GEN_CMD_FULL),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
- regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
+ regmap_field_write(dsi->field_gen_hdr, hdr_val);
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
val, (val & mask) == mask,
1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
@@ -409,20 +516,22 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
if (len < pld_data_bytes) {
word = 0;
memcpy(&word, tx_buf, len);
- regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
- le32_to_cpu(word));
+ regmap_field_write(dsi->field_gen_payload,
+ le32_to_cpu(word));
len = 0;
} else {
memcpy(&word, tx_buf, pld_data_bytes);
- regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
- le32_to_cpu(word));
+ regmap_field_write(dsi->field_gen_payload,
+ le32_to_cpu(word));
tx_buf += pld_data_bytes;
len -= pld_data_bytes;
}
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_W_FULL),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val,
+ !(val & GEN_PLD_W_FULL),
+ 1000,
+ CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev,
"failed to get available write payload FIFO\n");
@@ -443,9 +552,9 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
u32 val = 0;
/* Wait end of the read operation */
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_RD_CMD_BUSY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val, !(val & GEN_RD_CMD_BUSY),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Timeout during read operation\n");
return ret;
@@ -453,15 +562,17 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
for (i = 0; i < len; i += 4) {
/* Read fifo must not be empty before all bytes are read */
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_R_EMPTY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val,
+ !(val & GEN_PLD_R_EMPTY),
+ 1000,
+ CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Read payload FIFO is empty\n");
return ret;
}
- regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
+ regmap_field_read(dsi->field_gen_payload, &val);
for (j = 0; j < 4 && j + i < len; j++)
buf[i + j] = val >> (8 * j);
}
@@ -515,30 +626,30 @@ static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
{
- u32 val;
-
/*
* TODO dw drv improvements
* enabling low power is panel-dependent, we should use the
* panel configuration here...
*/
- val = ENABLE_LOW_POWER;
+ regmap_field_write(dsi->field_vid_mode_low_power, ENABLE_LOW_POWER);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
- val |= VID_MODE_TYPE_BURST;
+ regmap_field_write(dsi->field_vid_mode_type,
+ VID_MODE_TYPE_BURST);
else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
- val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
+ regmap_field_write(dsi->field_vid_mode_type,
+ VID_MODE_TYPE_NON_BURST_SYNC_PULSES);
else
- val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
+ regmap_field_write(dsi->field_vid_mode_type,
+ VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
#ifdef CONFIG_DEBUG_FS
if (dsi->vpg) {
- val |= VID_MODE_VPG_ENABLE;
- val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
+ regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_en, 1);
+ regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_horiz,
+ dsi->vpg_horizontal ? 1 : 0);
}
#endif /* CONFIG_DEBUG_FS */
-
- regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
}
static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
@@ -547,11 +658,13 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
regmap_write(dsi->regs, DSI_PWR_UP, RESET);
if (mode_flags & MIPI_DSI_MODE_VIDEO) {
- regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+ regmap_field_write(dsi->field_cmd_mode_en, 0);
+
dw_mipi_dsi_video_mode_config(dsi);
- regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+
+ regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
} else {
- regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_field_write(dsi->field_cmd_mode_en, 1);
}
regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
@@ -560,7 +673,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
{
regmap_write(dsi->regs, DSI_PWR_UP, RESET);
- regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
+ regmap_field_write(dsi->field_phy_unrstz, 0);
}
static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -589,14 +702,15 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
const struct drm_display_mode *mode)
{
- u32 val = 0, color = 0;
+ u32 color = 0;
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
color = DPI_COLOR_CODING_24BIT;
break;
case MIPI_DSI_FMT_RGB666:
- color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
+ color = DPI_COLOR_CODING_18BIT_2;
+ regmap_field_write(dsi->field_dpi_18loosely_en, 1);
break;
case MIPI_DSI_FMT_RGB666_PACKED:
color = DPI_COLOR_CODING_18BIT_1;
@@ -606,14 +720,15 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
break;
}
- if (mode->flags & DRM_MODE_FLAG_NVSYNC)
- val |= VSYNC_ACTIVE_LOW;
- if (mode->flags & DRM_MODE_FLAG_NHSYNC)
- val |= HSYNC_ACTIVE_LOW;
+ regmap_field_write(dsi->field_dpi_color_coding, color);
+
+ if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
+ regmap_field_write(dsi->field_dpi_vsync_active_low, 1);
+ if (!(mode->flags & DRM_MODE_FLAG_NHSYNC))
+ regmap_field_write(dsi->field_dpi_hsync_active_low, 1);
+
+ regmap_field_write(dsi->field_dpi_vid, DPI_VCID(dsi->channel));
- regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
- regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
- regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
/*
* TODO dw drv improvements
* largest packet sizes during hfp or during vsa/vpb/vfp
@@ -626,7 +741,8 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
{
- regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
+ regmap_field_write(dsi->field_pckhdl_cfg,
+ CRC_RX_EN | ECC_RX_EN | BTA_EN);
}
static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
@@ -639,11 +755,9 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
* DSI_VNPCR.NPSIZE... especially because this driver supports
* non-burst video modes, see dw_mipi_dsi_video_mode_config()...
*/
-
- regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
- dw_mipi_is_dual_mode(dsi) ?
- VID_PKT_SIZE(mode->hdisplay / 2) :
- VID_PKT_SIZE(mode->hdisplay));
+ regmap_field_write(dsi->field_vid_pkt_size,
+ dw_mipi_is_dual_mode(dsi) ?
+ mode->hdisplay / 2 : mode->hdisplay);
}
static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
@@ -653,15 +767,17 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
* compute high speed transmission counter timeout according
* to the timeout clock division (TO_CLK_DIVISION) and byte lane...
*/
- regmap_write(dsi->regs, DSI_TO_CNT_CFG,
- HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+ regmap_field_write(dsi->field_hstx_timeout_counter, 1000);
+ regmap_field_write(dsi->field_lprx_timeout_counter, 1000);
+
/*
* TODO dw drv improvements
* the Bus-Turn-Around Timeout Counter should be computed
* according to byte lane...
*/
- regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
- regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_field_write(dsi->field_phy_bta_time, 0xd00);
+
+ regmap_field_write(dsi->field_cmd_mode_en, 1);
}
/* Get lane byte clock cycles. */
@@ -695,13 +811,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
* computations below may be improved...
*/
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
- regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
+ regmap_field_write(dsi->field_vid_hline_time, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
- regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
+ regmap_field_write(dsi->field_vid_hsa_time, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
- regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
+ regmap_field_write(dsi->field_vid_hbp_time, lbcc);
}
static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
@@ -714,17 +830,16 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
vfp = mode->vsync_start - mode->vdisplay;
vbp = mode->vtotal - mode->vsync_end;
- regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
- regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
- regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
- regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
+ regmap_field_write(dsi->field_vid_vactive_time, vactive);
+ regmap_field_write(dsi->field_vid_vsa_time, vsa);
+ regmap_field_write(dsi->field_vid_vfp_time, vfp);
+ regmap_field_write(dsi->field_vid_vbp_time, vbp);
}
static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
{
const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
struct dw_mipi_dsi_dphy_timing timing;
- u32 hw_version;
int ret;
ret = phy_ops->get_timing(dsi->plat_data->priv_data,
@@ -739,26 +854,12 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
* note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
* DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
*/
+ regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
+ regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
- regmap_read(dsi->regs, DSI_VERSION, &hw_version);
- hw_version &= VERSION;
-
- if (hw_version >= HWVER_131) {
- regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
- PHY_LP2HS_TIME_V131(timing.data_lp2hs));
- regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
- MAX_RD_TIME_V131(10000));
- } else {
- regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME(timing.data_hs2lp) |
- PHY_LP2HS_TIME(timing.data_lp2hs) |
- MAX_RD_TIME(10000));
- }
-
- regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
- PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
- PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
+ regmap_field_write(dsi->field_phy_max_rd_time, 10000);
+ regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
+ regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
}
static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -768,18 +869,22 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
* stop wait time should be the maximum between host dsi
* and panel stop wait times
*/
- regmap_write(dsi->regs, DSI_PHY_IF_CFG,
- PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
+ regmap_field_write(dsi->field_phy_stop_wait_time, 0x20);
+ regmap_field_write(dsi->field_phy_nlanes, dsi->lanes - 1);
}
static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
{
/* Clear PHY state */
- regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
- | PHY_RSTZ | PHY_SHUTDOWNZ);
- regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
- regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
- regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ regmap_field_write(dsi->field_phy_enableclk, 0);
+ regmap_field_write(dsi->field_phy_unrstz, 0);
+ regmap_field_write(dsi->field_phy_unshutdownz, 0);
+
+ regmap_field_write(dsi->field_phy_forcepll, 0);
+
+ regmap_field_write(dsi->field_phy_testclr, 0);
+ regmap_field_write(dsi->field_phy_testclr, 1);
+ regmap_field_write(dsi->field_phy_testclr, 0);
}
static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
@@ -787,18 +892,21 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
u32 val = 0;
int ret;
- regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
- PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+ regmap_field_write(dsi->field_phy_enableclk, 1);
+ regmap_field_write(dsi->field_phy_unrstz, 1);
+ regmap_field_write(dsi->field_phy_unshutdownz, 1);
+
+ regmap_field_write(dsi->field_phy_forcepll, 1);
- ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
- val, val & PHY_LOCK,
- 1000, PHY_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
+ val, val & PHY_LOCK,
+ 1000, PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
- ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
- val, val & PHY_STOP_STATE_CLK_LANE, 1000,
- PHY_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
+ val, val & PHY_STOP_STATE_CLK_LANE,
+ 1000, PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
}
@@ -807,10 +915,10 @@ static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
{
u32 val;
- regmap_read(dsi->regs, DSI_INT_ST0, &val);
- regmap_read(dsi->regs, DSI_INT_ST1, &val);
- regmap_write(dsi->regs, DSI_INT_MSK0, 0);
- regmap_write(dsi->regs, DSI_INT_MSK1, 0);
+ regmap_field_read(dsi->field_int_stat0, &val);
+ regmap_field_read(dsi->field_int_stat1, &val);
+ regmap_field_write(dsi->field_int_mask0, 0);
+ regmap_field_write(dsi->field_int_mask1, 0);
}
static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
@@ -1005,6 +1113,86 @@ static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
dev_err(dsi->dev, "Failed to read DSI hw version register\n");
}
+#define INIT_FIELD(f) INIT_FIELD_CFG(field_##f, cfg_##f)
+#define INIT_FIELD_CFG(f, conf) \
+ do { \
+ dsi->f = devm_regmap_field_alloc(dsi->dev, dsi->regs, \
+ variant->conf); \
+ if (IS_ERR(dsi->f)) \
+ dev_warn(dsi->dev, "Ignoring regmap field " #f "\n"); \
+ } while (0)
+
+static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
+{
+ const struct dw_mipi_dsi_variant *variant;
+
+ switch (dsi->hw_version) {
+ case HWVER_130:
+ case HWVER_131:
+ variant = &dw_mipi_dsi_v130_v131_layout;
+ break;
+ default:
+ DRM_ERROR("Unrecognized DSI host controller HW revision\n");
+ return -ENODEV;
+ }
+
+ INIT_FIELD(dpi_18loosely_en);
+ INIT_FIELD(dpi_vid);
+ INIT_FIELD(dpi_color_coding);
+ INIT_FIELD(dpi_vsync_active_low);
+ INIT_FIELD(dpi_hsync_active_low);
+ INIT_FIELD(cmd_mode_ack_rqst_en);
+ INIT_FIELD(cmd_mode_all_lp_en);
+ INIT_FIELD(cmd_mode_en);
+ INIT_FIELD(cmd_pkt_status);
+ INIT_FIELD(vid_mode_en);
+ INIT_FIELD(vid_mode_type);
+ INIT_FIELD(vid_mode_low_power);
+ INIT_FIELD(vid_pkt_size);
+ INIT_FIELD(vid_hsa_time);
+ INIT_FIELD(vid_hbp_time);
+ INIT_FIELD(vid_hline_time);
+ INIT_FIELD(vid_vsa_time);
+ INIT_FIELD(vid_vbp_time);
+ INIT_FIELD(vid_vfp_time);
+ INIT_FIELD(vid_vactive_time);
+ INIT_FIELD(phy_txrequestclkhs);
+ INIT_FIELD(phy_testclr);
+ INIT_FIELD(phy_unshutdownz);
+ INIT_FIELD(phy_unrstz);
+ INIT_FIELD(phy_enableclk);
+ INIT_FIELD(phy_nlanes);
+ INIT_FIELD(phy_stop_wait_time);
+ INIT_FIELD(phy_status);
+ INIT_FIELD(pckhdl_cfg);
+ INIT_FIELD(hstx_timeout_counter);
+ INIT_FIELD(lprx_timeout_counter);
+ INIT_FIELD(int_stat0);
+ INIT_FIELD(int_stat1);
+ INIT_FIELD(int_mask0);
+ INIT_FIELD(int_mask1);
+ INIT_FIELD(gen_hdr);
+ INIT_FIELD(gen_payload);
+ INIT_FIELD(phy_bta_time);
+ INIT_FIELD(vid_mode_vpg_en);
+ INIT_FIELD(vid_mode_vpg_horiz);
+ INIT_FIELD(phy_clklp2hs_time);
+ INIT_FIELD(phy_clkhs2lp_time);
+ INIT_FIELD(phy_forcepll);
+
+ if (dsi->hw_version == HWVER_131) {
+ INIT_FIELD_CFG(field_phy_max_rd_time, cfg_phy_max_rd_time_v131);
+ INIT_FIELD_CFG(field_phy_lp2hs_time, cfg_phy_lp2hs_time_v131);
+ INIT_FIELD_CFG(field_phy_hs2lp_time, cfg_phy_hs2lp_time_v131);
+ } else {
+ INIT_FIELD(phy_max_rd_time);
+ INIT_FIELD(phy_lp2hs_time);
+ INIT_FIELD(phy_hs2lp_time);
+ }
+
+ return 0;
+}
+
static struct dw_mipi_dsi *
__dw_mipi_dsi_probe(struct platform_device *pdev,
const struct dw_mipi_dsi_plat_data *plat_data)
@@ -1081,6 +1269,12 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
dw_mipi_dsi_get_hw_version(dsi);
+ ret = dw_mipi_dsi_regmap_fields_init(dsi);
+ if (ret) {
+ dev_err(dev, "Failed to init register layout map: %d\n", ret);
+ return ERR_PTR(ret);
+ }
+
dw_mipi_dsi_debugfs_init(dsi);
pm_runtime_enable(dev);
--
2.26.0
Hi Adrian,
On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu <[email protected]> wrote:
>
> This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
> controller which is embedded in i.MX 6 SoCs.
>
> Based on following patches, but updated/extended to work with existing
> support found in the kernel:
>
> - drm: imx: Support Synopsys DesignWare MIPI DSI host controller
> Signed-off-by: Liu Ying <[email protected]>
>
> - ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
> Signed-off-by: Liu Ying <[email protected]>
This one looks like a devicetree patch, but this patch does not touch
devicetree.
> + ret = clk_prepare_enable(dsi->pllref_clk);
> + if (ret) {
> + dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
> + return ret;
> + }
> +
> + dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
> + if (IS_ERR(dsi->mux_sel)) {
> + ret = PTR_ERR(dsi->mux_sel);
> + dev_err(dev, "%s: Failed to get GPR regmap: %d\n",
> + __func__, ret);
> + return ret;
You should disable the dsi->pllref_clk clock prior to returning the error.
> + dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata);
> + if (IS_ERR(dsi->mipi_dsi)) {
> + ret = PTR_ERR(dsi->mipi_dsi);
> + dev_dbg(dev, "%s: Unable to probe DW DSI host device: %d\n",
> + __func__, ret);
> + return -ENODEV;
Same here. You should disable the clock. Shouldn't you return 'ret'
here instead of -ENODEV?
> +module_platform_driver(imx_mipi_dsi_driver);
> +
> +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver");
> +MODULE_AUTHOR("Liu Ying <[email protected]>");
The freescale.com domain is no longer functional.
Ying Liu's NXP address is [email protected]. You could probably add
your entry as well.
On Mon, Mar 30, 2020 at 8:35 AM Adrian Ratiu <[email protected]> wrote:
> + panel@0 {
> + compatible = "sharp,ls032b3sx01";
> + reg = <0>;
> + reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
> + ports {
> + port@0 {
There is a unit address here without a corresponding reg property.
This gives warning with 'make dt_binding_check'
Hello Fabio, Adrian:
On Mon, 2020-03-30 at 08:49 -0300, Fabio Estevam wrote:
> Hi Adrian,
>
> On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu <[email protected]> wrote:
> > This adds support for the Synopsis DesignWare MIPI DSI v1.01 host
> > controller which is embedded in i.MX 6 SoCs.
> >
> > Based on following patches, but updated/extended to work with existing
> > support found in the kernel:
> >
> > - drm: imx: Support Synopsys DesignWare MIPI DSI host controller
> > Signed-off-by: Liu Ying <[email protected]>
> >
> > - ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
> > Signed-off-by: Liu Ying <[email protected]>
>
> This one looks like a devicetree patch, but this patch does not touch
> devicetree.
>
> > + ret = clk_prepare_enable(dsi->pllref_clk);
> > + if (ret) {
> > + dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__);
> > + return ret;
> > + }
> > +
> > + dsi->mux_sel = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
> > + if (IS_ERR(dsi->mux_sel)) {
> > + ret = PTR_ERR(dsi->mux_sel);
> > + dev_err(dev, "%s: Failed to get GPR regmap: %d\n",
> > + __func__, ret);
> > + return ret;
>
> You should disable the dsi->pllref_clk clock prior to returning the error.
>
Another approach could be moving the clock on and off to
to component_ops.{bind,unbind} (as rockhip driver does).
What exactly is the PLL clock needed for? Would it make sense
to move it some of the PHY power on/off? (Maybe not, but it's worthing
checking).
Also, it seems the other IP blocks have this PLL clock, so maybe
it could be moved to the dw_mipi_dsi core? This could be something
for a follow-up, to avoid creeping this series.
Thanks,
Ezequiel
Hello Adrian,
Here i get a compile error:
On Mon, Mar 30, 2020 at 2:36 PM Adrian Ratiu <[email protected]> wrote:
>
> The Synopsis MIPI DSI v1.01 host controller is quite widely used
> on platforms like i.mx6 and is not very different from the other
> versions like the 1.31/1.30 used on rockchip/stm. The protocols
> appear to be the same, only the register layout is different and
> the newer versions have new features symbolized by new registers
> so adding support for it is just a matter of defining the new
> layout and adding a couple of dsi version checks.
>
> Signed-off-by: Adrian Ratiu <[email protected]>
> ---
> New in v5.
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +++++++++++++++++-
> 1 file changed, 119 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 5b78ff925af0..fb9dbc4fd0f5 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -32,6 +32,7 @@
>
> #define HWVER_131 0x31333100 /* IP version 1.31 */
> #define HWVER_130 0x31333000 /* IP version 1.30 */
> +#define HWVER_101 0x31303000 /* IP version 1.01 */
>
> #define DSI_VERSION 0x00
> #define VERSION GENMASK(31, 8)
> @@ -100,6 +101,25 @@
> #define DSI_EDPI_CMD_SIZE 0x64
>
> #define DSI_CMD_MODE_CFG 0x68
> +
> +#define DSI_DPI_CFG 0x0c
> +#define DSI_TMR_LINE_CFG 0x28
> +#define DSI_VTIMING_CFG 0x2c
> +#define DSI_PHY_TMR_CFG_V101 0x30
> +#define DSI_PHY_IF_CFG_V101 0x58
> +#define DSI_PHY_IF_CTRL 0x5c
> +#define DSI_PHY_RSTZ_V101 0x54
> +#define DSI_PHY_STATUS_V101 0x60
> +#define DSI_PHY_TST_CTRL0_V101 0x64
> +#define DSI_GEN_HDR_V101 0x34
> +#define DSI_GEN_PLD_DATA_V101 0x38
> +#define DSI_CMD_MODE_CFG_V101 0x24
> +#define DSI_CMD_PKT_STATUS_V101 0x3c
> +#define DSI_VID_PKT_CFG 0x20
> +#define DSI_VID_MODE_CFG_V101 0x1c
> +#define DSI_TO_CNT_CFG_V101 0x40
> +#define DSI_PCKHDL_CFG_V101 0x18
> +
> #define MAX_RD_PKT_SIZE_LP BIT(24)
> #define DCS_LW_TX_LP BIT(19)
> #define DCS_SR_0P_TX_LP BIT(18)
> @@ -127,6 +147,33 @@
> GEN_SW_1P_TX_LP | \
> GEN_SW_0P_TX_LP)
>
> +#define EN_TEAR_FX_V101 BIT(14)
> +#define DCS_LW_TX_LP_V101 BIT(12)
> +#define GEN_LW_TX_LP_V101 BIT(11)
> +#define MAX_RD_PKT_SIZE_LP_V101 BIT(10)
> +#define DCS_SW_2P_TX_LP_V101 BIT(9)
> +#define DCS_SW_1P_TX_LP_V101 BIT(8)
> +#define DCS_SW_0P_TX_LP_V101 BIT(7)
> +#define GEN_SR_2P_TX_LP_V101 BIT(6)
> +#define GEN_SR_1P_TX_LP_V101 BIT(5)
> +#define GEN_SR_0P_TX_LP_V101 BIT(4)
> +#define GEN_SW_2P_TX_LP_V101 BIT(3)
> +#define GEN_SW_1P_TX_LP_V101 BIT(2)
> +#define GEN_SW_0P_TX_LP_V101 BIT(1)
> +
> +#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
> + GEN_LW_TX_LP_V101 | \
> + MAX_RD_PKT_SIZE_LP_V101 | \
> + DCS_SW_2P_TX_LP_V101 | \
> + DCS_SW_1P_TX_LP_V101 | \
> + DCS_SW_0P_TX_LP_V101 | \
> + GEN_SR_2P_TX_LP_V101 | \
> + GEN_SR_1P_TX_LP_V101 | \
> + GEN_SR_0P_TX_LP_V101 | \
> + GEN_SW_2P_TX_LP_V101 | \
> + GEN_SW_1P_TX_LP_V101 | \
> + GEN_SW_0P_TX_LP_V101)
> +
> #define DSI_GEN_HDR 0x6c
> #define DSI_GEN_PLD_DATA 0x70
>
> @@ -165,6 +212,11 @@
> #define DSI_INT_MSK0 0xc4
> #define DSI_INT_MSK1 0xc8
>
> +#define DSI_ERROR_ST0_V101 0x44
> +#define DSI_ERROR_ST1_V101 0x48
> +#define DSI_ERROR_MSK0_V101 0x4c
> +#define DSI_ERROR_MSK1_V101 0x50
> +
> #define DSI_PHY_TMR_RD_CFG 0xf4
>
> #define PHY_STATUS_TIMEOUT_US 10000
> @@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
> };
>
> +static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
> + .cfg_dpi_vid = REG_FIELD(DSI_DPI_CFG, 0, 1),
> + .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
> + .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10),
> + .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6),
> + .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG, 7, 7),
> + .cfg_cmd_mode_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 0, 0),
> + .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 1, 12),
> + .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
> + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
> + .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
> + .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
> + .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
> + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_CFG, 0, 10),
> + .cfg_vid_hsa_time = REG_FIELD(DSI_TMR_LINE_CFG, 0, 8),
> + .cfg_vid_hbp_time = REG_FIELD(DSI_TMR_LINE_CFG, 9, 17),
> + .cfg_vid_hline_time = REG_FIELD(DSI_TMR_LINE_CFG, 18, 31),
> + .cfg_vid_vsa_time = REG_FIELD(DSI_VTIMING_CFG, 0, 3),
> + .cfg_vid_vbp_time = REG_FIELD(DSI_VTIMING_CFG, 4, 9),
> + .cfg_vid_vfp_time = REG_FIELD(DSI_VTIMING_CFG, 10, 15),
> + .cfg_vid_vactive_time = REG_FIELD(DSI_VTIMING_CFG, 16, 26),
> + .cfg_phy_txrequestclkhs = REG_FIELD(DSI_PHY_IF_CTRL, 0, 0),
> + .cfg_phy_bta_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 0, 11),
> + .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 12, 19),
> + .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 20, 27),
> + .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0_V101, 0, 0),
> + .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ_V101, 0, 0),
> + .cfg_phy_unrstz = REG_FIELD(DSI_PHY_RSTZ_V101, 1, 1),
> + .cfg_phy_enableclk = REG_FIELD(DSI_PHY_RSTZ_V101, 2, 2),
> + .cfg_phy_nlanes = REG_FIELD(DSI_PHY_IF_CFG_V101, 0, 1),
> + .cfg_phy_stop_wait_time = REG_FIELD(DSI_PHY_IF_CFG_V101, 2, 9),
> + .cfg_phy_status = REG_FIELD(DSI_PHY_STATUS_V101, 0, 0),
> + .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG_V101, 0, 4),
> + .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 0, 15),
> + .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 16, 31),
> + .cfg_int_stat0 = REG_FIELD(DSI_ERROR_ST0_V101, 0, 20),
> + .cfg_int_stat1 = REG_FIELD(DSI_ERROR_ST1_V101, 0, 17),
> + .cfg_int_mask0 = REG_FIELD(DSI_ERROR_MSK0_V101, 0, 20),
> + .cfg_int_mask1 = REG_FIELD(DSI_ERROR_MSK1_V101, 0, 17),
> + .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR_V101, 0, 31),
> + .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA_V101, 0, 31),
> +};
> +
> /*
> * Check if either a link to a master or slave is present
> */
> @@ -466,6 +561,9 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> case HWVER_131:
> cmd_mode_lp = CMD_MODE_ALL_LP;
> break;
> + case HWVER_101:
> + cmd_mode_lp = CMD_MODE_ALL_LP_V101;
> + break;
> }
>
> if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
> @@ -644,7 +742,7 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
>
> #ifdef CONFIG_DEBUG_FS
> - if (dsi->vpg) {
> + if (dsi->hw_version > HWVER_101 && dsi->vpg) {
> regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_en, 1);
> regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_horiz,
> dsi->vpg_horizontal ? 1 : 0);
"regmap_field_write" passed 3 arguments, but takes just 2.
> @@ -662,9 +760,15 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>
> dw_mipi_dsi_video_mode_config(dsi);
>
> + if (dsi->hw_version == HWVER_101)
> + regmap_field_write(dsi->field_vid_mode_en, 1);
> +
> regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
> } else {
> regmap_field_write(dsi->field_cmd_mode_en, 1);
> +
> + if (dsi->hw_version == HWVER_101)
> + regmap_field_write(dsi->field_vid_mode_en, 0);
> }
>
> regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
> @@ -857,9 +961,13 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
> regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
>
> - regmap_field_write(dsi->field_phy_max_rd_time, 10000);
> - regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
> - regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
> + if (dsi->hw_version > HWVER_101) {
> + regmap_field_write(dsi->field_phy_max_rd_time, 10000);
> + regmap_field_write(dsi->field_phy_clkhs2lp_time,
> + timing.clk_hs2lp);
> + regmap_field_write(dsi->field_phy_clklp2hs_time,
> + timing.clk_lp2hs);
> + }
> }
>
> static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> @@ -880,7 +988,8 @@ static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
> regmap_field_write(dsi->field_phy_unrstz, 0);
> regmap_field_write(dsi->field_phy_unshutdownz, 0);
>
> - regmap_field_write(dsi->field_phy_forcepll, 0);
> + if (dsi->hw_version > HWVER_101)
> + regmap_field_write(dsi->field_phy_forcepll, 0);
>
> regmap_field_write(dsi->field_phy_testclr, 0);
> regmap_field_write(dsi->field_phy_testclr, 1);
> @@ -896,7 +1005,8 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
> regmap_field_write(dsi->field_phy_unrstz, 1);
> regmap_field_write(dsi->field_phy_unshutdownz, 1);
>
> - regmap_field_write(dsi->field_phy_forcepll, 1);
> + if (dsi->hw_version > HWVER_101)
> + regmap_field_write(dsi->field_phy_forcepll, 1);
>
> ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
> val, val & PHY_LOCK,
> @@ -1131,6 +1241,9 @@ static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
> case HWVER_131:
> variant = &dw_mipi_dsi_v130_v131_layout;
> break;
> + case HWVER_101:
> + variant = &dw_mipi_dsi_v101_layout;
> + break;
> default:
> DRM_ERROR("Unrecognized DSI host controller HW revision\n");
> return -ENODEV;
> --
> 2.26.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Regards,
Adrian
Forgot to mention mention DSI version 1.1, see ref manual for
STM32F769 for more details:
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwiRm4mhy8LoAhUP4BoKHaiLAJcQFjAAegQIBRAB&url=https%3A%2F%2Fwww.st.com%2Fresource%2Fen%2Freference_manual%2Fdm00224583-stm32f76xxx-and-stm32f77xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf&usg=AOvVaw14nl_UqwBs39ORzC0yaope
On Mon, Mar 30, 2020 at 6:58 PM adrian61 <[email protected]> wrote:
>
> Hello Adrian,
>
> I am testing hese changes on my STM32F769-DISCO and i found that:
>
> On Mon, Mar 30, 2020 at 2:35 PM Adrian Ratiu <[email protected]> wrote:
> >
> > In order to support multiple versions of the Synopsis MIPI DSI host
> > controller, which have different register layouts but almost identical
> > HW protocols, we add a regmap infrastructure which can abstract away
> > register accesses for platform drivers using the bridge.
> >
> > The controller HW revision is detected during bridge probe which will
> > be used in future commits to load the relevant register layout which
> > the bridge will use transparently to the platform drivers.
> >
> > Signed-off-by: Adrian Ratiu <[email protected]>
> > ---
> > New in v5.
> > ---
> > drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 ++++++++++--------
> > 1 file changed, 117 insertions(+), 91 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> > index 5ef0f154aa7b..6d9e2f21c9cc 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> > @@ -15,6 +15,7 @@
> > #include <linux/module.h>
> > #include <linux/of_device.h>
> > #include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > #include <linux/reset.h>
> >
> > #include <video/mipi_display.h>
> > @@ -227,6 +228,7 @@ struct dw_mipi_dsi {
> > struct drm_bridge *panel_bridge;
> > struct device *dev;
> > void __iomem *base;
> > + struct regmap *regs;
> >
> > struct clk *pclk;
> >
> > @@ -235,6 +237,7 @@ struct dw_mipi_dsi {
> > u32 lanes;
> > u32 format;
> > unsigned long mode_flags;
> > + u32 hw_version;
> >
> > #ifdef CONFIG_DEBUG_FS
> > struct dentry *debugfs;
> > @@ -249,6 +252,13 @@ struct dw_mipi_dsi {
> > const struct dw_mipi_dsi_plat_data *plat_data;
> > };
> >
> > +static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > + .name = "dw-mipi-dsi",
> > +};
> > +
> > /*
> > * Check if either a link to a master or slave is present
> > */
> > @@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
> > return container_of(bridge, struct dw_mipi_dsi, bridge);
> > }
> >
> > -static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
> > -{
> > - writel(val, dsi->base + reg);
> > -}
> > -
> > -static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
> > -{
> > - return readl(dsi->base + reg);
> > -}
> > -
> > static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
> > struct mipi_dsi_device *device)
> > {
> > @@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> > if (lpm)
> > val |= CMD_MODE_ALL_LP;
> >
> > - dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> > - dsi_write(dsi, DSI_CMD_MODE_CFG, val);
> > + regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> > + regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
> > }
> >
> > static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> > {
> > int ret;
> > - u32 val, mask;
> > + u32 val = 0, mask;
> >
> > - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > - val, !(val & GEN_CMD_FULL), 1000,
> > - CMD_PKT_STATUS_TIMEOUT_US);
> > + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> > + val, !(val & GEN_CMD_FULL), 1000,
> > + CMD_PKT_STATUS_TIMEOUT_US);
> > if (ret) {
> > dev_err(dsi->dev, "failed to get available command FIFO\n");
> > return ret;
> > }
> >
> > - dsi_write(dsi, DSI_GEN_HDR, hdr_val);
> > + regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
> >
> > mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> > - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > - val, (val & mask) == mask,
> > - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> > + val, (val & mask) == mask,
> > + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > if (ret) {
> > dev_err(dsi->dev, "failed to write command FIFO\n");
> > return ret;
> > @@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
> > const u8 *tx_buf = packet->payload;
> > int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
> > __le32 word;
> > - u32 val;
> > + u32 val = 0;
> >
> > while (len) {
> > if (len < pld_data_bytes) {
> > word = 0;
> > memcpy(&word, tx_buf, len);
> > - dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
> > + regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> > + le32_to_cpu(word));
> > len = 0;
> > } else {
> > memcpy(&word, tx_buf, pld_data_bytes);
> > - dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
> > + regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> > + le32_to_cpu(word));
> > tx_buf += pld_data_bytes;
> > len -= pld_data_bytes;
> > }
> >
> > - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > - val, !(val & GEN_PLD_W_FULL), 1000,
> > - CMD_PKT_STATUS_TIMEOUT_US);
> > + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> > + val, !(val & GEN_PLD_W_FULL),
> > + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > if (ret) {
> > dev_err(dsi->dev,
> > "failed to get available write payload FIFO\n");
> > @@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
> > {
> > int i, j, ret, len = msg->rx_len;
> > u8 *buf = msg->rx_buf;
> > - u32 val;
> > + u32 val = 0;
> >
> > /* Wait end of the read operation */
> > - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > - val, !(val & GEN_RD_CMD_BUSY),
> > - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> > + val, !(val & GEN_RD_CMD_BUSY),
> > + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > if (ret) {
> > dev_err(dsi->dev, "Timeout during read operation\n");
> > return ret;
> > @@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
> >
> > for (i = 0; i < len; i += 4) {
> > /* Read fifo must not be empty before all bytes are read */
> > - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> > - val, !(val & GEN_PLD_R_EMPTY),
> > - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> > + val, !(val & GEN_PLD_R_EMPTY),
> > + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> > if (ret) {
> > dev_err(dsi->dev, "Read payload FIFO is empty\n");
> > return ret;
> > }
> >
> > - val = dsi_read(dsi, DSI_GEN_PLD_DATA);
> > + regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
> > for (j = 0; j < 4 && j + i < len; j++)
> > buf[i + j] = val >> (8 * j);
> > }
> > @@ -536,29 +538,29 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> > }
> > #endif /* CONFIG_DEBUG_FS */
> >
> > - dsi_write(dsi, DSI_VID_MODE_CFG, val);
> > + regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
> > }
> >
> > static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> > unsigned long mode_flags)
> > {
> > - dsi_write(dsi, DSI_PWR_UP, RESET);
> > + regmap_write(dsi->regs, DSI_PWR_UP, RESET);
> >
> > if (mode_flags & MIPI_DSI_MODE_VIDEO) {
> > - dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> > + regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> > dw_mipi_dsi_video_mode_config(dsi);
> > - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> > + regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> > } else {
> > - dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> > + regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
> > }
> >
> > - dsi_write(dsi, DSI_PWR_UP, POWERUP);
> > + regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
> > }
> >
> > static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> > {
> > - dsi_write(dsi, DSI_PWR_UP, RESET);
> > - dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
> > + regmap_write(dsi->regs, DSI_PWR_UP, RESET);
> > + regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
> > }
> >
> > static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> > @@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> > */
> > u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
> >
> > - dsi_write(dsi, DSI_PWR_UP, RESET);
> > + regmap_write(dsi->regs, DSI_PWR_UP, RESET);
> >
> > /*
> > * TODO dw drv improvements
> > * timeout clock division should be computed with the
> > * high speed transmission counter timeout and byte lane...
> > */
> > - dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
> > + regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
> > TX_ESC_CLK_DIVISION(esc_clk_division));
> > }
> >
> > @@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> > if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> > val |= HSYNC_ACTIVE_LOW;
> >
> > - dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
> > - dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
> > - dsi_write(dsi, DSI_DPI_CFG_POL, val);
> > + regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
> > + regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
> > + regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
> > /*
> > * TODO dw drv improvements
> > * largest packet sizes during hfp or during vsa/vpb/vfp
> > * should be computed according to byte lane, lane number and only
> > * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
> > */
> > - dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> > + regmap_write(dsi->regs, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> > | INVACT_LPCMD_TIME(4));
> > }
> >
> > static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
> > {
> > - dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
> > + regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
> > }
> >
> > static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> > @@ -638,7 +640,7 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> > * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
> > */
> >
> > - dsi_write(dsi, DSI_VID_PKT_SIZE,
> > + regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
> > dw_mipi_is_dual_mode(dsi) ?
> > VID_PKT_SIZE(mode->hdisplay / 2) :
> > VID_PKT_SIZE(mode->hdisplay));
> > @@ -651,14 +653,15 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> > * compute high speed transmission counter timeout according
> > * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
> > */
> > - dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> > + regmap_write(dsi->regs, DSI_TO_CNT_CFG,
> > + HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> > /*
> > * TODO dw drv improvements
> > * the Bus-Turn-Around Timeout Counter should be computed
> > * according to byte lane...
> > */
> > - dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
> > - dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> > + regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
> > + regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
> > }
> >
> > /* Get lane byte clock cycles. */
> > @@ -692,13 +695,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
> > * computations below may be improved...
> > */
> > lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> > - dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
> > + regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
> >
> > lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> > - dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
> > + regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
> >
> > lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> > - dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
> > + regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
> > }
> >
> > static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> > @@ -711,10 +714,10 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> > vfp = mode->vsync_start - mode->vdisplay;
> > vbp = mode->vtotal - mode->vsync_end;
> >
> > - dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
> > - dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
> > - dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
> > - dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
> > + regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
> > + regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
> > + regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
> > + regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
> > }
> >
> > static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> > @@ -737,23 +740,25 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> > * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
> > */
> >
> > - hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
> > + regmap_read(dsi->regs, DSI_VERSION, &hw_version);
> > + hw_version &= VERSION;
> >
> > if (hw_version >= HWVER_131) {
> > - dsi_write(dsi, DSI_PHY_TMR_CFG,
> > - PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> > - PHY_LP2HS_TIME_V131(timing.data_lp2hs));
> > - dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
> > + regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> > + PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> > + PHY_LP2HS_TIME_V131(timing.data_lp2hs));
> > + regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
> > + MAX_RD_TIME_V131(10000));
> > } else {
> > - dsi_write(dsi, DSI_PHY_TMR_CFG,
> > - PHY_HS2LP_TIME(timing.data_hs2lp) |
> > - PHY_LP2HS_TIME(timing.data_lp2hs) |
> > - MAX_RD_TIME(10000));
> > + regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> > + PHY_HS2LP_TIME(timing.data_hs2lp) |
> > + PHY_LP2HS_TIME(timing.data_lp2hs) |
> > + MAX_RD_TIME(10000));
> > }
> >
> > - dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
> > - PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> > - PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
> > + regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
> > + PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> > + PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
> > }
> >
> > static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> > @@ -763,46 +768,49 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> > * stop wait time should be the maximum between host dsi
> > * and panel stop wait times
> > */
> > - dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
> > - N_LANES(dsi->lanes));
> > + regmap_write(dsi->regs, DSI_PHY_IF_CFG,
> > + PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
> > }
> >
> > static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
> > {
> > /* Clear PHY state */
> > - dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> > - | PHY_RSTZ | PHY_SHUTDOWNZ);
> > - dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> > - dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> > - dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> > + regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> > + | PHY_RSTZ | PHY_SHUTDOWNZ);
> > + regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> > + regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> > + regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> > }
> >
> > static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
> > {
> > - u32 val;
> > + u32 val = 0;
> > int ret;
> >
> > - dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> > - PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> > + regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> > + PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> >
> > - ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
> > - val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
> > + ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> > + val, val & PHY_LOCK,
> > + 1000, PHY_STATUS_TIMEOUT_US);
> > if (ret)
> > DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
> >
> > - ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> > - val, val & PHY_STOP_STATE_CLK_LANE, 1000,
> > - PHY_STATUS_TIMEOUT_US);
> > + ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> > + val, val & PHY_STOP_STATE_CLK_LANE, 1000,
> > + PHY_STATUS_TIMEOUT_US);
> > if (ret)
> > DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
> > }
> >
> > static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
> > {
> > - dsi_read(dsi, DSI_INT_ST0);
> > - dsi_read(dsi, DSI_INT_ST1);
> > - dsi_write(dsi, DSI_INT_MSK0, 0);
> > - dsi_write(dsi, DSI_INT_MSK1, 0);
> > + u32 val;
> > +
> > + regmap_read(dsi->regs, DSI_INT_ST0, &val);
> > + regmap_read(dsi->regs, DSI_INT_ST1, &val);
> > + regmap_write(dsi->regs, DSI_INT_MSK0, 0);
> > + regmap_write(dsi->regs, DSI_INT_MSK1, 0);
> > }
> >
> > static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
> > @@ -989,6 +997,14 @@ static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
> >
> > #endif /* CONFIG_DEBUG_FS */
> >
> > +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
> > +{
> > + regmap_read(dsi->regs, DSI_VERSION, &dsi->hw_version);
> > + dsi->hw_version &= VERSION;
> > + if (!dsi->hw_version)
> Here, this is 0 on my board.
> > + dev_err(dsi->dev, "Failed to read DSI hw version register\n");
> > +}
> > +
> > static struct dw_mipi_dsi *
> > __dw_mipi_dsi_probe(struct platform_device *pdev,
> > const struct dw_mipi_dsi_plat_data *plat_data)
> > @@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> > dsi->base = plat_data->base;
> > }
> >
> > + dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
> > + &dw_mipi_dsi_regmap_cfg);
> > + if (IS_ERR(dsi->regs)) {
> > + ret = PTR_ERR(dsi->regs);
> > + DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
> > + return ERR_PTR(ret);
> > + }
> > +
> > dsi->pclk = devm_clk_get(dev, "pclk");
> > if (IS_ERR(dsi->pclk)) {
> > ret = PTR_ERR(dsi->pclk);
> > @@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> > clk_disable_unprepare(dsi->pclk);
> > }
> >
> > + dw_mipi_dsi_get_hw_version(dsi);
> > +
> > dw_mipi_dsi_debugfs_init(dsi);
> > pm_runtime_enable(dev);
> >
> > --
> > 2.26.0
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> Best regards,
> Adrian
On Mon, 30 Mar 2020 14:35:42 +0300, Adrian Ratiu wrote:
> This provides an example DT binding for the MIPI DSI host controller
> present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.
>
> Cc: Rob Herring <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: [email protected]
> Signed-off-by: Sjoerd Simons <[email protected]>
> Signed-off-by: Martyn Welch <[email protected]>
> Signed-off-by: Adrian Ratiu <[email protected]>
> ---
> Changes since v4:
> - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
> and addressed received binding feedback (Rob)
>
> Changes since v3:
> - Added commit message (Neil)
> - Converted to yaml format (Neil)
> - Minor dt node + driver fixes (Rob)
> - Added small panel example to the host controller binding
>
> Changes since v2:
> - Fixed commit tags (Emil)
> ---
> .../display/imx/fsl,mipi-dsi-imx6.yaml | 134 ++++++++++++++++++
> 1 file changed, 134 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dts:34.21-31: Warning (reg_format): /example-0/dsi@21e0000/ports/port@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dt.yaml: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dt.yaml: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dt.yaml: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dts:33.24-38.19: Warning (avoid_default_addr_size): /example-0/dsi@21e0000/ports/port@1: Relying on default #address-cells value
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dts:33.24-38.19: Warning (avoid_default_addr_size): /example-0/dsi@21e0000/ports/port@1: Relying on default #size-cells value
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dts:33.24-38.19: Warning (graph_port): /example-0/dsi@21e0000/ports/port@1: graph node '#address-cells' is -1, must be 1
Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.example.dts:33.24-38.19: Warning (graph_port): /example-0/dsi@21e0000/ports/port@1: graph node '#size-cells' is -1, must be 0
See https://patchwork.ozlabs.org/patch/1263893
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
Hello Adrian,
I am testing hese changes on my STM32F769-DISCO and i found that:
On Mon, Mar 30, 2020 at 2:35 PM Adrian Ratiu <[email protected]> wrote:
>
> In order to support multiple versions of the Synopsis MIPI DSI host
> controller, which have different register layouts but almost identical
> HW protocols, we add a regmap infrastructure which can abstract away
> register accesses for platform drivers using the bridge.
>
> The controller HW revision is detected during bridge probe which will
> be used in future commits to load the relevant register layout which
> the bridge will use transparently to the platform drivers.
>
> Signed-off-by: Adrian Ratiu <[email protected]>
> ---
> New in v5.
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208 ++++++++++--------
> 1 file changed, 117 insertions(+), 91 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 5ef0f154aa7b..6d9e2f21c9cc 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -15,6 +15,7 @@
> #include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> #include <linux/reset.h>
>
> #include <video/mipi_display.h>
> @@ -227,6 +228,7 @@ struct dw_mipi_dsi {
> struct drm_bridge *panel_bridge;
> struct device *dev;
> void __iomem *base;
> + struct regmap *regs;
>
> struct clk *pclk;
>
> @@ -235,6 +237,7 @@ struct dw_mipi_dsi {
> u32 lanes;
> u32 format;
> unsigned long mode_flags;
> + u32 hw_version;
>
> #ifdef CONFIG_DEBUG_FS
> struct dentry *debugfs;
> @@ -249,6 +252,13 @@ struct dw_mipi_dsi {
> const struct dw_mipi_dsi_plat_data *plat_data;
> };
>
> +static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .name = "dw-mipi-dsi",
> +};
> +
> /*
> * Check if either a link to a master or slave is present
> */
> @@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
> return container_of(bridge, struct dw_mipi_dsi, bridge);
> }
>
> -static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
> -{
> - writel(val, dsi->base + reg);
> -}
> -
> -static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
> -{
> - return readl(dsi->base + reg);
> -}
> -
> static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
> struct mipi_dsi_device *device)
> {
> @@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> if (lpm)
> val |= CMD_MODE_ALL_LP;
>
> - dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> - dsi_write(dsi, DSI_CMD_MODE_CFG, val);
> + regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> + regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
> }
>
> static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> {
> int ret;
> - u32 val, mask;
> + u32 val = 0, mask;
>
> - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_CMD_FULL), 1000,
> - CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> + val, !(val & GEN_CMD_FULL), 1000,
> + CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev, "failed to get available command FIFO\n");
> return ret;
> }
>
> - dsi_write(dsi, DSI_GEN_HDR, hdr_val);
> + regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
>
> mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> - val, (val & mask) == mask,
> - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> + val, (val & mask) == mask,
> + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev, "failed to write command FIFO\n");
> return ret;
> @@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
> const u8 *tx_buf = packet->payload;
> int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
> __le32 word;
> - u32 val;
> + u32 val = 0;
>
> while (len) {
> if (len < pld_data_bytes) {
> word = 0;
> memcpy(&word, tx_buf, len);
> - dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
> + regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> + le32_to_cpu(word));
> len = 0;
> } else {
> memcpy(&word, tx_buf, pld_data_bytes);
> - dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
> + regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> + le32_to_cpu(word));
> tx_buf += pld_data_bytes;
> len -= pld_data_bytes;
> }
>
> - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_PLD_W_FULL), 1000,
> - CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> + val, !(val & GEN_PLD_W_FULL),
> + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev,
> "failed to get available write payload FIFO\n");
> @@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
> {
> int i, j, ret, len = msg->rx_len;
> u8 *buf = msg->rx_buf;
> - u32 val;
> + u32 val = 0;
>
> /* Wait end of the read operation */
> - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_RD_CMD_BUSY),
> - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> + val, !(val & GEN_RD_CMD_BUSY),
> + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev, "Timeout during read operation\n");
> return ret;
> @@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
>
> for (i = 0; i < len; i += 4) {
> /* Read fifo must not be empty before all bytes are read */
> - ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_PLD_R_EMPTY),
> - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> + val, !(val & GEN_PLD_R_EMPTY),
> + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev, "Read payload FIFO is empty\n");
> return ret;
> }
>
> - val = dsi_read(dsi, DSI_GEN_PLD_DATA);
> + regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
> for (j = 0; j < 4 && j + i < len; j++)
> buf[i + j] = val >> (8 * j);
> }
> @@ -536,29 +538,29 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> }
> #endif /* CONFIG_DEBUG_FS */
>
> - dsi_write(dsi, DSI_VID_MODE_CFG, val);
> + regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
> }
>
> static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> unsigned long mode_flags)
> {
> - dsi_write(dsi, DSI_PWR_UP, RESET);
> + regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>
> if (mode_flags & MIPI_DSI_MODE_VIDEO) {
> - dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> + regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> dw_mipi_dsi_video_mode_config(dsi);
> - dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> + regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> } else {
> - dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> + regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
> }
>
> - dsi_write(dsi, DSI_PWR_UP, POWERUP);
> + regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
> }
>
> static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> {
> - dsi_write(dsi, DSI_PWR_UP, RESET);
> - dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
> + regmap_write(dsi->regs, DSI_PWR_UP, RESET);
> + regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
> }
>
> static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> @@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> */
> u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
>
> - dsi_write(dsi, DSI_PWR_UP, RESET);
> + regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>
> /*
> * TODO dw drv improvements
> * timeout clock division should be computed with the
> * high speed transmission counter timeout and byte lane...
> */
> - dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
> + regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
> TX_ESC_CLK_DIVISION(esc_clk_division));
> }
>
> @@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> val |= HSYNC_ACTIVE_LOW;
>
> - dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
> - dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
> - dsi_write(dsi, DSI_DPI_CFG_POL, val);
> + regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
> + regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
> + regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
> /*
> * TODO dw drv improvements
> * largest packet sizes during hfp or during vsa/vpb/vfp
> * should be computed according to byte lane, lane number and only
> * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
> */
> - dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> + regmap_write(dsi->regs, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
> | INVACT_LPCMD_TIME(4));
> }
>
> static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
> {
> - dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
> + regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
> }
>
> static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> @@ -638,7 +640,7 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
> */
>
> - dsi_write(dsi, DSI_VID_PKT_SIZE,
> + regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
> dw_mipi_is_dual_mode(dsi) ?
> VID_PKT_SIZE(mode->hdisplay / 2) :
> VID_PKT_SIZE(mode->hdisplay));
> @@ -651,14 +653,15 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> * compute high speed transmission counter timeout according
> * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
> */
> - dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> + regmap_write(dsi->regs, DSI_TO_CNT_CFG,
> + HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> /*
> * TODO dw drv improvements
> * the Bus-Turn-Around Timeout Counter should be computed
> * according to byte lane...
> */
> - dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
> - dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
> + regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
> + regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
> }
>
> /* Get lane byte clock cycles. */
> @@ -692,13 +695,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
> * computations below may be improved...
> */
> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> - dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
> + regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
>
> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> - dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
> + regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
>
> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> - dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
> + regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
> }
>
> static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> @@ -711,10 +714,10 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> vfp = mode->vsync_start - mode->vdisplay;
> vbp = mode->vtotal - mode->vsync_end;
>
> - dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
> - dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
> - dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
> - dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
> + regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
> + regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
> + regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
> + regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
> }
>
> static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> @@ -737,23 +740,25 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
> */
>
> - hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
> + regmap_read(dsi->regs, DSI_VERSION, &hw_version);
> + hw_version &= VERSION;
>
> if (hw_version >= HWVER_131) {
> - dsi_write(dsi, DSI_PHY_TMR_CFG,
> - PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> - PHY_LP2HS_TIME_V131(timing.data_lp2hs));
> - dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
> + regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> + PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> + PHY_LP2HS_TIME_V131(timing.data_lp2hs));
> + regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
> + MAX_RD_TIME_V131(10000));
> } else {
> - dsi_write(dsi, DSI_PHY_TMR_CFG,
> - PHY_HS2LP_TIME(timing.data_hs2lp) |
> - PHY_LP2HS_TIME(timing.data_lp2hs) |
> - MAX_RD_TIME(10000));
> + regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> + PHY_HS2LP_TIME(timing.data_hs2lp) |
> + PHY_LP2HS_TIME(timing.data_lp2hs) |
> + MAX_RD_TIME(10000));
> }
>
> - dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
> - PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> - PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
> + regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
> + PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> + PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
> }
>
> static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> @@ -763,46 +768,49 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> * stop wait time should be the maximum between host dsi
> * and panel stop wait times
> */
> - dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
> - N_LANES(dsi->lanes));
> + regmap_write(dsi->regs, DSI_PHY_IF_CFG,
> + PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
> }
>
> static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
> {
> /* Clear PHY state */
> - dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> - | PHY_RSTZ | PHY_SHUTDOWNZ);
> - dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> - dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> - dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> + regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> + | PHY_RSTZ | PHY_SHUTDOWNZ);
> + regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> + regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> + regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> }
>
> static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
> {
> - u32 val;
> + u32 val = 0;
> int ret;
>
> - dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> - PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> + regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> + PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>
> - ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
> - val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
> + ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> + val, val & PHY_LOCK,
> + 1000, PHY_STATUS_TIMEOUT_US);
> if (ret)
> DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>
> - ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
> - val, val & PHY_STOP_STATE_CLK_LANE, 1000,
> - PHY_STATUS_TIMEOUT_US);
> + ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> + val, val & PHY_STOP_STATE_CLK_LANE, 1000,
> + PHY_STATUS_TIMEOUT_US);
> if (ret)
> DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
> }
>
> static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
> {
> - dsi_read(dsi, DSI_INT_ST0);
> - dsi_read(dsi, DSI_INT_ST1);
> - dsi_write(dsi, DSI_INT_MSK0, 0);
> - dsi_write(dsi, DSI_INT_MSK1, 0);
> + u32 val;
> +
> + regmap_read(dsi->regs, DSI_INT_ST0, &val);
> + regmap_read(dsi->regs, DSI_INT_ST1, &val);
> + regmap_write(dsi->regs, DSI_INT_MSK0, 0);
> + regmap_write(dsi->regs, DSI_INT_MSK1, 0);
> }
>
> static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
> @@ -989,6 +997,14 @@ static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
>
> #endif /* CONFIG_DEBUG_FS */
>
> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
> +{
> + regmap_read(dsi->regs, DSI_VERSION, &dsi->hw_version);
> + dsi->hw_version &= VERSION;
> + if (!dsi->hw_version)
Here, this is 0 on my board.
> + dev_err(dsi->dev, "Failed to read DSI hw version register\n");
> +}
> +
> static struct dw_mipi_dsi *
> __dw_mipi_dsi_probe(struct platform_device *pdev,
> const struct dw_mipi_dsi_plat_data *plat_data)
> @@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> dsi->base = plat_data->base;
> }
>
> + dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
> + &dw_mipi_dsi_regmap_cfg);
> + if (IS_ERR(dsi->regs)) {
> + ret = PTR_ERR(dsi->regs);
> + DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
> + return ERR_PTR(ret);
> + }
> +
> dsi->pclk = devm_clk_get(dev, "pclk");
> if (IS_ERR(dsi->pclk)) {
> ret = PTR_ERR(dsi->pclk);
> @@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> clk_disable_unprepare(dsi->pclk);
> }
>
> + dw_mipi_dsi_get_hw_version(dsi);
> +
> dw_mipi_dsi_debugfs_init(dsi);
> pm_runtime_enable(dev);
>
> --
> 2.26.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Best regards,
Adrian
On Mon, 30 Mar 2020, adrian61 <[email protected]> wrote:
> Hello Adrian,
>
> I am testing hese changes on my STM32F769-DISCO and i found
> that:
>
> On Mon, Mar 30, 2020 at 2:35 PM Adrian Ratiu
> <[email protected]> wrote:
>>
>> In order to support multiple versions of the Synopsis MIPI DSI
>> host controller, which have different register layouts but
>> almost identical HW protocols, we add a regmap infrastructure
>> which can abstract away register accesses for platform drivers
>> using the bridge.
>>
>> The controller HW revision is detected during bridge probe
>> which will be used in future commits to load the relevant
>> register layout which the bridge will use transparently to the
>> platform drivers.
>>
>> Signed-off-by: Adrian Ratiu <[email protected]> ---
>> New in v5. ---
>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 208
>> ++++++++++-------- 1 file changed, 117 insertions(+), 91
>> deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index
>> 5ef0f154aa7b..6d9e2f21c9cc 100644 ---
>> a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -15,6 +15,7
>> @@
>> #include <linux/module.h> #include <linux/of_device.h>
>> #include <linux/pm_runtime.h>
>> +#include <linux/regmap.h>
>> #include <linux/reset.h>
>>
>> #include <video/mipi_display.h>
>> @@ -227,6 +228,7 @@ struct dw_mipi_dsi {
>> struct drm_bridge *panel_bridge; struct device *dev;
>> void __iomem *base;
>> + struct regmap *regs;
>>
>> struct clk *pclk;
>>
>> @@ -235,6 +237,7 @@ struct dw_mipi_dsi {
>> u32 lanes; u32 format; unsigned long mode_flags;
>> + u32 hw_version;
>>
>> #ifdef CONFIG_DEBUG_FS
>> struct dentry *debugfs;
>> @@ -249,6 +252,13 @@ struct dw_mipi_dsi {
>> const struct dw_mipi_dsi_plat_data *plat_data;
>> };
>>
>> +static const struct regmap_config dw_mipi_dsi_regmap_cfg = { +
>> .reg_bits = 32, + .val_bits = 32, + .reg_stride =
>> 4, + .name = "dw-mipi-dsi", +}; +
>> /*
>> * Check if either a link to a master or slave is present */
>> @@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi
>> *bridge_to_dsi(struct drm_bridge *bridge)
>> return container_of(bridge, struct dw_mipi_dsi,
>> bridge);
>> }
>>
>> -static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg,
>> u32 val) -{ - writel(val, dsi->base + reg); -} - -static
>> inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) -{ -
>> return readl(dsi->base + reg); -} -
>> static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>> struct mipi_dsi_device
>> *device)
>> {
>> @@ -366,29 +366,29 @@ static void dw_mipi_message_config(struct
>> dw_mipi_dsi *dsi,
>> if (lpm)
>> val |= CMD_MODE_ALL_LP;
>>
>> - dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 :
>> PHY_TXREQUESTCLKHS); - dsi_write(dsi, DSI_CMD_MODE_CFG,
>> val); + regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 :
>> PHY_TXREQUESTCLKHS); + regmap_write(dsi->regs,
>> DSI_CMD_MODE_CFG, val);
>> }
>>
>> static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi
>> *dsi, u32 hdr_val) {
>> int ret;
>> - u32 val, mask; + u32 val = 0, mask;
>>
>> - ret = readl_poll_timeout(dsi->base +
>> DSI_CMD_PKT_STATUS, - val, !(val
>> & GEN_CMD_FULL), 1000, -
>> CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, +
>> val, !(val & GEN_CMD_FULL), 1000, +
>> CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) {
>> dev_err(dsi->dev, "failed to get available
>> command FIFO\n"); return ret;
>> }
>>
>> - dsi_write(dsi, DSI_GEN_HDR, hdr_val); +
>> regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
>>
>> mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
>> - ret = readl_poll_timeout(dsi->base +
>> DSI_CMD_PKT_STATUS, - val, (val
>> & mask) == mask, - 1000,
>> CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, +
>> val, (val & mask) == mask, +
>> 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) {
>> dev_err(dsi->dev, "failed to write command
>> FIFO\n"); return ret;
>> @@ -403,24 +403,26 @@ static int dw_mipi_dsi_write(struct
>> dw_mipi_dsi *dsi,
>> const u8 *tx_buf = packet->payload; int len =
>> packet->payload_length, pld_data_bytes = sizeof(u32),
>> ret; __le32 word;
>> - u32 val; + u32 val = 0;
>>
>> while (len) {
>> if (len < pld_data_bytes) {
>> word = 0; memcpy(&word, tx_buf, len);
>> - dsi_write(dsi, DSI_GEN_PLD_DATA,
>> le32_to_cpu(word)); +
>> regmap_write(dsi->regs, DSI_GEN_PLD_DATA, +
>> le32_to_cpu(word));
>> len = 0;
>> } else {
>> memcpy(&word, tx_buf, pld_data_bytes);
>> - dsi_write(dsi, DSI_GEN_PLD_DATA,
>> le32_to_cpu(word)); +
>> regmap_write(dsi->regs, DSI_GEN_PLD_DATA, +
>> le32_to_cpu(word));
>> tx_buf += pld_data_bytes; len -=
>> pld_data_bytes;
>> }
>>
>> - ret = readl_poll_timeout(dsi->base +
>> DSI_CMD_PKT_STATUS, -
>> val, !(val & GEN_PLD_W_FULL), 1000, -
>> CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, +
>> val, !(val & GEN_PLD_W_FULL), +
>> 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) {
>> dev_err(dsi->dev,
>> "failed to get available write
>> payload FIFO\n");
>> @@ -438,12 +440,12 @@ static int dw_mipi_dsi_read(struct
>> dw_mipi_dsi *dsi,
>> {
>> int i, j, ret, len = msg->rx_len; u8 *buf =
>> msg->rx_buf;
>> - u32 val; + u32 val = 0;
>>
>> /* Wait end of the read operation */
>> - ret = readl_poll_timeout(dsi->base +
>> DSI_CMD_PKT_STATUS, - val, !(val
>> & GEN_RD_CMD_BUSY), - 1000,
>> CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, +
>> val, !(val & GEN_RD_CMD_BUSY), +
>> 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) {
>> dev_err(dsi->dev, "Timeout during read
>> operation\n"); return ret;
>> @@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct
>> dw_mipi_dsi *dsi,
>>
>> for (i = 0; i < len; i += 4) {
>> /* Read fifo must not be empty before all bytes
>> are read */
>> - ret = readl_poll_timeout(dsi->base +
>> DSI_CMD_PKT_STATUS, -
>> val, !(val & GEN_PLD_R_EMPTY), -
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS, +
>> val, !(val & GEN_PLD_R_EMPTY), +
>> 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) {
>> dev_err(dsi->dev, "Read payload FIFO is
>> empty\n"); return ret;
>> }
>>
>> - val = dsi_read(dsi, DSI_GEN_PLD_DATA); +
>> regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
>> for (j = 0; j < 4 && j + i < len; j++)
>> buf[i + j] = val >> (8 * j);
>> }
>> @@ -536,29 +538,29 @@ static void
>> dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
>> }
>> #endif /* CONFIG_DEBUG_FS */
>>
>> - dsi_write(dsi, DSI_VID_MODE_CFG, val); +
>> regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
>> }
>>
>> static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>> unsigned long mode_flags)
>> {
>> - dsi_write(dsi, DSI_PWR_UP, RESET); +
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>>
>> if (mode_flags & MIPI_DSI_MODE_VIDEO) {
>> - dsi_write(dsi, DSI_MODE_CFG,
>> ENABLE_VIDEO_MODE); + regmap_write(dsi->regs,
>> DSI_MODE_CFG, ENABLE_VIDEO_MODE);
>> dw_mipi_dsi_video_mode_config(dsi);
>> - dsi_write(dsi, DSI_LPCLK_CTRL,
>> PHY_TXREQUESTCLKHS); + regmap_write(dsi->regs,
>> DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
>> } else {
>> - dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>> + regmap_write(dsi->regs, DSI_MODE_CFG,
>> ENABLE_CMD_MODE);
>> }
>>
>> - dsi_write(dsi, DSI_PWR_UP, POWERUP); +
>> regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
>> }
>>
>> static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) {
>> - dsi_write(dsi, DSI_PWR_UP, RESET); -
>> dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); +
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); +
>> regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
>> }
>>
>> static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>> @@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct
>> dw_mipi_dsi *dsi)
>> */
>> u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
>>
>> - dsi_write(dsi, DSI_PWR_UP, RESET); +
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>>
>> /*
>> * TODO dw drv improvements * timeout clock division
>> should be computed with the * high speed transmission
>> counter timeout and byte lane... */
>> - dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | +
>> regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
>> TX_ESC_CLK_DIVISION(esc_clk_division));
>> }
>>
>> @@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct
>> dw_mipi_dsi *dsi,
>> if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>> val |= HSYNC_ACTIVE_LOW;
>>
>> - dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); -
>> dsi_write(dsi, DSI_DPI_COLOR_CODING, color); -
>> dsi_write(dsi, DSI_DPI_CFG_POL, val); +
>> regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
>> + regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color); +
>> regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
>> /*
>> * TODO dw drv improvements * largest packet sizes
>> during hfp or during vsa/vpb/vfp * should be computed
>> according to byte lane, lane number and only * if
>> sending lp cmds in high speed is enable
>> (PHY_TXREQUESTCLKHS) */
>> - dsi_write(dsi, DSI_DPI_LP_CMD_TIM,
>> OUTVACT_LPCMD_TIME(4) + regmap_write(dsi->regs,
>> DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
>> | INVACT_LPCMD_TIME(4));
>> }
>>
>> static void dw_mipi_dsi_packet_handler_config(struct
>> dw_mipi_dsi *dsi) {
>> - dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN |
>> BTA_EN); + regmap_write(dsi->regs, DSI_PCKHDL_CFG,
>> CRC_RX_EN | ECC_RX_EN | BTA_EN);
>> }
>>
>> static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi
>> *dsi,
>> @@ -638,7 +640,7 @@ static void
>> dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
>> * non-burst video modes, see
>> dw_mipi_dsi_video_mode_config()... */
>>
>> - dsi_write(dsi, DSI_VID_PKT_SIZE, +
>> regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
>> dw_mipi_is_dual_mode(dsi) ?
>> VID_PKT_SIZE(mode->hdisplay /
>> 2) :
>> VID_PKT_SIZE(mode->hdisplay));
>> @@ -651,14 +653,15 @@ static void
>> dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>> * compute high speed transmission counter timeout
>> according * to the timeout clock division
>> (TO_CLK_DIVISION) and byte lane... */
>> - dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) |
>> LPRX_TO_CNT(1000)); + regmap_write(dsi->regs,
>> DSI_TO_CNT_CFG, + HSTX_TO_CNT(1000) |
>> LPRX_TO_CNT(1000));
>> /*
>> * TODO dw drv improvements * the Bus-Turn-Around
>> Timeout Counter should be computed * according to byte
>> lane... */
>> - dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); -
>> dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); +
>> regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00); +
>> regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
>> }
>>
>> /* Get lane byte clock cycles. */
>> @@ -692,13 +695,13 @@ static void
>> dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
>> * computations below may be improved... */
>> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode,
>> htotal);
>> - dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); +
>> regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
>>
>> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
>> - dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); +
>> regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
>>
>> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
>> - dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); +
>> regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
>> }
>>
>> static void dw_mipi_dsi_vertical_timing_config(struct
>> dw_mipi_dsi *dsi,
>> @@ -711,10 +714,10 @@ static void
>> dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>> vfp = mode->vsync_start - mode->vdisplay; vbp =
>> mode->vtotal - mode->vsync_end;
>>
>> - dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); -
>> dsi_write(dsi, DSI_VID_VSA_LINES, vsa); - dsi_write(dsi,
>> DSI_VID_VFP_LINES, vfp); - dsi_write(dsi,
>> DSI_VID_VBP_LINES, vbp); + regmap_write(dsi->regs,
>> DSI_VID_VACTIVE_LINES, vactive); +
>> regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa); +
>> regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp); +
>> regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
>> }
>>
>> static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi
>> *dsi)
>> @@ -737,23 +740,25 @@ static void
>> dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>> * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see
>> CMD_MODE_ALL_LP) */
>>
>> - hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; +
>> regmap_read(dsi->regs, DSI_VERSION, &hw_version); +
>> hw_version &= VERSION;
>>
>> if (hw_version >= HWVER_131) {
>> - dsi_write(dsi, DSI_PHY_TMR_CFG, -
>> PHY_HS2LP_TIME_V131(timing.data_hs2lp) | -
>> PHY_LP2HS_TIME_V131(timing.data_lp2hs)); -
>> dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); +
>> regmap_write(dsi->regs, DSI_PHY_TMR_CFG, +
>> PHY_HS2LP_TIME_V131(timing.data_hs2lp) | +
>> PHY_LP2HS_TIME_V131(timing.data_lp2hs)); +
>> regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG, +
>> MAX_RD_TIME_V131(10000));
>> } else {
>> - dsi_write(dsi, DSI_PHY_TMR_CFG, -
>> PHY_HS2LP_TIME(timing.data_hs2lp) | -
>> PHY_LP2HS_TIME(timing.data_lp2hs) | -
>> MAX_RD_TIME(10000)); + regmap_write(dsi->regs,
>> DSI_PHY_TMR_CFG, +
>> PHY_HS2LP_TIME(timing.data_hs2lp) | +
>> PHY_LP2HS_TIME(timing.data_lp2hs) | +
>> MAX_RD_TIME(10000));
>> }
>>
>> - dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, -
>> PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | -
>> PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); +
>> regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG, +
>> PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | +
>> PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
>> }
>>
>> static void dw_mipi_dsi_dphy_interface_config(struct
>> dw_mipi_dsi *dsi)
>> @@ -763,46 +768,49 @@ static void
>> dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>> * stop wait time should be the maximum between host
>> dsi * and panel stop wait times */
>> - dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20)
>> | - N_LANES(dsi->lanes)); +
>> regmap_write(dsi->regs, DSI_PHY_IF_CFG, +
>> PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
>> }
>>
>> static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) {
>> /* Clear PHY state */
>> - dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL |
>> PHY_DISABLECLK - | PHY_RSTZ | PHY_SHUTDOWNZ); -
>> dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); -
>> dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); -
>> dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); +
>> regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL |
>> PHY_DISABLECLK + | PHY_RSTZ |
>> PHY_SHUTDOWNZ); + regmap_write(dsi->regs,
>> DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); +
>> regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR); +
>> regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> }
>>
>> static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) {
>> - u32 val; + u32 val = 0;
>> int ret;
>>
>> - dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL |
>> PHY_ENABLECLK | - PHY_UNRSTZ |
>> PHY_UNSHUTDOWNZ); + regmap_write(dsi->regs, DSI_PHY_RSTZ,
>> PHY_ENFORCEPLL | PHY_ENABLECLK | +
>> PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
>>
>> - ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
>> val, - val & PHY_LOCK, 1000,
>> PHY_STATUS_TIMEOUT_US); + ret =
>> regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS, +
>> val, val & PHY_LOCK, +
>> 1000, PHY_STATUS_TIMEOUT_US);
>> if (ret)
>> DRM_DEBUG_DRIVER("failed to wait phy lock
>> state\n");
>>
>> - ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, -
>> val, val & PHY_STOP_STATE_CLK_LANE, 1000, -
>> PHY_STATUS_TIMEOUT_US); + ret =
>> regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS, +
>> val, val & PHY_STOP_STATE_CLK_LANE, 1000, +
>> PHY_STATUS_TIMEOUT_US);
>> if (ret)
>> DRM_DEBUG_DRIVER("failed to wait phy clk lane
>> stop state\n");
>> }
>>
>> static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) {
>> - dsi_read(dsi, DSI_INT_ST0); - dsi_read(dsi,
>> DSI_INT_ST1); - dsi_write(dsi, DSI_INT_MSK0, 0); -
>> dsi_write(dsi, DSI_INT_MSK1, 0); + u32 val; + +
>> regmap_read(dsi->regs, DSI_INT_ST0, &val); +
>> regmap_read(dsi->regs, DSI_INT_ST1, &val); +
>> regmap_write(dsi->regs, DSI_INT_MSK0, 0); +
>> regmap_write(dsi->regs, DSI_INT_MSK1, 0);
>> }
>>
>> static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge
>> *bridge)
>> @@ -989,6 +997,14 @@ static void
>> dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
>>
>> #endif /* CONFIG_DEBUG_FS */
>>
>> +static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi
>> *dsi) +{ + regmap_read(dsi->regs, DSI_VERSION,
>> &dsi->hw_version); + dsi->hw_version &= VERSION; +
>> if (!dsi->hw_version)
> Here, this is 0 on my board.
So we did a live debugging session on the STM board and managed to
root cause this. The regmap series uncovered a bug introduced by
the upstream commit fa6251a747b7 ("drm/stm: dsi: check hardware
version") which disables the peripheral clock immediately after
reading the version, but it appears that clock is still required
for the other reads to succeed, otherwise 0 values are read and
register writes have no effect (display
remains black).
This obviously only happens on the stm driver, will post a fix in
v6.
Thanks Adrian, much appreciated!
>> + dev_err(dsi->dev, "Failed to read DSI hw version register\n");
>> +}
>> +
>> static struct dw_mipi_dsi *
>> __dw_mipi_dsi_probe(struct platform_device *pdev,
>> const struct dw_mipi_dsi_plat_data *plat_data)
>> @@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>> dsi->base = plat_data->base;
>> }
>>
>> + dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
>> + &dw_mipi_dsi_regmap_cfg);
>> + if (IS_ERR(dsi->regs)) {
>> + ret = PTR_ERR(dsi->regs);
>> + DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
>> + return ERR_PTR(ret);
>> + }
>> +
>> dsi->pclk = devm_clk_get(dev, "pclk");
>> if (IS_ERR(dsi->pclk)) {
>> ret = PTR_ERR(dsi->pclk);
>> @@ -1055,6 +1079,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>> clk_disable_unprepare(dsi->pclk);
>> }
>>
>> + dw_mipi_dsi_get_hw_version(dsi);
>> +
>> dw_mipi_dsi_debugfs_init(dsi);
>> pm_runtime_enable(dev);
>>
>> --
>> 2.26.0
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> Best regards,
> Adrian
>
> _______________________________________________
> Linux-rockchip mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
On Mon, 30 Mar 2020, adrian61 <[email protected]> wrote:
> Hello Adrian,
>
> Here i get a compile error:
I neglected to test with CONFIG_DEBUG_FS, oops!
Will fix in v6, thanks!
>
> On Mon, Mar 30, 2020 at 2:36 PM Adrian Ratiu <[email protected]> wrote:
>>
>> The Synopsis MIPI DSI v1.01 host controller is quite widely used
>> on platforms like i.mx6 and is not very different from the other
>> versions like the 1.31/1.30 used on rockchip/stm. The protocols
>> appear to be the same, only the register layout is different and
>> the newer versions have new features symbolized by new registers
>> so adding support for it is just a matter of defining the new
>> layout and adding a couple of dsi version checks.
>>
>> Signed-off-by: Adrian Ratiu <[email protected]>
>> ---
>> New in v5.
>> ---
>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +++++++++++++++++-
>> 1 file changed, 119 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> index 5b78ff925af0..fb9dbc4fd0f5 100644
>> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> @@ -32,6 +32,7 @@
>>
>> #define HWVER_131 0x31333100 /* IP version 1.31 */
>> #define HWVER_130 0x31333000 /* IP version 1.30 */
>> +#define HWVER_101 0x31303000 /* IP version 1.01 */
>>
>> #define DSI_VERSION 0x00
>> #define VERSION GENMASK(31, 8)
>> @@ -100,6 +101,25 @@
>> #define DSI_EDPI_CMD_SIZE 0x64
>>
>> #define DSI_CMD_MODE_CFG 0x68
>> +
>> +#define DSI_DPI_CFG 0x0c
>> +#define DSI_TMR_LINE_CFG 0x28
>> +#define DSI_VTIMING_CFG 0x2c
>> +#define DSI_PHY_TMR_CFG_V101 0x30
>> +#define DSI_PHY_IF_CFG_V101 0x58
>> +#define DSI_PHY_IF_CTRL 0x5c
>> +#define DSI_PHY_RSTZ_V101 0x54
>> +#define DSI_PHY_STATUS_V101 0x60
>> +#define DSI_PHY_TST_CTRL0_V101 0x64
>> +#define DSI_GEN_HDR_V101 0x34
>> +#define DSI_GEN_PLD_DATA_V101 0x38
>> +#define DSI_CMD_MODE_CFG_V101 0x24
>> +#define DSI_CMD_PKT_STATUS_V101 0x3c
>> +#define DSI_VID_PKT_CFG 0x20
>> +#define DSI_VID_MODE_CFG_V101 0x1c
>> +#define DSI_TO_CNT_CFG_V101 0x40
>> +#define DSI_PCKHDL_CFG_V101 0x18
>> +
>> #define MAX_RD_PKT_SIZE_LP BIT(24)
>> #define DCS_LW_TX_LP BIT(19)
>> #define DCS_SR_0P_TX_LP BIT(18)
>> @@ -127,6 +147,33 @@
>> GEN_SW_1P_TX_LP | \
>> GEN_SW_0P_TX_LP)
>>
>> +#define EN_TEAR_FX_V101 BIT(14)
>> +#define DCS_LW_TX_LP_V101 BIT(12)
>> +#define GEN_LW_TX_LP_V101 BIT(11)
>> +#define MAX_RD_PKT_SIZE_LP_V101 BIT(10)
>> +#define DCS_SW_2P_TX_LP_V101 BIT(9)
>> +#define DCS_SW_1P_TX_LP_V101 BIT(8)
>> +#define DCS_SW_0P_TX_LP_V101 BIT(7)
>> +#define GEN_SR_2P_TX_LP_V101 BIT(6)
>> +#define GEN_SR_1P_TX_LP_V101 BIT(5)
>> +#define GEN_SR_0P_TX_LP_V101 BIT(4)
>> +#define GEN_SW_2P_TX_LP_V101 BIT(3)
>> +#define GEN_SW_1P_TX_LP_V101 BIT(2)
>> +#define GEN_SW_0P_TX_LP_V101 BIT(1)
>> +
>> +#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
>> + GEN_LW_TX_LP_V101 | \
>> + MAX_RD_PKT_SIZE_LP_V101 | \
>> + DCS_SW_2P_TX_LP_V101 | \
>> + DCS_SW_1P_TX_LP_V101 | \
>> + DCS_SW_0P_TX_LP_V101 | \
>> + GEN_SR_2P_TX_LP_V101 | \
>> + GEN_SR_1P_TX_LP_V101 | \
>> + GEN_SR_0P_TX_LP_V101 | \
>> + GEN_SW_2P_TX_LP_V101 | \
>> + GEN_SW_1P_TX_LP_V101 | \
>> + GEN_SW_0P_TX_LP_V101)
>> +
>> #define DSI_GEN_HDR 0x6c
>> #define DSI_GEN_PLD_DATA 0x70
>>
>> @@ -165,6 +212,11 @@
>> #define DSI_INT_MSK0 0xc4
>> #define DSI_INT_MSK1 0xc8
>>
>> +#define DSI_ERROR_ST0_V101 0x44
>> +#define DSI_ERROR_ST1_V101 0x48
>> +#define DSI_ERROR_MSK0_V101 0x4c
>> +#define DSI_ERROR_MSK1_V101 0x50
>> +
>> #define DSI_PHY_TMR_RD_CFG 0xf4
>>
>> #define PHY_STATUS_TIMEOUT_US 10000
>> @@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
>> .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
>> };
>>
>> +static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
>> + .cfg_dpi_vid = REG_FIELD(DSI_DPI_CFG, 0, 1),
>> + .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_CFG, 2, 4),
>> + .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_CFG, 10, 10),
>> + .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG, 6, 6),
>> + .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG, 7, 7),
>> + .cfg_cmd_mode_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 0, 0),
>> + .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 1, 12),
>> + .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
>> + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
>> + .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
>> + .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
>> + .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
>> + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_CFG, 0, 10),
>> + .cfg_vid_hsa_time = REG_FIELD(DSI_TMR_LINE_CFG, 0, 8),
>> + .cfg_vid_hbp_time = REG_FIELD(DSI_TMR_LINE_CFG, 9, 17),
>> + .cfg_vid_hline_time = REG_FIELD(DSI_TMR_LINE_CFG, 18, 31),
>> + .cfg_vid_vsa_time = REG_FIELD(DSI_VTIMING_CFG, 0, 3),
>> + .cfg_vid_vbp_time = REG_FIELD(DSI_VTIMING_CFG, 4, 9),
>> + .cfg_vid_vfp_time = REG_FIELD(DSI_VTIMING_CFG, 10, 15),
>> + .cfg_vid_vactive_time = REG_FIELD(DSI_VTIMING_CFG, 16, 26),
>> + .cfg_phy_txrequestclkhs = REG_FIELD(DSI_PHY_IF_CTRL, 0, 0),
>> + .cfg_phy_bta_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 0, 11),
>> + .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 12, 19),
>> + .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG_V101, 20, 27),
>> + .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0_V101, 0, 0),
>> + .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ_V101, 0, 0),
>> + .cfg_phy_unrstz = REG_FIELD(DSI_PHY_RSTZ_V101, 1, 1),
>> + .cfg_phy_enableclk = REG_FIELD(DSI_PHY_RSTZ_V101, 2, 2),
>> + .cfg_phy_nlanes = REG_FIELD(DSI_PHY_IF_CFG_V101, 0, 1),
>> + .cfg_phy_stop_wait_time = REG_FIELD(DSI_PHY_IF_CFG_V101, 2, 9),
>> + .cfg_phy_status = REG_FIELD(DSI_PHY_STATUS_V101, 0, 0),
>> + .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG_V101, 0, 4),
>> + .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 0, 15),
>> + .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG_V101, 16, 31),
>> + .cfg_int_stat0 = REG_FIELD(DSI_ERROR_ST0_V101, 0, 20),
>> + .cfg_int_stat1 = REG_FIELD(DSI_ERROR_ST1_V101, 0, 17),
>> + .cfg_int_mask0 = REG_FIELD(DSI_ERROR_MSK0_V101, 0, 20),
>> + .cfg_int_mask1 = REG_FIELD(DSI_ERROR_MSK1_V101, 0, 17),
>> + .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR_V101, 0, 31),
>> + .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA_V101, 0, 31),
>> +};
>> +
>> /*
>> * Check if either a link to a master or slave is present
>> */
>> @@ -466,6 +561,9 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
>> case HWVER_131:
>> cmd_mode_lp = CMD_MODE_ALL_LP;
>> break;
>> + case HWVER_101:
>> + cmd_mode_lp = CMD_MODE_ALL_LP_V101;
>> + break;
>> }
>>
>> if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
>> @@ -644,7 +742,7 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
>> VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
>>
>> #ifdef CONFIG_DEBUG_FS
>> - if (dsi->vpg) {
>> + if (dsi->hw_version > HWVER_101 && dsi->vpg) {
>> regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_en, 1);
>> regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_horiz,
>> dsi->vpg_horizontal ? 1 : 0);
>
> "regmap_field_write" passed 3 arguments, but takes just 2.
>
>
>> @@ -662,9 +760,15 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>>
>> dw_mipi_dsi_video_mode_config(dsi);
>>
>> + if (dsi->hw_version == HWVER_101)
>> + regmap_field_write(dsi->field_vid_mode_en, 1);
>> +
>> regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
>> } else {
>> regmap_field_write(dsi->field_cmd_mode_en, 1);
>> +
>> + if (dsi->hw_version == HWVER_101)
>> + regmap_field_write(dsi->field_vid_mode_en, 0);
>> }
>>
>> regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
>> @@ -857,9 +961,13 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>> regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
>> regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
>>
>> - regmap_field_write(dsi->field_phy_max_rd_time, 10000);
>> - regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
>> - regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
>> + if (dsi->hw_version > HWVER_101) {
>> + regmap_field_write(dsi->field_phy_max_rd_time, 10000);
>> + regmap_field_write(dsi->field_phy_clkhs2lp_time,
>> + timing.clk_hs2lp);
>> + regmap_field_write(dsi->field_phy_clklp2hs_time,
>> + timing.clk_lp2hs);
>> + }
>> }
>>
>> static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>> @@ -880,7 +988,8 @@ static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>> regmap_field_write(dsi->field_phy_unrstz, 0);
>> regmap_field_write(dsi->field_phy_unshutdownz, 0);
>>
>> - regmap_field_write(dsi->field_phy_forcepll, 0);
>> + if (dsi->hw_version > HWVER_101)
>> + regmap_field_write(dsi->field_phy_forcepll, 0);
>>
>> regmap_field_write(dsi->field_phy_testclr, 0);
>> regmap_field_write(dsi->field_phy_testclr, 1);
>> @@ -896,7 +1005,8 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>> regmap_field_write(dsi->field_phy_unrstz, 1);
>> regmap_field_write(dsi->field_phy_unshutdownz, 1);
>>
>> - regmap_field_write(dsi->field_phy_forcepll, 1);
>> + if (dsi->hw_version > HWVER_101)
>> + regmap_field_write(dsi->field_phy_forcepll, 1);
>>
>> ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
>> val, val & PHY_LOCK,
>> @@ -1131,6 +1241,9 @@ static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
>> case HWVER_131:
>> variant = &dw_mipi_dsi_v130_v131_layout;
>> break;
>> + case HWVER_101:
>> + variant = &dw_mipi_dsi_v101_layout;
>> + break;
>> default:
>> DRM_ERROR("Unrecognized DSI host controller HW revision\n");
>> return -ENODEV;
>> --
>> 2.26.0
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> Regards,
> Adrian
On Mon, 30 Mar 2020, Fabio Estevam <[email protected]> wrote:
> Hi Adrian,
>
> On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu
> <[email protected]> wrote:
>>
>> This adds support for the Synopsis DesignWare MIPI DSI v1.01
>> host controller which is embedded in i.MX 6 SoCs.
>>
>> Based on following patches, but updated/extended to work with
>> existing support found in the kernel:
>>
>> - drm: imx: Support Synopsys DesignWare MIPI DSI host
>> controller
>> Signed-off-by: Liu Ying <[email protected]>
>>
>> - ARM: dtsi: imx6qdl: Add support for MIPI DSI host controller
>> Signed-off-by: Liu Ying <[email protected]>
>
> This one looks like a devicetree patch, but this patch does not
> touch devicetree.
>
>> + ret = clk_prepare_enable(dsi->pllref_clk); + if
>> (ret) { + dev_err(dev, "%s: Failed to enable
>> pllref_clk\n", __func__); + return ret; + }
>> + + dsi->mux_sel =
>> syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); +
>> if (IS_ERR(dsi->mux_sel)) { + ret =
>> PTR_ERR(dsi->mux_sel); + dev_err(dev, "%s: Failed
>> to get GPR regmap: %d\n", + __func__,
>> ret); + return ret;
>
> You should disable the dsi->pllref_clk clock prior to returning
> the error.
>
>> + dsi->mipi_dsi = dw_mipi_dsi_probe(pdev, pdata); +
>> if (IS_ERR(dsi->mipi_dsi)) { + ret =
>> PTR_ERR(dsi->mipi_dsi); + dev_dbg(dev, "%s:
>> Unable to probe DW DSI host device: %d\n", +
>> __func__, ret); + return -ENODEV;
>
> Same here. You should disable the clock. Shouldn't you return
> 'ret' here instead of -ENODEV?
>
>> +module_platform_driver(imx_mipi_dsi_driver); +
>> +MODULE_DESCRIPTION("i.MX6 MIPI DSI host controller driver");
>> +MODULE_AUTHOR("Liu Ying <[email protected]>");
>
> The freescale.com domain is no longer functional.
>
> Ying Liu's NXP address is [email protected]. You could probably
> add your entry as well.
Hi Fabio,
All the issues you pointed out are valid and will be addressed in
v6 (including the device tree ones).
Thank you, much appreciated,
Adrian
On Mon, 30 Mar 2020, Ezequiel Garcia <[email protected]>
wrote:
> Hello Fabio, Adrian:
>
> On Mon, 2020-03-30 at 08:49 -0300, Fabio Estevam wrote:
>> Hi Adrian, On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu
>> <[email protected]> wrote:
>> > This adds support for the Synopsis DesignWare MIPI DSI v1.01
>> > host controller which is embedded in i.MX 6 SoCs. Based on
>> > following patches, but updated/extended to work with existing
>> > support found in the kernel: - drm: imx: Support Synopsys
>> > DesignWare MIPI DSI host controller
>> > Signed-off-by: Liu Ying <[email protected]>
>> > - ARM: dtsi: imx6qdl: Add support for MIPI DSI host
>> > controller
>> > Signed-off-by: Liu Ying <[email protected]>
>> This one looks like a devicetree patch, but this patch does
>> not touch devicetree.
>> > + ret = clk_prepare_enable(dsi->pllref_clk); + if
>> > (ret) { + dev_err(dev, "%s: Failed to enable
>> > pllref_clk\n", __func__); + return ret; +
>> > } + + dsi->mux_sel =
>> > syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); +
>> > if (IS_ERR(dsi->mux_sel)) { + ret =
>> > PTR_ERR(dsi->mux_sel); + dev_err(dev, "%s:
>> > Failed to get GPR regmap: %d\n", +
>> > __func__, ret); + return ret;
>> You should disable the dsi->pllref_clk clock prior to
>> returning the error.
>
> Another approach could be moving the clock on and off to to
> component_ops.{bind,unbind} (as rockhip driver does).
>
> What exactly is the PLL clock needed for? Would it make sense to
> move it some of the PHY power on/off? (Maybe not, but it's
> worthing checking).
>
> Also, it seems the other IP blocks have this PLL clock, so maybe
> it could be moved to the dw_mipi_dsi core? This could be
> something for a follow-up, to avoid creeping this series.
Hi Ezequiel,
pll is the video reference clock which drives the data lanes and
yes all drivers have it as it's a basic requirement, so moving it
to the common bridge is indeed a good idea, however this kind of
driver refactoring is out of scope for this specific patch series,
because, for now, I'd like to get the regmap and the imx6 driver
in, once that is done we can think how to further abstract away
common logic and slim down the existing drivers further.
Basically I just want to avoid feature creep as I expect v6 to be
~ 8 patches big and the series is already over 1200 lines.
Thank you,
Adrian
>
> Thanks,
> Ezequiel
>
>
> _______________________________________________
> Linux-rockchip mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
On Tue, 2020-03-31 at 00:31 +0300, Adrian Ratiu wrote:
> On Mon, 30 Mar 2020, Ezequiel Garcia <[email protected]>
> wrote:
> > Hello Fabio, Adrian:
> >
> > On Mon, 2020-03-30 at 08:49 -0300, Fabio Estevam wrote:
> > > Hi Adrian, On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu
> > > <[email protected]> wrote:
> > > > This adds support for the Synopsis DesignWare MIPI DSI v1.01
> > > > host controller which is embedded in i.MX 6 SoCs. Based on
> > > > following patches, but updated/extended to work with existing
> > > > support found in the kernel: - drm: imx: Support Synopsys
> > > > DesignWare MIPI DSI host controller
> > > > Signed-off-by: Liu Ying <[email protected]>
> > > > - ARM: dtsi: imx6qdl: Add support for MIPI DSI host
> > > > controller
> > > > Signed-off-by: Liu Ying <[email protected]>
> > > This one looks like a devicetree patch, but this patch does
> > > not touch devicetree.
> > > > + ret = clk_prepare_enable(dsi->pllref_clk); + if
> > > > (ret) { + dev_err(dev, "%s: Failed to enable
> > > > pllref_clk\n", __func__); + return ret; +
> > > > } + + dsi->mux_sel =
> > > > syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr"); +
> > > > if (IS_ERR(dsi->mux_sel)) { + ret =
> > > > PTR_ERR(dsi->mux_sel); + dev_err(dev, "%s:
> > > > Failed to get GPR regmap: %d\n", +
> > > > __func__, ret); + return ret;
> > > You should disable the dsi->pllref_clk clock prior to
> > > returning the error.
> >
> > Another approach could be moving the clock on and off to to
> > component_ops.{bind,unbind} (as rockhip driver does).
> >
> > What exactly is the PLL clock needed for? Would it make sense to
> > move it some of the PHY power on/off? (Maybe not, but it's
> > worthing checking).
> >
> > Also, it seems the other IP blocks have this PLL clock, so maybe
> > it could be moved to the dw_mipi_dsi core? This could be
> > something for a follow-up, to avoid creeping this series.
>
> Hi Ezequiel,
>
> pll is the video reference clock which drives the data lanes and
> yes all drivers have it as it's a basic requirement, so moving it
> to the common bridge is indeed a good idea, however this kind of
> driver refactoring is out of scope for this specific patch series,
> because, for now, I'd like to get the regmap and the imx6 driver
> in, once that is done we can think how to further abstract away
> common logic and slim down the existing drivers further.
>
> Basically I just want to avoid feature creep as I expect v6 to be
> ~ 8 patches big and the series is already over 1200 lines.
>
Oh, absolutely: if there's one thing I try to avoid is
feature creep -- together with bikeshedding!
Do note however, that you could move the PLL clock handling
to component_ops.{bind,unbind} and maybe simplify the error
handling.
(BTW, great work!)
Cheers,
Ezequiel
On Tue, 31 Mar 2020, Ezequiel Garcia <[email protected]>
wrote:
> On Tue, 2020-03-31 at 00:31 +0300, Adrian Ratiu wrote:
>> On Mon, 30 Mar 2020, Ezequiel Garcia <[email protected]>
>> wrote:
>> > Hello Fabio, Adrian: On Mon, 2020-03-30 at 08:49 -0300,
>> > Fabio Estevam wrote:
>> > > Hi Adrian, On Mon, Mar 30, 2020 at 8:34 AM Adrian Ratiu
>> > > <[email protected]> wrote:
>> > > > This adds support for the Synopsis DesignWare MIPI DSI
>> > > > v1.01 host controller which is embedded in i.MX 6 SoCs.
>> > > > Based on following patches, but updated/extended to work
>> > > > with existing support found in the kernel: - drm: imx:
>> > > > Support Synopsys DesignWare MIPI DSI host controller
>> > > > Signed-off-by: Liu Ying <[email protected]>
>> > > > - ARM: dtsi: imx6qdl: Add support for MIPI DSI host
>> > > > controller
>> > > > Signed-off-by: Liu Ying <[email protected]>
>> > > This one looks like a devicetree patch, but this patch
>> > > does
>> > > not touch devicetree.
>> > > > + ret = clk_prepare_enable(dsi->pllref_clk); +
>> > > > if (ret) { + dev_err(dev, "%s: Failed to
>> > > > enable pllref_clk\n", __func__); + return
>> > > > ret; + } + + dsi->mux_sel =
>> > > > syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,gpr");
>> > > > + if (IS_ERR(dsi->mux_sel)) { + ret =
>> > > > PTR_ERR(dsi->mux_sel); + dev_err(dev, "%s:
>> > > > Failed to get GPR regmap: %d\n", + __func__, ret); +
>> > > > return ret;
>> > > You should disable the dsi->pllref_clk clock prior to
>> > > returning the error.
>> > Another approach could be moving the clock on and off to to
>> > component_ops.{bind,unbind} (as rockhip driver does). What
>> > exactly is the PLL clock needed for? Would it make sense to
>> > move it some of the PHY power on/off? (Maybe not, but it's
>> > worthing checking). Also, it seems the other IP blocks
>> > have this PLL clock, so maybe it could be moved to the
>> > dw_mipi_dsi core? This could be something for a follow-up,
>> > to avoid creeping this series.
>> Hi Ezequiel, pll is the video reference clock which drives
>> the data lanes and yes all drivers have it as it's a basic
>> requirement, so moving it to the common bridge is indeed a
>> good idea, however this kind of driver refactoring is out of
>> scope for this specific patch series, because, for now, I'd
>> like to get the regmap and the imx6 driver in, once that is
>> done we can think how to further abstract away common logic
>> and slim down the existing drivers further. Basically I just
>> want to avoid feature creep as I expect v6 to be ~ 8 patches
>> big and the series is already over 1200 lines.
>
> Oh, absolutely: if there's one thing I try to avoid is feature
> creep -- together with bikeshedding!
>
> Do note however, that you could move the PLL clock handling to
> component_ops.{bind,unbind} and maybe simplify the error
> handling.
>
> (BTW, great work!)
Thanks! I'll do the bind/unbind move for the new imx6 driver which
I'm
adding in this series to make it resemble the existing rockchip
driver a bit more, then I'll stop short of further driver
refactorings.
>
> Cheers,
> Ezequiel
Hi Adrian,
Due to different ways of work I use different mail client, so forgive me
if there are some misconfugrations.
W dniu 30.03.2020 o 13:35, Adrian Ratiu pisze:
> Hello everyone,
>
> The v5 series is a significantly cleaned up version from v4,
> started by Ezequiel Garcia's suggestion of splitting out the
> regmap infrastructure from the drivers (thank you!).
>
> Turns out no changes are required to the existing drivers and
> the bridge can transparently take care of the layout logic,
> so there's no need to expose the regmap via plat_data anymore.
>
> Starting from this version I also opted to add per-patch
> changelogs. All review comments up to now have been addressed.
>
> Tested on IMX6DL.
>
> Adrian Ratiu (5):
> drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
> drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
> drm: bridge: synopsis: add dsi v1.01 support
> drm: imx: Add i.MX 6 MIPI DSI host platform driver
> dt-bindings: display: add i.MX6 MIPI DSI host controller doc
>
> .../display/imx/fsl,mipi-dsi-imx6.yaml | 134 ++++
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 683 +++++++++++++-----
So we have above 400 lines more just to add slightly different register
layout of v1.01.
Quite big linecount for apparently small (?) functional change - I was
too lazy to check how many reg fields are really used (some are not used
at all), but it does not seem to be big enough to justyfy so big change IMO.
I will add more comments in specific patches.
Regards
Andrzej
> drivers/gpu/drm/imx/Kconfig | 7 +
> drivers/gpu/drm/imx/Makefile | 1 +
> drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
> 5 files changed, 1049 insertions(+), 175 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>
W dniu 30.03.2020 o 13:35, Adrian Ratiu pisze:
> Register existence, address/offsets, field layouts, reserved bits and
> so on differ between MIPI-DSI versions and between SoC vendor boards.
> Despite these differences the hw IP and protocols are mostly the same
> so the generic bridge can be made to compensate these differences.
>
> The current Rockchip and STM drivers hardcoded a lot of their common
> definitions in the bridge code because they're based on DSI v1.30 and
> 1.31 which are relatively close, but in order to support older/future
> versions with more diverging layouts like the v1.01 present on imx6,
> we abstract some of the register accesses via the regmap field APIs.
>
> The bridge detects the DSI core version and initializes the required
> regmap register layout. Other DSI versions / register layouts can
> easily be added in the future by only changing the bridge code.
>
> The platform drivers don't require any changes, DSI register layout
> versioning will be handled transparently by the bridge, but if in
> the future the regmap or layouts needs to be exposed to the drivres,
> it could easily be done via plat_data or a new API in dw_mipi_dsi.h.
>
> Suggested-by: Boris Brezillon <[email protected]>
> Reviewed-by: Emil Velikov <[email protected]>
> Signed-off-by: Adrian Ratiu <[email protected]>
> ---
> Changes since v4:
> - Move regmap infrastructure logic to a separate commit (Ezequiel)
> - Consolidate field infrastructure in this commit (Ezequiel)
> - Move the dsi v1.01 layout logic to a separate commit (Ezequiel)
>
> Changes since v2:
> - Added const declarations to dw_mipi_dsi structs (Emil)
> - Fixed commit tags (Emil)
>
> Changes since v1:
> - Moved register definitions & regmap initialization into bridge
> module. Platform drivers get the regmap via plat_data after calling
> the bridge probe (Emil).
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 510 ++++++++++++------
> 1 file changed, 352 insertions(+), 158 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 6d9e2f21c9cc..5b78ff925af0 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -31,6 +31,7 @@
> #include <drm/drm_probe_helper.h>
>
> #define HWVER_131 0x31333100 /* IP version 1.31 */
> +#define HWVER_130 0x31333000 /* IP version 1.30 */
>
> #define DSI_VERSION 0x00
> #define VERSION GENMASK(31, 8)
> @@ -47,7 +48,6 @@
> #define DPI_VCID(vcid) ((vcid) & 0x3)
>
> #define DSI_DPI_COLOR_CODING 0x10
> -#define LOOSELY18_EN BIT(8)
> #define DPI_COLOR_CODING_16BIT_1 0x0
> #define DPI_COLOR_CODING_16BIT_2 0x1
> #define DPI_COLOR_CODING_16BIT_3 0x2
> @@ -56,11 +56,6 @@
> #define DPI_COLOR_CODING_24BIT 0x5
>
> #define DSI_DPI_CFG_POL 0x14
> -#define COLORM_ACTIVE_LOW BIT(4)
> -#define SHUTD_ACTIVE_LOW BIT(3)
> -#define HSYNC_ACTIVE_LOW BIT(2)
> -#define VSYNC_ACTIVE_LOW BIT(1)
> -#define DATAEN_ACTIVE_LOW BIT(0)
>
> #define DSI_DPI_LP_CMD_TIM 0x18
> #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
> @@ -81,27 +76,19 @@
> #define DSI_GEN_VCID 0x30
>
> #define DSI_MODE_CFG 0x34
> -#define ENABLE_VIDEO_MODE 0
> -#define ENABLE_CMD_MODE BIT(0)
>
> #define DSI_VID_MODE_CFG 0x38
> -#define ENABLE_LOW_POWER (0x3f << 8)
> -#define ENABLE_LOW_POWER_MASK (0x3f << 8)
> +#define ENABLE_LOW_POWER 0x3f
> +
> #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
> #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
> #define VID_MODE_TYPE_BURST 0x2
> -#define VID_MODE_TYPE_MASK 0x3
> -#define VID_MODE_VPG_ENABLE BIT(16)
> -#define VID_MODE_VPG_HORIZONTAL BIT(24)
>
> #define DSI_VID_PKT_SIZE 0x3c
> -#define VID_PKT_SIZE(p) ((p) & 0x3fff)
>
> #define DSI_VID_NUM_CHUNKS 0x40
> -#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
>
> #define DSI_VID_NULL_SIZE 0x44
> -#define VID_NULL_SIZE(b) ((b) & 0x1fff)
>
> #define DSI_VID_HSA_TIME 0x48
> #define DSI_VID_HBP_TIME 0x4c
> @@ -125,7 +112,6 @@
> #define GEN_SW_2P_TX_LP BIT(10)
> #define GEN_SW_1P_TX_LP BIT(9)
> #define GEN_SW_0P_TX_LP BIT(8)
> -#define ACK_RQST_EN BIT(1)
> #define TEAR_FX_EN BIT(0)
>
> #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
> @@ -154,8 +140,6 @@
> #define GEN_CMD_EMPTY BIT(0)
>
> #define DSI_TO_CNT_CFG 0x78
> -#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
> -#define LPRX_TO_CNT(p) ((p) & 0xffff)
>
> #define DSI_HS_RD_TO_CNT 0x7c
> #define DSI_LP_RD_TO_CNT 0x80
> @@ -164,52 +148,17 @@
> #define DSI_BTA_TO_CNT 0x8c
>
> #define DSI_LPCLK_CTRL 0x94
> -#define AUTO_CLKLANE_CTRL BIT(1)
> -#define PHY_TXREQUESTCLKHS BIT(0)
> -
> #define DSI_PHY_TMR_LPCLK_CFG 0x98
> -#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
> -#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
> -
> #define DSI_PHY_TMR_CFG 0x9c
> -#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
> -#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
> -#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
> -#define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
> -#define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
> -
> #define DSI_PHY_RSTZ 0xa0
> -#define PHY_DISFORCEPLL 0
> -#define PHY_ENFORCEPLL BIT(3)
> -#define PHY_DISABLECLK 0
> -#define PHY_ENABLECLK BIT(2)
> -#define PHY_RSTZ 0
> -#define PHY_UNRSTZ BIT(1)
> -#define PHY_SHUTDOWNZ 0
> -#define PHY_UNSHUTDOWNZ BIT(0)
> -
> #define DSI_PHY_IF_CFG 0xa4
> -#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
> -#define N_LANES(n) (((n) - 1) & 0x3)
> -
> -#define DSI_PHY_ULPS_CTRL 0xa8
> -#define DSI_PHY_TX_TRIGGERS 0xac
>
> #define DSI_PHY_STATUS 0xb0
> #define PHY_STOP_STATE_CLK_LANE BIT(2)
> #define PHY_LOCK BIT(0)
>
> #define DSI_PHY_TST_CTRL0 0xb4
> -#define PHY_TESTCLK BIT(1)
> -#define PHY_UNTESTCLK 0
> -#define PHY_TESTCLR BIT(0)
> -#define PHY_UNTESTCLR 0
> -
> #define DSI_PHY_TST_CTRL1 0xb8
> -#define PHY_TESTEN BIT(16)
> -#define PHY_UNTESTEN 0
> -#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
> -#define PHY_TESTDIN(n) ((n) & 0xff)
>
> #define DSI_INT_ST0 0xbc
> #define DSI_INT_ST1 0xc0
> @@ -217,7 +166,6 @@
> #define DSI_INT_MSK1 0xc8
>
> #define DSI_PHY_TMR_RD_CFG 0xf4
> -#define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
>
> #define PHY_STATUS_TIMEOUT_US 10000
> #define CMD_PKT_STATUS_TIMEOUT_US 20000
> @@ -250,6 +198,53 @@ struct dw_mipi_dsi {
> struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
>
> const struct dw_mipi_dsi_plat_data *plat_data;
> +
> + struct regmap_field *field_dpi_18loosely_en;
> + struct regmap_field *field_dpi_color_coding;
> + struct regmap_field *field_dpi_vid;
> + struct regmap_field *field_dpi_vsync_active_low;
> + struct regmap_field *field_dpi_hsync_active_low;
> + struct regmap_field *field_cmd_mode_ack_rqst_en;
> + struct regmap_field *field_cmd_mode_all_lp_en;
> + struct regmap_field *field_cmd_mode_en;
> + struct regmap_field *field_cmd_pkt_status;
> + struct regmap_field *field_vid_mode_en;
> + struct regmap_field *field_vid_mode_type;
> + struct regmap_field *field_vid_mode_low_power;
> + struct regmap_field *field_vid_mode_vpg_en;
> + struct regmap_field *field_vid_mode_vpg_horiz;
> + struct regmap_field *field_vid_pkt_size;
> + struct regmap_field *field_vid_hsa_time;
> + struct regmap_field *field_vid_hbp_time;
> + struct regmap_field *field_vid_hline_time;
> + struct regmap_field *field_vid_vsa_time;
> + struct regmap_field *field_vid_vbp_time;
> + struct regmap_field *field_vid_vfp_time;
> + struct regmap_field *field_vid_vactive_time;
> + struct regmap_field *field_phy_txrequestclkhs;
> + struct regmap_field *field_phy_bta_time;
> + struct regmap_field *field_phy_max_rd_time;
> + struct regmap_field *field_phy_lp2hs_time;
> + struct regmap_field *field_phy_hs2lp_time;
> + struct regmap_field *field_phy_clklp2hs_time;
> + struct regmap_field *field_phy_clkhs2lp_time;
> + struct regmap_field *field_phy_testclr;
> + struct regmap_field *field_phy_unshutdownz;
> + struct regmap_field *field_phy_unrstz;
> + struct regmap_field *field_phy_enableclk;
> + struct regmap_field *field_phy_forcepll;
> + struct regmap_field *field_phy_nlanes;
> + struct regmap_field *field_phy_stop_wait_time;
> + struct regmap_field *field_phy_status;
> + struct regmap_field *field_pckhdl_cfg;
> + struct regmap_field *field_hstx_timeout_counter;
> + struct regmap_field *field_lprx_timeout_counter;
> + struct regmap_field *field_int_stat0;
> + struct regmap_field *field_int_stat1;
> + struct regmap_field *field_int_mask0;
> + struct regmap_field *field_int_mask1;
> + struct regmap_field *field_gen_hdr;
> + struct regmap_field *field_gen_payload;
> };
>
> static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
> @@ -259,6 +254,111 @@ static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
> .name = "dw-mipi-dsi",
> };
>
> +struct dw_mipi_dsi_variant {
> + /* Regmap field configs for DSI adapter */
> + struct reg_field cfg_dpi_18loosely_en;
> + struct reg_field cfg_dpi_color_coding;
> + struct reg_field cfg_dpi_vid;
> + struct reg_field cfg_dpi_vsync_active_low;
> + struct reg_field cfg_dpi_hsync_active_low;
> + struct reg_field cfg_cmd_mode_en;
> + struct reg_field cfg_cmd_mode_ack_rqst_en;
> + struct reg_field cfg_cmd_mode_all_lp_en;
> + struct reg_field cfg_cmd_pkt_status;
> + struct reg_field cfg_vid_mode_en;
> + struct reg_field cfg_vid_mode_type;
> + struct reg_field cfg_vid_mode_low_power;
> + struct reg_field cfg_vid_mode_vpg_en;
> + struct reg_field cfg_vid_mode_vpg_horiz;
> + struct reg_field cfg_vid_pkt_size;
> + struct reg_field cfg_vid_hsa_time;
> + struct reg_field cfg_vid_hbp_time;
> + struct reg_field cfg_vid_hline_time;
> + struct reg_field cfg_vid_vsa_time;
> + struct reg_field cfg_vid_vbp_time;
> + struct reg_field cfg_vid_vfp_time;
> + struct reg_field cfg_vid_vactive_time;
> + struct reg_field cfg_phy_txrequestclkhs;
> + struct reg_field cfg_phy_bta_time;
> + struct reg_field cfg_phy_max_rd_time;
> + struct reg_field cfg_phy_lp2hs_time;
> + struct reg_field cfg_phy_hs2lp_time;
> + struct reg_field cfg_phy_max_rd_time_v131;
> + struct reg_field cfg_phy_lp2hs_time_v131;
> + struct reg_field cfg_phy_hs2lp_time_v131;
> + struct reg_field cfg_phy_clklp2hs_time;
> + struct reg_field cfg_phy_clkhs2lp_time;
> + struct reg_field cfg_phy_testclr;
> + struct reg_field cfg_phy_unshutdownz;
> + struct reg_field cfg_phy_unrstz;
> + struct reg_field cfg_phy_enableclk;
> + struct reg_field cfg_phy_forcepll;
> + struct reg_field cfg_phy_nlanes;
> + struct reg_field cfg_phy_stop_wait_time;
> + struct reg_field cfg_phy_status;
> + struct reg_field cfg_pckhdl_cfg;
> + struct reg_field cfg_hstx_timeout_counter;
> + struct reg_field cfg_lprx_timeout_counter;
> + struct reg_field cfg_int_stat0;
> + struct reg_field cfg_int_stat1;
> + struct reg_field cfg_int_mask0;
> + struct reg_field cfg_int_mask1;
> + struct reg_field cfg_gen_hdr;
> + struct reg_field cfg_gen_payload;
> +};
> +
> +static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> + .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
> + .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
> + .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 2),
> + .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
> + .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
> + .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
> + .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG, 8, 24),
> + .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
> + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
> + .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
> + .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
> + .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
> + .cfg_vid_mode_vpg_en = REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
> + .cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
> + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
> + .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
> + .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
> + .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
> + .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
> + .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
> + .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
> + .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
> + .cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
> + .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
> + .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> + .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
> + .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
> + .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
> + .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> + .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
> + .cfg_phy_clklp2hs_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
> + .cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
> + .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
> + .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ, 0, 0),
> + .cfg_phy_unrstz = REG_FIELD(DSI_PHY_RSTZ, 1, 1),
> + .cfg_phy_enableclk = REG_FIELD(DSI_PHY_RSTZ, 2, 2),
> + .cfg_phy_forcepll = REG_FIELD(DSI_PHY_RSTZ, 3, 3),
> + .cfg_phy_nlanes = REG_FIELD(DSI_PHY_IF_CFG, 0, 1),
> + .cfg_phy_stop_wait_time = REG_FIELD(DSI_PHY_IF_CFG, 8, 15),
> + .cfg_phy_status = REG_FIELD(DSI_PHY_STATUS, 0, 0),
> + .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
> + .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
> + .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
> + .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 31),
> + .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 31),
> + .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 31),
> + .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 31),
> + .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 31),
> + .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
> +};
> +
> /*
> * Check if either a link to a master or slave is present
> */
> @@ -359,15 +459,22 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
> const struct mipi_dsi_msg *msg)
> {
> bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
> - u32 val = 0;
> + u32 cmd_mode_lp = 0;
> +
> + switch (dsi->hw_version) {
> + case HWVER_130:
> + case HWVER_131:
> + cmd_mode_lp = CMD_MODE_ALL_LP;
> + break;
> + }
>
> if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
> - val |= ACK_RQST_EN;
> + regmap_field_write(dsi->field_cmd_mode_ack_rqst_en, 1);
> +
> if (lpm)
> - val |= CMD_MODE_ALL_LP;
> + regmap_field_write(dsi->field_cmd_mode_all_lp_en, cmd_mode_lp);
>
> - regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
> - regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
> + regmap_field_write(dsi->field_phy_txrequestclkhs, lpm ? 0 : 1);
> }
>
> static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> @@ -375,18 +482,18 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> int ret;
> u32 val = 0, mask;
>
> - ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_CMD_FULL), 1000,
> - CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
> + val, !(val & GEN_CMD_FULL),
> + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev, "failed to get available command FIFO\n");
> return ret;
> }
>
> - regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
> + regmap_field_write(dsi->field_gen_hdr, hdr_val);
>
> mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
> - ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> + ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
> val, (val & mask) == mask,
> 1000, CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> @@ -409,20 +516,22 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
> if (len < pld_data_bytes) {
> word = 0;
> memcpy(&word, tx_buf, len);
> - regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> - le32_to_cpu(word));
> + regmap_field_write(dsi->field_gen_payload,
> + le32_to_cpu(word));
> len = 0;
> } else {
> memcpy(&word, tx_buf, pld_data_bytes);
> - regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
> - le32_to_cpu(word));
> + regmap_field_write(dsi->field_gen_payload,
> + le32_to_cpu(word));
> tx_buf += pld_data_bytes;
> len -= pld_data_bytes;
> }
>
> - ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_PLD_W_FULL),
> - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
> + val,
> + !(val & GEN_PLD_W_FULL),
> + 1000,
> + CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev,
> "failed to get available write payload FIFO\n");
> @@ -443,9 +552,9 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
> u32 val = 0;
>
> /* Wait end of the read operation */
> - ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_RD_CMD_BUSY),
> - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
> + val, !(val & GEN_RD_CMD_BUSY),
> + 1000, CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev, "Timeout during read operation\n");
> return ret;
> @@ -453,15 +562,17 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
>
> for (i = 0; i < len; i += 4) {
> /* Read fifo must not be empty before all bytes are read */
> - ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
> - val, !(val & GEN_PLD_R_EMPTY),
> - 1000, CMD_PKT_STATUS_TIMEOUT_US);
> + ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
> + val,
> + !(val & GEN_PLD_R_EMPTY),
> + 1000,
> + CMD_PKT_STATUS_TIMEOUT_US);
> if (ret) {
> dev_err(dsi->dev, "Read payload FIFO is empty\n");
> return ret;
> }
>
> - regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
> + regmap_field_read(dsi->field_gen_payload, &val);
> for (j = 0; j < 4 && j + i < len; j++)
> buf[i + j] = val >> (8 * j);
> }
> @@ -515,30 +626,30 @@ static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
>
> static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
> {
> - u32 val;
> -
> /*
> * TODO dw drv improvements
> * enabling low power is panel-dependent, we should use the
> * panel configuration here...
> */
> - val = ENABLE_LOW_POWER;
> + regmap_field_write(dsi->field_vid_mode_low_power, ENABLE_LOW_POWER);
>
> if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
> - val |= VID_MODE_TYPE_BURST;
> + regmap_field_write(dsi->field_vid_mode_type,
> + VID_MODE_TYPE_BURST);
> else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> - val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
> + regmap_field_write(dsi->field_vid_mode_type,
> + VID_MODE_TYPE_NON_BURST_SYNC_PULSES);
> else
> - val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
> + regmap_field_write(dsi->field_vid_mode_type,
> + VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
>
> #ifdef CONFIG_DEBUG_FS
> if (dsi->vpg) {
> - val |= VID_MODE_VPG_ENABLE;
> - val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
> + regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_en, 1);
> + regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_horiz,
> + dsi->vpg_horizontal ? 1 : 0);
> }
> #endif /* CONFIG_DEBUG_FS */
> -
> - regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
> }
>
> static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> @@ -547,11 +658,13 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>
> if (mode_flags & MIPI_DSI_MODE_VIDEO) {
> - regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
> + regmap_field_write(dsi->field_cmd_mode_en, 0);
> +
> dw_mipi_dsi_video_mode_config(dsi);
> - regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
> +
> + regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
> } else {
> - regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
> + regmap_field_write(dsi->field_cmd_mode_en, 1);
> }
>
> regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
> @@ -560,7 +673,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
> static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
> {
> regmap_write(dsi->regs, DSI_PWR_UP, RESET);
> - regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
> + regmap_field_write(dsi->field_phy_unrstz, 0);
> }
>
> static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> @@ -589,14 +702,15 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
> static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> const struct drm_display_mode *mode)
> {
> - u32 val = 0, color = 0;
> + u32 color = 0;
>
> switch (dsi->format) {
> case MIPI_DSI_FMT_RGB888:
> color = DPI_COLOR_CODING_24BIT;
> break;
> case MIPI_DSI_FMT_RGB666:
> - color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
> + color = DPI_COLOR_CODING_18BIT_2;
> + regmap_field_write(dsi->field_dpi_18loosely_en, 1);
> break;
> case MIPI_DSI_FMT_RGB666_PACKED:
> color = DPI_COLOR_CODING_18BIT_1;
> @@ -606,14 +720,15 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
> break;
> }
>
> - if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> - val |= VSYNC_ACTIVE_LOW;
> - if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> - val |= HSYNC_ACTIVE_LOW;
> + regmap_field_write(dsi->field_dpi_color_coding, color);
> +
> + if (!(mode->flags & DRM_MODE_FLAG_NVSYNC))
> + regmap_field_write(dsi->field_dpi_vsync_active_low, 1);
> + if (!(mode->flags & DRM_MODE_FLAG_NHSYNC))
> + regmap_field_write(dsi->field_dpi_hsync_active_low, 1);
> +
> + regmap_field_write(dsi->field_dpi_vid, DPI_VCID(dsi->channel));
>
> - regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
> - regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
> - regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
> /*
> * TODO dw drv improvements
> * largest packet sizes during hfp or during vsa/vpb/vfp
> @@ -626,7 +741,8 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>
> static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
> {
> - regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
> + regmap_field_write(dsi->field_pckhdl_cfg,
> + CRC_RX_EN | ECC_RX_EN | BTA_EN);
> }
>
> static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> @@ -639,11 +755,9 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
> * DSI_VNPCR.NPSIZE... especially because this driver supports
> * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
> */
> -
> - regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
> - dw_mipi_is_dual_mode(dsi) ?
> - VID_PKT_SIZE(mode->hdisplay / 2) :
> - VID_PKT_SIZE(mode->hdisplay));
> + regmap_field_write(dsi->field_vid_pkt_size,
> + dw_mipi_is_dual_mode(dsi) ?
> + mode->hdisplay / 2 : mode->hdisplay);
> }
>
> static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> @@ -653,15 +767,17 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
> * compute high speed transmission counter timeout according
> * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
> */
> - regmap_write(dsi->regs, DSI_TO_CNT_CFG,
> - HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
> + regmap_field_write(dsi->field_hstx_timeout_counter, 1000);
> + regmap_field_write(dsi->field_lprx_timeout_counter, 1000);
> +
> /*
> * TODO dw drv improvements
> * the Bus-Turn-Around Timeout Counter should be computed
> * according to byte lane...
> */
> - regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
> - regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
> + regmap_field_write(dsi->field_phy_bta_time, 0xd00);
> +
> + regmap_field_write(dsi->field_cmd_mode_en, 1);
> }
>
> /* Get lane byte clock cycles. */
> @@ -695,13 +811,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
> * computations below may be improved...
> */
> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
> - regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
> + regmap_field_write(dsi->field_vid_hline_time, lbcc);
>
> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
> - regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
> + regmap_field_write(dsi->field_vid_hsa_time, lbcc);
>
> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
> - regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
> + regmap_field_write(dsi->field_vid_hbp_time, lbcc);
> }
>
> static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> @@ -714,17 +830,16 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
> vfp = mode->vsync_start - mode->vdisplay;
> vbp = mode->vtotal - mode->vsync_end;
>
> - regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
> - regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
> - regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
> - regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
> + regmap_field_write(dsi->field_vid_vactive_time, vactive);
> + regmap_field_write(dsi->field_vid_vsa_time, vsa);
> + regmap_field_write(dsi->field_vid_vfp_time, vfp);
> + regmap_field_write(dsi->field_vid_vbp_time, vbp);
> }
>
> static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> {
> const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
> struct dw_mipi_dsi_dphy_timing timing;
> - u32 hw_version;
> int ret;
>
> ret = phy_ops->get_timing(dsi->plat_data->priv_data,
> @@ -739,26 +854,12 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
> * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
> * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
> */
> + regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
> + regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
>
> - regmap_read(dsi->regs, DSI_VERSION, &hw_version);
> - hw_version &= VERSION;
> -
> - if (hw_version >= HWVER_131) {
> - regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> - PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
> - PHY_LP2HS_TIME_V131(timing.data_lp2hs));
> - regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
> - MAX_RD_TIME_V131(10000));
> - } else {
> - regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
> - PHY_HS2LP_TIME(timing.data_hs2lp) |
> - PHY_LP2HS_TIME(timing.data_lp2hs) |
> - MAX_RD_TIME(10000));
> - }
> -
> - regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
> - PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
> - PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
> + regmap_field_write(dsi->field_phy_max_rd_time, 10000);
> + regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
> + regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
> }
>
> static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> @@ -768,18 +869,22 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
> * stop wait time should be the maximum between host dsi
> * and panel stop wait times
> */
> - regmap_write(dsi->regs, DSI_PHY_IF_CFG,
> - PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
> + regmap_field_write(dsi->field_phy_stop_wait_time, 0x20);
> + regmap_field_write(dsi->field_phy_nlanes, dsi->lanes - 1);
> }
>
> static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
> {
> /* Clear PHY state */
> - regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
> - | PHY_RSTZ | PHY_SHUTDOWNZ);
> - regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> - regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
> - regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
> + regmap_field_write(dsi->field_phy_enableclk, 0);
> + regmap_field_write(dsi->field_phy_unrstz, 0);
> + regmap_field_write(dsi->field_phy_unshutdownz, 0);
> +
> + regmap_field_write(dsi->field_phy_forcepll, 0);
> +
> + regmap_field_write(dsi->field_phy_testclr, 0);
> + regmap_field_write(dsi->field_phy_testclr, 1);
> + regmap_field_write(dsi->field_phy_testclr, 0);
> }
>
> static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
> @@ -787,18 +892,21 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
> u32 val = 0;
> int ret;
>
> - regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
> - PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
> + regmap_field_write(dsi->field_phy_enableclk, 1);
> + regmap_field_write(dsi->field_phy_unrstz, 1);
> + regmap_field_write(dsi->field_phy_unshutdownz, 1);
> +
> + regmap_field_write(dsi->field_phy_forcepll, 1);
>
> - ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> - val, val & PHY_LOCK,
> - 1000, PHY_STATUS_TIMEOUT_US);
> + ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
> + val, val & PHY_LOCK,
> + 1000, PHY_STATUS_TIMEOUT_US);
> if (ret)
> DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
>
> - ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
> - val, val & PHY_STOP_STATE_CLK_LANE, 1000,
> - PHY_STATUS_TIMEOUT_US);
> + ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
> + val, val & PHY_STOP_STATE_CLK_LANE,
> + 1000, PHY_STATUS_TIMEOUT_US);
> if (ret)
> DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
> }
> @@ -807,10 +915,10 @@ static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
> {
> u32 val;
>
> - regmap_read(dsi->regs, DSI_INT_ST0, &val);
> - regmap_read(dsi->regs, DSI_INT_ST1, &val);
> - regmap_write(dsi->regs, DSI_INT_MSK0, 0);
> - regmap_write(dsi->regs, DSI_INT_MSK1, 0);
> + regmap_field_read(dsi->field_int_stat0, &val);
> + regmap_field_read(dsi->field_int_stat1, &val);
> + regmap_field_write(dsi->field_int_mask0, 0);
> + regmap_field_write(dsi->field_int_mask1, 0);
> }
>
> static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
> @@ -1005,6 +1113,86 @@ static void dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
> dev_err(dsi->dev, "Failed to read DSI hw version register\n");
> }
>
> +#define INIT_FIELD(f) INIT_FIELD_CFG(field_##f, cfg_##f)
> +#define INIT_FIELD_CFG(f, conf) \
> + do { \
> + dsi->f = devm_regmap_field_alloc(dsi->dev, dsi->regs, \
> + variant->conf); \
> + if (IS_ERR(dsi->f)) \
> + dev_warn(dsi->dev, "Ignoring regmap field " #f "\n"); \
> + } while (0)
In kernel you can use gcc extension ({ ... }) instead "do { ... } while
(0)" [1].
[1]: https://gcc.gnu.org/onlinedocs/gcc/Statement-Exprs.html
> +
> +static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
> +{
> + const struct dw_mipi_dsi_variant *variant;
> +
> + switch (dsi->hw_version) {
> + case HWVER_130:
> + case HWVER_131:
> + variant = &dw_mipi_dsi_v130_v131_layout;
> + break;
> + default:
> + DRM_ERROR("Unrecognized DSI host controller HW revision\n");
> + return -ENODEV;
> + }
> +
> + INIT_FIELD(dpi_18loosely_en);
> + INIT_FIELD(dpi_vid);
> + INIT_FIELD(dpi_color_coding);
> + INIT_FIELD(dpi_vsync_active_low);
> + INIT_FIELD(dpi_hsync_active_low);
> + INIT_FIELD(cmd_mode_ack_rqst_en);
> + INIT_FIELD(cmd_mode_all_lp_en);
> + INIT_FIELD(cmd_mode_en);
> + INIT_FIELD(cmd_pkt_status);
> + INIT_FIELD(vid_mode_en);
> + INIT_FIELD(vid_mode_type);
> + INIT_FIELD(vid_mode_low_power);
> + INIT_FIELD(vid_pkt_size);
> + INIT_FIELD(vid_hsa_time);
> + INIT_FIELD(vid_hbp_time);
> + INIT_FIELD(vid_hline_time);
> + INIT_FIELD(vid_vsa_time);
> + INIT_FIELD(vid_vbp_time);
> + INIT_FIELD(vid_vfp_time);
> + INIT_FIELD(vid_vactive_time);
> + INIT_FIELD(phy_txrequestclkhs);
> + INIT_FIELD(phy_testclr);
> + INIT_FIELD(phy_unshutdownz);
> + INIT_FIELD(phy_unrstz);
> + INIT_FIELD(phy_enableclk);
> + INIT_FIELD(phy_nlanes);
> + INIT_FIELD(phy_stop_wait_time);
> + INIT_FIELD(phy_status);
> + INIT_FIELD(pckhdl_cfg);
> + INIT_FIELD(hstx_timeout_counter);
> + INIT_FIELD(lprx_timeout_counter);
> + INIT_FIELD(int_stat0);
> + INIT_FIELD(int_stat1);
> + INIT_FIELD(int_mask0);
> + INIT_FIELD(int_mask1);
> + INIT_FIELD(gen_hdr);
> + INIT_FIELD(gen_payload);
> + INIT_FIELD(phy_bta_time);
> + INIT_FIELD(vid_mode_vpg_en);
> + INIT_FIELD(vid_mode_vpg_horiz);
> + INIT_FIELD(phy_clklp2hs_time);
> + INIT_FIELD(phy_clkhs2lp_time);
> + INIT_FIELD(phy_forcepll);
> +
> + if (dsi->hw_version == HWVER_131) {
> + INIT_FIELD_CFG(field_phy_max_rd_time, cfg_phy_max_rd_time_v131);
> + INIT_FIELD_CFG(field_phy_lp2hs_time, cfg_phy_lp2hs_time_v131);
> + INIT_FIELD_CFG(field_phy_hs2lp_time, cfg_phy_hs2lp_time_v131);
> + } else {
> + INIT_FIELD(phy_max_rd_time);
> + INIT_FIELD(phy_lp2hs_time);
> + INIT_FIELD(phy_hs2lp_time);
> + }
And here we have devres storm - for every field we allocate memory,
enqueue deallocator, copy static values to dynamic struct and more.
I know that CPU power and memory are cheap, but this hurts my eyes :)
Other thing is that this complicates the driver - adding new field will
require changes at least in 4 (?) places, without counting real field usage.
And here is very simple alternative how different hw register layout can
be coded without much ado: [1][2].
[1]:
https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/exynos/exynos_hdmi.c#L55
[2]:
https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/exynos/exynos_hdmi.c#L667
To be clear, I am not totally against this approach - the patch seems to
me correct, it is just 'baroque' :) If you can show that approach from
[1] and [2] in this case will be more problematic we can go your way.
Anyway more comments appreciated.
Regards
Andrzej
> +
> + return 0;
> +}
> +
> static struct dw_mipi_dsi *
> __dw_mipi_dsi_probe(struct platform_device *pdev,
> const struct dw_mipi_dsi_plat_data *plat_data)
> @@ -1081,6 +1269,12 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>
> dw_mipi_dsi_get_hw_version(dsi);
>
> + ret = dw_mipi_dsi_regmap_fields_init(dsi);
> + if (ret) {
> + dev_err(dev, "Failed to init register layout map: %d\n", ret);
> + return ERR_PTR(ret);
> + }
> +
> dw_mipi_dsi_debugfs_init(dsi);
> pm_runtime_enable(dev);
>
Hi Andrzej,
Thank you for the feedback, I really appreciate it, replies are
below.
On Mon, 06 Apr 2020, Andrzej Hajda <[email protected]> wrote:
> W dniu 30.03.2020 o 13:35, Adrian Ratiu pisze:
>> Register existence, address/offsets, field layouts, reserved
>> bits and so on differ between MIPI-DSI versions and between SoC
>> vendor boards. Despite these differences the hw IP and
>> protocols are mostly the same so the generic bridge can be made
>> to compensate these differences.
>>
>> The current Rockchip and STM drivers hardcoded a lot of their
>> common definitions in the bridge code because they're based on
>> DSI v1.30 and 1.31 which are relatively close, but in order to
>> support older/future versions with more diverging layouts like
>> the v1.01 present on imx6, we abstract some of the register
>> accesses via the regmap field APIs.
>>
>> The bridge detects the DSI core version and initializes the
>> required regmap register layout. Other DSI versions / register
>> layouts can easily be added in the future by only changing the
>> bridge code.
>>
>> The platform drivers don't require any changes, DSI register
>> layout versioning will be handled transparently by the bridge,
>> but if in the future the regmap or layouts needs to be exposed
>> to the drivres, it could easily be done via plat_data or a new
>> API in dw_mipi_dsi.h.
>>
>> Suggested-by: Boris Brezillon <[email protected]>
>> Reviewed-by: Emil Velikov <[email protected]>
>> Signed-off-by: Adrian Ratiu <[email protected]> ---
>> Changes since v4:
>> - Move regmap infrastructure logic to a separate commit
>> (Ezequiel) - Consolidate field infrastructure in this commit
>> (Ezequiel) - Move the dsi v1.01 layout logic to a separate
>> commit (Ezequiel)
>>
>> Changes since v2:
>> - Added const declarations to dw_mipi_dsi structs (Emil) -
>> Fixed commit tags (Emil)
>>
>> Changes since v1:
>> - Moved register definitions & regmap initialization into
>> bridge module. Platform drivers get the regmap via plat_data
>> after calling the bridge probe (Emil).
>> ---
>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 510
>> ++++++++++++------ 1 file changed, 352 insertions(+), 158
>> deletions(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index
>> 6d9e2f21c9cc..5b78ff925af0 100644 ---
>> a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++
>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -31,6 +31,7
>> @@
>> #include <drm/drm_probe_helper.h> #define HWVER_131
>> 0x31333100 /* IP version 1.31 */
>> +#define HWVER_130 0x31333000 /* IP
>> version 1.30 */
>> #define DSI_VERSION 0x00 #define
>> VERSION GENMASK(31, 8)
>> @@ -47,7 +48,6 @@
>> #define DPI_VCID(vcid) ((vcid) & 0x3)
>> #define DSI_DPI_COLOR_CODING 0x10
>> -#define LOOSELY18_EN BIT(8)
>> #define DPI_COLOR_CODING_16BIT_1 0x0 #define
>> DPI_COLOR_CODING_16BIT_2 0x1 #define
>> DPI_COLOR_CODING_16BIT_3 0x2
>> @@ -56,11 +56,6 @@
>> #define DPI_COLOR_CODING_24BIT 0x5 #define
>> DSI_DPI_CFG_POL 0x14
>> -#define COLORM_ACTIVE_LOW BIT(4) -#define
>> SHUTD_ACTIVE_LOW BIT(3) -#define HSYNC_ACTIVE_LOW
>> BIT(2) -#define VSYNC_ACTIVE_LOW BIT(1) -#define
>> DATAEN_ACTIVE_LOW BIT(0)
>> #define DSI_DPI_LP_CMD_TIM 0x18 #define
>> OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
>> @@ -81,27 +76,19 @@
>> #define DSI_GEN_VCID 0x30 #define
>> DSI_MODE_CFG 0x34
>> -#define ENABLE_VIDEO_MODE 0 -#define ENABLE_CMD_MODE
>> BIT(0)
>> #define DSI_VID_MODE_CFG 0x38
>> -#define ENABLE_LOW_POWER (0x3f << 8) -#define
>> ENABLE_LOW_POWER_MASK (0x3f << 8) +#define
>> ENABLE_LOW_POWER 0x3f +
>> #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
>> #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
>> #define VID_MODE_TYPE_BURST 0x2
>> -#define VID_MODE_TYPE_MASK 0x3 -#define
>> VID_MODE_VPG_ENABLE BIT(16) -#define
>> VID_MODE_VPG_HORIZONTAL BIT(24)
>> #define DSI_VID_PKT_SIZE 0x3c
>> -#define VID_PKT_SIZE(p) ((p) & 0x3fff)
>> #define DSI_VID_NUM_CHUNKS 0x40
>> -#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
>> #define DSI_VID_NULL_SIZE 0x44
>> -#define VID_NULL_SIZE(b) ((b) & 0x1fff)
>> #define DSI_VID_HSA_TIME 0x48 #define
>> DSI_VID_HBP_TIME 0x4c
>> @@ -125,7 +112,6 @@
>> #define GEN_SW_2P_TX_LP BIT(10) #define
>> GEN_SW_1P_TX_LP BIT(9) #define
>> GEN_SW_0P_TX_LP BIT(8)
>> -#define ACK_RQST_EN BIT(1)
>> #define TEAR_FX_EN BIT(0) #define
>> CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
>> @@ -154,8 +140,6 @@
>> #define GEN_CMD_EMPTY BIT(0) #define
>> DSI_TO_CNT_CFG 0x78
>> -#define HSTX_TO_CNT(p) (((p) & 0xffff) <<
>> 16) -#define LPRX_TO_CNT(p) ((p) & 0xffff)
>> #define DSI_HS_RD_TO_CNT 0x7c #define
>> DSI_LP_RD_TO_CNT 0x80
>> @@ -164,52 +148,17 @@
>> #define DSI_BTA_TO_CNT 0x8c #define
>> DSI_LPCLK_CTRL 0x94
>> -#define AUTO_CLKLANE_CTRL BIT(1) -#define
>> PHY_TXREQUESTCLKHS BIT(0) -
>> #define DSI_PHY_TMR_LPCLK_CFG 0x98
>> -#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff)
>> << 16) -#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) &
>> 0x3ff) -
>> #define DSI_PHY_TMR_CFG 0x9c
>> -#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff)
>> << 24) -#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff)
>> << 16) -#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
>> -#define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
>> -#define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) -
>> #define DSI_PHY_RSTZ 0xa0
>> -#define PHY_DISFORCEPLL 0 -#define
>> PHY_ENFORCEPLL BIT(3) -#define
>> PHY_DISABLECLK 0 -#define PHY_ENABLECLK
>> BIT(2) -#define PHY_RSTZ 0 -#define
>> PHY_UNRSTZ BIT(1) -#define PHY_SHUTDOWNZ
>> 0 -#define PHY_UNSHUTDOWNZ BIT(0) -
>> #define DSI_PHY_IF_CFG 0xa4
>> -#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
>> -#define N_LANES(n) (((n) - 1) & 0x3) -
>> -#define DSI_PHY_ULPS_CTRL 0xa8 -#define
>> DSI_PHY_TX_TRIGGERS 0xac
>> #define DSI_PHY_STATUS 0xb0 #define
>> PHY_STOP_STATE_CLK_LANE BIT(2) #define PHY_LOCK
>> BIT(0) #define DSI_PHY_TST_CTRL0 0xb4
>> -#define PHY_TESTCLK BIT(1) -#define
>> PHY_UNTESTCLK 0 -#define PHY_TESTCLR
>> BIT(0) -#define PHY_UNTESTCLR 0 -
>> #define DSI_PHY_TST_CTRL1 0xb8
>> -#define PHY_TESTEN BIT(16) -#define
>> PHY_UNTESTEN 0 -#define PHY_TESTDOUT(n)
>> (((n) & 0xff) << 8) -#define PHY_TESTDIN(n)
>> ((n) & 0xff)
>> #define DSI_INT_ST0 0xbc #define
>> DSI_INT_ST1 0xc0
>> @@ -217,7 +166,6 @@
>> #define DSI_INT_MSK1 0xc8 #define
>> DSI_PHY_TMR_RD_CFG 0xf4
>> -#define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
>> #define PHY_STATUS_TIMEOUT_US 10000 #define
>> CMD_PKT_STATUS_TIMEOUT_US 20000
>> @@ -250,6 +198,53 @@ struct dw_mipi_dsi {
>> struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ const
>> struct dw_mipi_dsi_plat_data *plat_data;
>> + + struct regmap_field *field_dpi_18loosely_en; +
>> struct regmap_field *field_dpi_color_coding; + struct
>> regmap_field *field_dpi_vid; + struct regmap_field
>> *field_dpi_vsync_active_low; + struct regmap_field
>> *field_dpi_hsync_active_low; + struct regmap_field
>> *field_cmd_mode_ack_rqst_en; + struct regmap_field
>> *field_cmd_mode_all_lp_en; + struct regmap_field
>> *field_cmd_mode_en; + struct regmap_field
>> *field_cmd_pkt_status; + struct regmap_field
>> *field_vid_mode_en; + struct regmap_field
>> *field_vid_mode_type; + struct regmap_field
>> *field_vid_mode_low_power; + struct regmap_field
>> *field_vid_mode_vpg_en; + struct regmap_field
>> *field_vid_mode_vpg_horiz; + struct regmap_field
>> *field_vid_pkt_size; + struct regmap_field
>> *field_vid_hsa_time; + struct regmap_field
>> *field_vid_hbp_time; + struct regmap_field
>> *field_vid_hline_time; + struct regmap_field
>> *field_vid_vsa_time; + struct regmap_field
>> *field_vid_vbp_time; + struct regmap_field
>> *field_vid_vfp_time; + struct regmap_field
>> *field_vid_vactive_time; + struct regmap_field
>> *field_phy_txrequestclkhs; + struct regmap_field
>> *field_phy_bta_time; + struct regmap_field
>> *field_phy_max_rd_time; + struct regmap_field
>> *field_phy_lp2hs_time; + struct regmap_field
>> *field_phy_hs2lp_time; + struct regmap_field
>> *field_phy_clklp2hs_time; + struct regmap_field
>> *field_phy_clkhs2lp_time; + struct regmap_field
>> *field_phy_testclr; + struct regmap_field
>> *field_phy_unshutdownz; + struct regmap_field
>> *field_phy_unrstz; + struct regmap_field
>> *field_phy_enableclk; + struct regmap_field
>> *field_phy_forcepll; + struct regmap_field
>> *field_phy_nlanes; + struct regmap_field
>> *field_phy_stop_wait_time; + struct regmap_field
>> *field_phy_status; + struct regmap_field *field_pckhdl_cfg;
>> + struct regmap_field *field_hstx_timeout_counter; +
>> struct regmap_field *field_lprx_timeout_counter; + struct
>> regmap_field *field_int_stat0; + struct regmap_field
>> *field_int_stat1; + struct regmap_field *field_int_mask0;
>> + struct regmap_field *field_int_mask1; + struct
>> regmap_field *field_gen_hdr; + struct regmap_field
>> *field_gen_payload;
>> }; static const struct regmap_config dw_mipi_dsi_regmap_cfg
>> = {
>> @@ -259,6 +254,111 @@ static const struct regmap_config
>> dw_mipi_dsi_regmap_cfg = {
>> .name = "dw-mipi-dsi", };
>> +struct dw_mipi_dsi_variant { + /* Regmap field configs
>> for DSI adapter */ + struct reg_field
>> cfg_dpi_18loosely_en; + struct reg_field
>> cfg_dpi_color_coding; + struct reg_field
>> cfg_dpi_vid; + struct reg_field
>> cfg_dpi_vsync_active_low; + struct reg_field
>> cfg_dpi_hsync_active_low; + struct reg_field
>> cfg_cmd_mode_en; + struct reg_field
>> cfg_cmd_mode_ack_rqst_en; + struct reg_field
>> cfg_cmd_mode_all_lp_en; + struct reg_field
>> cfg_cmd_pkt_status; + struct reg_field
>> cfg_vid_mode_en; + struct reg_field cfg_vid_mode_type;
>> + struct reg_field cfg_vid_mode_low_power; +
>> struct reg_field cfg_vid_mode_vpg_en; + struct reg_field
>> cfg_vid_mode_vpg_horiz; + struct reg_field
>> cfg_vid_pkt_size; + struct reg_field cfg_vid_hsa_time;
>> + struct reg_field cfg_vid_hbp_time; + struct
>> reg_field cfg_vid_hline_time; + struct reg_field
>> cfg_vid_vsa_time; + struct reg_field cfg_vid_vbp_time;
>> + struct reg_field cfg_vid_vfp_time; + struct
>> reg_field cfg_vid_vactive_time; + struct reg_field
>> cfg_phy_txrequestclkhs; + struct reg_field
>> cfg_phy_bta_time; + struct reg_field
>> cfg_phy_max_rd_time; + struct reg_field
>> cfg_phy_lp2hs_time; + struct reg_field
>> cfg_phy_hs2lp_time; + struct reg_field
>> cfg_phy_max_rd_time_v131; + struct reg_field
>> cfg_phy_lp2hs_time_v131; + struct reg_field
>> cfg_phy_hs2lp_time_v131; + struct reg_field
>> cfg_phy_clklp2hs_time; + struct reg_field
>> cfg_phy_clkhs2lp_time; + struct reg_field
>> cfg_phy_testclr; + struct reg_field
>> cfg_phy_unshutdownz; + struct reg_field
>> cfg_phy_unrstz; + struct reg_field cfg_phy_enableclk;
>> + struct reg_field cfg_phy_forcepll; + struct
>> reg_field cfg_phy_nlanes; + struct reg_field
>> cfg_phy_stop_wait_time; + struct reg_field
>> cfg_phy_status; + struct reg_field cfg_pckhdl_cfg; +
>> struct reg_field cfg_hstx_timeout_counter; + struct
>> reg_field cfg_lprx_timeout_counter; + struct reg_field
>> cfg_int_stat0; + struct reg_field cfg_int_stat1; +
>> struct reg_field cfg_int_mask0; + struct reg_field
>> cfg_int_mask1; + struct reg_field cfg_gen_hdr; +
>> struct reg_field cfg_gen_payload; +}; + +static const
>> struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = { +
>> .cfg_dpi_color_coding =
>> REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3), +
>> .cfg_dpi_18loosely_en =
>> REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8), + .cfg_dpi_vid =
>> REG_FIELD(DSI_DPI_VCID, 0, 2), + .cfg_dpi_vsync_active_low
>> = REG_FIELD(DSI_DPI_CFG_POL, 1, 1), +
>> .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
>> + .cfg_cmd_mode_ack_rqst_en =
>> REG_FIELD(DSI_CMD_MODE_CFG, 1, 1), + .cfg_cmd_mode_all_lp_en =
>> REG_FIELD(DSI_CMD_MODE_CFG, 8, 24), + .cfg_cmd_mode_en =
>> REG_FIELD(DSI_MODE_CFG, 0, 31), + .cfg_cmd_pkt_status =
>> REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31), + .cfg_vid_mode_en =
>> REG_FIELD(DSI_MODE_CFG, 0, 31), + .cfg_vid_mode_type =
>> REG_FIELD(DSI_VID_MODE_CFG, 0, 1), + .cfg_vid_mode_low_power =
>> REG_FIELD(DSI_VID_MODE_CFG, 8, 13), +
>> .cfg_vid_mode_vpg_en =
>> REG_FIELD(DSI_VID_MODE_CFG, 16, 16), +
>> .cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24,
>> 24), + .cfg_vid_pkt_size =
>> REG_FIELD(DSI_VID_PKT_SIZE, 0, 10), + .cfg_vid_hsa_time
>> = REG_FIELD(DSI_VID_HSA_TIME, 0, 31), +
>> .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0,
>> 31), + .cfg_vid_hline_time =
>> REG_FIELD(DSI_VID_HLINE_TIME, 0, 31), + .cfg_vid_vsa_time
>> = REG_FIELD(DSI_VID_VSA_LINES, 0, 31), +
>> .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0,
>> 31), + .cfg_vid_vfp_time =
>> REG_FIELD(DSI_VID_VFP_LINES, 0, 31), +
>> .cfg_vid_vactive_time =
>> REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31), +
>> .cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0), +
>> .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
>> + .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG,
>> 0, 15), + .cfg_phy_lp2hs_time =
>> REG_FIELD(DSI_PHY_TMR_CFG, 16, 23), +
>> .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG,
>> 24, 31), + .cfg_phy_max_rd_time_v131 =
>> REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15), +
>> .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
>> + .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG,
>> 16, 31), + .cfg_phy_clklp2hs_time =
>> REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15), +
>> .cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG,
>> 16, 31), + .cfg_phy_testclr =
>> REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0), +
>> .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ, 0,
>> 0), + .cfg_phy_unrstz =
>> REG_FIELD(DSI_PHY_RSTZ, 1, 1), + .cfg_phy_enableclk =
>> REG_FIELD(DSI_PHY_RSTZ, 2, 2), + .cfg_phy_forcepll =
>> REG_FIELD(DSI_PHY_RSTZ, 3, 3), + .cfg_phy_nlanes =
>> REG_FIELD(DSI_PHY_IF_CFG, 0, 1), + .cfg_phy_stop_wait_time =
>> REG_FIELD(DSI_PHY_IF_CFG, 8, 15), + .cfg_phy_status =
>> REG_FIELD(DSI_PHY_STATUS, 0, 0), + .cfg_pckhdl_cfg =
>> REG_FIELD(DSI_PCKHDL_CFG, 0, 4), + .cfg_hstx_timeout_counter
>> = REG_FIELD(DSI_TO_CNT_CFG, 16, 31), +
>> .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
>> + .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0,
>> 31), + .cfg_int_stat1 =
>> REG_FIELD(DSI_INT_ST1, 0, 31), + .cfg_int_mask0 =
>> REG_FIELD(DSI_INT_MSK0, 0, 31), + .cfg_int_mask1 =
>> REG_FIELD(DSI_INT_MSK1, 0, 31), + .cfg_gen_hdr =
>> REG_FIELD(DSI_GEN_HDR, 0, 31), + .cfg_gen_payload =
>> REG_FIELD(DSI_GEN_PLD_DATA, 0, 31), +}; +
>> /*
>> * Check if either a link to a master or slave is present */
>> @@ -359,15 +459,22 @@ static void dw_mipi_message_config(struct
>> dw_mipi_dsi *dsi,
>> const struct mipi_dsi_msg *msg)
>> { bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
>> - u32 val = 0; + u32 cmd_mode_lp = 0; + + switch
>> (dsi->hw_version) { + case HWVER_130: + case
>> HWVER_131: + cmd_mode_lp = CMD_MODE_ALL_LP; +
>> break; + }
>> if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
>> - val |= ACK_RQST_EN; +
>> regmap_field_write(dsi->field_cmd_mode_ack_rqst_en, 1); +
>> if (lpm)
>> - val |= CMD_MODE_ALL_LP; +
>> regmap_field_write(dsi->field_cmd_mode_all_lp_en, cmd_mode_lp);
>>
>> - regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 :
>> PHY_TXREQUESTCLKHS); - regmap_write(dsi->regs,
>> DSI_CMD_MODE_CFG, val); +
>> regmap_field_write(dsi->field_phy_txrequestclkhs, lpm ? 0 : 1);
>> } static int dw_mipi_dsi_gen_pkt_hdr_write(struct
>> dw_mipi_dsi *dsi, u32 hdr_val)
>> @@ -375,18 +482,18 @@ static int
>> dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32
>> hdr_val)
>> int ret; u32 val = 0, mask;
>> - ret = regmap_read_poll_timeout(dsi->regs,
>> DSI_CMD_PKT_STATUS, -
>> val, !(val & GEN_CMD_FULL), 1000, -
>> CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status, +
>> val, !(val & GEN_CMD_FULL), +
>> 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) { dev_err(dsi->dev, "failed to get available
>> command FIFO\n"); return ret; }
>> - regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val); +
>> regmap_field_write(dsi->field_gen_hdr, hdr_val);
>> mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
>> - ret = regmap_read_poll_timeout(dsi->regs,
>> DSI_CMD_PKT_STATUS, + ret =
>> regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
>> val, (val & mask) == mask,
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); if (ret) {
>> @@ -409,20 +516,22 @@ static int dw_mipi_dsi_write(struct
>> dw_mipi_dsi *dsi,
>> if (len < pld_data_bytes) { word = 0;
>> memcpy(&word, tx_buf, len);
>> - regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
>> - le32_to_cpu(word)); +
>> regmap_field_write(dsi->field_gen_payload, +
>> le32_to_cpu(word));
>> len = 0; } else { memcpy(&word, tx_buf,
>> pld_data_bytes);
>> - regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
>> - le32_to_cpu(word)); +
>> regmap_field_write(dsi->field_gen_payload, +
>> le32_to_cpu(word));
>> tx_buf += pld_data_bytes; len -=
>> pld_data_bytes; }
>> - ret = regmap_read_poll_timeout(dsi->regs,
>> DSI_CMD_PKT_STATUS, -
>> val, !(val & GEN_PLD_W_FULL), -
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status, +
>> val, + !(val
>> & GEN_PLD_W_FULL), +
>> 1000, +
>> CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) { dev_err(dsi->dev, "failed to get
>> available write payload FIFO\n");
>> @@ -443,9 +552,9 @@ static int dw_mipi_dsi_read(struct
>> dw_mipi_dsi *dsi,
>> u32 val = 0; /* Wait end of the read operation */
>> - ret = regmap_read_poll_timeout(dsi->regs,
>> DSI_CMD_PKT_STATUS, -
>> val, !(val & GEN_RD_CMD_BUSY), -
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status, +
>> val, !(val & GEN_RD_CMD_BUSY), +
>> 1000, CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) { dev_err(dsi->dev, "Timeout during read
>> operation\n"); return ret;
>> @@ -453,15 +562,17 @@ static int dw_mipi_dsi_read(struct
>> dw_mipi_dsi *dsi,
>> for (i = 0; i < len; i += 4) { /* Read fifo must not be
>> empty before all bytes are read */
>> - ret = regmap_read_poll_timeout(dsi->regs,
>> DSI_CMD_PKT_STATUS, -
>> val, !(val & GEN_PLD_R_EMPTY), -
>> 1000, CMD_PKT_STATUS_TIMEOUT_US); + ret =
>> regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status, +
>> val, + !(val
>> & GEN_PLD_R_EMPTY), +
>> 1000, +
>> CMD_PKT_STATUS_TIMEOUT_US);
>> if (ret) { dev_err(dsi->dev, "Read payload FIFO is
>> empty\n"); return ret; }
>> - regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val); +
>> regmap_field_read(dsi->field_gen_payload, &val);
>> for (j = 0; j < 4 && j + i < len; j++) buf[i + j]
>> = val >> (8 * j); }
>> @@ -515,30 +626,30 @@ static const struct mipi_dsi_host_ops
>> dw_mipi_dsi_host_ops = {
>> static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi
>> *dsi) {
>> - u32 val; -
>> /* * TODO dw drv improvements * enabling low power is
>> panel-dependent, we should use the * panel configuration
>> here... */
>> - val = ENABLE_LOW_POWER; +
>> regmap_field_write(dsi->field_vid_mode_low_power,
>> ENABLE_LOW_POWER);
>> if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
>> - val |= VID_MODE_TYPE_BURST; +
>> regmap_field_write(dsi->field_vid_mode_type, +
>> VID_MODE_TYPE_BURST);
>> else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
>> - val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; +
>> regmap_field_write(dsi->field_vid_mode_type, +
>> VID_MODE_TYPE_NON_BURST_SYNC_PULSES);
>> else
>> - val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; +
>> regmap_field_write(dsi->field_vid_mode_type, +
>> VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
>> #ifdef CONFIG_DEBUG_FS if (dsi->vpg) {
>> - val |= VID_MODE_VPG_ENABLE; - val |=
>> dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0; +
>> regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_en, 1); +
>> regmap_field_write(dsi->regs, dsi->field_vid_mode_vpg_horiz, +
>> dsi->vpg_horizontal ? 1 : 0);
>> } #endif /* CONFIG_DEBUG_FS */
>> - - regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
>> } static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
>> @@ -547,11 +658,13 @@ static void dw_mipi_dsi_set_mode(struct
>> dw_mipi_dsi *dsi,
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET); if
>> (mode_flags & MIPI_DSI_MODE_VIDEO) {
>> - regmap_write(dsi->regs, DSI_MODE_CFG,
>> ENABLE_VIDEO_MODE); +
>> regmap_field_write(dsi->field_cmd_mode_en, 0); +
>> dw_mipi_dsi_video_mode_config(dsi);
>> - regmap_write(dsi->regs, DSI_LPCLK_CTRL,
>> PHY_TXREQUESTCLKHS); + +
>> regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
>> } else {
>> - regmap_write(dsi->regs, DSI_MODE_CFG,
>> ENABLE_CMD_MODE); +
>> regmap_field_write(dsi->field_cmd_mode_en, 1);
>> } regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
>> @@ -560,7 +673,7 @@ static void dw_mipi_dsi_set_mode(struct
>> dw_mipi_dsi *dsi,
>> static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) {
>> regmap_write(dsi->regs, DSI_PWR_UP, RESET);
>> - regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ); +
>> regmap_field_write(dsi->field_phy_unrstz, 0);
>> } static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
>> @@ -589,14 +702,15 @@ static void dw_mipi_dsi_init(struct
>> dw_mipi_dsi *dsi)
>> static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
>> const struct drm_display_mode *mode) {
>> - u32 val = 0, color = 0; + u32 color = 0;
>> switch (dsi->format) { case MIPI_DSI_FMT_RGB888: color =
>> DPI_COLOR_CODING_24BIT; break; case MIPI_DSI_FMT_RGB666:
>> - color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; +
>> color = DPI_COLOR_CODING_18BIT_2; +
>> regmap_field_write(dsi->field_dpi_18loosely_en, 1);
>> break; case MIPI_DSI_FMT_RGB666_PACKED: color =
>> DPI_COLOR_CODING_18BIT_1;
>> @@ -606,14 +720,15 @@ static void dw_mipi_dsi_dpi_config(struct
>> dw_mipi_dsi *dsi,
>> break; }
>> - if (mode->flags & DRM_MODE_FLAG_NVSYNC) -
>> val |= VSYNC_ACTIVE_LOW; - if (mode->flags &
>> DRM_MODE_FLAG_NHSYNC) - val |= HSYNC_ACTIVE_LOW; +
>> regmap_field_write(dsi->field_dpi_color_coding, color); + + if
>> (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) +
>> regmap_field_write(dsi->field_dpi_vsync_active_low, 1); + if
>> (!(mode->flags & DRM_MODE_FLAG_NHSYNC)) +
>> regmap_field_write(dsi->field_dpi_hsync_active_low, 1); + +
>> regmap_field_write(dsi->field_dpi_vid, DPI_VCID(dsi->channel));
>>
>> - regmap_write(dsi->regs, DSI_DPI_VCID,
>> DPI_VCID(dsi->channel)); - regmap_write(dsi->regs,
>> DSI_DPI_COLOR_CODING, color); - regmap_write(dsi->regs,
>> DSI_DPI_CFG_POL, val);
>> /* * TODO dw drv improvements * largest packet sizes
>> during hfp or during vsa/vpb/vfp
>> @@ -626,7 +741,8 @@ static void dw_mipi_dsi_dpi_config(struct
>> dw_mipi_dsi *dsi,
>> static void dw_mipi_dsi_packet_handler_config(struct
>> dw_mipi_dsi *dsi) {
>> - regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN |
>> ECC_RX_EN | BTA_EN); +
>> regmap_field_write(dsi->field_pckhdl_cfg, +
>> CRC_RX_EN | ECC_RX_EN | BTA_EN);
>> } static void dw_mipi_dsi_video_packet_config(struct
>> dw_mipi_dsi *dsi,
>> @@ -639,11 +755,9 @@ static void
>> dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
>> * DSI_VNPCR.NPSIZE... especially because this driver
>> supports * non-burst video modes, see
>> dw_mipi_dsi_video_mode_config()... */
>> - - regmap_write(dsi->regs, DSI_VID_PKT_SIZE, -
>> dw_mipi_is_dual_mode(dsi) ? -
>> VID_PKT_SIZE(mode->hdisplay / 2) : -
>> VID_PKT_SIZE(mode->hdisplay)); +
>> regmap_field_write(dsi->field_vid_pkt_size, +
>> dw_mipi_is_dual_mode(dsi) ? +
>> mode->hdisplay / 2 : mode->hdisplay);
>> } static void dw_mipi_dsi_command_mode_config(struct
>> dw_mipi_dsi *dsi)
>> @@ -653,15 +767,17 @@ static void
>> dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>> * compute high speed transmission counter timeout
>> according * to the timeout clock division (TO_CLK_DIVISION)
>> and byte lane... */
>> - regmap_write(dsi->regs, DSI_TO_CNT_CFG, -
>> HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); +
>> regmap_field_write(dsi->field_hstx_timeout_counter, 1000); +
>> regmap_field_write(dsi->field_lprx_timeout_counter, 1000); +
>> /* * TODO dw drv improvements * the Bus-Turn-Around
>> Timeout Counter should be computed * according to byte
>> lane... */
>> - regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00); -
>> regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE); +
>> regmap_field_write(dsi->field_phy_bta_time, 0xd00); + +
>> regmap_field_write(dsi->field_cmd_mode_en, 1);
>> } /* Get lane byte clock cycles. */
>> @@ -695,13 +811,13 @@ static void
>> dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
>> * computations below may be improved... */ lbcc =
>> dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
>> - regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc); +
>> regmap_field_write(dsi->field_vid_hline_time, lbcc);
>> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
>> - regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc); +
>> regmap_field_write(dsi->field_vid_hsa_time, lbcc);
>> lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
>> - regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc); +
>> regmap_field_write(dsi->field_vid_hbp_time, lbcc);
>> } static void dw_mipi_dsi_vertical_timing_config(struct
>> dw_mipi_dsi *dsi,
>> @@ -714,17 +830,16 @@ static void
>> dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
>> vfp = mode->vsync_start - mode->vdisplay; vbp =
>> mode->vtotal - mode->vsync_end;
>> - regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive); -
>> regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa); -
>> regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp); -
>> regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp); +
>> regmap_field_write(dsi->field_vid_vactive_time, vactive); +
>> regmap_field_write(dsi->field_vid_vsa_time, vsa); +
>> regmap_field_write(dsi->field_vid_vfp_time, vfp); +
>> regmap_field_write(dsi->field_vid_vbp_time, vbp);
>> } static void dw_mipi_dsi_dphy_timing_config(struct
>> dw_mipi_dsi *dsi) { const struct dw_mipi_dsi_phy_ops *phy_ops
>> = dsi->plat_data->phy_ops; struct dw_mipi_dsi_dphy_timing
>> timing;
>> - u32 hw_version;
>> int ret; ret =
>> phy_ops->get_timing(dsi->plat_data->priv_data,
>> @@ -739,26 +854,12 @@ static void
>> dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
>> * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line
>> with * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see
>> CMD_MODE_ALL_LP) */
>> + regmap_field_write(dsi->field_phy_lp2hs_time,
>> timing.data_lp2hs); +
>> regmap_field_write(dsi->field_phy_hs2lp_time,
>> timing.data_hs2lp);
>>
>> - regmap_read(dsi->regs, DSI_VERSION, &hw_version); -
>> hw_version &= VERSION; - - if (hw_version >= HWVER_131) { -
>> regmap_write(dsi->regs, DSI_PHY_TMR_CFG, -
>> PHY_HS2LP_TIME_V131(timing.data_hs2lp) | -
>> PHY_LP2HS_TIME_V131(timing.data_lp2hs)); -
>> regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG, -
>> MAX_RD_TIME_V131(10000)); - } else { -
>> regmap_write(dsi->regs, DSI_PHY_TMR_CFG, -
>> PHY_HS2LP_TIME(timing.data_hs2lp) | -
>> PHY_LP2HS_TIME(timing.data_lp2hs) | -
>> MAX_RD_TIME(10000)); - } - - regmap_write(dsi->regs,
>> DSI_PHY_TMR_LPCLK_CFG, -
>> PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | -
>> PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); +
>> regmap_field_write(dsi->field_phy_max_rd_time, 10000); +
>> regmap_field_write(dsi->field_phy_clkhs2lp_time,
>> timing.clk_hs2lp); +
>> regmap_field_write(dsi->field_phy_clklp2hs_time,
>> timing.clk_lp2hs);
>> } static void dw_mipi_dsi_dphy_interface_config(struct
>> dw_mipi_dsi *dsi)
>> @@ -768,18 +869,22 @@ static void
>> dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
>> * stop wait time should be the maximum between host dsi *
>> and panel stop wait times */
>> - regmap_write(dsi->regs, DSI_PHY_IF_CFG, -
>> PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes)); +
>> regmap_field_write(dsi->field_phy_stop_wait_time, 0x20); +
>> regmap_field_write(dsi->field_phy_nlanes, dsi->lanes - 1);
>> } static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
>> { /* Clear PHY state */
>> - regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL |
>> PHY_DISABLECLK - | PHY_RSTZ | PHY_SHUTDOWNZ);
>> - regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
>> - regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR); -
>> regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); +
>> regmap_field_write(dsi->field_phy_enableclk, 0); +
>> regmap_field_write(dsi->field_phy_unrstz, 0); +
>> regmap_field_write(dsi->field_phy_unshutdownz, 0); + +
>> regmap_field_write(dsi->field_phy_forcepll, 0); + +
>> regmap_field_write(dsi->field_phy_testclr, 0); +
>> regmap_field_write(dsi->field_phy_testclr, 1); +
>> regmap_field_write(dsi->field_phy_testclr, 0);
>> } static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi
>> *dsi)
>> @@ -787,18 +892,21 @@ static void
>> dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
>> u32 val = 0; int ret;
>> - regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL |
>> PHY_ENABLECLK | - PHY_UNRSTZ |
>> PHY_UNSHUTDOWNZ); +
>> regmap_field_write(dsi->field_phy_enableclk, 1); +
>> regmap_field_write(dsi->field_phy_unrstz, 1); +
>> regmap_field_write(dsi->field_phy_unshutdownz, 1); + +
>> regmap_field_write(dsi->field_phy_forcepll, 1);
>>
>> - ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
>> - val, val & PHY_LOCK, -
>> 1000, PHY_STATUS_TIMEOUT_US); + ret =
>> regmap_field_read_poll_timeout(dsi->field_phy_status, +
>> val, val & PHY_LOCK, +
>> 1000, PHY_STATUS_TIMEOUT_US);
>> if (ret) DRM_DEBUG_DRIVER("failed to wait phy lock
>> state\n");
>> - ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
>> - val, val &
>> PHY_STOP_STATE_CLK_LANE, 1000, -
>> PHY_STATUS_TIMEOUT_US); + ret =
>> regmap_field_read_poll_timeout(dsi->field_phy_status, +
>> val, val & PHY_STOP_STATE_CLK_LANE, +
>> 1000, PHY_STATUS_TIMEOUT_US);
>> if (ret) DRM_DEBUG_DRIVER("failed to wait phy clk lane
>> stop state\n"); }
>> @@ -807,10 +915,10 @@ static void dw_mipi_dsi_clear_err(struct
>> dw_mipi_dsi *dsi)
>> { u32 val;
>> - regmap_read(dsi->regs, DSI_INT_ST0, &val); -
>> regmap_read(dsi->regs, DSI_INT_ST1, &val); -
>> regmap_write(dsi->regs, DSI_INT_MSK0, 0); -
>> regmap_write(dsi->regs, DSI_INT_MSK1, 0); +
>> regmap_field_read(dsi->field_int_stat0, &val); +
>> regmap_field_read(dsi->field_int_stat1, &val); +
>> regmap_field_write(dsi->field_int_mask0, 0); +
>> regmap_field_write(dsi->field_int_mask1, 0);
>> } static void dw_mipi_dsi_bridge_post_disable(struct
>> drm_bridge *bridge)
>> @@ -1005,6 +1113,86 @@ static void
>> dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
>> dev_err(dsi->dev, "Failed to read DSI hw version
>> register\n"); }
>> +#define INIT_FIELD(f) INIT_FIELD_CFG(field_##f, cfg_##f)
>> +#define INIT_FIELD_CFG(f, conf)
>> \ + do {
>> \ + dsi->f = devm_regmap_field_alloc(dsi->dev,
>> dsi->regs, \ +
>> variant->conf); \ + if (IS_ERR(dsi->f))
>> \ + dev_warn(dsi->dev, "Ignoring regmap field
>> " #f "\n"); \ + } while (0)
>
> In kernel you can use gcc extension ({ ... }) instead "do {
> ... } while (0)" [1].
>
> [1]: https://gcc.gnu.org/onlinedocs/gcc/Statement-Exprs.html
Thanks, will do this in v6.
>
>> + +static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi
>> *dsi) +{ + const struct dw_mipi_dsi_variant *variant; + +
>> switch (dsi->hw_version) { + case HWVER_130: + case
>> HWVER_131: + variant = &dw_mipi_dsi_v130_v131_layout; +
>> break; + default: + DRM_ERROR("Unrecognized
>> DSI host controller HW revision\n"); + return
>> -ENODEV; + } + + INIT_FIELD(dpi_18loosely_en); +
>> INIT_FIELD(dpi_vid); + INIT_FIELD(dpi_color_coding); +
>> INIT_FIELD(dpi_vsync_active_low); +
>> INIT_FIELD(dpi_hsync_active_low); +
>> INIT_FIELD(cmd_mode_ack_rqst_en); +
>> INIT_FIELD(cmd_mode_all_lp_en); + INIT_FIELD(cmd_mode_en); +
>> INIT_FIELD(cmd_pkt_status); + INIT_FIELD(vid_mode_en); +
>> INIT_FIELD(vid_mode_type); + INIT_FIELD(vid_mode_low_power); +
>> INIT_FIELD(vid_pkt_size); + INIT_FIELD(vid_hsa_time); +
>> INIT_FIELD(vid_hbp_time); + INIT_FIELD(vid_hline_time); +
>> INIT_FIELD(vid_vsa_time); + INIT_FIELD(vid_vbp_time); +
>> INIT_FIELD(vid_vfp_time); + INIT_FIELD(vid_vactive_time); +
>> INIT_FIELD(phy_txrequestclkhs); + INIT_FIELD(phy_testclr); +
>> INIT_FIELD(phy_unshutdownz); + INIT_FIELD(phy_unrstz); +
>> INIT_FIELD(phy_enableclk); + INIT_FIELD(phy_nlanes); +
>> INIT_FIELD(phy_stop_wait_time); + INIT_FIELD(phy_status); +
>> INIT_FIELD(pckhdl_cfg); + INIT_FIELD(hstx_timeout_counter);
>> + INIT_FIELD(lprx_timeout_counter); +
>> INIT_FIELD(int_stat0); + INIT_FIELD(int_stat1); +
>> INIT_FIELD(int_mask0); + INIT_FIELD(int_mask1); +
>> INIT_FIELD(gen_hdr); + INIT_FIELD(gen_payload); +
>> INIT_FIELD(phy_bta_time); + INIT_FIELD(vid_mode_vpg_en); +
>> INIT_FIELD(vid_mode_vpg_horiz); +
>> INIT_FIELD(phy_clklp2hs_time); +
>> INIT_FIELD(phy_clkhs2lp_time); + INIT_FIELD(phy_forcepll);
>> + + if (dsi->hw_version == HWVER_131) { +
>> INIT_FIELD_CFG(field_phy_max_rd_time,
>> cfg_phy_max_rd_time_v131); +
>> INIT_FIELD_CFG(field_phy_lp2hs_time, cfg_phy_lp2hs_time_v131);
>> + INIT_FIELD_CFG(field_phy_hs2lp_time,
>> cfg_phy_hs2lp_time_v131); + } else { +
>> INIT_FIELD(phy_max_rd_time); +
>> INIT_FIELD(phy_lp2hs_time); +
>> INIT_FIELD(phy_hs2lp_time); + }
>
> And here we have devres storm - for every field we allocate
> memory, enqueue deallocator, copy static values to dynamic
> struct and more.
>
> I know that CPU power and memory are cheap, but this hurts my
> eyes :)
We do this only once when loading the bridge and fields are cheap
so this is not as big a disadvantage as the other good point you
raised :)
>
> Other thing is that this complicates the driver - adding new
> field will require changes at least in 4 (?) places, without
> counting real field usage.
>
> And here is very simple alternative how different hw register
> layout can be coded without much ado: [1][2].
>
> [1]:
> https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/exynos/exynos_hdmi.c#L55
>
> [2]:
> https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/exynos/exynos_hdmi.c#L667
>
> To be clear, I am not totally against this approach - the patch
> seems to me correct, it is just 'baroque' :) If you can show
> that approach from [1] and [2] in this case will be more
> problematic we can go your way.
>
> Anyway more comments appreciated.
It is true, regmap fields are a bit more verbose than just mapping
enums, however please consider that verbosity has its advantages
especially when it helps avoid cryptic bit manipulations on
changing register layouts.
This is made apparent in v6 which I will post soon where I took
some time to go through NXP, STM and Rockchip documentations and
fix bad read/writes in reserved register spaces. You can get a
glimpse of that change here [1].
Regmap fields make it much easier to take the reference manuals
and compare them to what drivers do because fields are explicitely
defined and more verbose by design.
Also it's not like the verbosity is increased by big amounts, at
[2] you can find another commit I made for v6 which does a field
conversion.
To cut the story short, I think the trade-off is worth it.
I'm holding off on posting v6 because I got some testing done on
STM stm32mp1 and stm32f7 which revealed a low-power-mgmt bug which
I'm not sure yet if is related to the patch series or not.
P.S. If we really have to resort to name-calling then I'd call
"baroque" computing cryptic bit-manipulations and mapping enums as
opposed to using a clearer albeit more verbose regmap
infrastructure. :)
[1]
https://gitlab.collabora.com/aratiu/linux-public/-/commit/f36774373118ef0c1785acb533c824b8355e1e43
[2]
https://gitlab.collabora.com/aratiu/linux-public/-/commit/0f8026412822b3a1842702f18eb9f3d0cd115f67
>
>
> Regards
>
> Andrzej
>
>
>> +
>> + return 0;
>> +}
>> +
>> static struct dw_mipi_dsi *
>> __dw_mipi_dsi_probe(struct platform_device *pdev,
>> const struct dw_mipi_dsi_plat_data *plat_data)
>> @@ -1081,6 +1269,12 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
>>
>> dw_mipi_dsi_get_hw_version(dsi);
>>
>> + ret = dw_mipi_dsi_regmap_fields_init(dsi);
>> + if (ret) {
>> + dev_err(dev, "Failed to init register layout map: %d\n", ret);
>> + return ERR_PTR(ret);
>> + }
>> +
>> dw_mipi_dsi_debugfs_init(dsi);
>> pm_runtime_enable(dev);
>>