Good Morning,
This series aims to fix some early issues with the rk356x and enable
nodes that are currently supported by the available drivers.
1. increases the max clocks in the dt-bindings to permit patch 3.
2. fixes the mbi-alias, which points to the wrong location
3. adds the gpio debounce clocks which are necessary for gpio to bind
4. adds the common gmac1 node
5. adds the tsadc nodes
6. adds the missing cru and pmucru phandles necessary to reclock
7. adjusts the gpll and ppll clocks to better support hardware
8. enables the gmac1 on the Quartz64
9. adds thermal support to the Quartz64
Peter Geis (9):
dt-bindings: gpio: rockchip,gpio-bank: increase max clocks
arm64: dts: rockchip: fix rk3568 mbi-alias
arm64: dts: rockchip: add rk356x gpio debounce clocks
arm64: dts: rockchip: add rk356x gmac1 node
arm64: dts: rockchip: add rk3568 tsadc nodes
arm64: dts: rockchip: add missing rk3568 cru phandles
arm64: dts: rockchip: adjust rk3568 pll clocks
arm64: dts: rockchip: enable gmac node on quartz64-a
arm64: dts: rockchip: add thermal support to Quartz64 Model A
.../bindings/gpio/rockchip,gpio-bank.yaml | 2 +-
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 66 +++++++++
.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 +
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 136 +++++++++++++++++-
4 files changed, 203 insertions(+), 7 deletions(-)
--
2.25.1
The rk356x adds a debounce clock to the gpio devices.
Increase the maximum clocks to account for it.
Signed-off-by: Peter Geis <[email protected]>
---
Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
index d993e002cebe..489a5263a7a1 100644
--- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
+++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
@@ -22,7 +22,7 @@ properties:
maxItems: 1
clocks:
- maxItems: 1
+ maxItems: 2
gpio-controller: true
--
2.25.1
The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
These are set incorrectly by the bootloader, so fix them here.
Signed-off-by: Peter Geis <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 8ba0516eedd8..91ae3c541c1a 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,8 @@ cru: clock-controller@fdd20000 {
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
+ assigned-clock-rates = <1200000000>, <200000000>;
};
i2c0: i2c@fdd40000 {
--
2.25.1
The rk356x added a debounce clock to the gpio devices. This clock is
necessary for the new v2 gpio driver to bind.
Add the clocks to the rk356x device tree.
Signed-off-by: Peter Geis <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index f7ecdfd66f86..c2aa7aeec58d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -750,7 +750,7 @@ gpio0: gpio@fdd60000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfdd60000 0x0 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmucru PCLK_GPIO0>;
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -761,7 +761,7 @@ gpio1: gpio@fe740000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe740000 0x0 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO1>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -772,7 +772,7 @@ gpio2: gpio@fe750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe750000 0x0 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO2>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -783,7 +783,7 @@ gpio3: gpio@fe760000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe760000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO3>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -794,7 +794,7 @@ gpio4: gpio@fe770000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe770000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_GPIO4>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.25.1
The mbi-alias incorrectly points to 0xfd100000 when it should point to
0xfd410000.
This fixes MSIs on rk3568.
Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568
SoC")
Signed-off-by: Peter Geis <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 322971318d5a..f7ecdfd66f86 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -195,7 +195,7 @@ gic: interrupt-controller@fd400000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
- mbi-alias = <0x0 0xfd100000>;
+ mbi-alias = <0x0 0xfd410000>;
mbi-ranges = <296 24>;
msi-controller;
};
--
2.25.1
Add the thermal nodes for the Quartz64 Model A.
The Model A supports a single speed gpio fan.
Signed-off-by: Peter Geis <[email protected]>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 90cdabfac86b..eb311ea19f6a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -26,6 +26,14 @@ gmac1_clkin: external-gmac1-clock {
#clock-cells = <0>;
};
+ fan: gpio_fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = <0 0
+ 4500 1>;
+ #cooling-cells = <2>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -123,6 +131,23 @@ &cpu3 {
cpu-supply = <&vdd_cpu>;
};
+&cpu_thermal {
+ trips {
+ cpu_hot: cpu_hot {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map1 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
@@ -432,6 +457,10 @@ &sdmmc0 {
status = "okay";
};
+&tsadc {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
--
2.25.1
Add the gmac1 controller to the rk356x device tree.
This is the controller common to both the rk3568 and rk3566.
Signed-off-by: Peter Geis <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 48 ++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index c2aa7aeec58d..77c679304916 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -18,6 +18,7 @@ / {
#size-cells = <2>;
aliases {
+ ethernet1 = &gmac1;
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
@@ -344,6 +345,53 @@ sdmmc2: mmc@fe000000 {
status = "disabled";
};
+ gmac1: ethernet@fe010000 {
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xfe010000 0x0 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
+ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_refout",
+ "aclk_mac", "pclk_mac",
+ "clk_mac_speed", "ptp_ref";
+ resets = <&cru SRST_A_GMAC1>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ snps,mixed-burst;
+ snps,tso;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
qos_gpu: qos@fe128000 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe128000 0x0 0x20>;
--
2.25.1
Add the thermal and tsadc nodes to the rk3568 device tree.
There are two sensors, one for the cpu, one for the gpu.
Signed-off-by: Peter Geis <[email protected]>
---
.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
index a588ca95ace2..b464c7bda1f7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
@@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 {
};
tsadc {
+ /omit-if-no-ref/
+ tsadc_gpio: tsadc-gpio {
+ rockchip,pins =
+ <0 RK_PA1 0 &pcfg_pull_none>;
+ };
+
/omit-if-no-ref/
tsadcm0_shut: tsadcm0-shut {
rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 77c679304916..0905fac0726a 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -51,6 +51,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&scmi_clk 0>;
+ #cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
@@ -59,6 +60,7 @@ cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
+ #cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
@@ -67,6 +69,7 @@ cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
+ #cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
@@ -75,6 +78,7 @@ cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
+ #cooling-cells = <2>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
@@ -774,6 +778,73 @@ uart9: serial@fe6d0000 {
status = "disabled";
};
+ thermal_zones: thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 1>;
+ };
+ };
+
+ tsadc: tsadc@fe710000 {
+ compatible = "rockchip,rk3568-tsadc";
+ reg = <0x0 0xfe710000 0x0 0x100>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
+ assigned-clock-rates = <17000000>, <700000>;
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
+ <&cru SRST_TSADCPHY>;
+ reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
+ rockchip,grf = <&grf>;
+ rockchip,hw-tshut-temp = <95000>;
+ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+ pinctrl-names = "gpio", "otpout";
+ pinctrl-0 = <&tsadc_gpio>;
+ pinctrl-1 = <&tsadc_shutorg>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
saradc: saradc@fe720000 {
compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xfe720000 0x0 0x100>;
--
2.25.1
The grf and pmugrf phandles are necessary for the pmucru and cru to
modify clocks. Add these phandles to permit adjusting the clock rates
and muxes.
Signed-off-by: Peter Geis <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 0905fac0726a..8ba0516eedd8 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ rockchip,pmugrf = <&pmugrf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
cru: clock-controller@fdd20000 {
compatible = "rockchip,rk3568-cru";
reg = <0x0 0xfdd20000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.25.1
Enable the gmac controller on the Pine64 Quartz64 Model A.
Signed-off-by: Peter Geis <[email protected]>
---
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index a3cdb6c2bec6..90cdabfac86b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -19,6 +19,13 @@ chosen: chosen {
stdout-path = "serial2:1500000n8";
};
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
leds {
compatible = "gpio-leds";
@@ -116,6 +123,29 @@ &cpu3 {
cpu-supply = <&vdd_cpu>;
};
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_3v3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
@@ -336,6 +366,13 @@ regulator-state-mem {
};
};
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&pinctrl {
bt {
bt_enable_h: bt-enable-h {
--
2.25.1
Hi Peter,
Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> The grf and pmugrf phandles are necessary for the pmucru and cru to
> modify clocks. Add these phandles to permit adjusting the clock rates
> and muxes.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 0905fac0726a..8ba0516eedd8 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> pmucru: clock-controller@fdd00000 {
> compatible = "rockchip,rk3568-pmucru";
> reg = <0x0 0xfdd00000 0x0 0x1000>;
> + rockchip,grf = <&grf>;
> + rockchip,pmugrf = <&pmugrf>;
I don't think the pmucru needs both and in fact the mainline
clock driver should just reference its specific grf at all, i.e.
pmucru -> pmugrf (via the rockchip,grf handle)
cru -> grf
I've not seen anything breaking this scope so far.
Heiko
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
> @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> cru: clock-controller@fdd20000 {
> compatible = "rockchip,rk3568-cru";
> reg = <0x0 0xfdd20000 0x0 0x1000>;
> + rockchip,grf = <&grf>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
>
Hi Peter,
Am Mittwoch, 28. Juli 2021, 15:55:32 CEST schrieb Peter Geis:
> The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
> These are set incorrectly by the bootloader, so fix them here.
Can you specify where the "should run at" comes from?
Normally I'd assume setting desired PLL frequencies would be quite
board-specific.
So if we're setting defaults for all boards, I'd like some reasoning
behind that ;-) ... especially when the other option would be to
fix the bootloader.
Thanks
Heiko
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 8ba0516eedd8..91ae3c541c1a 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -230,6 +230,8 @@ cru: clock-controller@fdd20000 {
> rockchip,grf = <&grf>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
> + assigned-clock-rates = <1200000000>, <200000000>;
> };
>
> i2c0: i2c@fdd40000 {
>
Hi Peter,
Am Mittwoch, 28. Juli 2021, 15:55:26 CEST schrieb Peter Geis:
> The rk356x adds a debounce clock to the gpio devices.
> Increase the maximum clocks to account for it.
>
> Signed-off-by: Peter Geis <[email protected]>
that binding change is also part of Jianqun's gpio driver series,
also adds clock descriptions for both and even got an Ack from Rob
already, so we should be going with that other variant ;-)
Heiko
> ---
> Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> index d993e002cebe..489a5263a7a1 100644
> --- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> @@ -22,7 +22,7 @@ properties:
> maxItems: 1
>
> clocks:
> - maxItems: 1
> + maxItems: 2
>
> gpio-controller: true
>
>
On Wed, Jul 28, 2021 at 10:06 AM Heiko Stübner <[email protected]> wrote:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> > The grf and pmugrf phandles are necessary for the pmucru and cru to
> > modify clocks. Add these phandles to permit adjusting the clock rates
> > and muxes.
> >
> > Signed-off-by: Peter Geis <[email protected]>
> > ---
> > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 0905fac0726a..8ba0516eedd8 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> > pmucru: clock-controller@fdd00000 {
> > compatible = "rockchip,rk3568-pmucru";
> > reg = <0x0 0xfdd00000 0x0 0x1000>;
> > + rockchip,grf = <&grf>;
> > + rockchip,pmugrf = <&pmugrf>;
>
> I don't think the pmucru needs both and in fact the mainline
> clock driver should just reference its specific grf at all, i.e.
> pmucru -> pmugrf (via the rockchip,grf handle)
> cru -> grf
>
> I've not seen anything breaking this scope so far.
I thought the same thing as well, but for some reason the driver
refuses to apply assigned-clocks to the plls unless these are all
present.
If the driver can get these assignments automatically eventually,
perhaps it's a loading order issue?
Thinking about it, it's probably the grf and pmugrf haven't probed
when the driver is attempting to assign these, and tying them together
forces the probe to happen first.
>
>
> Heiko
>
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > };
> > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> > cru: clock-controller@fdd20000 {
> > compatible = "rockchip,rk3568-cru";
> > reg = <0x0 0xfdd20000 0x0 0x1000>;
> > + rockchip,grf = <&grf>;
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > };
> >
>
>
>
>
Hi Peter,
Am Mittwoch, 28. Juli 2021, 15:55:29 CEST schrieb Peter Geis:
> Add the gmac1 controller to the rk356x device tree.
> This is the controller common to both the rk3568 and rk3566.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 48 ++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index c2aa7aeec58d..77c679304916 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -18,6 +18,7 @@ / {
> #size-cells = <2>;
>
> aliases {
> + ethernet1 = &gmac1;
> gpio0 = &gpio0;
> gpio1 = &gpio1;
> gpio2 = &gpio2;
Looking back at the discussion about mmc aliases in board-dts vs. soc-dtsi
I get the feeling the ethernet alias would be same case, as not all boards
will expose ethernet.
In the very least the ethernet alias should be part of the rk3566/rk3568 dtsi
files, doing ethernet0 = &gmac1 for rk3566 and ethernet1 = &gmac1 for rk3568.
But I do think the board-dts would be the more appropriate place.
Heiko
> @@ -344,6 +345,53 @@ sdmmc2: mmc@fe000000 {
> status = "disabled";
> };
>
> + gmac1: ethernet@fe010000 {
> + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
> + reg = <0x0 0xfe010000 0x0 0x10000>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq", "eth_wake_irq";
> + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
> + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
> + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
> + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
> + clock-names = "stmmaceth", "mac_clk_rx",
> + "mac_clk_tx", "clk_mac_refout",
> + "aclk_mac", "pclk_mac",
> + "clk_mac_speed", "ptp_ref";
> + resets = <&cru SRST_A_GMAC1>;
> + reset-names = "stmmaceth";
> + rockchip,grf = <&grf>;
> + snps,mixed-burst;
> + snps,tso;
> + snps,axi-config = <&gmac1_stmmac_axi_setup>;
> + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
> + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
> + status = "disabled";
> +
> + mdio1: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + };
> +
> + gmac1_stmmac_axi_setup: stmmac-axi-config {
> + snps,wr_osr_lmt = <4>;
> + snps,rd_osr_lmt = <8>;
> + snps,blen = <0 0 0 0 16 8 4>;
> + };
> +
> + gmac1_mtl_rx_setup: rx-queues-config {
> + snps,rx-queues-to-use = <1>;
> + queue0 {};
> + };
> +
> + gmac1_mtl_tx_setup: tx-queues-config {
> + snps,tx-queues-to-use = <1>;
> + queue0 {};
> + };
> + };
> +
> qos_gpu: qos@fe128000 {
> compatible = "rockchip,rk3568-qos", "syscon";
> reg = <0x0 0xfe128000 0x0 0x20>;
>
On Wed, Jul 28, 2021 at 10:09 AM Heiko Stübner <[email protected]> wrote:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:32 CEST schrieb Peter Geis:
> > The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
> > These are set incorrectly by the bootloader, so fix them here.
>
> Can you specify where the "should run at" comes from?
> Normally I'd assume setting desired PLL frequencies would be quite
> board-specific.
gpll boots at 1188mhz, but to get accurate dividers for all
gpll_dividers it needs to run
at 1200mhz, otherwise everyone downstream isn't quite right.
ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is
required to reach a 100mhz clock input for them.
Downstream also makes this fix.
rk356x has a number of dividers that produce expected clock values for
various peripherals, so changing the defaults would mean reclocking a
number of child dividers.
>
> So if we're setting defaults for all boards, I'd like some reasoning
> behind that ;-) ... especially when the other option would be to
> fix the bootloader.
Currently we are forced to use downstream u-boot (mainline isn't ready yet).
Downstream doesn't seem to want to assign clocks correctly, so the
simplest method right now is to have the kernel ensure they are
correct.
>
> Thanks
> Heiko
>
> >
> > Signed-off-by: Peter Geis <[email protected]>
> > ---
> > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 8ba0516eedd8..91ae3c541c1a 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -230,6 +230,8 @@ cru: clock-controller@fdd20000 {
> > rockchip,grf = <&grf>;
> > #clock-cells = <1>;
> > #reset-cells = <1>;
> > + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
> > + assigned-clock-rates = <1200000000>, <200000000>;
> > };
> >
> > i2c0: i2c@fdd40000 {
> >
>
>
>
>
On Wed, Jul 28, 2021 at 10:21 AM Heiko Stübner <[email protected]> wrote:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:29 CEST schrieb Peter Geis:
> > Add the gmac1 controller to the rk356x device tree.
> > This is the controller common to both the rk3568 and rk3566.
> >
> > Signed-off-by: Peter Geis <[email protected]>
> > ---
> > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 48 ++++++++++++++++++++++++
> > 1 file changed, 48 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index c2aa7aeec58d..77c679304916 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -18,6 +18,7 @@ / {
> > #size-cells = <2>;
> >
> > aliases {
> > + ethernet1 = &gmac1;
> > gpio0 = &gpio0;
> > gpio1 = &gpio1;
> > gpio2 = &gpio2;
>
> Looking back at the discussion about mmc aliases in board-dts vs. soc-dtsi
> I get the feeling the ethernet alias would be same case, as not all boards
> will expose ethernet.
>
> In the very least the ethernet alias should be part of the rk3566/rk3568 dtsi
> files, doing ethernet0 = &gmac1 for rk3566 and ethernet1 = &gmac1 for rk3568.
>
> But I do think the board-dts would be the more appropriate place.
Okay, that makes sense, I'll move this to the board.
In regards to the 0 vs 1, this was to avoid issues with downstream
u-boot/rkbin which treats the rk3566 as a rk3568.
Currently it doesn't seem to affect anything in the way the kernel
probes it, as it still shows up as eth0.
>
>
> Heiko
>
> > @@ -344,6 +345,53 @@ sdmmc2: mmc@fe000000 {
> > status = "disabled";
> > };
> >
> > + gmac1: ethernet@fe010000 {
> > + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
> > + reg = <0x0 0xfe010000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq", "eth_wake_irq";
> > + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
> > + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
> > + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
> > + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
> > + clock-names = "stmmaceth", "mac_clk_rx",
> > + "mac_clk_tx", "clk_mac_refout",
> > + "aclk_mac", "pclk_mac",
> > + "clk_mac_speed", "ptp_ref";
> > + resets = <&cru SRST_A_GMAC1>;
> > + reset-names = "stmmaceth";
> > + rockchip,grf = <&grf>;
> > + snps,mixed-burst;
> > + snps,tso;
> > + snps,axi-config = <&gmac1_stmmac_axi_setup>;
> > + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
> > + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
> > + status = "disabled";
> > +
> > + mdio1: mdio {
> > + compatible = "snps,dwmac-mdio";
> > + #address-cells = <0x1>;
> > + #size-cells = <0x0>;
> > + };
> > +
> > + gmac1_stmmac_axi_setup: stmmac-axi-config {
> > + snps,wr_osr_lmt = <4>;
> > + snps,rd_osr_lmt = <8>;
> > + snps,blen = <0 0 0 0 16 8 4>;
> > + };
> > +
> > + gmac1_mtl_rx_setup: rx-queues-config {
> > + snps,rx-queues-to-use = <1>;
> > + queue0 {};
> > + };
> > +
> > + gmac1_mtl_tx_setup: tx-queues-config {
> > + snps,tx-queues-to-use = <1>;
> > + queue0 {};
> > + };
> > + };
> > +
> > qos_gpu: qos@fe128000 {
> > compatible = "rockchip,rk3568-qos", "syscon";
> > reg = <0x0 0xfe128000 0x0 0x20>;
> >
>
>
>
>
Am Mittwoch, 28. Juli 2021, 16:18:49 CEST schrieb Peter Geis:
> On Wed, Jul 28, 2021 at 10:06 AM Heiko St?bner <[email protected]> wrote:
> >
> > Hi Peter,
> >
> > Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> > > The grf and pmugrf phandles are necessary for the pmucru and cru to
> > > modify clocks. Add these phandles to permit adjusting the clock rates
> > > and muxes.
> > >
> > > Signed-off-by: Peter Geis <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > index 0905fac0726a..8ba0516eedd8 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> > > pmucru: clock-controller@fdd00000 {
> > > compatible = "rockchip,rk3568-pmucru";
> > > reg = <0x0 0xfdd00000 0x0 0x1000>;
> > > + rockchip,grf = <&grf>;
> > > + rockchip,pmugrf = <&pmugrf>;
> >
> > I don't think the pmucru needs both and in fact the mainline
> > clock driver should just reference its specific grf at all, i.e.
> > pmucru -> pmugrf (via the rockchip,grf handle)
> > cru -> grf
> >
> > I've not seen anything breaking this scope so far.
>
> I thought the same thing as well, but for some reason the driver
> refuses to apply assigned-clocks to the plls unless these are all
> present.
> If the driver can get these assignments automatically eventually,
> perhaps it's a loading order issue?
>
> Thinking about it, it's probably the grf and pmugrf haven't probed
> when the driver is attempting to assign these, and tying them together
> forces the probe to happen first.
though nothing references the regular grf from the pmucru I think.
I.e. the pmucru PLL read their lock state from RK3568_PMU_MODE_CON
The rk3568 reuses the pll_rk3328-type which in turn is a modified pll_rk3036
and uses their ops. Which in turn means the pll shouldn't access the GRF at
all, as it uses the pll's own register to check the locked state.
Can you try to change clk-pll.c from
switch (pll_type) {
case pll_rk3036:
case pll_rk3328:
if (!pll->rate_table || IS_ERR(ctx->grf))
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
...
to
switch (pll_type) {
case pll_rk3036:
case pll_rk3328:
if (!pll->rate_table)
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
similar to rk3399?
Heiko
> > > #clock-cells = <1>;
> > > #reset-cells = <1>;
> > > };
> > > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> > > cru: clock-controller@fdd20000 {
> > > compatible = "rockchip,rk3568-cru";
> > > reg = <0x0 0xfdd20000 0x0 0x1000>;
> > > + rockchip,grf = <&grf>;
> > > #clock-cells = <1>;
> > > #reset-cells = <1>;
> > > };
> > >
> >
> >
> >
> >
>
Am Mittwoch, 28. Juli 2021, 15:55:30 CEST schrieb Peter Geis:
> Add the thermal and tsadc nodes to the rk3568 device tree.
> There are two sensors, one for the cpu, one for the gpu.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++
> 2 files changed, 77 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> index a588ca95ace2..b464c7bda1f7 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 {
> };
>
> tsadc {
> + /omit-if-no-ref/
> + tsadc_gpio: tsadc-gpio {
> + rockchip,pins =
> + <0 RK_PA1 0 &pcfg_pull_none>;
> + };
> +
> /omit-if-no-ref/
> tsadcm0_shut: tsadcm0-shut {
> rockchip,pins =
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 77c679304916..0905fac0726a 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -51,6 +51,7 @@ cpu0: cpu@0 {
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> clocks = <&scmi_clk 0>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -59,6 +60,7 @@ cpu1: cpu@100 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x100>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -67,6 +69,7 @@ cpu2: cpu@200 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x200>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -75,6 +78,7 @@ cpu3: cpu@300 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x300>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 {
> status = "disabled";
> };
>
> + thermal_zones: thermal-zones {
> + cpu_thermal: cpu-thermal {
> + polling-delay-passive = <100>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsadc 0>;
> +
> + trips {
> + cpu_alert0: cpu_alert0 {
> + temperature = <70000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu_alert1: cpu_alert1 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu_crit: cpu_crit {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert0>;
> + cooling-device =
> + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu_thermal: gpu-thermal {
> + polling-delay-passive = <20>; /* milliseconds */
> + polling-delay = <1000>; /* milliseconds */
> +
> + thermal-sensors = <&tsadc 1>;
> + };
> + };
> +
> + tsadc: tsadc@fe710000 {
> + compatible = "rockchip,rk3568-tsadc";
> + reg = <0x0 0xfe710000 0x0 0x100>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
> + assigned-clock-rates = <17000000>, <700000>;
> + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
> + clock-names = "tsadc", "apb_pclk";
> + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
> + <&cru SRST_TSADCPHY>;
> + reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
> + rockchip,grf = <&grf>;
> + rockchip,hw-tshut-temp = <95000>;
> + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
> + pinctrl-names = "gpio", "otpout";
> + pinctrl-0 = <&tsadc_gpio>;
> + pinctrl-1 = <&tsadc_shutorg>;
The mainline thermal driver doesn't specify these pinctrl states at all.
Heiko
> + #thermal-sensor-cells = <1>;
> + status = "disabled";
> + };
> +
> saradc: saradc@fe720000 {
> compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
> reg = <0x0 0xfe720000 0x0 0x100>;
>
On Wed, Jul 28, 2021 at 10:46 AM Heiko Stübner <[email protected]> wrote:
>
> Am Mittwoch, 28. Juli 2021, 15:55:30 CEST schrieb Peter Geis:
> > Add the thermal and tsadc nodes to the rk3568 device tree.
> > There are two sensors, one for the cpu, one for the gpu.
> >
> > Signed-off-by: Peter Geis <[email protected]>
> > ---
> > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++
> > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++
> > 2 files changed, 77 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > index a588ca95ace2..b464c7bda1f7 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 {
> > };
> >
> > tsadc {
> > + /omit-if-no-ref/
> > + tsadc_gpio: tsadc-gpio {
> > + rockchip,pins =
> > + <0 RK_PA1 0 &pcfg_pull_none>;
> > + };
> > +
> > /omit-if-no-ref/
> > tsadcm0_shut: tsadcm0-shut {
> > rockchip,pins =
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 77c679304916..0905fac0726a 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -51,6 +51,7 @@ cpu0: cpu@0 {
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x0>;
> > clocks = <&scmi_clk 0>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -59,6 +60,7 @@ cpu1: cpu@100 {
> > device_type = "cpu";
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x100>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -67,6 +69,7 @@ cpu2: cpu@200 {
> > device_type = "cpu";
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x200>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -75,6 +78,7 @@ cpu3: cpu@300 {
> > device_type = "cpu";
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x300>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 {
> > status = "disabled";
> > };
> >
> > + thermal_zones: thermal-zones {
> > + cpu_thermal: cpu-thermal {
> > + polling-delay-passive = <100>;
> > + polling-delay = <1000>;
> > +
> > + thermal-sensors = <&tsadc 0>;
> > +
> > + trips {
> > + cpu_alert0: cpu_alert0 {
> > + temperature = <70000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > + cpu_alert1: cpu_alert1 {
> > + temperature = <75000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > + cpu_crit: cpu_crit {
> > + temperature = <95000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> > +
> > + cooling-maps {
> > + map0 {
> > + trip = <&cpu_alert0>;
> > + cooling-device =
> > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + };
> > + };
> > +
> > + gpu_thermal: gpu-thermal {
> > + polling-delay-passive = <20>; /* milliseconds */
> > + polling-delay = <1000>; /* milliseconds */
> > +
> > + thermal-sensors = <&tsadc 1>;
> > + };
> > + };
> > +
> > + tsadc: tsadc@fe710000 {
> > + compatible = "rockchip,rk3568-tsadc";
> > + reg = <0x0 0xfe710000 0x0 0x100>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
> > + assigned-clock-rates = <17000000>, <700000>;
> > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
> > + clock-names = "tsadc", "apb_pclk";
> > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
> > + <&cru SRST_TSADCPHY>;
> > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
> > + rockchip,grf = <&grf>;
> > + rockchip,hw-tshut-temp = <95000>;
> > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
> > + pinctrl-names = "gpio", "otpout";
> > + pinctrl-0 = <&tsadc_gpio>;
> > + pinctrl-1 = <&tsadc_shutorg>;
>
> The mainline thermal driver doesn't specify these pinctrl states at all.
>
> Heiko
Oh, yes this seems to be the case.
Is this something that should get fixed?
In practice it likely won't ever cause problems, but in theory if
someone changed the pinmux mode it could break it.
>
> > + #thermal-sensor-cells = <1>;
> > + status = "disabled";
> > + };
> > +
> > saradc: saradc@fe720000 {
> > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
> > reg = <0x0 0xfe720000 0x0 0x100>;
> >
>
>
>
>
On Wed, Jul 28, 2021 at 10:41 AM Heiko Stübner <[email protected]> wrote:
>
> Am Mittwoch, 28. Juli 2021, 16:18:49 CEST schrieb Peter Geis:
> > On Wed, Jul 28, 2021 at 10:06 AM Heiko Stübner <[email protected]> wrote:
> > >
> > > Hi Peter,
> > >
> > > Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> > > > The grf and pmugrf phandles are necessary for the pmucru and cru to
> > > > modify clocks. Add these phandles to permit adjusting the clock rates
> > > > and muxes.
> > > >
> > > > Signed-off-by: Peter Geis <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> > > > 1 file changed, 3 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > index 0905fac0726a..8ba0516eedd8 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> > > > pmucru: clock-controller@fdd00000 {
> > > > compatible = "rockchip,rk3568-pmucru";
> > > > reg = <0x0 0xfdd00000 0x0 0x1000>;
> > > > + rockchip,grf = <&grf>;
> > > > + rockchip,pmugrf = <&pmugrf>;
> > >
> > > I don't think the pmucru needs both and in fact the mainline
> > > clock driver should just reference its specific grf at all, i.e.
> > > pmucru -> pmugrf (via the rockchip,grf handle)
> > > cru -> grf
> > >
> > > I've not seen anything breaking this scope so far.
> >
> > I thought the same thing as well, but for some reason the driver
> > refuses to apply assigned-clocks to the plls unless these are all
> > present.
> > If the driver can get these assignments automatically eventually,
> > perhaps it's a loading order issue?
> >
> > Thinking about it, it's probably the grf and pmugrf haven't probed
> > when the driver is attempting to assign these, and tying them together
> > forces the probe to happen first.
>
> though nothing references the regular grf from the pmucru I think.
>
> I.e. the pmucru PLL read their lock state from RK3568_PMU_MODE_CON
>
> The rk3568 reuses the pll_rk3328-type which in turn is a modified pll_rk3036
> and uses their ops. Which in turn means the pll shouldn't access the GRF at
> all, as it uses the pll's own register to check the locked state.
>
> Can you try to change clk-pll.c from
>
> switch (pll_type) {
> case pll_rk3036:
> case pll_rk3328:
> if (!pll->rate_table || IS_ERR(ctx->grf))
> init.ops = &rockchip_rk3036_pll_clk_norate_ops;
> ...
> to
> switch (pll_type) {
> case pll_rk3036:
> case pll_rk3328:
> if (!pll->rate_table)
> init.ops = &rockchip_rk3036_pll_clk_norate_ops;
>
> similar to rk3399?
Thanks, I'll test this!
>
> Heiko
>
> > > > #clock-cells = <1>;
> > > > #reset-cells = <1>;
> > > > };
> > > > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> > > > cru: clock-controller@fdd20000 {
> > > > compatible = "rockchip,rk3568-cru";
> > > > reg = <0x0 0xfdd20000 0x0 0x1000>;
> > > > + rockchip,grf = <&grf>;
> > > > #clock-cells = <1>;
> > > > #reset-cells = <1>;
> > > > };
> > > >
> > >
> > >
> > >
> > >
> >
>
>
>
>
On Wed, Jul 28, 2021 at 10:10 AM Heiko Stübner <[email protected]> wrote:
>
> Hi Peter,
>
> Am Mittwoch, 28. Juli 2021, 15:55:26 CEST schrieb Peter Geis:
> > The rk356x adds a debounce clock to the gpio devices.
> > Increase the maximum clocks to account for it.
> >
> > Signed-off-by: Peter Geis <[email protected]>
>
> that binding change is also part of Jianqun's gpio driver series,
> also adds clock descriptions for both and even got an Ack from Rob
> already, so we should be going with that other variant ;-)
Roger, I'll drop this for the next version, thanks!
>
> Heiko
>
> > ---
> > Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> > index d993e002cebe..489a5263a7a1 100644
> > --- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> > +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
> > @@ -22,7 +22,7 @@ properties:
> > maxItems: 1
> >
> > clocks:
> > - maxItems: 1
> > + maxItems: 2
> >
> > gpio-controller: true
> >
> >
>
>
>
>
Am Mittwoch, 28. Juli 2021, 17:14:17 CEST schrieb Peter Geis:
> On Wed, Jul 28, 2021 at 10:46 AM Heiko St?bner <[email protected]> wrote:
> >
> > Am Mittwoch, 28. Juli 2021, 15:55:30 CEST schrieb Peter Geis:
> > > Add the thermal and tsadc nodes to the rk3568 device tree.
> > > There are two sensors, one for the cpu, one for the gpu.
> > >
> > > Signed-off-by: Peter Geis <[email protected]>
> > > ---
> > > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++
> > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++
> > > 2 files changed, 77 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > > index a588ca95ace2..b464c7bda1f7 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 {
> > > };
> > >
> > > tsadc {
> > > + /omit-if-no-ref/
> > > + tsadc_gpio: tsadc-gpio {
> > > + rockchip,pins =
> > > + <0 RK_PA1 0 &pcfg_pull_none>;
> > > + };
> > > +
> > > /omit-if-no-ref/
> > > tsadcm0_shut: tsadcm0-shut {
> > > rockchip,pins =
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > index 77c679304916..0905fac0726a 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > @@ -51,6 +51,7 @@ cpu0: cpu@0 {
> > > compatible = "arm,cortex-a55";
> > > reg = <0x0 0x0>;
> > > clocks = <&scmi_clk 0>;
> > > + #cooling-cells = <2>;
> > > enable-method = "psci";
> > > operating-points-v2 = <&cpu0_opp_table>;
> > > };
> > > @@ -59,6 +60,7 @@ cpu1: cpu@100 {
> > > device_type = "cpu";
> > > compatible = "arm,cortex-a55";
> > > reg = <0x0 0x100>;
> > > + #cooling-cells = <2>;
> > > enable-method = "psci";
> > > operating-points-v2 = <&cpu0_opp_table>;
> > > };
> > > @@ -67,6 +69,7 @@ cpu2: cpu@200 {
> > > device_type = "cpu";
> > > compatible = "arm,cortex-a55";
> > > reg = <0x0 0x200>;
> > > + #cooling-cells = <2>;
> > > enable-method = "psci";
> > > operating-points-v2 = <&cpu0_opp_table>;
> > > };
> > > @@ -75,6 +78,7 @@ cpu3: cpu@300 {
> > > device_type = "cpu";
> > > compatible = "arm,cortex-a55";
> > > reg = <0x0 0x300>;
> > > + #cooling-cells = <2>;
> > > enable-method = "psci";
> > > operating-points-v2 = <&cpu0_opp_table>;
> > > };
> > > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 {
> > > status = "disabled";
> > > };
> > >
> > > + thermal_zones: thermal-zones {
> > > + cpu_thermal: cpu-thermal {
> > > + polling-delay-passive = <100>;
> > > + polling-delay = <1000>;
> > > +
> > > + thermal-sensors = <&tsadc 0>;
> > > +
> > > + trips {
> > > + cpu_alert0: cpu_alert0 {
> > > + temperature = <70000>;
> > > + hysteresis = <2000>;
> > > + type = "passive";
> > > + };
> > > + cpu_alert1: cpu_alert1 {
> > > + temperature = <75000>;
> > > + hysteresis = <2000>;
> > > + type = "passive";
> > > + };
> > > + cpu_crit: cpu_crit {
> > > + temperature = <95000>;
> > > + hysteresis = <2000>;
> > > + type = "critical";
> > > + };
> > > + };
> > > +
> > > + cooling-maps {
> > > + map0 {
> > > + trip = <&cpu_alert0>;
> > > + cooling-device =
> > > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > > + };
> > > + };
> > > + };
> > > +
> > > + gpu_thermal: gpu-thermal {
> > > + polling-delay-passive = <20>; /* milliseconds */
> > > + polling-delay = <1000>; /* milliseconds */
> > > +
> > > + thermal-sensors = <&tsadc 1>;
> > > + };
> > > + };
> > > +
> > > + tsadc: tsadc@fe710000 {
> > > + compatible = "rockchip,rk3568-tsadc";
> > > + reg = <0x0 0xfe710000 0x0 0x100>;
> > > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> > > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
> > > + assigned-clock-rates = <17000000>, <700000>;
> > > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
> > > + clock-names = "tsadc", "apb_pclk";
> > > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
> > > + <&cru SRST_TSADCPHY>;
> > > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
> > > + rockchip,grf = <&grf>;
> > > + rockchip,hw-tshut-temp = <95000>;
> > > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> > > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
> > > + pinctrl-names = "gpio", "otpout";
> > > + pinctrl-0 = <&tsadc_gpio>;
> > > + pinctrl-1 = <&tsadc_shutorg>;
> >
> > The mainline thermal driver doesn't specify these pinctrl states at all.
> >
> > Heiko
>
> Oh, yes this seems to be the case.
>
> Is this something that should get fixed?
> In practice it likely won't ever cause problems, but in theory if
> someone changed the pinmux mode it could break it.
take a look at for example the rk3399.dtsi where the tsadc uses
the generic pinctrl names of "init" (before-probe), "default" (after probe)
and "sleep"
Heiko
>
> >
> > > + #thermal-sensor-cells = <1>;
> > > + status = "disabled";
> > > + };
> > > +
> > > saradc: saradc@fe720000 {
> > > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
> > > reg = <0x0 0xfe720000 0x0 0x100>;
> > >
> >
> >
> >
> >
>
Hi Peter,
On 7/28/21 3:55 PM, Peter Geis wrote:
> Add the thermal and tsadc nodes to the rk3568 device tree.
> There are two sensors, one for the cpu, one for the gpu.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++
> 2 files changed, 77 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> index a588ca95ace2..b464c7bda1f7 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 {
> };
>
> tsadc {
> + /omit-if-no-ref/
> + tsadc_gpio: tsadc-gpio {
nodenames ending on -gpio -gpios are kind of reserved.
Maybe use -pin or -pins.
From dt-schema/schemas/gpio/gpio-consumer.yaml
patternProperties:
"(?<!,nr)-gpios?$":
$ref: "/schemas/types.yaml#/definitions/phandle-array"
> + rockchip,pins =
> + <0 RK_PA1 0 &pcfg_pull_none>;
> + };
> +
> /omit-if-no-ref/
> tsadcm0_shut: tsadcm0-shut {
> rockchip,pins =
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 77c679304916..0905fac0726a 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -51,6 +51,7 @@ cpu0: cpu@0 {
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> clocks = <&scmi_clk 0>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -59,6 +60,7 @@ cpu1: cpu@100 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x100>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -67,6 +69,7 @@ cpu2: cpu@200 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x200>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -75,6 +78,7 @@ cpu3: cpu@300 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x300>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 {
> status = "disabled";
> };
>
> + thermal_zones: thermal-zones {
> + cpu_thermal: cpu-thermal {
> + polling-delay-passive = <100>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsadc 0>;
> +
> + trips {
> + cpu_alert0: cpu_alert0 {
> + temperature = <70000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu_alert1: cpu_alert1 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu_crit: cpu_crit {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert0>;
> + cooling-device =
> + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu_thermal: gpu-thermal {
> + polling-delay-passive = <20>; /* milliseconds */
> + polling-delay = <1000>; /* milliseconds */
> +
> + thermal-sensors = <&tsadc 1>;
> + };
> + };
> +
> + tsadc: tsadc@fe710000 {
> + compatible = "rockchip,rk3568-tsadc";
> + reg = <0x0 0xfe710000 0x0 0x100>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
> + assigned-clock-rates = <17000000>, <700000>;
> + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
> + clock-names = "tsadc", "apb_pclk";
> + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
> + <&cru SRST_TSADCPHY>;
> + reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
> + rockchip,grf = <&grf>;
> + rockchip,hw-tshut-temp = <95000>;
> + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
> + pinctrl-names = "gpio", "otpout";
> + pinctrl-0 = <&tsadc_gpio>;
> + pinctrl-1 = <&tsadc_shutorg>;
> + #thermal-sensor-cells = <1>;
> + status = "disabled";
> + };
> +
> saradc: saradc@fe720000 {
> compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
> reg = <0x0 0xfe720000 0x0 0x100>;
>
On Wed, 28 Jul 2021 09:55:26 -0400, Peter Geis wrote:
> The rk356x adds a debounce clock to the gpio devices.
> Increase the maximum clocks to account for it.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.example.dt.yaml: gpio@2000a000: clocks: [[4294967295, 9]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.example.dt.yaml: gpio@2003c000: clocks: [[4294967295, 10]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1510854
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Wed, Jul 28, 2021 at 11:16 AM Peter Geis <[email protected]> wrote:
>
> On Wed, Jul 28, 2021 at 10:41 AM Heiko Stübner <[email protected]> wrote:
> >
> > Am Mittwoch, 28. Juli 2021, 16:18:49 CEST schrieb Peter Geis:
> > > On Wed, Jul 28, 2021 at 10:06 AM Heiko Stübner <[email protected]> wrote:
> > > >
> > > > Hi Peter,
> > > >
> > > > Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> > > > > The grf and pmugrf phandles are necessary for the pmucru and cru to
> > > > > modify clocks. Add these phandles to permit adjusting the clock rates
> > > > > and muxes.
> > > > >
> > > > > Signed-off-by: Peter Geis <[email protected]>
> > > > > ---
> > > > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> > > > > 1 file changed, 3 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > > index 0905fac0726a..8ba0516eedd8 100644
> > > > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> > > > > pmucru: clock-controller@fdd00000 {
> > > > > compatible = "rockchip,rk3568-pmucru";
> > > > > reg = <0x0 0xfdd00000 0x0 0x1000>;
> > > > > + rockchip,grf = <&grf>;
> > > > > + rockchip,pmugrf = <&pmugrf>;
> > > >
> > > > I don't think the pmucru needs both and in fact the mainline
> > > > clock driver should just reference its specific grf at all, i.e.
> > > > pmucru -> pmugrf (via the rockchip,grf handle)
> > > > cru -> grf
> > > >
> > > > I've not seen anything breaking this scope so far.
> > >
> > > I thought the same thing as well, but for some reason the driver
> > > refuses to apply assigned-clocks to the plls unless these are all
> > > present.
> > > If the driver can get these assignments automatically eventually,
> > > perhaps it's a loading order issue?
> > >
> > > Thinking about it, it's probably the grf and pmugrf haven't probed
> > > when the driver is attempting to assign these, and tying them together
> > > forces the probe to happen first.
> >
> > though nothing references the regular grf from the pmucru I think.
> >
> > I.e. the pmucru PLL read their lock state from RK3568_PMU_MODE_CON
> >
> > The rk3568 reuses the pll_rk3328-type which in turn is a modified pll_rk3036
> > and uses their ops. Which in turn means the pll shouldn't access the GRF at
> > all, as it uses the pll's own register to check the locked state.
> >
> > Can you try to change clk-pll.c from
> >
> > switch (pll_type) {
> > case pll_rk3036:
> > case pll_rk3328:
> > if (!pll->rate_table || IS_ERR(ctx->grf))
> > init.ops = &rockchip_rk3036_pll_clk_norate_ops;
> > ...
> > to
> > switch (pll_type) {
> > case pll_rk3036:
> > case pll_rk3328:
> > if (!pll->rate_table)
> > init.ops = &rockchip_rk3036_pll_clk_norate_ops;
> >
> > similar to rk3399?
>
> Thanks, I'll test this!
Confirmed this fixed the issue for the rk3566, so as long as it
doesn't break rk3328 this works.
I'll include the patch in the next series.
>
> >
> > Heiko
> >
> > > > > #clock-cells = <1>;
> > > > > #reset-cells = <1>;
> > > > > };
> > > > > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> > > > > cru: clock-controller@fdd20000 {
> > > > > compatible = "rockchip,rk3568-cru";
> > > > > reg = <0x0 0xfdd20000 0x0 0x1000>;
> > > > > + rockchip,grf = <&grf>;
> > > > > #clock-cells = <1>;
> > > > > #reset-cells = <1>;
> > > > > };
> > > > >
> > > >
> > > >
> > > >
> > > >
> > >
> >
> >
> >
> >
Am Mittwoch, 28. Juli 2021, 18:49:47 CEST schrieb Peter Geis:
> On Wed, Jul 28, 2021 at 11:16 AM Peter Geis <[email protected]> wrote:
> >
> > On Wed, Jul 28, 2021 at 10:41 AM Heiko St?bner <[email protected]> wrote:
> > >
> > > Am Mittwoch, 28. Juli 2021, 16:18:49 CEST schrieb Peter Geis:
> > > > On Wed, Jul 28, 2021 at 10:06 AM Heiko St?bner <[email protected]> wrote:
> > > > >
> > > > > Hi Peter,
> > > > >
> > > > > Am Mittwoch, 28. Juli 2021, 15:55:31 CEST schrieb Peter Geis:
> > > > > > The grf and pmugrf phandles are necessary for the pmucru and cru to
> > > > > > modify clocks. Add these phandles to permit adjusting the clock rates
> > > > > > and muxes.
> > > > > >
> > > > > > Signed-off-by: Peter Geis <[email protected]>
> > > > > > ---
> > > > > > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +++
> > > > > > 1 file changed, 3 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > > > index 0905fac0726a..8ba0516eedd8 100644
> > > > > > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > > > > > @@ -218,6 +218,8 @@ grf: syscon@fdc60000 {
> > > > > > pmucru: clock-controller@fdd00000 {
> > > > > > compatible = "rockchip,rk3568-pmucru";
> > > > > > reg = <0x0 0xfdd00000 0x0 0x1000>;
> > > > > > + rockchip,grf = <&grf>;
> > > > > > + rockchip,pmugrf = <&pmugrf>;
> > > > >
> > > > > I don't think the pmucru needs both and in fact the mainline
> > > > > clock driver should just reference its specific grf at all, i.e.
> > > > > pmucru -> pmugrf (via the rockchip,grf handle)
> > > > > cru -> grf
> > > > >
> > > > > I've not seen anything breaking this scope so far.
> > > >
> > > > I thought the same thing as well, but for some reason the driver
> > > > refuses to apply assigned-clocks to the plls unless these are all
> > > > present.
> > > > If the driver can get these assignments automatically eventually,
> > > > perhaps it's a loading order issue?
> > > >
> > > > Thinking about it, it's probably the grf and pmugrf haven't probed
> > > > when the driver is attempting to assign these, and tying them together
> > > > forces the probe to happen first.
> > >
> > > though nothing references the regular grf from the pmucru I think.
> > >
> > > I.e. the pmucru PLL read their lock state from RK3568_PMU_MODE_CON
> > >
> > > The rk3568 reuses the pll_rk3328-type which in turn is a modified pll_rk3036
> > > and uses their ops. Which in turn means the pll shouldn't access the GRF at
> > > all, as it uses the pll's own register to check the locked state.
> > >
> > > Can you try to change clk-pll.c from
> > >
> > > switch (pll_type) {
> > > case pll_rk3036:
> > > case pll_rk3328:
> > > if (!pll->rate_table || IS_ERR(ctx->grf))
> > > init.ops = &rockchip_rk3036_pll_clk_norate_ops;
> > > ...
> > > to
> > > switch (pll_type) {
> > > case pll_rk3036:
> > > case pll_rk3328:
> > > if (!pll->rate_table)
> > > init.ops = &rockchip_rk3036_pll_clk_norate_ops;
> > >
> > > similar to rk3399?
> >
> > Thanks, I'll test this!
>
> Confirmed this fixed the issue for the rk3566, so as long as it
> doesn't break rk3328 this works.
It doesn't break anything ... i.e. the change for rk3328/rk3036 plls
from using the grf register to using the pll-internal lock status is in
the kernel for quite a while now - januar 2020 to be exact, and nobody
complained - including me when testing in my boardfarm ;-)
> I'll include the patch in the next series.
>
> >
> > >
> > > Heiko
> > >
> > > > > > #clock-cells = <1>;
> > > > > > #reset-cells = <1>;
> > > > > > };
> > > > > > @@ -225,6 +227,7 @@ pmucru: clock-controller@fdd00000 {
> > > > > > cru: clock-controller@fdd20000 {
> > > > > > compatible = "rockchip,rk3568-cru";
> > > > > > reg = <0x0 0xfdd20000 0x0 0x1000>;
> > > > > > + rockchip,grf = <&grf>;
> > > > > > #clock-cells = <1>;
> > > > > > #reset-cells = <1>;
> > > > > > };
> > > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > >
> > >
> > >
> > >
> > >
>
> Wiadomość napisana przez Peter Geis <[email protected]> w dniu 28.07.2021, o godz. 15:55:
>
> Add the thermal and tsadc nodes to the rk3568 device tree.
> There are two sensors, one for the cpu, one for the gpu.
>
> Signed-off-by: Peter Geis <[email protected]>
> ---
> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++
> 2 files changed, 77 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> index a588ca95ace2..b464c7bda1f7 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 {
> };
>
> tsadc {
> + /omit-if-no-ref/
> + tsadc_gpio: tsadc-gpio {
> + rockchip,pins =
> + <0 RK_PA1 0 &pcfg_pull_none>;
> + };
> +
> /omit-if-no-ref/
> tsadcm0_shut: tsadcm0-shut {
> rockchip,pins =
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 77c679304916..0905fac0726a 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -51,6 +51,7 @@ cpu0: cpu@0 {
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> clocks = <&scmi_clk 0>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -59,6 +60,7 @@ cpu1: cpu@100 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x100>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -67,6 +69,7 @@ cpu2: cpu@200 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x200>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -75,6 +78,7 @@ cpu3: cpu@300 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x300>;
> + #cooling-cells = <2>;
> enable-method = "psci";
> operating-points-v2 = <&cpu0_opp_table>;
> };
> @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 {
> status = "disabled";
> };
>
> + thermal_zones: thermal-zones {
> + cpu_thermal: cpu-thermal {
> + polling-delay-passive = <100>;
> + polling-delay = <1000>;
> +
> + thermal-sensors = <&tsadc 0>;
> +
> + trips {
> + cpu_alert0: cpu_alert0 {
> + temperature = <70000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu_alert1: cpu_alert1 {
> + temperature = <75000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> + cpu_crit: cpu_crit {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert0>;
> + cooling-device =
> + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu_thermal: gpu-thermal {
> + polling-delay-passive = <20>; /* milliseconds */
> + polling-delay = <1000>; /* milliseconds */
> +
> + thermal-sensors = <&tsadc 1>;
> + };
> + };
> +
> + tsadc: tsadc@fe710000 {
> + compatible = "rockchip,rk3568-tsadc";
> + reg = <0x0 0xfe710000 0x0 0x100>;
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
> + assigned-clock-rates = <17000000>, <700000>;
> + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
> + clock-names = "tsadc", "apb_pclk";
> + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
> + <&cru SRST_TSADCPHY>;
> + reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
> + rockchip,grf = <&grf>;
> + rockchip,hw-tshut-temp = <95000>;
> + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
> + pinctrl-names = "gpio", "otpout";
> + pinctrl-0 = <&tsadc_gpio>;
> + pinctrl-1 = <&tsadc_shutorg>;
> + #thermal-sensor-cells = <1>;
> + status = "disabled";
> + };
> +
> saradc: saradc@fe720000 {
> compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
> reg = <0x0 0xfe720000 0x0 0x100>;
> --
> 2.25.1
>
>
> _______________________________________________
> Linux-rockchip mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
Peter,
I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6).
Driver loads but i'm getting following error:
[ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517
[ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517
Maybe you have some hints here?
On Mon, Jan 17, 2022 at 3:43 AM Piotr Oniszczuk
<[email protected]> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <[email protected]> w dniu 28.07.2021, o godz. 15:55:
> >
> > Add the thermal and tsadc nodes to the rk3568 device tree.
> > There are two sensors, one for the cpu, one for the gpu.
> >
> > Signed-off-by: Peter Geis <[email protected]>
> > ---
> > .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 6 ++
> > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 71 +++++++++++++++++++
> > 2 files changed, 77 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > index a588ca95ace2..b464c7bda1f7 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> > @@ -2420,6 +2420,12 @@ spi3m1_cs1: spi3m1-cs1 {
> > };
> >
> > tsadc {
> > + /omit-if-no-ref/
> > + tsadc_gpio: tsadc-gpio {
> > + rockchip,pins =
> > + <0 RK_PA1 0 &pcfg_pull_none>;
> > + };
> > +
> > /omit-if-no-ref/
> > tsadcm0_shut: tsadcm0-shut {
> > rockchip,pins =
> > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > index 77c679304916..0905fac0726a 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> > @@ -51,6 +51,7 @@ cpu0: cpu@0 {
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x0>;
> > clocks = <&scmi_clk 0>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -59,6 +60,7 @@ cpu1: cpu@100 {
> > device_type = "cpu";
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x100>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -67,6 +69,7 @@ cpu2: cpu@200 {
> > device_type = "cpu";
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x200>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -75,6 +78,7 @@ cpu3: cpu@300 {
> > device_type = "cpu";
> > compatible = "arm,cortex-a55";
> > reg = <0x0 0x300>;
> > + #cooling-cells = <2>;
> > enable-method = "psci";
> > operating-points-v2 = <&cpu0_opp_table>;
> > };
> > @@ -774,6 +778,73 @@ uart9: serial@fe6d0000 {
> > status = "disabled";
> > };
> >
> > + thermal_zones: thermal-zones {
> > + cpu_thermal: cpu-thermal {
> > + polling-delay-passive = <100>;
> > + polling-delay = <1000>;
> > +
> > + thermal-sensors = <&tsadc 0>;
> > +
> > + trips {
> > + cpu_alert0: cpu_alert0 {
> > + temperature = <70000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > + cpu_alert1: cpu_alert1 {
> > + temperature = <75000>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > + cpu_crit: cpu_crit {
> > + temperature = <95000>;
> > + hysteresis = <2000>;
> > + type = "critical";
> > + };
> > + };
> > +
> > + cooling-maps {
> > + map0 {
> > + trip = <&cpu_alert0>;
> > + cooling-device =
> > + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > + };
> > + };
> > + };
> > +
> > + gpu_thermal: gpu-thermal {
> > + polling-delay-passive = <20>; /* milliseconds */
> > + polling-delay = <1000>; /* milliseconds */
> > +
> > + thermal-sensors = <&tsadc 1>;
> > + };
> > + };
> > +
> > + tsadc: tsadc@fe710000 {
> > + compatible = "rockchip,rk3568-tsadc";
> > + reg = <0x0 0xfe710000 0x0 0x100>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> > + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
> > + assigned-clock-rates = <17000000>, <700000>;
> > + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
> > + clock-names = "tsadc", "apb_pclk";
> > + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
> > + <&cru SRST_TSADCPHY>;
> > + reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
> > + rockchip,grf = <&grf>;
> > + rockchip,hw-tshut-temp = <95000>;
> > + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
> > + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
> > + pinctrl-names = "gpio", "otpout";
> > + pinctrl-0 = <&tsadc_gpio>;
> > + pinctrl-1 = <&tsadc_shutorg>;
> > + #thermal-sensor-cells = <1>;
> > + status = "disabled";
> > + };
> > +
> > saradc: saradc@fe720000 {
> > compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
> > reg = <0x0 0xfe720000 0x0 0x100>;
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > Linux-rockchip mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
> Peter,
>
> I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6).
> Driver loads but i'm getting following error:
>
> [ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517
> [ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517
>
> Maybe you have some hints here?
Error -517 means -EPROBE_DEFER, a device it relies on hasn't probed.
TSADC doesn't directly rely on anything that shouldn't already be
enabled. (Pinctrl, clocks, and grf all break a lot more than tsadc if
disabled)
Does your kernel config have all of the rockchip elements enabled?
>
>
> Wiadomość napisana przez Peter Geis <[email protected]> w dniu 17.01.2022, o godz. 14:49:
>
>>
>> Peter,
>>
>> I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6).
>> Driver loads but i'm getting following error:
>>
>> [ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517
>> [ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517
>>
>> Maybe you have some hints here?
>
> Error -517 means -EPROBE_DEFER, a device it relies on hasn't probed.
> TSADC doesn't directly rely on anything that shouldn't already be
> enabled. (Pinctrl, clocks, and grf all break a lot more than tsadc if
> disabled)
> Does your kernel config have all of the rockchip elements enabled?
>
Peter,
For sure I can't say 'yes' with 100% confidence.
I'm trying do my best for rk3566 (currently have working: SD/Eth/HDMI/Sound/USB2port0/BT).
Maybe you may point me pls for good reference of rk356x defconfig?
btw: a bit of context:
In my application (https://github.com/warpme/minimyth2) i have target to have single OS binary for all supported Allwinner/Amlogic/Rockchip/Broadcom devices.
By this kernel config i'm using is painfully assembled to have minimal working kernel for all targets.
It's a painful road....but still want to go this route for: minimal image size; shortest build time & one-for-all binary.
my current config: https://github.com/warpme/minimyth2/blob/master/script/kernel/linux-5.16/files/linux-5.16-arm64-armv8.config
btw2: for rk3566 i'm using majority of your patches!
Great work of you!
On Mon, Jan 17, 2022 at 9:13 AM Piotr Oniszczuk
<[email protected]> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <[email protected]> w dniu 17.01.2022, o godz. 14:49:
> >
> >>
> >> Peter,
> >>
> >> I'm trying to use this series to get thermal on rk3566 based tvbox (x96-x6).
> >> Driver loads but i'm getting following error:
> >>
> >> [ 132.873979] rockchip-thermal fe710000.tsadc: failed to register sensor 0: -517
> >> [ 132.874650] rockchip-thermal fe710000.tsadc: failed to register sensor[0] : error = -517
> >>
> >> Maybe you have some hints here?
> >
> > Error -517 means -EPROBE_DEFER, a device it relies on hasn't probed.
> > TSADC doesn't directly rely on anything that shouldn't already be
> > enabled. (Pinctrl, clocks, and grf all break a lot more than tsadc if
> > disabled)
> > Does your kernel config have all of the rockchip elements enabled?
> >
>
> Peter,
> For sure I can't say 'yes' with 100% confidence.
> I'm trying do my best for rk3566 (currently have working: SD/Eth/HDMI/Sound/USB2port0/BT).
>
> Maybe you may point me pls for good reference of rk356x defconfig?
>
> btw: a bit of context:
> In my application (https://github.com/warpme/minimyth2) i have target to have single OS binary for all supported Allwinner/Amlogic/Rockchip/Broadcom devices.
> By this kernel config i'm using is painfully assembled to have minimal working kernel for all targets.
> It's a painful road....but still want to go this route for: minimal image size; shortest build time & one-for-all binary.
> my current config: https://github.com/warpme/minimyth2/blob/master/script/kernel/linux-5.16/files/linux-5.16-arm64-armv8.config
I recommend you use `make savedefconfig`.
It produces a simplified defconfig based on your .config.
Your issue is in your dts.
You have retained the quartz64-a &cpu_thermal active thermal node
without tying in an active thermal control device (a fan).
By default the rk356x dtsi passive thermal trips are hooked up and
will throttle the device in case of overtemp.
If your device has no active thermal control, you don't need to add
the &cpu_thermal node at all to your dts.
>
> btw2: for rk3566 i'm using majority of your patches!
> Great work of you!
>
>
>
>
>
>
>
> Wiadomość napisana przez Peter Geis <[email protected]> w dniu 17.01.2022, o godz. 15:38:
>
>
>
> Your issue is in your dts.
> You have retained the quartz64-a &cpu_thermal active thermal node
> without tying in an active thermal control device (a fan).
> By default the rk356x dtsi passive thermal trips are hooked up and
> will throttle the device in case of overtemp.
> If your device has no active thermal control, you don't need to add
> the &cpu_thermal node at all to your dts.
>
>>
>> btw2: for rk3566 i'm using majority of your patches!
>> Great work of you!
Peter,
Many thx!
Now it works nicely:
cpu_thermal-virtual-0
Adapter: Virtual device
temp1: +33.8°C (crit = +95.0°C)
gpu_thermal-virtual-0
Adapter: Virtual device
temp1: +34.4°C (crit = +95.0°C)
again: many thx!
forgive me unrelated q:
may hint me for script you are using in your gitlab ci for building quartz64 u-boot in ci pipeline?
I'm using yours binaries - but want to add building from sources in my project....