In a uniprocessor implementation the interrupt processor targets
registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
gic_get_cpumask() will print a critical message saying
GIC CPU mask not found - kernel will fail to boot.
if these registers all read as zero, but there won't actually be
a problem on uniprocessor systems and the kernel will boot just
fine. Skip this check if we're running a UP kernel or if we
detect that the hardware only supports a single processor.
Cc: Nicolas Pitre <[email protected]>
Cc: Russell King <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
---
Maybe we should just drop the check entirely? It looks like it may
just be debug code that won't ever trigger in practice, even on the
11MPCore that caused this code to be introduced.
drivers/irqchip/irq-gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 19ceaa6..589c760 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
break;
}
- if (!mask)
+ if (!mask && num_possible_cpus() > 1)
pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
return mask;
--
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hosted by The Linux Foundation
On Sat, Jul 06, 2013 at 12:39:33AM +0100, Stephen Boyd wrote:
> In a uniprocessor implementation the interrupt processor targets
> registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> gic_get_cpumask() will print a critical message saying
>
> GIC CPU mask not found - kernel will fail to boot.
>
> if these registers all read as zero, but there won't actually be
> a problem on uniprocessor systems and the kernel will boot just
> fine. Skip this check if we're running a UP kernel or if we
> detect that the hardware only supports a single processor.
>
> Cc: Nicolas Pitre <[email protected]>
> Cc: Russell King <[email protected]>
> Signed-off-by: Stephen Boyd <[email protected]>
> ---
>
> Maybe we should just drop the check entirely? It looks like it may
> just be debug code that won't ever trigger in practice, even on the
> 11MPCore that caused this code to be introduced.
I agree, we should drop the check. It's annoying in uniprocessors and
unlikely to be found in the real world unless your gic entry in the dt
is wrong.
On 07/12, Javi Merino wrote:
> On Sat, Jul 06, 2013 at 12:39:33AM +0100, Stephen Boyd wrote:
> > In a uniprocessor implementation the interrupt processor targets
> > registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> > gic_get_cpumask() will print a critical message saying
> >
> > GIC CPU mask not found - kernel will fail to boot.
> >
> > if these registers all read as zero, but there won't actually be
> > a problem on uniprocessor systems and the kernel will boot just
> > fine. Skip this check if we're running a UP kernel or if we
> > detect that the hardware only supports a single processor.
> >
> > Cc: Nicolas Pitre <[email protected]>
> > Cc: Russell King <[email protected]>
> > Signed-off-by: Stephen Boyd <[email protected]>
> > ---
> >
> > Maybe we should just drop the check entirely? It looks like it may
> > just be debug code that won't ever trigger in practice, even on the
> > 11MPCore that caused this code to be introduced.
>
> I agree, we should drop the check. It's annoying in uniprocessors and
> unlikely to be found in the real world unless your gic entry in the dt
> is wrong.
>
Ok. How about this?
----8<-----
Subject: [PATCH v2] irqchip: gic: Don't complain in gic_get_cpumask()
In a uniprocessor implementation the interrupt processor targets
registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
gic_get_cpumask() will print a critical message saying
GIC CPU mask not found - kernel will fail to boot.
if these registers all read as zero, but there won't actually be
a problem on uniprocessor systems and the kernel will boot just
fine. Remove this check because if you're on a multiprocessor
system it's unlikely to be printed unless your DT is wrong or
your hardware is broken.
Cc: Nicolas Pitre <[email protected]>
Cc: Russell King <[email protected]>
Cc: Javi Merino <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
---
drivers/irqchip/irq-gic.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 19ceaa60..4fbcea9 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -368,9 +368,6 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
break;
}
- if (!mask)
- pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
-
return mask;
}
--
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hosted by The Linux Foundation
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
On 07/12/13 05:10, Stephen Boyd wrote:
> On 07/12, Javi Merino wrote:
>> I agree, we should drop the check. It's annoying in uniprocessors and
>> unlikely to be found in the real world unless your gic entry in the dt
>> is wrong.
>>
> Ok. How about this?
Any comments?
>
> ----8<-----
> Subject: [PATCH v2] irqchip: gic: Don't complain in gic_get_cpumask()
>
> In a uniprocessor implementation the interrupt processor targets
> registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> gic_get_cpumask() will print a critical message saying
>
> GIC CPU mask not found - kernel will fail to boot.
>
> if these registers all read as zero, but there won't actually be
> a problem on uniprocessor systems and the kernel will boot just
> fine. Remove this check because if you're on a multiprocessor
> system it's unlikely to be printed unless your DT is wrong or
> your hardware is broken.
>
> Cc: Nicolas Pitre <[email protected]>
> Cc: Russell King <[email protected]>
> Cc: Javi Merino <[email protected]>
> Signed-off-by: Stephen Boyd <[email protected]>
> ---
> drivers/irqchip/irq-gic.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 19ceaa60..4fbcea9 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -368,9 +368,6 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> break;
> }
>
> - if (!mask)
> - pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
> -
> return mask;
> }
>
--
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hosted by The Linux Foundation
On Wed, 17 Jul 2013, Stephen Boyd wrote:
> On 07/12/13 05:10, Stephen Boyd wrote:
> > On 07/12, Javi Merino wrote:
> >> I agree, we should drop the check. It's annoying in uniprocessors and
> >> unlikely to be found in the real world unless your gic entry in the dt
> >> is wrong.
And that's a likely outcome in the real world.
> >>
> > Ok. How about this?
>
> Any comments?
What about this instead:
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 19ceaa60e0..86d21bc6cb 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
break;
}
- if (!mask)
+ if (is_smp() && !mask)
pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
return mask;
Nicolas
On 07/17/13 15:34, Nicolas Pitre wrote:
> On Wed, 17 Jul 2013, Stephen Boyd wrote:
>
>> On 07/12/13 05:10, Stephen Boyd wrote:
>>> On 07/12, Javi Merino wrote:
>>>> I agree, we should drop the check. It's annoying in uniprocessors and
>>>> unlikely to be found in the real world unless your gic entry in the dt
>>>> is wrong.
> And that's a likely outcome in the real world.
>
>>> Ok. How about this?
>> Any comments?
> What about this instead:
Unfortunately arm64 doesn't have SMP_ON_UP. It sounds like you preferred
the first patch using num_possible_cpus()
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 19ceaa60e0..86d21bc6cb 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> break;
> }
>
> - if (!mask)
> + if (is_smp() && !mask)
> pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
>
> return mask;
>
>
> Nicolas
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hosted by The Linux Foundation
On 07/17/13 15:53, Nicolas Pitre wrote:
> On Wed, 17 Jul 2013, Stephen Boyd wrote:
>
>> On 07/17/13 15:34, Nicolas Pitre wrote:
>>> On Wed, 17 Jul 2013, Stephen Boyd wrote:
>>>
>>>> On 07/12/13 05:10, Stephen Boyd wrote:
>>>>> On 07/12, Javi Merino wrote:
>>>>>> I agree, we should drop the check. It's annoying in uniprocessors and
>>>>>> unlikely to be found in the real world unless your gic entry in the dt
>>>>>> is wrong.
>>> And that's a likely outcome in the real world.
>>>
>>>>> Ok. How about this?
>>>> Any comments?
>>> What about this instead:
>> Unfortunately arm64 doesn't have SMP_ON_UP.
> And why does that matter?
Because the gic driver is compiled on both arm and arm64? I suppose we
could define is_smp() to 1 on arm64 but its probably better to rely on
generic kernel things instead of arch specific functions.
>
>> It sounds like you preferred the first patch using num_possible_cpus()
> Probably, yes. I didn't follow the early conversation though.
This was the first patch:
---8<----
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 19ceaa6..589c760 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
break;
}
- if (!mask)
+ if (!mask && num_possible_cpus() > 1)
pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
return mask;
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
On Wed, 17 Jul 2013, Stephen Boyd wrote:
> On 07/17/13 15:34, Nicolas Pitre wrote:
> > On Wed, 17 Jul 2013, Stephen Boyd wrote:
> >
> >> On 07/12/13 05:10, Stephen Boyd wrote:
> >>> On 07/12, Javi Merino wrote:
> >>>> I agree, we should drop the check. It's annoying in uniprocessors and
> >>>> unlikely to be found in the real world unless your gic entry in the dt
> >>>> is wrong.
> > And that's a likely outcome in the real world.
> >
> >>> Ok. How about this?
> >> Any comments?
> > What about this instead:
>
> Unfortunately arm64 doesn't have SMP_ON_UP.
And why does that matter?
> It sounds like you preferred the first patch using num_possible_cpus()
Probably, yes. I didn't follow the early conversation though.
Nicolas
Hi,
On Sat, Jul 06, 2013 at 05:09:33, Stephen Boyd wrote:
> In a uniprocessor implementation the interrupt processor targets
> registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> gic_get_cpumask() will print a critical message saying
>
> GIC CPU mask not found - kernel will fail to boot.
>
> if these registers all read as zero, but there won't actually be
> a problem on uniprocessor systems and the kernel will boot just
> fine. Skip this check if we're running a UP kernel or if we
> detect that the hardware only supports a single processor.
>
> Cc: Nicolas Pitre <[email protected]>
> Cc: Russell King <[email protected]>
> Signed-off-by: Stephen Boyd <[email protected]>
> ---
>
> Maybe we should just drop the check entirely? It looks like it may
> just be debug code that won't ever trigger in practice, even on the
> 11MPCore that caused this code to be introduced.
>
Apologies if I missed v2 of this patch if there was one. I could not
locate it in my inbox or the list archives.
We have a yet to be released single-core A9 MPCore system (AM437x) which
needs to co-exist in omap2plus_defconfig wherein NR_CPUS is set to 2.
This currently leads to the "GIC CPU mask not found..." being printed
twice during bootup. If the check is really some debug code, can it be
completely dropped?
Regards,
Vaibhav B.
On 07/20, Bedia, Vaibhav wrote:
> Hi,
>
> On Sat, Jul 06, 2013 at 05:09:33, Stephen Boyd wrote:
> > In a uniprocessor implementation the interrupt processor targets
> > registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> > gic_get_cpumask() will print a critical message saying
> >
> > GIC CPU mask not found - kernel will fail to boot.
> >
> > if these registers all read as zero, but there won't actually be
> > a problem on uniprocessor systems and the kernel will boot just
> > fine. Skip this check if we're running a UP kernel or if we
> > detect that the hardware only supports a single processor.
> >
> > Cc: Nicolas Pitre <[email protected]>
> > Cc: Russell King <[email protected]>
> > Signed-off-by: Stephen Boyd <[email protected]>
> > ---
> >
> > Maybe we should just drop the check entirely? It looks like it may
> > just be debug code that won't ever trigger in practice, even on the
> > 11MPCore that caused this code to be introduced.
> >
>
> Apologies if I missed v2 of this patch if there was one. I could not
> locate it in my inbox or the list archives.
>
> We have a yet to be released single-core A9 MPCore system (AM437x) which
> needs to co-exist in omap2plus_defconfig wherein NR_CPUS is set to 2.
> This currently leads to the "GIC CPU mask not found..." being printed
> twice during bootup. If the check is really some debug code, can it be
> completely dropped?
I have sent both versions of the patch in hopes that one or the
other will be accepted. Either way works for me.
--
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hosted by The Linux Foundation
On 07/17, Stephen Boyd wrote:
> On 07/17/13 15:53, Nicolas Pitre wrote:
> > On Wed, 17 Jul 2013, Stephen Boyd wrote:
> >
> >> On 07/17/13 15:34, Nicolas Pitre wrote:
> >>> On Wed, 17 Jul 2013, Stephen Boyd wrote:
> >>>
> >>>> On 07/12/13 05:10, Stephen Boyd wrote:
> >>>>> On 07/12, Javi Merino wrote:
> >>>>>> I agree, we should drop the check. It's annoying in uniprocessors and
> >>>>>> unlikely to be found in the real world unless your gic entry in the dt
> >>>>>> is wrong.
> >>> And that's a likely outcome in the real world.
> >>>
> >>>>> Ok. How about this?
> >>>> Any comments?
> >>> What about this instead:
> >> Unfortunately arm64 doesn't have SMP_ON_UP.
> > And why does that matter?
>
> Because the gic driver is compiled on both arm and arm64? I suppose we
> could define is_smp() to 1 on arm64 but its probably better to rely on
> generic kernel things instead of arch specific functions.
>
> >
> >> It sounds like you preferred the first patch using num_possible_cpus()
> > Probably, yes. I didn't follow the early conversation though.
>
> This was the first patch:
>
> ---8<----
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index 19ceaa6..589c760 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> break;
> }
>
> - if (!mask)
> + if (!mask && num_possible_cpus() > 1)
> pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
>
> return mask;
Can one of these two patches be picked up?
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hosted by The Linux Foundation
On Thu, 22 Aug 2013, Stephen Boyd wrote:
> On 07/17, Stephen Boyd wrote:
> > On 07/17/13 15:53, Nicolas Pitre wrote:
> > > On Wed, 17 Jul 2013, Stephen Boyd wrote:
> > >
> > >> On 07/17/13 15:34, Nicolas Pitre wrote:
> > >>> On Wed, 17 Jul 2013, Stephen Boyd wrote:
> > >>>
> > >>>> On 07/12/13 05:10, Stephen Boyd wrote:
> > >>>>> On 07/12, Javi Merino wrote:
> > >>>>>> I agree, we should drop the check. It's annoying in uniprocessors and
> > >>>>>> unlikely to be found in the real world unless your gic entry in the dt
> > >>>>>> is wrong.
> > >>> And that's a likely outcome in the real world.
> > >>>
> > >>>>> Ok. How about this?
> > >>>> Any comments?
> > >>> What about this instead:
> > >> Unfortunately arm64 doesn't have SMP_ON_UP.
> > > And why does that matter?
> >
> > Because the gic driver is compiled on both arm and arm64? I suppose we
> > could define is_smp() to 1 on arm64 but its probably better to rely on
> > generic kernel things instead of arch specific functions.
> >
> > >
> > >> It sounds like you preferred the first patch using num_possible_cpus()
> > > Probably, yes. I didn't follow the early conversation though.
> >
> > This was the first patch:
> >
> > ---8<----
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index 19ceaa6..589c760 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gic.c
> > @@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> > break;
> > }
> >
> > - if (!mask)
> > + if (!mask && num_possible_cpus() > 1)
> > pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
> >
> > return mask;
>
> Can one of these two patches be picked up?
Sure. Just send it to RMK's patch system with my ACK.
Nicolas
On 08/22, Nicolas Pitre wrote:
> On Thu, 22 Aug 2013, Stephen Boyd wrote:
>
> > On 07/17, Stephen Boyd wrote:
> > > On 07/17/13 15:53, Nicolas Pitre wrote:
> > > > On Wed, 17 Jul 2013, Stephen Boyd wrote:
> > > >
> > > >> On 07/17/13 15:34, Nicolas Pitre wrote:
> > > >>> On Wed, 17 Jul 2013, Stephen Boyd wrote:
> > > >>>
> > > >>>> On 07/12/13 05:10, Stephen Boyd wrote:
> > > >>>>> On 07/12, Javi Merino wrote:
> > > >>>>>> I agree, we should drop the check. It's annoying in uniprocessors and
> > > >>>>>> unlikely to be found in the real world unless your gic entry in the dt
> > > >>>>>> is wrong.
> > > >>> And that's a likely outcome in the real world.
> > > >>>
> > > >>>>> Ok. How about this?
> > > >>>> Any comments?
> > > >>> What about this instead:
> > > >> Unfortunately arm64 doesn't have SMP_ON_UP.
> > > > And why does that matter?
> > >
> > > Because the gic driver is compiled on both arm and arm64? I suppose we
> > > could define is_smp() to 1 on arm64 but its probably better to rely on
> > > generic kernel things instead of arch specific functions.
> > >
> > > >
> > > >> It sounds like you preferred the first patch using num_possible_cpus()
> > > > Probably, yes. I didn't follow the early conversation though.
> > >
> > > This was the first patch:
> > >
> > > ---8<----
> > >
> > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > > index 19ceaa6..589c760 100644
> > > --- a/drivers/irqchip/irq-gic.c
> > > +++ b/drivers/irqchip/irq-gic.c
> > > @@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> > > break;
> > > }
> > >
> > > - if (!mask)
> > > + if (!mask && num_possible_cpus() > 1)
> > > pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
> > >
> > > return mask;
> >
> > Can one of these two patches be picked up?
>
> Sure. Just send it to RMK's patch system with my ACK.
>
I'm confused on that. MAINTAINERS says this patch should go
through Thomas Gleixner's irq/core branch but it looks like only
arm-soc has been taking patches for the current location.
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hosted by The Linux Foundation
On Thu, 22 Aug 2013, Stephen Boyd wrote:
> On 08/22, Nicolas Pitre wrote:
> > On Thu, 22 Aug 2013, Stephen Boyd wrote:
> >
> > > On 07/17, Stephen Boyd wrote:
> > > > On 07/17/13 15:53, Nicolas Pitre wrote:
> > > > > On Wed, 17 Jul 2013, Stephen Boyd wrote:
> > > > >
> > > > >> On 07/17/13 15:34, Nicolas Pitre wrote:
> > > > >>> On Wed, 17 Jul 2013, Stephen Boyd wrote:
> > > > >>>
> > > > >>>> On 07/12/13 05:10, Stephen Boyd wrote:
> > > > >>>>> On 07/12, Javi Merino wrote:
> > > > >>>>>> I agree, we should drop the check. It's annoying in uniprocessors and
> > > > >>>>>> unlikely to be found in the real world unless your gic entry in the dt
> > > > >>>>>> is wrong.
> > > > >>> And that's a likely outcome in the real world.
> > > > >>>
> > > > >>>>> Ok. How about this?
> > > > >>>> Any comments?
> > > > >>> What about this instead:
> > > > >> Unfortunately arm64 doesn't have SMP_ON_UP.
> > > > > And why does that matter?
> > > >
> > > > Because the gic driver is compiled on both arm and arm64? I suppose we
> > > > could define is_smp() to 1 on arm64 but its probably better to rely on
> > > > generic kernel things instead of arch specific functions.
> > > >
> > > > >
> > > > >> It sounds like you preferred the first patch using num_possible_cpus()
> > > > > Probably, yes. I didn't follow the early conversation though.
> > > >
> > > > This was the first patch:
> > > >
> > > > ---8<----
> > > >
> > > > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > > > index 19ceaa6..589c760 100644
> > > > --- a/drivers/irqchip/irq-gic.c
> > > > +++ b/drivers/irqchip/irq-gic.c
> > > > @@ -368,7 +368,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> > > > break;
> > > > }
> > > >
> > > > - if (!mask)
> > > > + if (!mask && num_possible_cpus() > 1)
> > > > pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
> > > >
> > > > return mask;
> > >
> > > Can one of these two patches be picked up?
> >
> > Sure. Just send it to RMK's patch system with my ACK.
> >
>
> I'm confused on that. MAINTAINERS says this patch should go
> through Thomas Gleixner's irq/core branch but it looks like only
> arm-soc has been taking patches for the current location.
Blah. OK then, just send it to Thomas.
Initially this code was written and committed by RMK which is why I
suggested you send him the fix.
Nicolas
On Fri, Aug 23, 2013 at 12:51:59AM -0400, Nicolas Pitre wrote:
> Blah. OK then, just send it to Thomas.
>
> Initially this code was written and committed by RMK which is why I
> suggested you send him the fix.
It _should_, because the author of the file presumably knows how the
driver is supposed to work much better than the maintainer of the
subsystem. So driver authors _should_ always be involved in the
handling of the patch.
Unfortunately, that rarely happens, and I've given up any hope of the
old kernel process(es) remaining where authors were responsible for the
code they wrote. Somehow, kernel maintanence has been perversed so that
subsystem maintainers get to decide whether patches to drivers that they
don't have hardware for are to be applied irrespective of whether the
driver author has any input to it.
On 2015-01-31 01:43, Stephen Boyd wrote:
> In a uniprocessor implementation the interrupt processor targets
> registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> gic_get_cpumask() will print a critical message saying
>
> GIC CPU mask not found - kernel will fail to boot.
>
> if these registers all read as zero, but there won't actually be
> a problem on uniprocessor systems and the kernel will boot just
> fine. Skip this check if we're running a UP kernel or if we
> detect that the hardware only supports a single processor.
Does the job for my device too, thx.
Acked-by: Stefan Agner <[email protected]>
>
> Acked-by: Nicolas Pitre <[email protected]>
> Cc: Russell King <[email protected]>
> Cc: Stefan Agner <[email protected]>
> Signed-off-by: Stephen Boyd <[email protected]>
> ---
> drivers/irqchip/irq-gic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> index d617ee5a3d8a..1b70e0de0f6e 100644
> --- a/drivers/irqchip/irq-gic.c
> +++ b/drivers/irqchip/irq-gic.c
> @@ -346,7 +346,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> break;
> }
>
> - if (!mask)
> + if (!mask && num_possible_cpus() > 1)
> pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
>
> return mask;
On 01:09-20150131, Felipe Balbi wrote:
> +linux-omap
>
> On Fri, Jan 30, 2015 at 04:43:30PM -0800, Stephen Boyd wrote:
> > In a uniprocessor implementation the interrupt processor targets
> > registers are read-as-zero/write-ignored (RAZ/WI). Unfortunately
> > gic_get_cpumask() will print a critical message saying
> >
> > GIC CPU mask not found - kernel will fail to boot.
> >
> > if these registers all read as zero, but there won't actually be
> > a problem on uniprocessor systems and the kernel will boot just
> > fine. Skip this check if we're running a UP kernel or if we
> > detect that the hardware only supports a single processor.
> >
>
> Nice, I'll test this on AM437x on Monday but certainly looks promising:
>
> Acked-by: Felipe Balbi <[email protected]>
>
>
> > Acked-by: Nicolas Pitre <[email protected]>
> > Cc: Russell King <[email protected]>
> > Cc: Stefan Agner <[email protected]>
> > Signed-off-by: Stephen Boyd <[email protected]>
> > ---
> > drivers/irqchip/irq-gic.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
> > index d617ee5a3d8a..1b70e0de0f6e 100644
> > --- a/drivers/irqchip/irq-gic.c
> > +++ b/drivers/irqchip/irq-gic.c
> > @@ -346,7 +346,7 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic)
> > break;
> > }
> >
> > - if (!mask)
> > + if (!mask && num_possible_cpus() > 1)
> > pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
> >
> > return mask;
> > --
> > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> > a Linux Foundation Collaborative Project
> >
> > --
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> > Please read the FAQ at http://www.tux.org/lkml/
>
> --
> balbi
Acked-by: Nishanth Menon <[email protected]>
--
Regards,
Nishanth Menon