From: Geetha <[email protected]>
Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync
The following patchset does software workaround for these two erratas.
This series is based on RFC patch.
https://www.spinics.net/lists/arm-kernel/msg575739.html
As suggested by Will Deacon, code is modified to use silicon id to
enable errata#74 workaround.
Linu Cherian (1):
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
Geetha (2):
arm64: Add MIDR values for Cavium cn99xx SoCs
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
Documentation/arm64/silicon-errata.txt | 2 ++
arch/arm64/include/asm/cputype.h | 3 ++
drivers/acpi/arm64/iort.c | 14 +++++++-
drivers/iommu/arm-smmu-v3.c | 64 +++++++++++++++++++++++++++++-----
4 files changed, 73 insertions(+), 10 deletions(-)
--
1.9.1
From: Geetha <[email protected]>
Add MIDR values for Cavium cn99xx SoCs
Signed-off-by: Geetha <[email protected]>
---
arch/arm64/include/asm/cputype.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index fc50271..066fad0 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -85,6 +85,7 @@
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
+#define CAVIUM_CPU_PART_THUNDERX_99XX 0x0AF
#define BRCM_CPU_PART_VULCAN 0x516
@@ -94,6 +95,8 @@
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
+#define MIDR_THUNDERX_99XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_99XX)
+#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
#ifndef __ASSEMBLY__
--
1.9.1
From: Geetha <[email protected]>
Cavium 99xx SMMU doesn't support MSI and also doesn't have unique irq
lines for gerror, eventq and cmdq-sync.
This patch addresses the issue by checking if any interrupt sources are
using same irq number, then they are registered as shared irqs.
Signed-off-by: Geetha <[email protected]>
---
Documentation/arm64/silicon-errata.txt | 1 +
drivers/iommu/arm-smmu-v3.c | 32 ++++++++++++++++++++++++++++----
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 629e2ce..cc15f25 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -62,6 +62,7 @@ stable kernels.
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
| Cavium | ThunderX2 SMMUv3| #74 | N/A |
+| Cavium | ThunderX2 SMMUv3| #126 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index ee23ccd..eb55d38 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -2211,10 +2211,30 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
devm_add_action(dev, arm_smmu_free_msis, dev);
}
+static int get_irq_flags(struct arm_smmu_device *smmu, int irq)
+{
+ int match_count = 0;
+
+ if (irq == smmu->evtq.q.irq)
+ match_count++;
+ if (irq == smmu->cmdq.q.irq)
+ match_count++;
+ if (irq == smmu->gerr_irq)
+ match_count++;
+ if (irq == smmu->priq.q.irq)
+ match_count++;
+
+ if (match_count > 1)
+ return IRQF_SHARED | IRQF_ONESHOT;
+
+ return 0;
+}
+
static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
{
int ret, irq;
u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN;
+ u32 irqflags = 0;
/* Disable IRQs first */
ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL,
@@ -2229,9 +2249,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
/* Request interrupt lines */
irq = smmu->evtq.q.irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
arm_smmu_evtq_thread,
- IRQF_ONESHOT,
+ IRQF_ONESHOT | irqflags,
"arm-smmu-v3-evtq", smmu);
if (ret < 0)
dev_warn(smmu->dev, "failed to enable evtq irq\n");
@@ -2239,8 +2260,9 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
irq = smmu->cmdq.q.irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_irq(smmu->dev, irq,
- arm_smmu_cmdq_sync_handler, 0,
+ arm_smmu_cmdq_sync_handler, irqflags,
"arm-smmu-v3-cmdq-sync", smmu);
if (ret < 0)
dev_warn(smmu->dev, "failed to enable cmdq-sync irq\n");
@@ -2248,8 +2270,9 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
irq = smmu->gerr_irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler,
- 0, "arm-smmu-v3-gerror", smmu);
+ irqflags, "arm-smmu-v3-gerror", smmu);
if (ret < 0)
dev_warn(smmu->dev, "failed to enable gerror irq\n");
}
@@ -2257,9 +2280,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
if (smmu->features & ARM_SMMU_FEAT_PRI) {
irq = smmu->priq.q.irq;
if (irq) {
+ irqflags = get_irq_flags(smmu, irq);
ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
arm_smmu_priq_thread,
- IRQF_ONESHOT,
+ IRQF_ONESHOT | irqflags,
"arm-smmu-v3-priq",
smmu);
if (ret < 0)
--
1.9.1
From: Linu Cherian <[email protected]>
Cavium 99xx SMMU implementation doesn't support page 1 register space.
Based on silicon id, ARM_SMMU_PAGE0_REGS_ONLY macro is set as an errata
workaround.
This macro when set, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
Signed-off-by: Linu Cherian <[email protected]>
Signed-off-by: Geetha <[email protected]>
---
Documentation/arm64/silicon-errata.txt | 1 +
drivers/acpi/arm64/iort.c | 14 +++++++++++++-
drivers/iommu/arm-smmu-v3.c | 32 +++++++++++++++++++++++++++-----
3 files changed, 41 insertions(+), 6 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 2f66683..629e2ce 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -61,6 +61,7 @@ stable kernels.
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
+| Cavium | ThunderX2 SMMUv3| #74 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
| | | | |
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index 4a5bb96..a074ce9 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -25,6 +25,7 @@
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <asm/cputype.h>
#define IORT_TYPE_MASK(type) (1 << (type))
#define IORT_MSI_TYPE (1 << ACPI_IORT_NODE_ITS_GROUP)
@@ -669,12 +670,23 @@ static void __init arm_smmu_v3_init_resources(struct resource *res,
{
struct acpi_iort_smmu_v3 *smmu;
int num_res = 0;
+ u32 cpu_model;
+ unsigned long size = SZ_128K;
/* Retrieve SMMUv3 specific data */
smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
+ /*
+ * Override the size, for Cavium CN99xx implementations
+ * which doesn't support the page 1 SMMU register space.
+ */
+ cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
+ if (cpu_model == MIDR_THUNDERX_99XX ||
+ cpu_model == MIDR_BRCM_VULCAN)
+ size = SZ_64K;
+
res[num_res].start = smmu->base_address;
- res[num_res].end = smmu->base_address + SZ_128K - 1;
+ res[num_res].end = smmu->base_address + size - 1;
res[num_res].flags = IORESOURCE_MEM;
num_res++;
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 1dcd154..ee23ccd 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -38,6 +38,7 @@
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
+#include <asm/cputype.h>
#include "io-pgtable.h"
@@ -176,15 +177,15 @@
#define ARM_SMMU_CMDQ_CONS 0x9c
#define ARM_SMMU_EVTQ_BASE 0xa0
-#define ARM_SMMU_EVTQ_PROD 0x100a8
-#define ARM_SMMU_EVTQ_CONS 0x100ac
+#define ARM_SMMU_EVTQ_PROD (page1_offset_adjust(0x100a8))
+#define ARM_SMMU_EVTQ_CONS (page1_offset_adjust(0x100ac))
#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0
#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8
#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc
#define ARM_SMMU_PRIQ_BASE 0xc0
-#define ARM_SMMU_PRIQ_PROD 0x100c8
-#define ARM_SMMU_PRIQ_CONS 0x100cc
+#define ARM_SMMU_PRIQ_PROD (page1_offset_adjust(0x100c8))
+#define ARM_SMMU_PRIQ_CONS (page1_offset_adjust(0x100cc))
#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0
#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8
#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
@@ -412,6 +413,10 @@
#define MSI_IOVA_BASE 0x8000000
#define MSI_IOVA_LENGTH 0x100000
+#define ARM_SMMU_PAGE0_REGS_ONLY \
+ (((read_cpuid_id() & MIDR_CPU_MODEL_MASK) == MIDR_THUNDERX_99XX) \
+ || ((read_cpuid_id() & MIDR_CPU_MODEL_MASK) == MIDR_BRCM_VULCAN))
+
static bool disable_bypass;
module_param_named(disable_bypass, disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
@@ -660,6 +665,15 @@ struct arm_smmu_option_prop {
{ 0, NULL},
};
+static inline unsigned long page1_offset_adjust(
+ unsigned long off)
+{
+ if (!ARM_SMMU_PAGE0_REGS_ONLY)
+ return off;
+ else
+ return (off - SZ_64K);
+}
+
static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
{
return container_of(dom, struct arm_smmu_domain, domain);
@@ -2631,6 +2645,14 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev,
return ret;
}
+static unsigned long arm_smmu_resource_size(void)
+{
+ if (ARM_SMMU_PAGE0_REGS_ONLY)
+ return SZ_64K;
+ else
+ return SZ_128K;
+}
+
static int arm_smmu_device_probe(struct platform_device *pdev)
{
int irq, ret;
@@ -2649,7 +2671,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
/* Base address */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (resource_size(res) + 1 < SZ_128K) {
+ if (resource_size(res) + 1 < arm_smmu_resource_size()) {
dev_err(dev, "MMIO region too small (%pr)\n", res);
return -EINVAL;
}
--
1.9.1
On Thu, Apr 27, 2017 at 5:16 PM, Geetha sowjanya
<[email protected]> wrote:
> From: Geetha <[email protected]>
>
> Add MIDR values for Cavium cn99xx SoCs
>
> Signed-off-by: Geetha <[email protected]>
> ---
> arch/arm64/include/asm/cputype.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index fc50271..066fad0 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -85,6 +85,7 @@
>
> #define CAVIUM_CPU_PART_THUNDERX 0x0A1
> #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
> +#define CAVIUM_CPU_PART_THUNDERX_99XX 0x0AF
Can you please use the name CAVIUM_CPU_PART_THUNDERX2? We have used
ThunderX2 consistently for this platform, having THUNDERX here would
be confusing.
> #define BRCM_CPU_PART_VULCAN 0x516
>
> @@ -94,6 +95,8 @@
> #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
> #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
> +#define MIDR_THUNDERX_99XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_99XX)
> +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
> #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
>
> #ifndef __ASSEMBLY__
Thanks,
JC.
On 27.04.17 17:16:21, Geetha sowjanya wrote:
> From: Geetha <[email protected]>
>
> Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
> 1. Errata ID #74
> SMMU register alias Page 1 is not implemented
> 2. Errata ID #126
> SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync
>
> The following patchset does software workaround for these two erratas.
>
> This series is based on RFC patch.
> https://www.spinics.net/lists/arm-kernel/msg575739.html
>
> As suggested by Will Deacon, code is modified to use silicon id to
> enable errata#74 workaround.
Can we go with the previous series [1] and:
* drop the iort model numbering part,
* add an enablement function that enables flags (smmu->options)
depending on midr values (which replaces the macro code)?
E.g.:
static void acpi_smmu_enable_cavium(struct arm_smmu_device *smmu)
{
u32 cpu_model;
if (!IS_ENABLED(CONFIG_ARM64))
return;
cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
switch (cpu_model) {
case ...:
case ...:
break;
default:
/* No Cavium CN99xx SMMU v3 */
return;
}
smmu->options |= (ARM_SMMU_OPT_PAGE0_REGS_ONLY |
ARM_SMMU_OPT_USE_SHARED_IRQS);
}
-Robert
[1] [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds
https://marc.info/?l=linux-acpi&m=149192179623708&w=2
>
> Linu Cherian (1):
> iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
>
> Geetha (2):
> arm64: Add MIDR values for Cavium cn99xx SoCs
> iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
>
> Documentation/arm64/silicon-errata.txt | 2 ++
> arch/arm64/include/asm/cputype.h | 3 ++
> drivers/acpi/arm64/iort.c | 14 +++++++-
> drivers/iommu/arm-smmu-v3.c | 64 +++++++++++++++++++++++++++++-----
> 4 files changed, 73 insertions(+), 10 deletions(-)
>
> --
> 1.9.1
>
On Thu, Apr 27, 2017 at 7:09 PM, Robert Richter
<[email protected]> wrote:
> On 27.04.17 17:16:21, Geetha sowjanya wrote:
>> From: Geetha <[email protected]>
>>
>> Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
>> 1. Errata ID #74
>> SMMU register alias Page 1 is not implemented
>> 2. Errata ID #126
>> SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync
>>
>> The following patchset does software workaround for these two erratas.
>>
>> This series is based on RFC patch.
>> https://www.spinics.net/lists/arm-kernel/msg575739.html
>>
>> As suggested by Will Deacon, code is modified to use silicon id to
>> enable errata#74 workaround.
>
> Can we go with the previous series [1] and:
>
> * drop the iort model numbering part,
>
> * add an enablement function that enables flags (smmu->options)
> depending on midr values (which replaces the macro code)?
I don't see how it is efficient and consistent, if we take data from DT
for non-ACPI mode and read CPU ID from MIDR for ACPI mode.
Thanks,
Sunil.
>
> E.g.:
>
> static void acpi_smmu_enable_cavium(struct arm_smmu_device *smmu)
> {
> u32 cpu_model;
>
> if (!IS_ENABLED(CONFIG_ARM64))
> return;
>
> cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> switch (cpu_model) {
> case ...:
> case ...:
> break;
> default:
> /* No Cavium CN99xx SMMU v3 */
> return;
> }
>
> smmu->options |= (ARM_SMMU_OPT_PAGE0_REGS_ONLY |
> ARM_SMMU_OPT_USE_SHARED_IRQS);
> }
>
> -Robert
>
>
> [1] [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds
> https://marc.info/?l=linux-acpi&m=149192179623708&w=2
>
>>
>> Linu Cherian (1):
>> iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
>>
>> Geetha (2):
>> arm64: Add MIDR values for Cavium cn99xx SoCs
>> iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
>>
>> Documentation/arm64/silicon-errata.txt | 2 ++
>> arch/arm64/include/asm/cputype.h | 3 ++
>> drivers/acpi/arm64/iort.c | 14 +++++++-
>> drivers/iommu/arm-smmu-v3.c | 64 +++++++++++++++++++++++++++++-----
>> 4 files changed, 73 insertions(+), 10 deletions(-)
>>
>> --
>> 1.9.1
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> + /*
> + * Override the size, for Cavium CN99xx implementations
> + * which doesn't support the page 1 SMMU register space.
> + */
> + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> + if (cpu_model == MIDR_THUNDERX_99XX ||
> + cpu_model == MIDR_BRCM_VULCAN)
> + size = SZ_64K;
If you're trying to identify an SMMU erratum, identify the SMMU, not the
CPU it happens to be paired with this time.
There are ID registers in the SMMU you can use to do so.
NAK to using the CPU ID here.
Mark.
On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> > + /*
> > + * Override the size, for Cavium CN99xx implementations
> > + * which doesn't support the page 1 SMMU register space.
> > + */
> > + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> > + if (cpu_model == MIDR_THUNDERX_99XX ||
> > + cpu_model == MIDR_BRCM_VULCAN)
> > + size = SZ_64K;
>
> If you're trying to identify an SMMU erratum, identify the SMMU, not the
> CPU it happens to be paired with this time.
>
> There are ID registers in the SMMU you can use to do so.
>
> NAK to using the CPU ID here.
Agreed. I had some off-list discussion with Geetha where we agreed to use
the "silicon ID", which I assumed was the SMMU IIDR register.
Will