Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.
A64 DE2 behaviour similar to Allwinner A83T where mixer0, connected to tcon0
with RGB, LVDS MIPI-DSI and mixer1, connected to tcon1 with HDMI as per
Display System Block DiagramAllwinner_A64_User_Manual_V1.1.pdf
This is the first series on Allwinner A64 DE2 HDMI support which followed
with previous RFC series [1] (thanks to Maxime, Jernej for comments on RFC series)
and rest will add in future patches.
patch 1: dt-bindings for a64 de2 ccu
patch 2: add node support for a64 de2 ccu
patch 3: enable DE2_CCU for Allwinner 64-bit SoCs
patch 4: dt-bindings for a64 de2 pipeline
patch 5: add support for a64 de2
patch 6: defconfig: enable CONFIG_DRM_SUN4I
patch 7 -8: dt-bindings for a64 HDMI and HDMI PHY
patch 9: add support for a64 HDMI
patch 10: enable DesignWare HDMI for Allwinner 64-bit SoCs
patch 11 - 12: dt-bindings for a64 mixer1 and tcon1
patch 13: enable de2 mixer for Allwinner 64-bit SoCs
patch 14: add support for a64 HDMI pipeline
patch 15: add support for HVCC regulator
patch 16: enable HDMI out for bananapi-m64
patch 17: enable HDMI out for nanopi-a64
patch 18: enable HDMI out for orangepi-win
patch 19: enable HDMI out for a64-olinuxino
patch 20: enable HDMI out for pine64
patch 21: enable HDMI out for sopine
Since this series added HDMI through mixer1 through tcon1,
I have used CLK_PLL_VIDEO1 as pll-0 we need to update the driver
to support both CLK_PLL_VIDEO0 and 1 once we have add hdmi through mixer0.
Note:
with pine64 and sopine, I'm unable to see any display on screen but
loadded fine, request to verify anyone.
Log:
---
# modprobe -a sun4i-drm sun8i-mixer sun4i_tv sun4i-drm-hdmi sun8i-drm-hdmi
[ 13.390465] sun4i-drm display-engine: bound 1200000.mixer (ops sun8i_mixer_ops [sun8i_mixer])
[ 13.399247] sun4i-drm display-engine: No panel or bridge found... RGB output disabled
[ 13.407113] sun4i-drm display-engine: bound 1c0d000.lcd-controller (ops sun4i_tcon_ops [sun4i_tcon])
[ 13.417386] sun8i-dw-hdmi 1ee0000.hdmi: Detected HDMI TX controller v1.32a with HDCP (sun8i_dw_hdmi_ph
y)
[ 13.427436] sun8i-dw-hdmi 1ee0000.hdmi: registered DesignWare HDMI I2C bus driver
[ 13.435987] sun4i-drm display-engine: bound 1ee0000.hdmi (ops sun8i_dw_hdmi_ops [sun8i_drm_hdmi])
[ 13.444868] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 13.451498] [drm] No driver support for vblank timestamp query.
[ 13.922226] Console: switching to colour frame buffer device 320x90
[ 14.008789] sun4i-drm display-engine: fb0: frame buffer device
[ 14.028297] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on minor 0
[1] https://lkml.org/lkml/2018/4/24/547
Icenowy Zheng (1):
drm: sun4i: add support for HVCC regulator for DWC HDMI glue
Jagan Teki (20):
dt-bindings: clock: Add compatible for A64 DE2 CCU
arm64: dts: allwinner: a64: Add DE2 CCU
clk: sunxi-ng: Enable DE2_CCU for Allwinner 64-bit SoCs
bindings: display: Add compatible for A64 DE2 pipeline
drm/sun4i: Add support for A64 display engine
arm64: defconfig: Enable CONFIG_DRM_SUN4I
bindings: display: Add compatible for A64 HDMI
bindings: display: Add compatible for A64 HDMI PHY
arm64: dts: allwinner: a64: Add HDMI support
drm/sun4i: Enable DesignWare HDMI for Allwinner 64-bit SoCs
bindings: display: Add compatible for A64 Mixer1
bindings: display: Add compatible for A64 tcon-tv
drm/sun4i: Enable DE2 Mixer for Allwinner 64-bit SoCs
arm64: dts: allwinner: a64: Add HDMI pipeline
arm64: dts: allwinner: a64: bananapi-m64: Enable HDMI output
arm64: dts: allwinner: a64: nanopi-a64: Enable HDMI output
arm64: dts: allwinner: a64: orangepi-win: Enable HDMI output
arm64: dts: allwinner: a64: a64-olinuxino: Enable HDMI output
arm64: dts: allwinner: a64: pine64: Enable HDMI output
arm64: dts: allwinner: a64: sopine: Enable HDMI output
.../devicetree/bindings/clock/sun8i-de2.txt | 1 +
.../bindings/display/sunxi/sun4i-drm.txt | 5 +
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 26 +++++
.../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 26 +++++
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 26 +++++
.../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 26 +++++
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 26 +++++
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 26 +++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 126 +++++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/sunxi-ng/Kconfig | 2 +
drivers/gpu/drm/sun4i/Kconfig | 3 +-
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 +++
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +
include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +
16 files changed, 312 insertions(+), 1 deletion(-)
--
2.14.3
DE2 in A64 has clock control unit and behavior is
same like H3/H5, so reuse the same in A64.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1b2ef28c42bd..67b80bbe5bf5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -43,9 +43,11 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
/ {
interrupt-parent = <&gic>;
@@ -168,6 +170,19 @@
#size-cells = <1>;
ranges;
+ display_clocks: clock@1000000 {
+ compatible = "allwinner,sun50i-a64-de2-clk",
+ "allwinner,sun50i-h5-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
syscon: syscon@1c00000 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
--
2.14.3
Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
as default.
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/clk/sunxi-ng/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 79dfd296c3d1..1fffd3bf6ff3 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -58,6 +58,8 @@ config SUN8I_V3S_CCU
config SUN8I_DE2_CCU
bool "Support for the Allwinner SoCs DE2 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (DRM_SUN4I && (ARM64 && ARCH_SUNXI)) || COMPILE_TEST
config SUN8I_R40_CCU
bool "Support for the Allwinner R40 CCU"
--
2.14.3
Allwinner A64 has DE2 pipeline similar to other Allwinner
SOC's like A83T, H3/H5.
Signed-off-by: Jagan Teki <[email protected]>
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 3346c1e2a7a0..f0fd9274a25d 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -343,6 +343,7 @@ Required properties:
* allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
+ * allwinner,sun50i-a64-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
--
2.14.3
HDMI on Allwinner A64 has similar like H3/H5.
Signed-off-by: Jagan Teki <[email protected]>
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index f0fd9274a25d..9ea4353caadd 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -78,6 +78,7 @@ Required properties:
- compatible: value must be one of:
* "allwinner,sun8i-a83t-dw-hdmi"
+ * "allwinner,sun50i-a64-dw-hdmi"
- reg: base address and size of memory-mapped region
- reg-io-width: See dw_hdmi.txt. Shall be 1.
- interrupts: HDMI interrupt number
--
2.14.3
Allwinner 64-bit SoC like H5/A64 has DesignWare HDMI so
enable them as default.
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/gpu/drm/sun4i/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index eee6bc0eaf97..60468a779a63 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -42,6 +42,7 @@ config DRM_SUN4I_BACKEND
config DRM_SUN8I_DW_HDMI
tristate "Support for Allwinner version of DesignWare HDMI"
+ default ARM64 && ARCH_SUNXI
depends on DRM_SUN4I
select DRM_DW_HDMI
help
--
2.14.3
HDMI on Allwinner A64 has similar behavior like H3/H5, so
reuse the same dts node details for A64.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 28 +++++++++++++++++++++++++++
include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++
2 files changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 67b80bbe5bf5..da9128ae836d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -644,6 +644,34 @@
#interrupt-cells = <3>;
};
+ hdmi: hdmi@1ee0000 {
+ compatible = "allwinner,sun50i-a64-dw-hdmi",
+ "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ status = "disabled";
+ };
+
+ hdmi_phy: hdmi-phy@1ef0000 {
+ compatible = "allwinner,sun50i-a64-hdmi-phy",
+ "allwinner,sun8i-h3-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+ <&ccu CLK_PLL_VIDEO1>;
+ clock-names = "bus", "mod", "pll-0";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index d66432c6e675..41c09df797ef 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -45,6 +45,8 @@
#define CLK_PLL_PERIPH0 11
+#define CLK_PLL_VIDEO1 15
+
#define CLK_BUS_MIPI_DSI 28
#define CLK_BUS_CE 29
#define CLK_BUS_DMA 30
--
2.14.3
tcon-tv on Allwinner A64 has similar behavior like Allwinner A83T.
Signed-off-by: Jagan Teki <[email protected]>
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 5d448ef2132f..8b6b4bc43d98 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -150,6 +150,7 @@ Required properties:
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
+ * allwinner,sun50i-a64-tcon-tv
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON.
--
2.14.3
A64 display engine has two mixers which are connected to
LVDS/RGB/MIPI-DSI and HDMI output through tcon0 and tcon1.
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 50d19605c38f..c84102a750f8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -368,6 +368,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ .compatible = "allwinner,sun9i-a80-display-engine" },
+ { .compatible = "allwinner,sun50i-a64-display-engine" },
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
--
2.14.3
HDMI pipeline on A64 has similar behavior like A83T where
tcon1 is connected to HDMI. So reuse similar dts nodes for A64.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 83 +++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index da9128ae836d..f017baa4f5db 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -107,6 +107,12 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun50i-a64-display-engine";
+ allwinner,pipelines = <&mixer1>;
+ status = "disabled";
+ };
+
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -183,6 +189,31 @@
#reset-cells = <1>;
};
+ mixer1: mixer@1200000 {
+ compatible = "allwinner,sun50i-a64-de2-mixer-1",
+ "allwinner,sun8i-a83t-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint {
+ remote-endpoint = <&tcon1_in_mixer1>;
+ };
+ };
+ };
+ };
+
+
syscon: syscon@1c00000 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
@@ -200,6 +231,41 @@
#dma-cells = <1>;
};
+ tcon1: lcd-controller@1c0d000 {
+ compatible = "allwinner,sun50i-a64-tcon-tv",
+ "allwinner,sun8i-a83t-tcon-tv";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON1>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ reg = <0>;
+
+ tcon1_in_mixer1: endpoint {
+ remote-endpoint = <&mixer1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ };
+ };
+ };
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@@ -658,6 +724,23 @@
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon1: endpoint {
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
};
hdmi_phy: hdmi-phy@1ef0000 {
--
2.14.3
From: Icenowy Zheng <[email protected]>
Allwinner SoCs with DWC HDMI controller have a "HVCC" power pin for the
HDMI part, and on some boards it's connected to a dedicated regulator
rather than the main 3.3v.
Add support for optional HVCC regulator. For boards that doesn't use a
dedicated regulator to power it, the default dummy regulator is used.
Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 ++++++++++++++
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index 9f40a44b456b..7c33faff7ad4 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -73,6 +73,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
if (encoder->possible_crtcs == 0)
return -EPROBE_DEFER;
+ hdmi->vcc_hdmi = devm_regulator_get(dev, "hvcc");
+ if (IS_ERR(hdmi->vcc_hdmi)) {
+ dev_err(dev, "Could not get HDMI power supply\n");
+ return PTR_ERR(hdmi->vcc_hdmi);
+ }
+
hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
if (IS_ERR(hdmi->rst_ctrl)) {
dev_err(dev, "Could not get ctrl reset control\n");
@@ -91,6 +97,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
return ret;
}
+ ret = regulator_enable(hdmi->vcc_hdmi);
+ if (ret) {
+ dev_err(dev, "Cannot enable HDMI power supply\n");
+ goto err_disable_vcc;
+ }
+
ret = clk_prepare_enable(hdmi->clk_tmds);
if (ret) {
dev_err(dev, "Could not enable tmds clock\n");
@@ -143,6 +155,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(hdmi->clk_tmds);
err_assert_ctrl_reset:
reset_control_assert(hdmi->rst_ctrl);
+err_disable_vcc:
+ regulator_disable(hdmi->vcc_hdmi);
return ret;
}
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index 79154f0f674a..c25d75ef9303 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -10,6 +10,7 @@
#include <drm/drm_encoder.h>
#include <linux/clk.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
@@ -173,6 +174,7 @@ struct sun8i_dw_hdmi {
struct drm_encoder encoder;
struct sun8i_hdmi_phy *phy;
struct dw_hdmi_plat_data plat_data;
+ struct regulator *vcc_hdmi;
struct reset_control *rst_ctrl;
};
--
2.14.3
Enable HDMI output on nanopi-a64 board.
Signed-off-by: Jagan Teki <[email protected]>
---
.../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index e2dce48fa29a..19fe7eed45e9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -57,6 +57,21 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+};
+
+&de {
+ status = "okay";
};
&ehci0 {
@@ -67,6 +82,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
/* i2c1 connected with gpio headers like pine64, bananapi */
&i2c1 {
pinctrl-names = "default";
--
2.14.3
Enable HDMI output on Orangepi-win board.
Signed-off-by: Jagan Teki <[email protected]>
---
.../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index bf42690a3361..b6fdd052d473 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -57,12 +57,38 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+};
+
+&de {
+ status = "okay";
};
&ehci1 {
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
--
2.14.3
Enable HDMI output on pine64 board.
Signed-off-by: Jagan Teki <[email protected]>
---
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index a75825798a71..a4ec0900a885 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -62,6 +62,21 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+};
+
+&de {
+ status = "okay";
};
&ehci0 {
@@ -82,6 +97,17 @@
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
--
2.14.3
Enable HDMI output on sopine board.
Signed-off-by: Jagan Teki <[email protected]>
---
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index abe179de35d7..72f29b78117c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
reg_vcc1v8: vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
@@ -69,6 +80,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -86,6 +101,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
--
2.14.3
Enable HDMI output on Bananpi-m64 board.
Signed-off-by: Jagan Teki <[email protected]>
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 2250dec9974c..69063c1fbddf 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -86,6 +97,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -99,6 +114,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
--
2.14.3
Enable HDMI output on a64-olinuxino board.
Signed-off-by: Jagan Teki <[email protected]>
---
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 3b3081b10ecb..83329c8fec4f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -58,12 +58,38 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
--
2.14.3
Allwinner 64-bit SoC like H5/A64 has DE2 Mixer so enable them
as default.
Signed-off-by: Jagan Teki <[email protected]>
---
drivers/gpu/drm/sun4i/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 60468a779a63..95ae04964756 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -52,7 +52,7 @@ config DRM_SUN8I_DW_HDMI
config DRM_SUN8I_MIXER
tristate "Support for Allwinner Display Engine 2.0 Mixer"
- default MACH_SUN8I
+ default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
help
Choose this option if you have an Allwinner SoC with the
Allwinner Display Engine 2.0, which has a mixer to do some
--
2.14.3
HDMI PHY on Allwinner A64 has similar like H3/H5.
Signed-off-by: Jagan Teki <[email protected]>
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 9ea4353caadd..7dcd1d64dfe4 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -104,6 +104,7 @@ Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
+ * allwinner,sun50i-a64-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
* bus: the HDMI PHY interface clock
--
2.14.3
Mixer1 on Allwinner A64 has similar behavior like Allwinner A83T.
Signed-off-by: Jagan Teki <[email protected]>
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 7dcd1d64dfe4..5d448ef2132f 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -313,6 +313,7 @@ Required properties:
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun50i-a64-de2-mixer-1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
--
2.14.3
Enable DRM Support for Allwinner Display Engine, built as a module.
Signed-off-by: Jagan Teki <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 8ac1feafe563..723e6a5121fa 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -410,6 +410,7 @@ CONFIG_DRM_EXYNOS_DSI=y
CONFIG_DRM_EXYNOS_HDMI=y
CONFIG_DRM_EXYNOS_MIC=y
CONFIG_DRM_ROCKCHIP=m
+CONFIG_DRM_SUN4I=m
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_CDN_DP=y
CONFIG_ROCKCHIP_DW_HDMI=y
--
2.14.3
Allwinner A64 has DE2 CCU which is similar to H3/H5 SoC.
Signed-off-by: Jagan Teki <[email protected]>
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index f2fa87c4765c..7f425bc0e820 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -7,6 +7,7 @@ Required properties :
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
+ - "allwinner,sun50i-a64-de2-clk"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
--
2.14.3
On Mon, Apr 30, 2018 at 05:10:38PM +0530, Jagan Teki wrote:
> Allwinner A64 has DE2 CCU which is similar to H3/H5 SoC.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <[email protected]>
On Mon, Apr 30, 2018 at 05:10:41PM +0530, Jagan Teki wrote:
> Allwinner A64 has DE2 pipeline similar to other Allwinner
> SOC's like A83T, H3/H5.
'dt-bindings: ' for the subject prefix.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
> 1 file changed, 1 insertion(+)
Otherwise,
Reviewed-by: Rob Herring <[email protected]>
On Mon, Apr 30, 2018 at 05:10:45PM +0530, Jagan Teki wrote:
> HDMI PHY on Allwinner A64 has similar like H3/H5.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> index 9ea4353caadd..7dcd1d64dfe4 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -104,6 +104,7 @@ Required properties:
> - compatible: value must be one of:
> * allwinner,sun8i-a83t-hdmi-phy
> * allwinner,sun8i-h3-hdmi-phy
> + * allwinner,sun50i-a64-hdmi-phy
This should be one valid combination per line. The dts shows that the h3
string is a fallback which should be captured in the binding doc.
> - reg: base address and size of memory-mapped region
> - clocks: phandles to the clocks feeding the HDMI PHY
> * bus: the HDMI PHY interface clock
> --
> 2.14.3
>
On Wed, May 2, 2018 at 12:16 AM, Rob Herring <[email protected]> wrote:
> On Mon, Apr 30, 2018 at 05:10:38PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 CCU which is similar to H3/H5 SoC.
>>
>> Signed-off-by: Jagan Teki <[email protected]>
>> ---
>> Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 +
>> 1 file changed, 1 insertion(+)
>
> Reviewed-by: Rob Herring <[email protected]>
Hi Rob,
Do we need to add this if it's just a soc-specific compatible
we add in the device tree to future proof things in case we
discover quirks later on?
AFAIK we haven't been doing this, and this is likely to create
some confusion, because they aren't actually mentioned anywhere
in the driver.
ChenYu
On Mon, Apr 30, 2018 at 05:10:48PM +0530, Jagan Teki wrote:
> Mixer1 on Allwinner A64 has similar behavior like Allwinner A83T.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> index 7dcd1d64dfe4..5d448ef2132f 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -313,6 +313,7 @@ Required properties:
> * allwinner,sun8i-a83t-de2-mixer-1
> * allwinner,sun8i-h3-de2-mixer-0
> * allwinner,sun8i-v3s-de2-mixer
> + * allwinner,sun50i-a64-de2-mixer-1
Need to capture fallbacks here.
> - reg: base address and size of the memory-mapped region.
> - clocks: phandles to the clocks feeding the mixer
> * bus: the mixer interface clock
> --
> 2.14.3
>
On Mon, Apr 30, 2018 at 05:10:49PM +0530, Jagan Teki wrote:
> tcon-tv on Allwinner A64 has similar behavior like Allwinner A83T.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> index 5d448ef2132f..8b6b4bc43d98 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -150,6 +150,7 @@ Required properties:
> * allwinner,sun8i-v3s-tcon
> * allwinner,sun9i-a80-tcon-lcd
> * allwinner,sun9i-a80-tcon-tv
> + * allwinner,sun50i-a64-tcon-tv
Fallback?
> - reg: base address and size of memory-mapped region
> - interrupts: interrupt associated to this IP
> - clocks: phandles to the clocks feeding the TCON.
> --
> 2.14.3
>
On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
> HDMI on Allwinner A64 has similar behavior like H3/H5, so
> reuse the same dts node details for A64.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 28 +++++++++++++++++++++++++++
> include/dt-bindings/clock/sun50i-a64-ccu.h | 2 ++
> 2 files changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 67b80bbe5bf5..da9128ae836d 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -644,6 +644,34 @@
> #interrupt-cells = <3>;
> };
>
> + hdmi: hdmi@1ee0000 {
> + compatible = "allwinner,sun50i-a64-dw-hdmi",
> + "allwinner,sun8i-a83t-dw-hdmi";
> + reg = <0x01ee0000 0x10000>;
> + reg-io-width = <1>;
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> + <&ccu CLK_HDMI>;
> + clock-names = "iahb", "isfr", "tmds";
> + resets = <&ccu RST_BUS_HDMI1>;
> + reset-names = "ctrl";
> + phys = <&hdmi_phy>;
> + phy-names = "hdmi-phy";
> + status = "disabled";
> + };
> +
> + hdmi_phy: hdmi-phy@1ef0000 {
> + compatible = "allwinner,sun50i-a64-hdmi-phy",
> + "allwinner,sun8i-h3-hdmi-phy";
> + reg = <0x01ef0000 0x10000>;
> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> + <&ccu CLK_PLL_VIDEO1>;
> + clock-names = "bus", "mod", "pll-0";
> + resets = <&ccu RST_BUS_HDMI0>;
> + reset-names = "phy";
> + #phy-cells = <0>;
HDMI is disabled by default, but the phy is not?
> + };
> +
> rtc: rtc@1f00000 {
> compatible = "allwinner,sun6i-a31-rtc";
> reg = <0x01f00000 0x54>;
> diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
> index d66432c6e675..41c09df797ef 100644
> --- a/include/dt-bindings/clock/sun50i-a64-ccu.h
> +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
> @@ -45,6 +45,8 @@
>
> #define CLK_PLL_PERIPH0 11
>
> +#define CLK_PLL_VIDEO1 15
> +
This belongs in the clock binding patch.
> #define CLK_BUS_MIPI_DSI 28
> #define CLK_BUS_CE 29
> #define CLK_BUS_DMA 30
> --
> 2.14.3
>
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki <[email protected]> wrote:
> Allwinner 64-bit SoC like H5/A64 has DesignWare HDMI so
> enable them as default.
Should we not also enable it by default for SUN8I (A83T, H3, R40?, etc.)
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> drivers/gpu/drm/sun4i/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
> index eee6bc0eaf97..60468a779a63 100644
> --- a/drivers/gpu/drm/sun4i/Kconfig
> +++ b/drivers/gpu/drm/sun4i/Kconfig
> @@ -42,6 +42,7 @@ config DRM_SUN4I_BACKEND
>
> config DRM_SUN8I_DW_HDMI
> tristate "Support for Allwinner version of DesignWare HDMI"
> + default ARM64 && ARCH_SUNXI
> depends on DRM_SUN4I
> select DRM_DW_HDMI
> help
> --
> 2.14.3
>
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki <[email protected]> wrote:
> Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
> as default.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> drivers/clk/sunxi-ng/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 79dfd296c3d1..1fffd3bf6ff3 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -58,6 +58,8 @@ config SUN8I_V3S_CCU
>
> config SUN8I_DE2_CCU
> bool "Support for the Allwinner SoCs DE2 CCU"
> + default ARM64 && ARCH_SUNXI
> + depends on (DRM_SUN4I && (ARM64 && ARCH_SUNXI)) || COMPILE_TEST
There is no reason to depend on DRM_SUN4I. There is no compile dependency.
Also, this is needed on SUN8I as well, pretty much anything with DE 2.0.
So you shouldn't limit it to ARM64. That pretty much breaks things for
people with A83T's or H3's. In fact you should enable it by default for
these as well.
ChenYu
>
> config SUN8I_R40_CCU
> bool "Support for the Allwinner R40 CCU"
> --
> 2.14.3
>
On Wed, May 2, 2018 at 12:17 AM, Rob Herring <[email protected]> wrote:
> On Mon, Apr 30, 2018 at 05:10:41PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 pipeline similar to other Allwinner
>> SOC's like A83T, H3/H5.
>
> 'dt-bindings: ' for the subject prefix.
>
>>
>> Signed-off-by: Jagan Teki <[email protected]>
>> ---
>> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
>> 1 file changed, 1 insertion(+)
>
> Otherwise,
>
> Reviewed-by: Rob Herring <[email protected]>
Would it make sense to put all the display component related compatible
string additions in the same patch? i.e. "Add compatible strings for all
documented display component blocks". MIPI-DSI is missing, but it's not
documented.
ChenYu
On Tue, May 1, 2018 at 11:19 AM, Chen-Yu Tsai <[email protected]> wrote:
> On Wed, May 2, 2018 at 12:16 AM, Rob Herring <[email protected]> wrote:
>> On Mon, Apr 30, 2018 at 05:10:38PM +0530, Jagan Teki wrote:
>>> Allwinner A64 has DE2 CCU which is similar to H3/H5 SoC.
>>>
>>> Signed-off-by: Jagan Teki <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 +
>>> 1 file changed, 1 insertion(+)
>>
>> Reviewed-by: Rob Herring <[email protected]>
>
> Hi Rob,
>
> Do we need to add this if it's just a soc-specific compatible
> we add in the device tree to future proof things in case we
> discover quirks later on?
Yes, but the fallbacks should be documented too as I found in the rest
of the series.
> AFAIK we haven't been doing this, and this is likely to create
> some confusion, because they aren't actually mentioned anywhere
> in the driver.
The binding doc needs to written such that compatible can be validated
to contain the correct set of strings. We can't do that now with free
form text, but when we move to a schema we will.
Rob
On Tue, May 1, 2018 at 11:31 AM, Chen-Yu Tsai <[email protected]> wrote:
> On Wed, May 2, 2018 at 12:17 AM, Rob Herring <[email protected]> wrote:
>> On Mon, Apr 30, 2018 at 05:10:41PM +0530, Jagan Teki wrote:
>>> Allwinner A64 has DE2 pipeline similar to other Allwinner
>>> SOC's like A83T, H3/H5.
>>
>> 'dt-bindings: ' for the subject prefix.
>>
>>>
>>> Signed-off-by: Jagan Teki <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
>>> 1 file changed, 1 insertion(+)
>>
>> Otherwise,
>>
>> Reviewed-by: Rob Herring <[email protected]>
>
> Would it make sense to put all the display component related compatible
> string additions in the same patch? i.e. "Add compatible strings for all
> documented display component blocks". MIPI-DSI is missing, but it's not
> documented.
That's fine by me.
Rob
Hi Rob,
On Tue, May 1, 2018 at 9:49 PM, Rob Herring <[email protected]> wrote:
>
> On Mon, Apr 30, 2018 at 05:10:45PM +0530, Jagan Teki wrote:
> > HDMI PHY on Allwinner A64 has similar like H3/H5.
> >
> > Signed-off-by: Jagan Teki <[email protected]>
> > ---
> > Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > index 9ea4353caadd..7dcd1d64dfe4 100644
> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > @@ -104,6 +104,7 @@ Required properties:
> > - compatible: value must be one of:
> > * allwinner,sun8i-a83t-hdmi-phy
> > * allwinner,sun8i-h3-hdmi-phy
> > + * allwinner,sun50i-a64-hdmi-phy
>
> This should be one valid combination per line. The dts shows that the h3
> string is a fallback which should be captured in the binding doc.
The fallback compatible "allwinner,sun8i-h3-hdmi-phy" is already
documented above, what we need to capture here? or did I miss anything
here?
On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
> DE2 in A64 has clock control unit and behavior is
> same like H3/H5, so reuse the same in A64.
>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1b2ef28c42bd..67b80bbe5bf5 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -43,9 +43,11 @@
> */
>
> #include <dt-bindings/clock/sun50i-a64-ccu.h>
> +#include <dt-bindings/clock/sun8i-de2.h>
> #include <dt-bindings/clock/sun8i-r-ccu.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/sun50i-a64-ccu.h>
> +#include <dt-bindings/reset/sun8i-de2.h>
>
> / {
> interrupt-parent = <&gic>;
> @@ -168,6 +170,19 @@
> #size-cells = <1>;
> ranges;
>
> + display_clocks: clock@1000000 {
> + compatible = "allwinner,sun50i-a64-de2-clk",
> + "allwinner,sun50i-h5-de2-clk";
The A64 was released before the H5, so that should be the other way
around.
> + reg = <0x01000000 0x100000>;
> + clocks = <&ccu CLK_DE>,
> + <&ccu CLK_BUS_DE>;
> + clock-names = "mod",
> + "bus";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
So it turns out we don't need the SRAM to access the CCU driver?
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
Hi,
On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
> + hdmi_phy: hdmi-phy@1ef0000 {
> + compatible = "allwinner,sun50i-a64-hdmi-phy",
> + "allwinner,sun8i-h3-hdmi-phy";
> + reg = <0x01ef0000 0x10000>;
> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> + <&ccu CLK_PLL_VIDEO1>;
You were discussing that the PLL0 could also be used to clock the PHY,
has that been figured out?
Thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard <[email protected]> 写到:
>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>> DE2 in A64 has clock control unit and behavior is
>> same like H3/H5, so reuse the same in A64.
>>
>> Signed-off-by: Jagan Teki <[email protected]>
>> ---
>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> index 1b2ef28c42bd..67b80bbe5bf5 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>> @@ -43,9 +43,11 @@
>> */
>>
>> #include <dt-bindings/clock/sun50i-a64-ccu.h>
>> +#include <dt-bindings/clock/sun8i-de2.h>
>> #include <dt-bindings/clock/sun8i-r-ccu.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/reset/sun50i-a64-ccu.h>
>> +#include <dt-bindings/reset/sun8i-de2.h>
>>
>> / {
>> interrupt-parent = <&gic>;
>> @@ -168,6 +170,19 @@
>> #size-cells = <1>;
>> ranges;
>>
>> + display_clocks: clock@1000000 {
>> + compatible = "allwinner,sun50i-a64-de2-clk",
>> + "allwinner,sun50i-h5-de2-clk";
>
>The A64 was released before the H5, so that should be the other way
>around.
>
>> + reg = <0x01000000 0x100000>;
>> + clocks = <&ccu CLK_DE>,
>> + <&ccu CLK_BUS_DE>;
>> + clock-names = "mod",
>> + "bus";
>> + resets = <&ccu RST_BUS_DE>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>
>So it turns out we don't need the SRAM to access the CCU driver?
As now U-Boot claims SRAM, people may forget thus :-(
>
>Maxime
On Mon, Apr 30, 2018 at 05:10:52PM +0530, Jagan Teki wrote:
> From: Icenowy Zheng <[email protected]>
>
> Allwinner SoCs with DWC HDMI controller have a "HVCC" power pin for the
> HDMI part, and on some boards it's connected to a dedicated regulator
> rather than the main 3.3v.
>
> Add support for optional HVCC regulator. For boards that doesn't use a
> dedicated regulator to power it, the default dummy regulator is used.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 ++++++++++++++
> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> index 9f40a44b456b..7c33faff7ad4 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
> @@ -73,6 +73,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
> if (encoder->possible_crtcs == 0)
> return -EPROBE_DEFER;
>
> + hdmi->vcc_hdmi = devm_regulator_get(dev, "hvcc");
> + if (IS_ERR(hdmi->vcc_hdmi)) {
> + dev_err(dev, "Could not get HDMI power supply\n");
> + return PTR_ERR(hdmi->vcc_hdmi);
> + }
> +
You're not making it optional here, unlike what your commit log
says. Not that I'm fine with both, but we need to be consistent :)
> hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
> if (IS_ERR(hdmi->rst_ctrl)) {
> dev_err(dev, "Could not get ctrl reset control\n");
> @@ -91,6 +97,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
> return ret;
> }
>
> + ret = regulator_enable(hdmi->vcc_hdmi);
> + if (ret) {
> + dev_err(dev, "Cannot enable HDMI power supply\n");
> + goto err_disable_vcc;
> + }
> +
> ret = clk_prepare_enable(hdmi->clk_tmds);
> if (ret) {
> dev_err(dev, "Could not enable tmds clock\n");
> @@ -143,6 +155,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
> clk_disable_unprepare(hdmi->clk_tmds);
> err_assert_ctrl_reset:
> reset_control_assert(hdmi->rst_ctrl);
> +err_disable_vcc:
> + regulator_disable(hdmi->vcc_hdmi);
The err_disable_vcc label will disable the regulator, but if there's
an error in regulator_enable, it will disable it while it wasn't
enabled in the first place, which is not really something we want to
do.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
On Wed, May 2, 2018 at 5:04 PM, Icenowy Zheng <[email protected]> wrote:
>
>
> 于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard <[email protected]> 写到:
>>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>>> DE2 in A64 has clock control unit and behavior is
>>> same like H3/H5, so reuse the same in A64.
>>>
>>> Signed-off-by: Jagan Teki <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
>>> 1 file changed, 15 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>> index 1b2ef28c42bd..67b80bbe5bf5 100644
>>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>> @@ -43,9 +43,11 @@
>>> */
>>>
>>> #include <dt-bindings/clock/sun50i-a64-ccu.h>
>>> +#include <dt-bindings/clock/sun8i-de2.h>
>>> #include <dt-bindings/clock/sun8i-r-ccu.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/reset/sun50i-a64-ccu.h>
>>> +#include <dt-bindings/reset/sun8i-de2.h>
>>>
>>> / {
>>> interrupt-parent = <&gic>;
>>> @@ -168,6 +170,19 @@
>>> #size-cells = <1>;
>>> ranges;
>>>
>>> + display_clocks: clock@1000000 {
>>> + compatible = "allwinner,sun50i-a64-de2-clk",
>>> + "allwinner,sun50i-h5-de2-clk";
>>
>>The A64 was released before the H5, so that should be the other way
>>around.
>>
>>> + reg = <0x01000000 0x100000>;
>>> + clocks = <&ccu CLK_DE>,
>>> + <&ccu CLK_BUS_DE>;
>>> + clock-names = "mod",
>>> + "bus";
>>> + resets = <&ccu RST_BUS_DE>;
>>> + #clock-cells = <1>;
>>> + #reset-cells = <1>;
>>> + };
>>> +
>>
>>So it turns out we don't need the SRAM to access the CCU driver?
>
> As now U-Boot claims SRAM, people may forget thus :-(
I've sent few mails about how we represent de2 with sram_c [1] but
none response after. Can I get further inputs so-that we can include
sram_c in proper manner.
[1] https://patchwork.kernel.org/patch/10289737/
Jagan.
On Wed, May 02, 2018 at 07:34:21PM +0800, Icenowy Zheng wrote:
>
>
> 于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard <[email protected]> 写到:
> >On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
> >> DE2 in A64 has clock control unit and behavior is
> >> same like H3/H5, so reuse the same in A64.
> >>
> >> Signed-off-by: Jagan Teki <[email protected]>
> >> ---
> >> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
> >> 1 file changed, 15 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> index 1b2ef28c42bd..67b80bbe5bf5 100644
> >> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> @@ -43,9 +43,11 @@
> >> */
> >>
> >> #include <dt-bindings/clock/sun50i-a64-ccu.h>
> >> +#include <dt-bindings/clock/sun8i-de2.h>
> >> #include <dt-bindings/clock/sun8i-r-ccu.h>
> >> #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> #include <dt-bindings/reset/sun50i-a64-ccu.h>
> >> +#include <dt-bindings/reset/sun8i-de2.h>
> >>
> >> / {
> >> interrupt-parent = <&gic>;
> >> @@ -168,6 +170,19 @@
> >> #size-cells = <1>;
> >> ranges;
> >>
> >> + display_clocks: clock@1000000 {
> >> + compatible = "allwinner,sun50i-a64-de2-clk",
> >> + "allwinner,sun50i-h5-de2-clk";
> >
> >The A64 was released before the H5, so that should be the other way
> >around.
> >
> >> + reg = <0x01000000 0x100000>;
> >> + clocks = <&ccu CLK_DE>,
> >> + <&ccu CLK_BUS_DE>;
> >> + clock-names = "mod",
> >> + "bus";
> >> + resets = <&ccu RST_BUS_DE>;
> >> + #clock-cells = <1>;
> >> + #reset-cells = <1>;
> >> + };
> >> +
> >
> >So it turns out we don't need the SRAM to access the CCU driver?
>
> As now U-Boot claims SRAM, people may forget thus :-(
This is definitely not ok. We should have that described in the DT as
well.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
于 2018年5月2日 GMT+08:00 下午7:48:43, Maxime Ripard <[email protected]> 写到:
>On Mon, Apr 30, 2018 at 05:10:52PM +0530, Jagan Teki wrote:
>> From: Icenowy Zheng <[email protected]>
>>
>> Allwinner SoCs with DWC HDMI controller have a "HVCC" power pin for
>the
>> HDMI part, and on some boards it's connected to a dedicated regulator
>> rather than the main 3.3v.
>>
>> Add support for optional HVCC regulator. For boards that doesn't use
>a
>> dedicated regulator to power it, the default dummy regulator is used.
>>
>> Signed-off-by: Icenowy Zheng <[email protected]>
>> Signed-off-by: Jagan Teki <[email protected]>
>> ---
>> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 ++++++++++++++
>> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
>> 2 files changed, 16 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>> index 9f40a44b456b..7c33faff7ad4 100644
>> --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>> +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
>> @@ -73,6 +73,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
>struct device *master,
>> if (encoder->possible_crtcs == 0)
>> return -EPROBE_DEFER;
>>
>> + hdmi->vcc_hdmi = devm_regulator_get(dev, "hvcc");
>> + if (IS_ERR(hdmi->vcc_hdmi)) {
>> + dev_err(dev, "Could not get HDMI power supply\n");
>> + return PTR_ERR(hdmi->vcc_hdmi);
>> + }
>> +
>
>You're not making it optional here, unlike what your commit log
>says. Not that I'm fine with both, but we need to be consistent :)
If it's not set, regulator subsystem will generate a dummy
regulator as a spaceholder, except using the exclusive variant
of the function.
The word "optional" is from DT perspectove, as it's possible that
it's bound to some critical regulators.
>
>> hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
>> if (IS_ERR(hdmi->rst_ctrl)) {
>> dev_err(dev, "Could not get ctrl reset control\n");
>> @@ -91,6 +97,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
>struct device *master,
>> return ret;
>> }
>>
>> + ret = regulator_enable(hdmi->vcc_hdmi);
>> + if (ret) {
>> + dev_err(dev, "Cannot enable HDMI power supply\n");
>> + goto err_disable_vcc;
>> + }
>> +
>> ret = clk_prepare_enable(hdmi->clk_tmds);
>> if (ret) {
>> dev_err(dev, "Could not enable tmds clock\n");
>> @@ -143,6 +155,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev,
>struct device *master,
>> clk_disable_unprepare(hdmi->clk_tmds);
>> err_assert_ctrl_reset:
>> reset_control_assert(hdmi->rst_ctrl);
>> +err_disable_vcc:
>> + regulator_disable(hdmi->vcc_hdmi);
>
>
>The err_disable_vcc label will disable the regulator, but if there's
>an error in regulator_enable, it will disable it while it wasn't
>enabled in the first place, which is not really something we want to
>do.
>
>Maxime
于 2018年5月2日 GMT+08:00 下午7:50:19, Jagan Teki <[email protected]> 写到:
>On Wed, May 2, 2018 at 5:04 PM, Icenowy Zheng <[email protected]> wrote:
>>
>>
>> 于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard
><[email protected]> 写到:
>>>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>>>> DE2 in A64 has clock control unit and behavior is
>>>> same like H3/H5, so reuse the same in A64.
>>>>
>>>> Signed-off-by: Jagan Teki <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
>>>> 1 file changed, 15 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> index 1b2ef28c42bd..67b80bbe5bf5 100644
>>>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>> @@ -43,9 +43,11 @@
>>>> */
>>>>
>>>> #include <dt-bindings/clock/sun50i-a64-ccu.h>
>>>> +#include <dt-bindings/clock/sun8i-de2.h>
>>>> #include <dt-bindings/clock/sun8i-r-ccu.h>
>>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>> #include <dt-bindings/reset/sun50i-a64-ccu.h>
>>>> +#include <dt-bindings/reset/sun8i-de2.h>
>>>>
>>>> / {
>>>> interrupt-parent = <&gic>;
>>>> @@ -168,6 +170,19 @@
>>>> #size-cells = <1>;
>>>> ranges;
>>>>
>>>> + display_clocks: clock@1000000 {
>>>> + compatible = "allwinner,sun50i-a64-de2-clk",
>>>> + "allwinner,sun50i-h5-de2-clk";
>>>
>>>The A64 was released before the H5, so that should be the other way
>>>around.
>>>
>>>> + reg = <0x01000000 0x100000>;
>>>> + clocks = <&ccu CLK_DE>,
>>>> + <&ccu CLK_BUS_DE>;
>>>> + clock-names = "mod",
>>>> + "bus";
>>>> + resets = <&ccu RST_BUS_DE>;
>>>> + #clock-cells = <1>;
>>>> + #reset-cells = <1>;
>>>> + };
>>>> +
>>>
>>>So it turns out we don't need the SRAM to access the CCU driver?
>>
>> As now U-Boot claims SRAM, people may forget thus :-(
>
>I've sent few mails about how we represent de2 with sram_c [1] but
>none response after. Can I get further inputs so-that we can include
>sram_c in proper manner.
Please wait for the SRAMC driver sent by Chen-Yu (and commited
by me) and the DE2 bus driver pending for the SRAMC part.
>
>[1] https://patchwork.kernel.org/patch/10289737/
>
>Jagan.
>
>_______________________________________________
>linux-arm-kernel mailing list
>[email protected]
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Wed, May 2, 2018 at 1:27 AM, Jagan Teki <[email protected]> wrote:
> Hi Rob,
>
> On Tue, May 1, 2018 at 9:49 PM, Rob Herring <[email protected]> wrote:
>>
>> On Mon, Apr 30, 2018 at 05:10:45PM +0530, Jagan Teki wrote:
>> > HDMI PHY on Allwinner A64 has similar like H3/H5.
>> >
>> > Signed-off-by: Jagan Teki <[email protected]>
>> > ---
>> > Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
>> > 1 file changed, 1 insertion(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > index 9ea4353caadd..7dcd1d64dfe4 100644
>> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > @@ -104,6 +104,7 @@ Required properties:
>> > - compatible: value must be one of:
>> > * allwinner,sun8i-a83t-hdmi-phy
>> > * allwinner,sun8i-h3-hdmi-phy
>> > + * allwinner,sun50i-a64-hdmi-phy
>>
>> This should be one valid combination per line. The dts shows that the h3
>> string is a fallback which should be captured in the binding doc.
>
> The fallback compatible "allwinner,sun8i-h3-hdmi-phy" is already
> documented above, what we need to capture here? or did I miss anything
> here?
The documentation should make it clear which of these is valid in a dts:
"allwinner,sun50i-a64-hdmi-phy", "allwinner,sun8i-h3-hdmi-phy"
or:
"allwinner,sun50i-a64-hdmi-phy"
IOW, your list should look like this:
* "allwinner,sun8i-a83t-hdmi-phy", "allwinner,sun8i-h3-hdmi-phy"
* "allwinner,sun50i-a64-hdmi-phy", "allwinner,sun8i-h3-hdmi-phy"
* "allwinner,sun8i-h3-hdmi-phy"
Depending on whether the a83t is also compatible with h3.
Rob
On Tue, May 1, 2018 at 9:53 PM, Chen-Yu Tsai <[email protected]> wrote:
> On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki <[email protected]> wrote:
>> Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
>> as default.
>>
>> Signed-off-by: Jagan Teki <[email protected]>
>> ---
>> drivers/clk/sunxi-ng/Kconfig | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
>> index 79dfd296c3d1..1fffd3bf6ff3 100644
>> --- a/drivers/clk/sunxi-ng/Kconfig
>> +++ b/drivers/clk/sunxi-ng/Kconfig
>> @@ -58,6 +58,8 @@ config SUN8I_V3S_CCU
>>
>> config SUN8I_DE2_CCU
>> bool "Support for the Allwinner SoCs DE2 CCU"
>> + default ARM64 && ARCH_SUNXI
>> + depends on (DRM_SUN4I && (ARM64 && ARCH_SUNXI)) || COMPILE_TEST
>
> There is no reason to depend on DRM_SUN4I. There is no compile dependency.
Since this CCU is for DE2 I've make DRM_SUN4I for that matter, any problem?
>
> Also, this is needed on SUN8I as well, pretty much anything with DE 2.0.
> So you shouldn't limit it to ARM64. That pretty much breaks things for
> people with A83T's or H3's. In fact you should enable it by default for
> these as well.
True, I've skipped SUN8I since this series for A64.
Jagan.
--
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
On Wed, May 2, 2018 at 5:04 PM, Maxime Ripard <[email protected]> wrote:
> Hi,
>
> On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
>> + hdmi_phy: hdmi-phy@1ef0000 {
>> + compatible = "allwinner,sun50i-a64-hdmi-phy",
>> + "allwinner,sun8i-h3-hdmi-phy";
>> + reg = <0x01ef0000 0x10000>;
>> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
>> + <&ccu CLK_PLL_VIDEO1>;
>
> You were discussing that the PLL0 could also be used to clock the PHY,
> has that been figured out?
This is what I understand from Fig: 3-3. Module Clock Diagram, both
tcon0 and tcon1 are using HDMI. I'm thinking based on the tcon
configuration we need use proper PLL or some logic to get common PLL
don't know yet. Since this series adding tcon1 I've attached PLL1.
Jagan.
--
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
On Mon, May 14, 2018 at 02:03:36PM +0530, Jagan Teki wrote:
> On Wed, May 2, 2018 at 5:04 PM, Maxime Ripard <[email protected]> wrote:
> > Hi,
> >
> > On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
> >> + hdmi_phy: hdmi-phy@1ef0000 {
> >> + compatible = "allwinner,sun50i-a64-hdmi-phy",
> >> + "allwinner,sun8i-h3-hdmi-phy";
> >> + reg = <0x01ef0000 0x10000>;
> >> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> >> + <&ccu CLK_PLL_VIDEO1>;
> >
> > You were discussing that the PLL0 could also be used to clock the PHY,
> > has that been figured out?
>
> This is what I understand from Fig: 3-3. Module Clock Diagram, both
> tcon0 and tcon1 are using HDMI. I'm thinking based on the tcon
> configuration we need use proper PLL or some logic to get common PLL
> don't know yet. Since this series adding tcon1 I've attached PLL1.
You're not describing the TCON node here though, but the HDMI one, and
the HDMI block is listed in both the PLL video 0 and 1.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
On Mon, May 14, 2018 at 2:10 PM, Maxime Ripard
<[email protected]> wrote:
> On Mon, May 14, 2018 at 02:03:36PM +0530, Jagan Teki wrote:
>> On Wed, May 2, 2018 at 5:04 PM, Maxime Ripard <[email protected]> wrote:
>> > Hi,
>> >
>> > On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
>> >> + hdmi_phy: hdmi-phy@1ef0000 {
>> >> + compatible = "allwinner,sun50i-a64-hdmi-phy",
>> >> + "allwinner,sun8i-h3-hdmi-phy";
>> >> + reg = <0x01ef0000 0x10000>;
>> >> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
>> >> + <&ccu CLK_PLL_VIDEO1>;
>> >
>> > You were discussing that the PLL0 could also be used to clock the PHY,
>> > has that been figured out?
>>
>> This is what I understand from Fig: 3-3. Module Clock Diagram, both
>> tcon0 and tcon1 are using HDMI. I'm thinking based on the tcon
>> configuration we need use proper PLL or some logic to get common PLL
>> don't know yet. Since this series adding tcon1 I've attached PLL1.
>
> You're not describing the TCON node here though, but the HDMI one, and
> the HDMI block is listed in both the PLL video 0 and 1.
So how can we attach particular PLL with particular HDMI(PLL0 to HDMI0
and so-on) or do we need to attached both the PLL's any suggestion?
On Mon, May 14, 2018 at 1:20 AM, Jagan Teki <[email protected]> wrote:
> On Tue, May 1, 2018 at 9:53 PM, Chen-Yu Tsai <[email protected]> wrote:
>> On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki <[email protected]> wrote:
>>> Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
>>> as default.
>>>
>>> Signed-off-by: Jagan Teki <[email protected]>
>>> ---
>>> drivers/clk/sunxi-ng/Kconfig | 2 ++
>>> 1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
>>> index 79dfd296c3d1..1fffd3bf6ff3 100644
>>> --- a/drivers/clk/sunxi-ng/Kconfig
>>> +++ b/drivers/clk/sunxi-ng/Kconfig
>>> @@ -58,6 +58,8 @@ config SUN8I_V3S_CCU
>>>
>>> config SUN8I_DE2_CCU
>>> bool "Support for the Allwinner SoCs DE2 CCU"
>>> + default ARM64 && ARCH_SUNXI
>>> + depends on (DRM_SUN4I && (ARM64 && ARCH_SUNXI)) || COMPILE_TEST
>>
>> There is no reason to depend on DRM_SUN4I. There is no compile dependency.
>
> Since this CCU is for DE2 I've make DRM_SUN4I for that matter, any problem?
Users may very well be just using simplefb, but with all the clock drivers
enabled. That is a valid, if very limited, use case. So again, you should
not limit this driver based on DRM_SUN4I. There is no compile dependency.
>
>>
>> Also, this is needed on SUN8I as well, pretty much anything with DE 2.0.
>> So you shouldn't limit it to ARM64. That pretty much breaks things for
>> people with A83T's or H3's. In fact you should enable it by default for
>> these as well.
>
> True, I've skipped SUN8I since this series for A64.
And yet you are breaking existing users, which is a big no-no.
ChenYu
On Mon, May 14, 2018 at 04:01:15PM +0530, Jagan Teki wrote:
> On Mon, May 14, 2018 at 2:10 PM, Maxime Ripard
> <[email protected]> wrote:
> > On Mon, May 14, 2018 at 02:03:36PM +0530, Jagan Teki wrote:
> >> On Wed, May 2, 2018 at 5:04 PM, Maxime Ripard <[email protected]> wrote:
> >> > Hi,
> >> >
> >> > On Mon, Apr 30, 2018 at 05:10:46PM +0530, Jagan Teki wrote:
> >> >> + hdmi_phy: hdmi-phy@1ef0000 {
> >> >> + compatible = "allwinner,sun50i-a64-hdmi-phy",
> >> >> + "allwinner,sun8i-h3-hdmi-phy";
> >> >> + reg = <0x01ef0000 0x10000>;
> >> >> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> >> >> + <&ccu CLK_PLL_VIDEO1>;
> >> >
> >> > You were discussing that the PLL0 could also be used to clock the PHY,
> >> > has that been figured out?
> >>
> >> This is what I understand from Fig: 3-3. Module Clock Diagram, both
> >> tcon0 and tcon1 are using HDMI. I'm thinking based on the tcon
> >> configuration we need use proper PLL or some logic to get common PLL
> >> don't know yet. Since this series adding tcon1 I've attached PLL1.
> >
> > You're not describing the TCON node here though, but the HDMI one, and
> > the HDMI block is listed in both the PLL video 0 and 1.
>
> So how can we attach particular PLL with particular HDMI(PLL0 to HDMI0
> and so-on) or do we need to attached both the PLL's any suggestion?
I'm not sure what your question is here, just add the possibility to
have an extra PLL if that makes sense to the binding.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com