Hi all,
This series extends support of SPI protocols to new protocols such as
SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
op codes, timing parameters (number of mode and dummy cycles) and erase
sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
tables, when available, as defined in the JEDEC JESD216 specifications.
When SFDP tables are not available, legacy settings are still used for
backward compatibility (SPI and earlier QSPI memories).
Support of SPI memories >128Mbits is also improved by using the 4byte
address instruction set, when available. Using those dedicated op codes
is stateless as opposed to enter the 4byte address mode, hence a better
compatibility with some boot loaders which expect to use 3byte address
op codes.
This series was tested on a Atmel sama5d2 xplained board with the
atmel-qspi.c driver. Except for SST memories, the SPI bus clock was set
to 83MHz. The config MTD_SPI_NOR_USE_4K_SECTORS was selected.
For my tests, I used some shell scripts using mtd_debug and sha1sum to
check the data integrity.
e.g:
#!/bin/sh
mtd_debug erase /dev/mtd5 0 0x780000
mtd_debug write /dev/mtd5 0 7674703 sama5d4_doc11238.pdf
mtd_debug read /dev/mtd5 0 7674703 sam5d4_tmp.pdf
sha1sum sama5d4_doc11238.pdf sam5d4_tmp.pdf
Depending on the actual memory size, I may have used other partitions
(/dev/mtd4) and input file size (2880044 and 320044 bytes).
The series was tested with the following QSPI memories:
Spansion/Cypress:
- s25fl127s OK
- s25fl512s OK
- s25fl164k OK
Micron:
- n25q128a OK
Macronix:
- mx25l6433f OK
- mx25l6473f OK
- mx25l12835f OK
- mx25l12845g OK
- mx25l12873g OK
- mx25l25645g OK
- mx25l25673g OK
- mx25l51245g OK
- mx66l1g45g OK (1)
SST:
- sst26vf016b OK (2)
- sst26vf032b OK (2)
- sst26vf064b OK (2)
(1): requires patch 8
(2): requires patch 9, the SPI bus clock frequency was decreased down to 55.3MHz
Best regards,
Cyrille
ChangeLog:
v1 -> v2
- fix patch 3 to resolve compiler errors on hisi-sfc.c and cadence-quadspi.c
drivers
Cyrille Pitchen (9):
mtd: spi-nor: improve macronix_quad_enable()
mtd: spi-nor: add an alternative method to support memory >16MiB
mtd: spi-nor: add support of SPI protocols like SPI 1-2-2 and SPI
1-4-4
mtd: spi-nor: remove unused set_quad_mode() function
mtd: m25p80: add support of dual and quad spi protocols to all
commands
mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables
mtd: spi-nor: parse SFDP 4-byte Address Instruction Table
mtd: spi-nor: add support to Macronix mx66l1g45g
mtd: spi-nor: add support to SST sst26* QSPI memories
drivers/mtd/devices/m25p80.c | 204 +++++--
drivers/mtd/devices/serial_flash_cmds.h | 7 -
drivers/mtd/devices/st_spi_fsm.c | 28 +-
drivers/mtd/spi-nor/atmel-quadspi.c | 83 ++-
drivers/mtd/spi-nor/cadence-quadspi.c | 18 +-
drivers/mtd/spi-nor/fsl-quadspi.c | 8 +-
drivers/mtd/spi-nor/hisi-sfc.c | 32 +-
drivers/mtd/spi-nor/mtk-quadspi.c | 16 +-
drivers/mtd/spi-nor/nxp-spifi.c | 21 +-
drivers/mtd/spi-nor/spi-nor.c | 1013 ++++++++++++++++++++++++++++---
include/linux/mtd/spi-nor.h | 165 ++++-
11 files changed, 1359 insertions(+), 236 deletions(-)
--
2.7.4
The patch checks whether the Quad Enable bit is already set in the Status
Register. If so, the function exits immediately with a successful return
code. Otherwise, a message is now printed telling we're setting the
non-volatile bit.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index d0fc165d7d66..5c87b2d99507 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1211,6 +1211,11 @@ static int macronix_quad_enable(struct spi_nor *nor)
val = read_sr(nor);
if (val < 0)
return val;
+ if (val & SR_QUAD_EN_MX)
+ return 0;
+
+ /* Update the Quad Enable bit. */
+ dev_info(nor->dev, "setting Macronix Quad Enable (non-volatile) bit\n");
write_enable(nor);
write_sr(nor, val | SR_QUAD_EN_MX);
--
2.7.4
This patch provides an alternative mean to support memory above 16MiB
(128Mib) by replacing 3byte address op codes by their associated 4byte
address versions.
Using the dedicated 4byte address op codes doesn't change the internal
state of the SPI NOR memory as opposed to using other means such as
updating a Base Address Register (BAR) and sending command to enter/leave
the 4byte mode.
Hence when a CPU reset occurs, early bootloaders don't need to be aware
of BAR value or 4byte mode being enabled: they can still access the first
16MiB of the SPI NOR memory using the regular 3byte address op codes.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/devices/serial_flash_cmds.h | 7 ---
drivers/mtd/devices/st_spi_fsm.c | 28 ++++-----
drivers/mtd/spi-nor/spi-nor.c | 104 +++++++++++++++++++++++++-------
include/linux/mtd/spi-nor.h | 22 +++++--
4 files changed, 113 insertions(+), 48 deletions(-)
diff --git a/drivers/mtd/devices/serial_flash_cmds.h b/drivers/mtd/devices/serial_flash_cmds.h
index f59a125295d0..8b81e15105dd 100644
--- a/drivers/mtd/devices/serial_flash_cmds.h
+++ b/drivers/mtd/devices/serial_flash_cmds.h
@@ -18,19 +18,12 @@
#define SPINOR_OP_RDVCR 0x85
/* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
-#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */
-#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */
-
#define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
#define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
#define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
#define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
#define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
-/* READ commands with 32-bit addressing */
-#define SPINOR_OP_READ4_1_2_2 0xbc
-#define SPINOR_OP_READ4_1_4_4 0xec
-
/* Configuration flags */
#define FLASH_FLAG_SINGLE 0x000000ff
#define FLASH_FLAG_READ_WRITE 0x00000001
diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
index 5454b4113589..804313a33f2b 100644
--- a/drivers/mtd/devices/st_spi_fsm.c
+++ b/drivers/mtd/devices/st_spi_fsm.c
@@ -507,13 +507,13 @@ static struct seq_rw_config n25q_read3_configs[] = {
* - 'FAST' variants configured for 8 dummy cycles (see note above.)
*/
static struct seq_rw_config n25q_read4_configs[] = {
- {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
- {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
- {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
- {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
- {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
- {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
- {0x00, 0, 0, 0, 0, 0x00, 0, 0},
+ {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8},
+ {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
+ {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8},
+ {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
+ {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
+ {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
+ {0x00, 0, 0, 0, 0, 0x00, 0, 0},
};
/*
@@ -553,13 +553,13 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq)
* entering a state that is incompatible with the SPIBoot Controller.
*/
static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
- {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
- {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
- {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
- {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
- {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
- {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
- {0x00, 0, 0, 0, 0, 0x00, 0, 0},
+ {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 2, 4},
+ {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
+ {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 4, 0},
+ {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
+ {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
+ {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
+ {0x00, 0, 0, 0, 0, 0x00, 0, 0},
};
static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 5c87b2d99507..423448c1c7a8 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -75,6 +75,10 @@ struct flash_info {
* bit. Must be used with
* SPI_NOR_HAS_LOCK.
*/
+#define SPI_NOR_4B_OPCODES BIT(10) /*
+ * Use dedicated 4byte address op codes
+ * to support memory size above 128Mib.
+ */
};
#define JEDEC_MFR(info) ((info)->id[0])
@@ -188,6 +192,81 @@ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
+
+struct spi_nor_address_entry {
+ u8 src_opcode;
+ u8 dst_opcode;
+};
+
+static u8 spi_nor_convert_opcode(u8 opcode,
+ const struct spi_nor_address_entry *entries,
+ size_t num_entries)
+{
+ int min, max;
+
+ min = 0;
+ max = num_entries - 1;
+ while (min <= max) {
+ int mid = (min + max) >> 1;
+ const struct spi_nor_address_entry *entry = &entries[mid];
+
+ if (opcode == entry->src_opcode)
+ return entry->dst_opcode;
+
+ if (opcode < entry->src_opcode)
+ max = mid - 1;
+ else
+ min = mid + 1;
+ }
+
+ /* No conversion found */
+ return opcode;
+}
+
+static u8 spi_nor_3to4_opcode(u8 opcode)
+{
+ /* MUST be sorted by 3byte opcode */
+#define ENTRY_3TO4(_opcode) { _opcode, _opcode##_4B }
+ static const struct spi_nor_address_entry spi_nor_3to4_table[] = {
+ ENTRY_3TO4(SPINOR_OP_PP), /* 0x02 */
+ ENTRY_3TO4(SPINOR_OP_READ), /* 0x03 */
+ ENTRY_3TO4(SPINOR_OP_READ_FAST), /* 0x0b */
+ ENTRY_3TO4(SPINOR_OP_BE_4K), /* 0x20 */
+ ENTRY_3TO4(SPINOR_OP_PP_1_1_4), /* 0x32 */
+ ENTRY_3TO4(SPINOR_OP_PP_1_4_4), /* 0x38 */
+ ENTRY_3TO4(SPINOR_OP_READ_1_1_2), /* 0x3b */
+ ENTRY_3TO4(SPINOR_OP_BE_32K), /* 0x52 */
+ ENTRY_3TO4(SPINOR_OP_READ_1_1_4), /* 0x6b */
+ ENTRY_3TO4(SPINOR_OP_READ_1_2_2), /* 0xbb */
+ ENTRY_3TO4(SPINOR_OP_SE), /* 0xd8 */
+ ENTRY_3TO4(SPINOR_OP_READ_1_4_4), /* 0xeb */
+ };
+#undef ENTRY_3TO4
+
+ return spi_nor_convert_opcode(opcode, spi_nor_3to4_table,
+ ARRAY_SIZE(spi_nor_3to4_table));
+}
+
+static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
+ const struct flash_info *info)
+{
+ /* Do some manufacturer fixups first */
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_SPANSION:
+ /* No small sector erase for 4-byte command set */
+ nor->erase_opcode = SPINOR_OP_SE;
+ nor->mtd.erasesize = info->sector_size;
+ break;
+
+ default:
+ break;
+ }
+
+ nor->read_opcode = spi_nor_3to4_opcode(nor->read_opcode);
+ nor->program_opcode = spi_nor_3to4_opcode(nor->program_opcode);
+ nor->erase_opcode = spi_nor_3to4_opcode(nor->erase_opcode);
+}
+
/* Enable/disable 4-byte addressing mode. */
static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
int enable)
@@ -1476,27 +1555,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
else if (mtd->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
- if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
- /* Dedicated 4-byte command set */
- switch (nor->flash_read) {
- case SPI_NOR_QUAD:
- nor->read_opcode = SPINOR_OP_READ4_1_1_4;
- break;
- case SPI_NOR_DUAL:
- nor->read_opcode = SPINOR_OP_READ4_1_1_2;
- break;
- case SPI_NOR_FAST:
- nor->read_opcode = SPINOR_OP_READ4_FAST;
- break;
- case SPI_NOR_NORMAL:
- nor->read_opcode = SPINOR_OP_READ4;
- break;
- }
- nor->program_opcode = SPINOR_OP_PP_4B;
- /* No small sector erase for 4-byte command set */
- nor->erase_opcode = SPINOR_OP_SE_4B;
- mtd->erasesize = info->sector_size;
- } else
+ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
+ info->flags & SPI_NOR_4B_OPCODES)
+ spi_nor_set_4byte_opcodes(nor, info);
+ else
set_4byte(nor, info, 1);
} else {
nor->addr_width = 3;
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index c425c7b4c2a0..8b02fd7864d0 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -43,9 +43,13 @@
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
-#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
-#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
+#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
+#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
+#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
+#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
+#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
+#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
@@ -56,11 +60,17 @@
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
-#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
-#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
-#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
-#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
+#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
+#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
+#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
+#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
+#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
+#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
+#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
+#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
+#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
+#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
/* Used for SST flashes only. */
--
2.7.4
This patch changes the prototype of spi_nor_scan(): its 3rd parameter
is replaced by a const struct spi_nor_modes pointer, which tells the
spi-nor framework about which SPI protocols are supported by the SPI
controller.
Besides, this patch also introduces a new spi_nor_basic_flash_parameter
structure telling the spi-nor framework about the SPI protocols supported
by the SPI memory and the needed op codes to use these SPI protocols.
Currently the struct spi_nor_basic_flash_parameter is filled with legacy
values but a later patch will allow to fill it dynamically by reading the
JESD216 Serial Flash Discoverable Parameter (SFDP) tables from the SPI
memory.
With both structures, the spi-nor framework can now compute the best
match between SPI protocols supported by both the (Q)SPI memory and
controller hence selecting the relevant op codes for (Fast) Read, Page
Program and Sector Erase operations.
The spi_nor_basic_flash_parameter structure also provides the spi-nor
framework with the number of dummy cycles to be used with each Fast Read
commands and the erase block size associated to the erase block op codes.
Finally the spi_nor_basic_flash_parameter structure, through the optional
.enable_quad_io() hook, tells the spi-nor framework how to set the Quad
Enable (QE) bit of the QSPI memory to enable its Quad SPI features.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/devices/m25p80.c | 17 ++-
drivers/mtd/spi-nor/atmel-quadspi.c | 83 ++++++----
drivers/mtd/spi-nor/cadence-quadspi.c | 18 ++-
drivers/mtd/spi-nor/fsl-quadspi.c | 8 +-
drivers/mtd/spi-nor/hisi-sfc.c | 32 +++-
drivers/mtd/spi-nor/mtk-quadspi.c | 16 +-
drivers/mtd/spi-nor/nxp-spifi.c | 21 +--
drivers/mtd/spi-nor/spi-nor.c | 280 +++++++++++++++++++++++++++-------
include/linux/mtd/spi-nor.h | 136 +++++++++++++++--
9 files changed, 482 insertions(+), 129 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 9cf7fcd28034..f0a55c01406b 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -111,10 +111,10 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
{
- switch (nor->flash_read) {
- case SPI_NOR_DUAL:
+ switch (SNOR_PROTO_DATA_FROM_PROTO(nor->read_proto)) {
+ case 2:
return 2;
- case SPI_NOR_QUAD:
+ case 4:
return 4;
default:
return 0;
@@ -195,7 +195,10 @@ static int m25p_probe(struct spi_device *spi)
struct flash_platform_data *data;
struct m25p *flash;
struct spi_nor *nor;
- enum read_mode mode = SPI_NOR_NORMAL;
+ struct spi_nor_modes modes = {
+ .rd_modes = SNOR_MODE_SLOW,
+ .wr_modes = SNOR_MODE_1_1_1,
+ };
char *flash_name;
int ret;
@@ -221,9 +224,9 @@ static int m25p_probe(struct spi_device *spi)
flash->spi = spi;
if (spi->mode & SPI_RX_QUAD)
- mode = SPI_NOR_QUAD;
+ modes.rd_modes |= SNOR_MODE_1_1_4;
else if (spi->mode & SPI_RX_DUAL)
- mode = SPI_NOR_DUAL;
+ modes.rd_modes |= SNOR_MODE_1_1_2;
if (data && data->name)
nor->mtd.name = data->name;
@@ -240,7 +243,7 @@ static int m25p_probe(struct spi_device *spi)
else
flash_name = spi->modalias;
- ret = spi_nor_scan(nor, flash_name, mode);
+ ret = spi_nor_scan(nor, flash_name, &modes);
if (ret)
return ret;
diff --git a/drivers/mtd/spi-nor/atmel-quadspi.c b/drivers/mtd/spi-nor/atmel-quadspi.c
index 47937d9beec6..9f7e3124e8b8 100644
--- a/drivers/mtd/spi-nor/atmel-quadspi.c
+++ b/drivers/mtd/spi-nor/atmel-quadspi.c
@@ -275,14 +275,48 @@ static void atmel_qspi_debug_command(struct atmel_qspi *aq,
static int atmel_qspi_run_command(struct atmel_qspi *aq,
const struct atmel_qspi_command *cmd,
- u32 ifr_tfrtyp, u32 ifr_width)
+ u32 ifr_tfrtyp, enum spi_nor_protocol proto)
{
u32 iar, icr, ifr, sr;
int err = 0;
iar = 0;
icr = 0;
- ifr = ifr_tfrtyp | ifr_width;
+ ifr = ifr_tfrtyp;
+
+ /* Set the SPI protocol */
+ switch (proto) {
+ case SNOR_PROTO_1_1_1:
+ ifr |= QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
+ break;
+
+ case SNOR_PROTO_1_1_2:
+ ifr |= QSPI_IFR_WIDTH_DUAL_OUTPUT;
+ break;
+
+ case SNOR_PROTO_1_1_4:
+ ifr |= QSPI_IFR_WIDTH_QUAD_OUTPUT;
+ break;
+
+ case SNOR_PROTO_1_2_2:
+ ifr |= QSPI_IFR_WIDTH_DUAL_IO;
+ break;
+
+ case SNOR_PROTO_1_4_4:
+ ifr |= QSPI_IFR_WIDTH_QUAD_IO;
+ break;
+
+ case SNOR_PROTO_2_2_2:
+ ifr |= QSPI_IFR_WIDTH_DUAL_CMD;
+ break;
+
+ case SNOR_PROTO_4_4_4:
+ ifr |= QSPI_IFR_WIDTH_QUAD_CMD;
+ break;
+
+ default:
+ return -EINVAL;
+ }
/* Compute instruction parameters */
if (cmd->enable.bits.instruction) {
@@ -434,7 +468,7 @@ static int atmel_qspi_read_reg(struct spi_nor *nor, u8 opcode,
cmd.rx_buf = buf;
cmd.buf_len = len;
return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ,
- QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
+ nor->reg_proto);
}
static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode,
@@ -450,7 +484,7 @@ static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode,
cmd.tx_buf = buf;
cmd.buf_len = len;
return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
- QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
+ nor->reg_proto);
}
static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
@@ -469,7 +503,7 @@ static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
cmd.tx_buf = write_buf;
cmd.buf_len = len;
ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM,
- QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
+ nor->write_proto);
return (ret < 0) ? ret : len;
}
@@ -484,7 +518,7 @@ static int atmel_qspi_erase(struct spi_nor *nor, loff_t offs)
cmd.instruction = nor->erase_opcode;
cmd.address = (u32)offs;
return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
- QSPI_IFR_WIDTH_SINGLE_BIT_SPI);
+ nor->reg_proto);
}
static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
@@ -493,27 +527,8 @@ static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
struct atmel_qspi *aq = nor->priv;
struct atmel_qspi_command cmd;
u8 num_mode_cycles, num_dummy_cycles;
- u32 ifr_width;
ssize_t ret;
- switch (nor->flash_read) {
- case SPI_NOR_NORMAL:
- case SPI_NOR_FAST:
- ifr_width = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
- break;
-
- case SPI_NOR_DUAL:
- ifr_width = QSPI_IFR_WIDTH_DUAL_OUTPUT;
- break;
-
- case SPI_NOR_QUAD:
- ifr_width = QSPI_IFR_WIDTH_QUAD_OUTPUT;
- break;
-
- default:
- return -EINVAL;
- }
-
if (nor->read_dummy >= 2) {
num_mode_cycles = 2;
num_dummy_cycles = nor->read_dummy - 2;
@@ -536,7 +551,7 @@ static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
cmd.rx_buf = read_buf;
cmd.buf_len = len;
ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ_MEM,
- ifr_width);
+ nor->read_proto);
return (ret < 0) ? ret : len;
}
@@ -596,6 +611,20 @@ static int atmel_qspi_probe(struct platform_device *pdev)
struct spi_nor *nor;
struct mtd_info *mtd;
int irq, err = 0;
+ struct spi_nor_modes modes = {
+ .rd_modes = (SNOR_MODE_SLOW |
+ SNOR_MODE_1_1_1 |
+ SNOR_MODE_1_1_2 |
+ SNOR_MODE_1_1_4 |
+ SNOR_MODE_1_2_2 |
+ SNOR_MODE_1_4_4),
+ .wr_modes = (SNOR_MODE_SLOW |
+ SNOR_MODE_1_1_1 |
+ SNOR_MODE_1_1_2 |
+ SNOR_MODE_1_1_4 |
+ SNOR_MODE_1_2_2 |
+ SNOR_MODE_1_4_4),
+ };
if (of_get_child_count(np) != 1)
return -ENODEV;
@@ -679,7 +708,7 @@ static int atmel_qspi_probe(struct platform_device *pdev)
if (err)
goto disable_clk;
- err = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
+ err = spi_nor_scan(nor, NULL, &modes);
if (err)
goto disable_clk;
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index d403ba7b8f43..87e49231b4ee 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -853,15 +853,14 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
if (read) {
- switch (nor->flash_read) {
- case SPI_NOR_NORMAL:
- case SPI_NOR_FAST:
+ switch (nor->read_proto) {
+ case SNOR_PROTO_1_1_1:
f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
break;
- case SPI_NOR_DUAL:
+ case SNOR_PROTO_1_1_2:
f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
break;
- case SPI_NOR_QUAD:
+ case SNOR_PROTO_1_1_4:
f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
break;
default:
@@ -1074,6 +1073,13 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
struct mtd_info *mtd;
unsigned int cs;
int i, ret;
+ static const struct spi_nor_modes modes = {
+ .rd_modes = (SNOR_MODE_SLOW |
+ SNOR_MODE_1_1_1 |
+ SNOR_MODE_1_1_2 |
+ SNOR_MODE_1_1_4),
+ .wr_modes = SNOR_MODE_1_1_1,
+ };
/* Get flash device data */
for_each_available_child_of_node(dev->of_node, np) {
@@ -1119,7 +1125,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
goto err;
}
- ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
+ ret = spi_nor_scan(nor, NULL, &modes);
if (ret)
goto err;
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 5c82e4ef1904..01e7356d6623 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -980,6 +980,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
struct spi_nor *nor;
struct mtd_info *mtd;
int ret, i = 0;
+ static const struct spi_nor_modes modes = {
+ .rd_modes = (SNOR_MODE_SLOW |
+ SNOR_MODE_1_1_1 |
+ SNOR_MODE_1_1_4),
+ .wr_modes = SNOR_MODE_1_1_1,
+ };
q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
if (!q)
@@ -1081,7 +1087,7 @@ static int fsl_qspi_probe(struct platform_device *pdev)
/* set the chip address for READID */
fsl_qspi_set_base_addr(q, nor);
- ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
+ ret = spi_nor_scan(nor, NULL, &modes);
if (ret)
goto mutex_failed;
diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c
index 20378b0d55e9..e4d7625b4397 100644
--- a/drivers/mtd/spi-nor/hisi-sfc.c
+++ b/drivers/mtd/spi-nor/hisi-sfc.c
@@ -120,19 +120,24 @@ static inline int wait_op_finish(struct hifmc_host *host)
(reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
}
-static int get_if_type(enum read_mode flash_read)
+static int get_if_type(enum spi_nor_protocol proto)
{
enum hifmc_iftype if_type;
- switch (flash_read) {
- case SPI_NOR_DUAL:
+ switch (proto) {
+ case SNOR_PROTO_1_1_2:
if_type = IF_TYPE_DUAL;
break;
- case SPI_NOR_QUAD:
+ case SNOR_PROTO_1_2_2:
+ if_type = IF_TYPE_DIO;
+ break;
+ case SNOR_PROTO_1_1_4:
if_type = IF_TYPE_QUAD;
break;
- case SPI_NOR_NORMAL:
- case SPI_NOR_FAST:
+ case SNOR_PROTO_1_4_4:
+ if_type = IF_TYPE_QIO;
+ break;
+ case SNOR_PROTO_1_1_1:
default:
if_type = IF_TYPE_STD;
break;
@@ -238,6 +243,7 @@ static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
{
struct hifmc_priv *priv = nor->priv;
struct hifmc_host *host = priv->host;
+ enum spi_nor_protocol proto;
u8 if_type = 0;
u32 reg;
@@ -253,7 +259,10 @@ static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN);
reg = OP_CFG_FM_CS(priv->chipselect);
- if_type = get_if_type(nor->flash_read);
+ proto = (op_type == FMC_OP_READ)
+ ? nor->read_proto
+ : nor->write_proto;
+ if_type = get_if_type(proto);
reg |= OP_CFG_MEM_IF_TYPE(if_type);
if (op_type == FMC_OP_READ)
reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
@@ -326,6 +335,13 @@ static int hisi_spi_nor_register(struct device_node *np,
struct hifmc_priv *priv;
struct mtd_info *mtd;
int ret;
+ static const struct spi_nor_modes modes = {
+ .rd_modes = (SNOR_MODE_SLOW |
+ SNOR_MODE_1_1_1 |
+ SNOR_MODE_1_1_2 |
+ SNOR_MODE_1_1_4),
+ .wr_modes = SNOR_MODE_1_1_1,
+ };
nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
if (!nor)
@@ -362,7 +378,7 @@ static int hisi_spi_nor_register(struct device_node *np,
nor->read = hisi_spi_nor_read;
nor->write = hisi_spi_nor_write;
nor->erase = NULL;
- ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
+ ret = spi_nor_scan(nor, NULL, &modes);
if (ret)
return ret;
diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
index e661877c23de..4dc2bb8eb488 100644
--- a/drivers/mtd/spi-nor/mtk-quadspi.c
+++ b/drivers/mtd/spi-nor/mtk-quadspi.c
@@ -121,20 +121,20 @@ static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor)
{
struct spi_nor *nor = &mt8173_nor->nor;
- switch (nor->flash_read) {
- case SPI_NOR_FAST:
+ switch (SNOR_PROTO_DATA_FROM_PROTO(nor->read_proto)) {
+ case 1:
writeb(nor->read_opcode, mt8173_nor->base +
MTK_NOR_PRGDATA3_REG);
writeb(MTK_NOR_FAST_READ, mt8173_nor->base +
MTK_NOR_CFG1_REG);
break;
- case SPI_NOR_DUAL:
+ case 2:
writeb(nor->read_opcode, mt8173_nor->base +
MTK_NOR_PRGDATA3_REG);
writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base +
MTK_NOR_DUAL_REG);
break;
- case SPI_NOR_QUAD:
+ case 4:
writeb(nor->read_opcode, mt8173_nor->base +
MTK_NOR_PRGDATA4_REG);
writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base +
@@ -383,6 +383,12 @@ static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
{
int ret;
struct spi_nor *nor;
+ static const struct spi_nor_modes modes = {
+ .rd_modes = (SNOR_MODE_SLOW |
+ SNOR_MODE_1_1_1 |
+ SNOR_MODE_1_1_2),
+ .wr_modes = SNOR_MODE_1_1_1,
+ };
/* initialize controller to accept commands */
writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG);
@@ -399,7 +405,7 @@ static int mtk_nor_init(struct mt8173_nor *mt8173_nor,
nor->write_reg = mt8173_nor_write_reg;
nor->mtd.name = "mtk_nor";
/* initialized with NULL */
- ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL);
+ ret = spi_nor_scan(nor, NULL, &modes);
if (ret)
return ret;
diff --git a/drivers/mtd/spi-nor/nxp-spifi.c b/drivers/mtd/spi-nor/nxp-spifi.c
index 73a14f40928b..327c5b5fe9da 100644
--- a/drivers/mtd/spi-nor/nxp-spifi.c
+++ b/drivers/mtd/spi-nor/nxp-spifi.c
@@ -240,13 +240,12 @@ static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
{
- switch (spifi->nor.flash_read) {
- case SPI_NOR_NORMAL:
- case SPI_NOR_FAST:
+ switch (SNOR_PROTO_DATA_FROM_PROTO(spifi->nor.read_proto)) {
+ case 1:
spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
break;
- case SPI_NOR_DUAL:
- case SPI_NOR_QUAD:
+ case 2:
+ case 4:
spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
break;
default:
@@ -274,7 +273,10 @@ static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
struct device_node *np)
{
- enum read_mode flash_read;
+ struct spi_nor_modes modes = {
+ .rd_modes = (SNOR_MODE_SLOW | SNOR_MODE_1_1_1),
+ .wr_modes = SNOR_MODE_1_1_1,
+ };
u32 ctrl, property;
u16 mode = 0;
int ret;
@@ -308,13 +310,12 @@ static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
if (mode & SPI_RX_DUAL) {
ctrl |= SPIFI_CTRL_DUAL;
- flash_read = SPI_NOR_DUAL;
+ modes.rd_modes |= SNOR_MODE_1_1_2;
} else if (mode & SPI_RX_QUAD) {
ctrl &= ~SPIFI_CTRL_DUAL;
- flash_read = SPI_NOR_QUAD;
+ modes.rd_modes |= SNOR_MODE_1_1_4;
} else {
ctrl |= SPIFI_CTRL_DUAL;
- flash_read = SPI_NOR_NORMAL;
}
switch (mode & (SPI_CPHA | SPI_CPOL)) {
@@ -351,7 +352,7 @@ static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
*/
nxp_spifi_dummy_id_read(&spifi->nor);
- ret = spi_nor_scan(&spifi->nor, NULL, flash_read);
+ ret = spi_nor_scan(&spifi->nor, NULL, &modes);
if (ret) {
dev_err(spifi->dev, "device scan failed\n");
return ret;
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 423448c1c7a8..51eac2278ec0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -143,24 +143,6 @@ static int read_cr(struct spi_nor *nor)
}
/*
- * Dummy Cycle calculation for different type of read.
- * It can be used to support more commands with
- * different dummy cycle requirements.
- */
-static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
-{
- switch (nor->flash_read) {
- case SPI_NOR_FAST:
- case SPI_NOR_DUAL:
- case SPI_NOR_QUAD:
- return 8;
- case SPI_NOR_NORMAL:
- return 0;
- }
- return 0;
-}
-
-/*
* Write status register 1 byte
* Returns negative if error occurred.
*/
@@ -1384,8 +1366,206 @@ static int spi_nor_check(struct spi_nor *nor)
return 0;
}
-int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
+static inline void spi_nor_set_read_settings(struct spi_nor_read *read,
+ u8 num_mode_clocks,
+ u8 num_wait_states,
+ u8 opcode)
+{
+ read->num_mode_clocks = num_mode_clocks;
+ read->num_wait_states = num_wait_states;
+ read->opcode = opcode;
+}
+
+static inline void spi_nor_set_erase_settings(struct spi_nor_erase_type *erase,
+ u8 size, u8 opcode)
+{
+ erase->size = size;
+ erase->opcode = opcode;
+}
+
+static int spi_nor_init_params(struct spi_nor *nor,
+ const struct flash_info *info,
+ struct spi_nor_basic_flash_parameter *params)
+{
+ // TODO: parse SFDP table
+
+ /* If SFDP tables are not available, use legacy settings. */
+ memset(params, 0, sizeof(*params));
+
+ /* (Fast) Read settings. */
+ params->rd_modes = SNOR_MODE_SLOW;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_PINDEX_SLOW],
+ 0, 0, SPINOR_OP_READ);
+ if (!(info->flags & SPI_NOR_NO_FR)) {
+ params->rd_modes |= SNOR_MODE_1_1_1;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_PINDEX_1_1_1],
+ 0, 8, SPINOR_OP_READ_FAST);
+ }
+ if (info->flags & SPI_NOR_DUAL_READ) {
+ params->rd_modes |= SNOR_MODE_1_1_2;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_PINDEX_1_1_2],
+ 0, 8, SPINOR_OP_READ_1_1_2);
+ }
+ if (info->flags & SPI_NOR_QUAD_READ) {
+ params->rd_modes|= SNOR_MODE_1_1_4;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_PINDEX_1_1_4],
+ 0, 8, SPINOR_OP_READ_1_1_4);
+ }
+
+ /* Page Program settings. */
+ params->wr_modes = SNOR_MODE_1_1_1;
+ params->page_programs[SNOR_PINDEX_1_1_1] = SPINOR_OP_PP;
+
+ /* Sector Erase settings. */
+ spi_nor_set_erase_settings(¶ms->erase_types[0],
+ SNOR_ERASE_64K, SPINOR_OP_SE);
+ if (info->flags & SECT_4K)
+ spi_nor_set_erase_settings(¶ms->erase_types[1],
+ SNOR_ERASE_4K, SPINOR_OP_BE_4K);
+ else if (info->flags & SECT_4K_PMC)
+ spi_nor_set_erase_settings(¶ms->erase_types[1],
+ SNOR_ERASE_4K, SPINOR_OP_BE_4K_PMC);
+
+ /* Select the procedure to set the Quad Enable bit. */
+ if (params->rd_modes & (SNOR_MODE_1_1_4 |
+ SNOR_MODE_1_4_4 |
+ SNOR_MODE_4_4_4)) {
+ switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_MACRONIX:
+ params->enable_quad_io = macronix_quad_enable;
+ break;
+
+ case SNOR_MFR_MICRON:
+ break;
+
+ default:
+ params->enable_quad_io = spansion_quad_enable;
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int spi_nor_pindex2proto(int pindex, enum spi_nor_protocol *proto)
+{
+ enum spi_nor_protocol_width pwidth;
+ enum spi_nor_protocol_class pclass;
+ uint8_t width;
+
+ if (pindex < 0)
+ return -EINVAL;
+
+ pwidth = (enum spi_nor_protocol_width)(pindex / SNOR_PCLASS_MAX);
+ pclass = (enum spi_nor_protocol_class)(pindex % SNOR_PCLASS_MAX);
+
+ width = (1 << pwidth) & 0xf;
+ if (!width)
+ return -EINVAL;
+
+ switch (pclass) {
+ case SNOR_PCLASS_1_1_N:
+ *proto = SNOR_PROTO(1, 1, width);
+ break;
+
+ case SNOR_PCLASS_1_N_N:
+ *proto = SNOR_PROTO(1, width, width);
+ break;
+
+ case SNOR_PCLASS_N_N_N:
+ *proto = SNOR_PROTO(width, width, width);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
+ const struct spi_nor_basic_flash_parameter *params,
+ const struct spi_nor_modes *modes)
{
+ bool enable_quad_io;
+ u32 rd_modes, wr_modes, mask;
+ const struct spi_nor_erase_type *erase_type = NULL;
+ const struct spi_nor_read *read;
+ int rd_pindex, wr_pindex, i, err = 0;
+ u8 erase_size = SNOR_ERASE_64K;
+
+ /* 2-2-2 or 4-4-4 modes are not supported yet. */
+ mask = (SNOR_MODE_2_2_2 | SNOR_MODE_4_4_4);
+ rd_modes = modes->rd_modes & ~mask;
+ wr_modes = modes->wr_modes & ~mask;
+
+ /* Setup read operation. */
+ rd_pindex = fls(params->rd_modes & rd_modes) - 1;
+ if (spi_nor_pindex2proto(rd_pindex, &nor->read_proto)) {
+ dev_err(nor->dev, "invalid (fast) read\n");
+ return -EINVAL;
+ }
+ read = ¶ms->reads[rd_pindex];
+ nor->read_opcode = read->opcode;
+ nor->read_dummy = read->num_mode_clocks + read->num_wait_states;
+
+ /* Set page program op code and protocol. */
+ wr_pindex = fls(params->wr_modes & wr_modes) - 1;
+ if (spi_nor_pindex2proto(wr_pindex, &nor->write_proto)) {
+ dev_err(nor->dev, "invalid page program\n");
+ return -EINVAL;
+ }
+ nor->program_opcode = params->page_programs[wr_pindex];
+
+ /* Set sector erase op code and size. */
+ erase_type = ¶ms->erase_types[0];
+#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
+ erase_size = SNOR_ERASE_4K;
+#endif
+ for (i = 0; i < SNOR_MAX_ERASE_TYPES; ++i) {
+ if (params->erase_types[i].size == erase_size) {
+ erase_type = ¶ms->erase_types[i];
+ break;
+ } else if (!erase_type->size && params->erase_types[i].size) {
+ erase_type = ¶ms->erase_types[i];
+ }
+ }
+ nor->erase_opcode = erase_type->opcode;
+ nor->mtd.erasesize = (1 << erase_type->size);
+
+
+ enable_quad_io = (SNOR_PROTO_DATA_FROM_PROTO(nor->read_proto) == 4 ||
+ SNOR_PROTO_DATA_FROM_PROTO(nor->write_proto) == 4);
+
+ /* Enable Quad I/O if needed. */
+ if (enable_quad_io && params->enable_quad_io) {
+ err = params->enable_quad_io(nor);
+ if (err) {
+ dev_err(nor->dev,
+ "failed to enable the Quad I/O mode\n");
+ return err;
+ }
+ }
+
+ dev_dbg(nor->dev,
+ "(Fast) Read: opcode=%02Xh, protocol=%03x, mode=%u, wait=%u\n",
+ nor->read_opcode, nor->read_proto,
+ read->num_mode_clocks, read->num_wait_states);
+ dev_dbg(nor->dev,
+ "Page Program: opcode=%02Xh, protocol=%03x\n",
+ nor->program_opcode, nor->write_proto);
+ dev_dbg(nor->dev,
+ "Sector Erase: opcode=%02Xh, protocol=%03x, sector size=%u\n",
+ nor->erase_opcode, nor->reg_proto, (u32)nor->mtd.erasesize);
+
+ return 0;
+}
+
+int spi_nor_scan(struct spi_nor *nor, const char *name,
+ const struct spi_nor_modes *modes)
+{
+ struct spi_nor_basic_flash_parameter params;
+ struct spi_nor_modes fixed_modes = *modes;
const struct flash_info *info = NULL;
struct device *dev = nor->dev;
struct mtd_info *mtd = &nor->mtd;
@@ -1397,6 +1577,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
if (ret)
return ret;
+ /* Reset SPI protocol for all commands */
+ nor->reg_proto = SNOR_PROTO_1_1_1;
+ nor->read_proto = SNOR_PROTO_1_1_1;
+ nor->write_proto = SNOR_PROTO_1_1_1;
+
if (name)
info = spi_nor_match_id(name);
/* Try to auto-detect if chip name wasn't specified or not found */
@@ -1429,6 +1614,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
}
}
+ /* Parse the Serial Flash Discoverable Parameters table */
+ ret = spi_nor_init_params(nor, info, ¶ms);
+ if (ret)
+ return ret;
+
mutex_init(&nor->lock);
/*
@@ -1505,51 +1695,31 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
if (np) {
/* If we were instantiated by DT, use it */
if (of_property_read_bool(np, "m25p,fast-read"))
- nor->flash_read = SPI_NOR_FAST;
+ fixed_modes.rd_modes |= SNOR_MODE_1_1_1;
else
- nor->flash_read = SPI_NOR_NORMAL;
+ fixed_modes.rd_modes &= ~SNOR_MODE_1_1_1;
} else {
/* If we weren't instantiated by DT, default to fast-read */
- nor->flash_read = SPI_NOR_FAST;
+ fixed_modes.rd_modes |= SNOR_MODE_1_1_1;
}
/* Some devices cannot do fast-read, no matter what DT tells us */
if (info->flags & SPI_NOR_NO_FR)
- nor->flash_read = SPI_NOR_NORMAL;
-
- /* Quad/Dual-read mode takes precedence over fast/normal */
- if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
- ret = set_quad_mode(nor, info);
- if (ret) {
- dev_err(dev, "quad mode not supported\n");
- return ret;
- }
- nor->flash_read = SPI_NOR_QUAD;
- } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
- nor->flash_read = SPI_NOR_DUAL;
- }
-
- /* Default commands */
- switch (nor->flash_read) {
- case SPI_NOR_QUAD:
- nor->read_opcode = SPINOR_OP_READ_1_1_4;
- break;
- case SPI_NOR_DUAL:
- nor->read_opcode = SPINOR_OP_READ_1_1_2;
- break;
- case SPI_NOR_FAST:
- nor->read_opcode = SPINOR_OP_READ_FAST;
- break;
- case SPI_NOR_NORMAL:
- nor->read_opcode = SPINOR_OP_READ;
- break;
- default:
- dev_err(dev, "No Read opcode defined\n");
- return -EINVAL;
- }
+ fixed_modes.rd_modes &= ~SNOR_MODE_1_1_1;
nor->program_opcode = SPINOR_OP_PP;
+ /*
+ * Configure the SPI memory:
+ * - select op codes for (Fast) Read, Page Program and Sector Erase.
+ * - set the number of dummy cycles (mode cycles + wait states).
+ * - set the SPI protocols for register and memory accesses.
+ * - set the Quad Enable bit if needed (required by SPI x-y-4 protos).
+ */
+ ret = spi_nor_setup(nor, info, ¶ms, &fixed_modes);
+ if (ret)
+ return ret;
+
if (info->addr_width)
nor->addr_width = info->addr_width;
else if (mtd->size > 0x1000000) {
@@ -1570,8 +1740,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
return -EINVAL;
}
- nor->read_dummy = spi_nor_read_dummy_cycles(nor);
-
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
(long long)mtd->size >> 10);
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b02fd7864d0..730f33dce1ea 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -110,11 +110,124 @@
/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
-enum read_mode {
- SPI_NOR_NORMAL = 0,
- SPI_NOR_FAST,
- SPI_NOR_DUAL,
- SPI_NOR_QUAD,
+
+/* Supported SPI protocols */
+enum spi_nor_protocol_class {
+ SNOR_PCLASS_1_1_N,
+ SNOR_PCLASS_1_N_N,
+ SNOR_PCLASS_N_N_N,
+
+ SNOR_PCLASS_MAX
+};
+
+enum spi_nor_protocol_width {
+ SNOR_PWIDTH_1,
+ SNOR_PWIDTH_2,
+ SNOR_PWIDTH_4,
+ SNOR_PWIDTH_8,
+};
+
+/* The encoding is chosen so the higher index the higher priority */
+#define SNOR_PINDEX(pwidth, pclass) \
+ ((pwidth) * SNOR_PCLASS_MAX + (pclass))
+enum spi_nor_protocol_index {
+ SNOR_PINDEX_SLOW = SNOR_PINDEX(SNOR_PWIDTH_1, SNOR_PCLASS_1_1_N),
+ /* Little trick to make the difference between Read and Fast Read commands. */
+ SNOR_PINDEX_1_1_1 = SNOR_PINDEX(SNOR_PWIDTH_1, SNOR_PCLASS_1_N_N),
+ SNOR_PINDEX_1_1_2 = SNOR_PINDEX(SNOR_PWIDTH_2, SNOR_PCLASS_1_1_N),
+ SNOR_PINDEX_1_2_2 = SNOR_PINDEX(SNOR_PWIDTH_2, SNOR_PCLASS_1_N_N),
+ SNOR_PINDEX_2_2_2 = SNOR_PINDEX(SNOR_PWIDTH_2, SNOR_PCLASS_N_N_N),
+ SNOR_PINDEX_1_1_4 = SNOR_PINDEX(SNOR_PWIDTH_4, SNOR_PCLASS_1_1_N),
+ SNOR_PINDEX_1_4_4 = SNOR_PINDEX(SNOR_PWIDTH_4, SNOR_PCLASS_1_N_N),
+ SNOR_PINDEX_4_4_4 = SNOR_PINDEX(SNOR_PWIDTH_4, SNOR_PCLASS_N_N_N),
+
+ SNOR_PINDEX_MAX
+};
+
+#define SNOR_MODE_SLOW BIT(SNOR_PINDEX_SLOW)
+#define SNOR_MODE_1_1_1 BIT(SNOR_PINDEX_1_1_1)
+#define SNOR_MODE_1_1_2 BIT(SNOR_PINDEX_1_1_2)
+#define SNOR_MODE_1_2_2 BIT(SNOR_PINDEX_1_2_2)
+#define SNOR_MODE_2_2_2 BIT(SNOR_PINDEX_2_2_2)
+#define SNOR_MODE_1_1_4 BIT(SNOR_PINDEX_1_1_4)
+#define SNOR_MODE_1_4_4 BIT(SNOR_PINDEX_1_4_4)
+#define SNOR_MODE_4_4_4 BIT(SNOR_PINDEX_4_4_4)
+
+struct spi_nor_modes {
+ u32 rd_modes; /* supported SPI modes for (Fast) Read */
+ u32 wr_modes; /* supported SPI modes for Page Program */
+};
+
+
+struct spi_nor_read {
+ u8 num_wait_states:5;
+ u8 num_mode_clocks:3;
+ u8 opcode;
+};
+
+struct spi_nor_erase_type {
+ u8 size; /* specifies 'N' so erase size = 2^N */
+ u8 opcode;
+};
+
+#define SNOR_ERASE_64K 0x10
+#define SNOR_ERASE_32K 0x0f
+#define SNOR_ERASE_4K 0x0c
+
+struct spi_nor;
+
+#define SNOR_MAX_ERASE_TYPES 4
+
+struct spi_nor_basic_flash_parameter {
+ /* Fast Read settings */
+ u32 rd_modes;
+ struct spi_nor_read reads[SNOR_PINDEX_MAX];
+
+ /* Page Program settings */
+ u32 wr_modes;
+ u8 page_programs[SNOR_PINDEX_MAX];
+
+ /* Sector Erase settings */
+ struct spi_nor_erase_type erase_types[SNOR_MAX_ERASE_TYPES];
+
+ int (*enable_quad_io)(struct spi_nor *nor);
+};
+
+
+#define SNOR_PROTO_CODE_OFF 8
+#define SNOR_PROTO_CODE_MASK GENMASK(11, 8)
+#define SNOR_PROTO_CODE_TO_PROTO(code) \
+ (((code) << SNOR_PROTO_CODE_OFF) & SNOR_PROTO_CODE_MASK)
+#define SNOR_PROTO_CODE_FROM_PROTO(proto) \
+ ((((u32)(proto)) & SNOR_PROTO_CODE_MASK) >> SNOR_PROTO_CODE_OFF)
+
+#define SNOR_PROTO_ADDR_OFF 4
+#define SNOR_PROTO_ADDR_MASK GENMASK(7, 4)
+#define SNOR_PROTO_ADDR_TO_PROTO(addr) \
+ (((addr) << SNOR_PROTO_ADDR_OFF) & SNOR_PROTO_ADDR_MASK)
+#define SNOR_PROTO_ADDR_FROM_PROTO(proto) \
+ ((((u32)(proto)) & SNOR_PROTO_ADDR_MASK) >> SNOR_PROTO_ADDR_OFF)
+
+#define SNOR_PROTO_DATA_OFF 0
+#define SNOR_PROTO_DATA_MASK GENMASK(3, 0)
+#define SNOR_PROTO_DATA_TO_PROTO(data) \
+ (((data) << SNOR_PROTO_DATA_OFF) & SNOR_PROTO_DATA_MASK)
+#define SNOR_PROTO_DATA_FROM_PROTO(proto) \
+ ((((u32)(proto)) & SNOR_PROTO_DATA_MASK) >> SNOR_PROTO_DATA_OFF)
+
+#define SNOR_PROTO(code, addr, data) \
+ (SNOR_PROTO_CODE_TO_PROTO(code) | \
+ SNOR_PROTO_ADDR_TO_PROTO(addr) | \
+ SNOR_PROTO_DATA_TO_PROTO(data))
+
+enum spi_nor_protocol {
+ SNOR_PROTO_1_1_1 = SNOR_PROTO(1, 1, 1), /* SPI */
+ SNOR_PROTO_1_1_2 = SNOR_PROTO(1, 1, 2), /* Dual Output */
+ SNOR_PROTO_1_1_4 = SNOR_PROTO(1, 1, 4), /* Quad Output */
+ SNOR_PROTO_1_2_2 = SNOR_PROTO(1, 2, 2), /* Dual IO */
+ SNOR_PROTO_1_4_4 = SNOR_PROTO(1, 4, 4), /* Quad IO */
+ SNOR_PROTO_2_2_2 = SNOR_PROTO(2, 2, 2), /* Dual Command */
+ SNOR_PROTO_4_4_4 = SNOR_PROTO(4, 4, 4), /* Quad Command */
};
#define SPI_NOR_MAX_CMD_SIZE 8
@@ -142,9 +255,11 @@ enum spi_nor_option_flags {
* @read_opcode: the read opcode
* @read_dummy: the dummy needed by the read operation
* @program_opcode: the program opcode
- * @flash_read: the mode of the read
* @sst_write_second: used by the SST write operation
* @flags: flag options for the current SPI-NOR (SNOR_F_*)
+ * @read_proto: the SPI protocol used by read operations
+ * @write_proto: the SPI protocol used by write operations
+ * @reg_proto the SPI protocol used by read_reg/write_reg operations
* @cmd_buf: used by the write_reg
* @prepare: [OPTIONAL] do some preparations for the
* read/write/erase/lock/unlock operations
@@ -173,7 +288,9 @@ struct spi_nor {
u8 read_opcode;
u8 read_dummy;
u8 program_opcode;
- enum read_mode flash_read;
+ enum spi_nor_protocol read_proto;
+ enum spi_nor_protocol write_proto;
+ enum spi_nor_protocol reg_proto;
bool sst_write_second;
u32 flags;
u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
@@ -211,7 +328,7 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
* spi_nor_scan() - scan the SPI NOR
* @nor: the spi_nor structure
* @name: the chip type name
- * @mode: the read mode supported by the driver
+ * @modes: the SPI modes supported by the controller driver
*
* The drivers can use this fuction to scan the SPI NOR.
* In the scanning, it will try to get all the necessary information to
@@ -221,6 +338,7 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
*
* Return: 0 for success, others for failure.
*/
-int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);
+int spi_nor_scan(struct spi_nor *nor, const char *name,
+ const struct spi_nor_modes *modes);
#endif
--
2.7.4
The set_quad_mode() function is no longer used, so we remove it.
This patch is not squashed into the previous patch on purpose for
readiness issue and to ease the review process of the whole series.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 24 ------------------------
1 file changed, 24 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 51eac2278ec0..ce06c4b49dba 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1331,30 +1331,6 @@ static int spansion_quad_enable(struct spi_nor *nor)
return 0;
}
-static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
-{
- int status;
-
- switch (JEDEC_MFR(info)) {
- case SNOR_MFR_MACRONIX:
- status = macronix_quad_enable(nor);
- if (status) {
- dev_err(nor->dev, "Macronix quad-read not enabled\n");
- return -EINVAL;
- }
- return status;
- case SNOR_MFR_MICRON:
- return 0;
- default:
- status = spansion_quad_enable(nor);
- if (status) {
- dev_err(nor->dev, "Spansion quad-read not enabled\n");
- return -EINVAL;
- }
- return status;
- }
-}
-
static int spi_nor_check(struct spi_nor *nor)
{
if (!nor->dev || !nor->read || !nor->write ||
--
2.7.4
Before this patch, m25p80_read() supported few SPI protocols:
- regular SPI 1-1-1
- SPI Dual Output 1-1-2
- SPI Quad Output 1-1-4
On the other hand, all other m25p80_*() hooks only supported SPI 1-1-1.
This patch adds support to all currently existing SPI protocols to
cover as many protocols as possible.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/devices/m25p80.c | 193 +++++++++++++++++++++++++++++++++----------
1 file changed, 149 insertions(+), 44 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index f0a55c01406b..38778eac6c21 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -27,22 +27,64 @@
#include <linux/spi/flash.h>
#include <linux/mtd/spi-nor.h>
-#define MAX_CMD_SIZE 6
+#define MAX_CMD_SIZE 16
struct m25p {
struct spi_device *spi;
struct spi_nor spi_nor;
u8 command[MAX_CMD_SIZE];
};
+static inline int m25p80_proto2nbits(enum spi_nor_protocol proto,
+ unsigned *code_nbits,
+ unsigned *addr_nbits,
+ unsigned *data_nbits)
+{
+ if (code_nbits)
+ *code_nbits = SNOR_PROTO_CODE_FROM_PROTO(proto);
+ if (addr_nbits)
+ *addr_nbits = SNOR_PROTO_ADDR_FROM_PROTO(proto);
+ if (data_nbits)
+ *data_nbits = SNOR_PROTO_DATA_FROM_PROTO(proto);
+
+ return 0;
+}
+
static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
+ unsigned code_nbits, data_nbits;
+ struct spi_transfer xfers[2];
int ret;
- ret = spi_write_then_read(spi, &code, 1, val, len);
+ /* Check the total length of command op code and data. */
+ if (len + 1 > MAX_CMD_SIZE)
+ return -EINVAL;
+
+ /* Get transfer protocols (addr_nbits is not relevant here). */
+ ret = m25p80_proto2nbits(nor->reg_proto,
+ &code_nbits, NULL, &data_nbits);
+ if (ret < 0)
+ return ret;
+
+ /* Set up transfers. */
+ memset(xfers, 0, sizeof(xfers));
+
+ flash->command[0] = code;
+ xfers[0].len = 1;
+ xfers[0].tx_buf = flash->command;
+ xfers[0].tx_nbits = code_nbits;
+
+ xfers[1].len = len;
+ xfers[1].rx_buf = &flash->command[1];
+ xfers[1].rx_nbits = data_nbits;
+
+ /* Process command. */
+ ret = spi_sync_transfer(spi, xfers, 2);
if (ret < 0)
dev_err(&spi->dev, "error %d reading %x\n", ret, code);
+ else
+ memcpy(val, &flash->command[1], len);
return ret;
}
@@ -65,12 +107,42 @@ static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
+ unsigned code_nbits, data_nbits, num_xfers = 1;
+ struct spi_transfer xfers[2];
+ int ret;
+
+ /* Check the total length of command op code and data. */
+ if (buf && (len + 1 > MAX_CMD_SIZE))
+ return -EINVAL;
+
+ /* Get transfer protocols (addr_nbits is not relevant here). */
+ ret = m25p80_proto2nbits(nor->reg_proto,
+ &code_nbits, NULL, &data_nbits);
+ if (ret < 0)
+ return ret;
+
+ /* Set up transfer(s). */
+ memset(xfers, 0, sizeof(xfers));
flash->command[0] = opcode;
- if (buf)
+ xfers[0].len = 1;
+ xfers[0].tx_buf = flash->command;
+ xfers[0].tx_nbits = code_nbits;
+
+ if (buf) {
memcpy(&flash->command[1], buf, len);
+ if (data_nbits == code_nbits) {
+ xfers[0].len += len;
+ } else {
+ xfers[1].len = len;
+ xfers[1].tx_buf = &flash->command[1];
+ xfers[1].tx_nbits = data_nbits;
+ num_xfers++;
+ }
+ }
- return spi_write(spi, flash->command, len + 1);
+ /* Process command. */
+ return spi_sync_transfer(spi, xfers, num_xfers);
}
static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
@@ -78,27 +150,48 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
- struct spi_transfer t[2] = {};
+ unsigned code_nbits, addr_nbits, data_nbits, num_xfers = 1;
+ struct spi_transfer xfers[3];
struct spi_message m;
int cmd_sz = m25p_cmdsz(nor);
ssize_t ret;
- spi_message_init(&m);
-
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
cmd_sz = 1;
- flash->command[0] = nor->program_opcode;
- m25p_addr2cmd(nor, to, flash->command);
+ /* Get transfer protocols. */
+ ret = m25p80_proto2nbits(nor->write_proto,
+ &code_nbits, &addr_nbits, &data_nbits);
+ if (ret < 0)
+ return ret;
- t[0].tx_buf = flash->command;
- t[0].len = cmd_sz;
- spi_message_add_tail(&t[0], &m);
+ /* Set up transfers. */
+ memset(xfers, 0, sizeof(xfers));
+
+ flash->command[0] = nor->program_opcode;
+ xfers[0].len = 1;
+ xfers[0].tx_buf = flash->command;
+ xfers[0].tx_nbits = code_nbits;
+
+ if (cmd_sz > 1) {
+ m25p_addr2cmd(nor, to, flash->command);
+ if (addr_nbits == code_nbits) {
+ xfers[0].len += nor->addr_width;
+ } else {
+ xfers[1].len = nor->addr_width;
+ xfers[1].tx_buf = &flash->command[1];
+ xfers[1].tx_nbits = addr_nbits;
+ num_xfers++;
+ }
+ }
- t[1].tx_buf = buf;
- t[1].len = len;
- spi_message_add_tail(&t[1], &m);
+ xfers[num_xfers].len = len;
+ xfers[num_xfers].tx_buf = buf;
+ xfers[num_xfers].tx_nbits = data_nbits;
+ num_xfers++;
+ /* Process command. */
+ spi_message_init_with_transfers(&m, xfers, num_xfers);
ret = spi_sync(spi, &m);
if (ret)
return ret;
@@ -109,18 +202,6 @@ static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
return ret;
}
-static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
-{
- switch (SNOR_PROTO_DATA_FROM_PROTO(nor->read_proto)) {
- case 2:
- return 2;
- case 4:
- return 4;
- default:
- return 0;
- }
-}
-
/*
* Read an address range from the nor chip. The address range
* may be any size provided it is within the physical boundaries.
@@ -130,14 +211,22 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
- struct spi_transfer t[2];
- struct spi_message m;
+ unsigned code_nbits, addr_nbits, data_nbits, num_xfers = 1;
unsigned int dummy = nor->read_dummy;
ssize_t ret;
+ struct spi_transfer xfers[3];
+ struct spi_message m;
+
+ /* Get transfer protocols. */
+ ret = m25p80_proto2nbits(nor->read_proto,
+ &code_nbits, &addr_nbits, &data_nbits);
+ if (ret < 0)
+ return ret;
/* convert the dummy cycles to the number of bytes */
- dummy /= 8;
+ dummy = (dummy * addr_nbits) / 8;
+ /* Use the SPI flash API if supported. */
if (spi_flash_read_supported(spi)) {
struct spi_flash_read_message msg;
@@ -149,10 +238,9 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
msg.read_opcode = nor->read_opcode;
msg.addr_width = nor->addr_width;
msg.dummy_bytes = dummy;
- /* TODO: Support other combinations */
- msg.opcode_nbits = SPI_NBITS_SINGLE;
- msg.addr_nbits = SPI_NBITS_SINGLE;
- msg.data_nbits = m25p80_rx_nbits(nor);
+ msg.opcode_nbits = code_nbits;
+ msg.addr_nbits = addr_nbits;
+ msg.data_nbits = data_nbits;
ret = spi_flash_read(spi, &msg);
if (ret < 0)
@@ -160,21 +248,38 @@ static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
return msg.retlen;
}
- spi_message_init(&m);
- memset(t, 0, (sizeof t));
+ /* Set up transfers. */
+ memset(xfers, 0, sizeof(xfers));
flash->command[0] = nor->read_opcode;
- m25p_addr2cmd(nor, from, flash->command);
+ xfers[0].len = 1;
+ xfers[0].tx_buf = flash->command;
+ xfers[0].tx_nbits = code_nbits;
- t[0].tx_buf = flash->command;
- t[0].len = m25p_cmdsz(nor) + dummy;
- spi_message_add_tail(&t[0], &m);
+ m25p_addr2cmd(nor, from, flash->command);
+ /*
+ * Clear all dummy/mode cycle bits to avoid sending some manufacturer
+ * specific pattern, which might make the memory enter its Continuous
+ * Read mode by mistake.
+ */
+ memset(flash->command + 1 + nor->addr_width, 0, dummy);
+
+ if (addr_nbits == code_nbits) {
+ xfers[0].len += nor->addr_width + dummy;
+ } else {
+ xfers[1].len = nor->addr_width + dummy;
+ xfers[1].tx_buf = &flash->command[1];
+ xfers[1].tx_nbits = addr_nbits;
+ num_xfers++;
+ }
- t[1].rx_buf = buf;
- t[1].rx_nbits = m25p80_rx_nbits(nor);
- t[1].len = min(len, spi_max_transfer_size(spi));
- spi_message_add_tail(&t[1], &m);
+ xfers[num_xfers].len = len;
+ xfers[num_xfers].rx_buf = buf;
+ xfers[num_xfers].rx_nbits = data_nbits;
+ num_xfers++;
+ /* Process command. */
+ spi_message_init_with_transfers(&m, xfers, num_xfers);
ret = spi_sync(spi, &m);
if (ret)
return ret;
--
2.7.4
This patch adds support the the JESD216B standard and parse the SFDP
tables to dynamically initialize the spi_nor_basic_flash_parameter
structure.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 455 +++++++++++++++++++++++++++++++++++++++++-
include/linux/mtd/spi-nor.h | 6 +
2 files changed, 460 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index ce06c4b49dba..e91b3c39b68e 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -17,6 +17,7 @@
#include <linux/mutex.h>
#include <linux/math64.h>
#include <linux/sizes.h>
+#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/of_platform.h>
@@ -79,6 +80,7 @@ struct flash_info {
* Use dedicated 4byte address op codes
* to support memory size above 128Mib.
*/
+#define SPI_NOR_SKIP_SFDP BIT(11) /* Skip read of SFDP tables */
};
#define JEDEC_MFR(info) ((info)->id[0])
@@ -1331,6 +1333,87 @@ static int spansion_quad_enable(struct spi_nor *nor)
return 0;
}
+static int spansion_new_quad_enable(struct spi_nor *nor)
+{
+ u8 sr_cr[2];
+ int ret;
+
+ /* Check current Quad Enable bit value. */
+ ret = read_cr(nor);
+ if (ret < 0) {
+ dev_err(nor->dev,
+ "error while reading configuration register\n");
+ return -EINVAL;
+ }
+ sr_cr[1] = ret;
+ if (sr_cr[1] & CR_QUAD_EN_SPAN)
+ return 0;
+
+ dev_info(nor->dev, "setting Spansion Quad Enable (non-volatile) bit\n");
+
+ /* Keep the current value of the Status Register. */
+ ret = read_sr(nor);
+ if (ret < 0) {
+ dev_err(nor->dev,
+ "error while reading status register\n");
+ return -EINVAL;
+ }
+ sr_cr[0] = ret;
+ sr_cr[1] |= CR_QUAD_EN_SPAN;
+
+ write_enable(nor);
+
+ ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2);
+ if (ret < 0) {
+ dev_err(nor->dev,
+ "error while writing configuration register\n");
+ return -EINVAL;
+ }
+
+ /* read back and check it */
+ ret = read_cr(nor);
+ if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
+ dev_err(nor->dev, "Spansion Quad bit not set\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int sr2_bit7_quad_enable(struct spi_nor *nor)
+{
+ u8 sr2;
+ int ret;
+
+ /* Check current Quad Enable bit value. */
+ ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
+ if (ret)
+ return ret;
+ if (sr2 & SR2_QUAD_EN_BIT7)
+ return 0;
+
+ /* Update the Quad Enable bit. */
+ sr2 |= SR2_QUAD_EN_BIT7;
+
+ write_enable(nor);
+
+ ret = nor->write_reg(nor, SPINOR_OP_WRSR2, &sr2, 1);
+ if (ret < 0) {
+ dev_err(nor->dev,
+ "error while writing status register 2\n");
+ return -EINVAL;
+ }
+
+ /* Read back and check it. */
+ ret = nor->read_reg(nor, SPINOR_OP_RDSR2, &sr2, 1);
+ if (ret || !(sr2 & SR2_QUAD_EN_BIT7)) {
+ dev_err(nor->dev, "SR2 Quad bit not set\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int spi_nor_check(struct spi_nor *nor)
{
if (!nor->dev || !nor->read || !nor->write ||
@@ -1359,11 +1442,380 @@ static inline void spi_nor_set_erase_settings(struct spi_nor_erase_type *erase,
erase->opcode = opcode;
}
+static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, size_t len, void *buf)
+{
+ u8 addr_width, read_opcode, read_dummy;
+ int ret;
+
+ read_opcode = nor->read_opcode;
+ addr_width = nor->addr_width;
+ read_dummy = nor->read_dummy;
+
+ nor->read_opcode = SPINOR_OP_RDSFDP;
+ nor->addr_width = 3;
+ nor->read_dummy = 8;
+
+ ret = nor->read(nor, addr, len, (u8 *)buf);
+
+ nor->read_opcode = read_opcode;
+ nor->addr_width = addr_width;
+ nor->read_dummy = read_dummy;
+
+ return (ret < 0) ? ret : 0;
+}
+
+struct sfdp_parameter_header {
+ u8 id_lsb;
+ u8 minor;
+ u8 major;
+ u8 length; /* in double words */
+ u8 parameter_table_pointer[3]; /* byte address */
+ u8 id_msb;
+};
+
+#define SFDP_PARAM_HEADER_ID(p) ((u16)(((p)->id_msb << 8) | (p)->id_lsb))
+#define SFDP_PARAM_HEADER_PTP(p) \
+ ((u32)(((p)->parameter_table_pointer[2] << 16) | \
+ ((p)->parameter_table_pointer[1] << 8) | \
+ ((p)->parameter_table_pointer[0] << 0)))
+
+
+#define SFDP_BFPT_ID 0xff00u /* Basic Flash Parameter Table */
+
+#define SFDP_SIGNATURE 0x50444653u
+#define SFDP_JESD216_MAJOR 1
+#define SFDP_JESD216_MINOR 0
+#define SFDP_JESD216A_MINOR 5
+#define SFDP_JESD216B_MINOR 6
+
+struct sfdp_header {
+ u32 signature; /* Ox50444653 <=> "SFDP" */
+ u8 minor;
+ u8 major;
+ u8 nph; /* 0-base number of parameter headers */
+ u8 unused;
+
+ /* Basic Flash Parameter Table. */
+ struct sfdp_parameter_header bfpt_header;
+};
+
+/* Basic Flash Parameter Table */
+
+/* 1st DWORD. */
+#define BFPT_WORD0_FAST_READ_1_1_2 BIT(16)
+#define BFPT_WORD0_ADDRESS_BYTES_MASK GENMASK(18, 17)
+#define BFPT_WORD0_ADDRESS_BYTES_3_ONLY (0u << 17)
+#define BFPT_WORD0_ADDRESS_BYTES_3_OR_4 (1u << 17)
+#define BFPT_WORD0_ADDRESS_BYTES_4_ONLY (2u << 17)
+#define BFPT_WORD0_DTR BIT(19)
+#define BFPT_WORD0_FAST_READ_1_2_2 BIT(20)
+#define BFPT_WORD0_FAST_READ_1_4_4 BIT(21)
+#define BFPT_WORD0_FAST_READ_1_1_4 BIT(22)
+
+/* 15th DWORD. */
+
+/*
+ * (from JESD216B)
+ * Quad Enable Requirements (QER):
+ * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
+ * reads based on instruction. DQ3/HOLD# functions are hold during
+ * instruction pahse.
+ * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
+ * two data bytes where bit 1 of the second byte is one.
+ * [...]
+ * Writing only one byte to the status register has the side-effect of
+ * clearing status register 2, including the QE bit. The 100b code is
+ * used if writing one byte to the status register does not modify
+ * status register 2.
+ * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
+ * one data byte where bit 6 is one.
+ * [...]
+ * - 011b: QE is bit 7 of status register 2. It is set via Write status
+ * register 2 instruction 3Eh with one data byte where bit 7 is one.
+ * [...]
+ * The status register 2 is read using instruction 3Fh.
+ * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
+ * two data bytes where bit 1 of the second byte is one.
+ * [...]
+ * In contrast to the 001b code, writing one byte to the status
+ * register does not modify status register 2.
+ * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
+ * Read Status instruction 05h. Status register2 is read using
+ * instruction 35h. QE is set via Writ Status instruction 01h with
+ * two data bytes where bit 1 of the second byte is one.
+ * [...]
+ */
+#define BFPT_WORD14_QER_MASK GENMASK(22, 20)
+#define BFPT_WORD14_QER_NONE (0 << 20) /* Micron */
+#define BFPT_WORD14_QER_SR2_BIT1_BUGGY (1 << 20)
+#define BFPT_WORD14_QER_SR1_BIT6 (2 << 20) /* Macronix */
+#define BFPT_WORD14_QER_SR2_BIT7 (3 << 20)
+#define BFPT_WORD14_QER_SR2_BIT1_NO_RD (4 << 20)
+#define BFPT_WORD14_QER_SR2_BIT1 (5 << 20) /* Spansion */
+
+/* JESD216B defines a Basic Flash Parameter Table of 16 words. */
+#define SFDP_BFPT_MAX_WORDS 16
+
+struct sfdp_bfpt {
+ u32 word[SFDP_BFPT_MAX_WORDS];
+};
+
+/* Fast Read settings. */
+#define BFPT_FAST_READ_WAIT_STATES(half) ((((u16)(half)) >> 0) & 0x1f)
+#define BFPT_FAST_READ_MODE_CLOCKS(half) ((((u16)(half)) >> 5) & 0x07)
+#define BFPT_FAST_READ_OP_CODE(half) ((((u16)(half)) >> 8) & 0xff)
+
+struct sfdp_read {
+ /* The protocol index of SPI x-y-z. */
+ enum spi_nor_protocol_index pindex;
+
+ /*
+ * The bit <wbit> in DWORD<windex> tells us whether the
+ * Fast Read x-y-z command is supported.
+ */
+ int windex;
+ int wbit;
+
+ /*
+ * The half-word at offset <hshift> in DWORD<hindex> encodes the
+ * op code, the number of mode clocks and the number of wait states
+ * to be used by Fast Read x-y-z commands.
+ */
+ int hindex;
+ int hshift;
+};
+
+static const struct sfdp_read sfdp_reads[] = {
+ /* Supported: DWORD0 bit 16, Settings: DWORD3 bit[15:0] */
+ {SNOR_PINDEX_1_1_2, 0, 16, 3, 0},
+
+ /* Supported: DWORD0 bit 20, Settings: DWORD3 bit[31:16] */
+ {SNOR_PINDEX_1_2_2, 0, 20, 3, 16},
+
+ /* Supported: DWORD4 bit 0, Settings: DWORD5 bit[31:16] */
+ {SNOR_PINDEX_2_2_2, 4, 0, 5, 16},
+
+ /* Supported: DWORD0 bit 22, Settings: DWORD2 bit[31:16] */
+ {SNOR_PINDEX_1_1_4, 0, 22, 2, 16},
+
+ /* Supported: DWORD0 bit 21, Settings: DWORD2 bit[15:0] */
+ {SNOR_PINDEX_1_4_4, 0, 21, 2, 0},
+
+ /* Supported: DWORD4 bit 4, Settings: DWORD6 bit[31:16] */
+ {SNOR_PINDEX_4_4_4, 4, 4, 6, 16},
+};
+
+
+/* Sector Erase settings. */
+#define BFPT_ERASE_SIZE(half) ((((u16)(half)) >> 0) & 0xff)
+#define BFPT_ERASE_OP_CODE(half) ((((u16)(half)) >> 8) & 0xff)
+
+struct sfdp_erase {
+ /*
+ * The half-word at offset <hshift> in DWORD<hindex> encodes the
+ * op code and erase sector size to be used by Sector Erase commands.
+ */
+ int hindex;
+ int hshift;
+};
+
+static const struct sfdp_erase sfdp_erases[SNOR_MAX_ERASE_TYPES] = {
+ /* Erase Type 1 in DWORD7 bits[15:0] */
+ {7, 0},
+
+ /* Erase Type 2 in DWORD7 bits[31:16] */
+ {7, 16},
+
+ /* Erase Type 3 in DWORD8 bits[15:0] */
+ {8, 0},
+
+ /* Erase Type 4: in DWORD8 bits[31:16] */
+ {8, 16},
+};
+
+
+static int spi_nor_parse_bfpt(struct spi_nor *nor,
+ const struct sfdp_parameter_header *bfpt_header,
+ struct spi_nor_basic_flash_parameter *params)
+{
+ struct sfdp_bfpt bfpt;
+ size_t len;
+ int i, err;
+ u32 addr;
+ u16 half;
+
+ /* JESD216 Basic Flash Parameter Table length is at least 9 words. */
+ if (bfpt_header->length < 9)
+ return -EINVAL;
+
+ /* Read the Basic Flash Parameter Table. */
+ len = min_t(size_t, sizeof(bfpt),
+ bfpt_header->length * sizeof(uint32_t));
+ addr = SFDP_PARAM_HEADER_PTP(bfpt_header);
+ memset(&bfpt, 0, sizeof(bfpt));
+ err = spi_nor_read_sfdp(nor, addr, len, &bfpt);
+ if (err)
+ return err;
+
+ for (i = 0; i < SFDP_BFPT_MAX_WORDS; ++i)
+ bfpt.word[i] = le32_to_cpu(bfpt.word[i]);
+
+ memset(params, 0, sizeof(*params));
+
+ /* Fast Read settings. */
+ params->rd_modes = (SNOR_MODE_SLOW | SNOR_MODE_1_1_1);
+ spi_nor_set_read_settings(¶ms->reads[SNOR_PINDEX_SLOW],
+ 0, 0, SPINOR_OP_READ);
+ spi_nor_set_read_settings(¶ms->reads[SNOR_PINDEX_1_1_1],
+ 0, 8, SPINOR_OP_READ_FAST);
+
+ for (i = 0; i < ARRAY_SIZE(sfdp_reads); ++i) {
+ const struct sfdp_read *rd_info = &sfdp_reads[i];
+ struct spi_nor_read *read = ¶ms->reads[rd_info->pindex];
+
+ if (!(bfpt.word[rd_info->windex] & BIT(rd_info->wbit)))
+ continue;
+
+ params->rd_modes |= BIT(rd_info->pindex);
+ half = bfpt.word[rd_info->hindex] >> rd_info->hshift;
+ read->num_mode_clocks = BFPT_FAST_READ_MODE_CLOCKS(half);
+ read->num_wait_states = BFPT_FAST_READ_WAIT_STATES(half);
+ read->opcode = BFPT_FAST_READ_OP_CODE(half);
+ }
+
+ /* Page Program settings. */
+ params->wr_modes = SNOR_MODE_1_1_1;
+ params->page_programs[SNOR_PINDEX_1_1_1] = SPINOR_OP_PP;
+
+ /* Sector Erase settings. */
+ for (i = 0; i < SNOR_MAX_ERASE_TYPES; ++i) {
+ const struct sfdp_erase *er_info = &sfdp_erases[i];
+ struct spi_nor_erase_type *erase = ¶ms->erase_types[i];
+
+ half = bfpt.word[er_info->hindex] >> er_info->hshift;
+ erase->size = BFPT_ERASE_SIZE(half);
+ erase->opcode = BFPT_ERASE_OP_CODE(half);
+ }
+
+ /* Stop here if not JESD216 rev B or later. */
+ if (bfpt_header->length < 15)
+ return 0;
+
+ /* Enable Quad I/O. */
+ switch (bfpt.word[14] & BFPT_WORD14_QER_MASK) {
+ default:
+ case BFPT_WORD14_QER_NONE:
+ break;
+
+ case BFPT_WORD14_QER_SR2_BIT1_BUGGY:
+ case BFPT_WORD14_QER_SR2_BIT1_NO_RD:
+ params->enable_quad_io = spansion_quad_enable;
+ break;
+
+ case BFPT_WORD14_QER_SR1_BIT6:
+ params->enable_quad_io = macronix_quad_enable;
+ break;
+
+ case BFPT_WORD14_QER_SR2_BIT7:
+ params->enable_quad_io = sr2_bit7_quad_enable;
+ break;
+
+ case BFPT_WORD14_QER_SR2_BIT1:
+ params->enable_quad_io = spansion_new_quad_enable;
+ break;
+ }
+
+ return 0;
+}
+
+static int spi_nor_parse_sfdp(struct spi_nor *nor,
+ struct spi_nor_basic_flash_parameter *params)
+{
+ const struct sfdp_parameter_header *param_header, *bfpt_header;
+ struct sfdp_parameter_header *param_headers = NULL;
+ struct sfdp_header header;
+ size_t psize;
+ int i, err;
+
+ /* Get the SFDP header. */
+ err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
+ if (err)
+ return err;
+
+ /* Check the SFDP header version. */
+ if (le32_to_cpu(header.signature) != SFDP_SIGNATURE ||
+ header.major != SFDP_JESD216_MAJOR ||
+ header.minor < SFDP_JESD216_MINOR)
+ return -EINVAL;
+
+ /*
+ * Verify that the first and only mandatory parameter header is a
+ * Basic Flash Parameter Table header as specified in JESD216.
+ */
+ bfpt_header = &header.bfpt_header;
+ if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID ||
+ bfpt_header->major != SFDP_JESD216_MAJOR)
+ return -EINVAL;
+
+ /* Allocate memory for parameter headers. */
+ if (header.nph) {
+ psize = header.nph * sizeof(*param_headers);
+
+ param_headers = kmalloc(psize, GFP_KERNEL);
+ if (!param_headers) {
+ dev_err(nor->dev,
+ "failed to allocate memory for SFDP parameter headers\n");
+ return -ENOMEM;
+ }
+
+ err = spi_nor_read_sfdp(nor, sizeof(header),
+ psize, param_headers);
+ if (err) {
+ dev_err(nor->dev,
+ "failed to read SFDP parameter headers\n");
+ goto exit;
+ }
+ }
+
+ /*
+ * Check other parameter headers to get the latest revision of
+ * the basic flash parameter table.
+ */
+ for (i = 0; i < header.nph; ++i) {
+ param_header = ¶m_headers[i];
+
+ if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID &&
+ param_header->major == SFDP_JESD216_MAJOR &&
+ (param_header->minor > bfpt_header->minor ||
+ (param_header->minor == bfpt_header->minor &&
+ param_header->length > bfpt_header->length)))
+ bfpt_header = param_header;
+ }
+ err = spi_nor_parse_bfpt(nor, bfpt_header, params);
+ if (err)
+ goto exit;
+
+exit:
+ kfree(param_headers);
+ return (err) ? err : bfpt_header->minor;
+}
+
static int spi_nor_init_params(struct spi_nor *nor,
const struct flash_info *info,
struct spi_nor_basic_flash_parameter *params)
{
- // TODO: parse SFDP table
+ int jesd216_minor = -EINVAL;
+
+ /* First trying to parse SFDP tables. */
+ if (!(info->flags & SPI_NOR_SKIP_SFDP)) {
+ jesd216_minor = spi_nor_parse_sfdp(nor, params);
+
+ if (jesd216_minor >= SFDP_JESD216B_MINOR)
+ return 0;
+
+ if (jesd216_minor >= SFDP_JESD216_MINOR)
+ goto set_enable_quad_io;
+ }
/* If SFDP tables are not available, use legacy settings. */
memset(params, 0, sizeof(*params));
@@ -1402,6 +1854,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
spi_nor_set_erase_settings(¶ms->erase_types[1],
SNOR_ERASE_4K, SPINOR_OP_BE_4K_PMC);
+set_enable_quad_io:
/* Select the procedure to set the Quad Enable bit. */
if (params->rd_modes & (SNOR_MODE_1_1_4 |
SNOR_MODE_1_4_4 |
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 730f33dce1ea..ede7ad83c9c5 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -41,6 +41,8 @@
#define SPINOR_OP_WREN 0x06 /* Write enable */
#define SPINOR_OP_RDSR 0x05 /* Read status register */
#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
+#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
+#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
@@ -56,6 +58,7 @@
#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
+#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
@@ -110,6 +113,9 @@
/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
+/* Status Register 2 bits. */
+#define SR2_QUAD_EN_BIT7 BIT(7)
+
/* Supported SPI protocols */
enum spi_nor_protocol_class {
--
2.7.4
This patch adds supports for SFDP (JESD216B) 4-byte Address Instruction
Table. This table is optional but when available, we parse it to get the
4-byte address op codes supported by the memory.
Using these op codes is stateless as opposed to entering the 4-byte
address mode or setting the Base Address Register (BAR).
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 140 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 139 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index e91b3c39b68e..879b98ef1d80 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1481,6 +1481,7 @@ struct sfdp_parameter_header {
#define SFDP_BFPT_ID 0xff00u /* Basic Flash Parameter Table */
+#define SFDP_4BAIT_ID 0xff84u /* 4-byte Address Instruction Table */
#define SFDP_SIGNATURE 0x50444653u
#define SFDP_JESD216_MAJOR 1
@@ -1728,6 +1729,124 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
return 0;
}
+struct sfdp_4bait {
+ enum spi_nor_protocol_index pindex;
+ int wbit;
+};
+
+static int spi_nor_parse_4bait(struct spi_nor *nor,
+ const struct sfdp_parameter_header *param_header,
+ struct spi_nor_basic_flash_parameter *params)
+{
+ static const struct sfdp_4bait reads[] = {
+ {SNOR_PINDEX_SLOW, 0}, /* 0x13 */
+ {SNOR_PINDEX_1_1_1, 1}, /* 0x0c */
+ {SNOR_PINDEX_1_1_2, 2}, /* 0x3c */
+ {SNOR_PINDEX_1_2_2, 3}, /* 0xbc */
+ {SNOR_PINDEX_1_1_4, 4}, /* 0x6c */
+ {SNOR_PINDEX_1_4_4, 5}, /* 0xec */
+ };
+ static const struct sfdp_4bait programs[] = {
+ {SNOR_PINDEX_1_1_1, 6}, /* 0x12 */
+ {SNOR_PINDEX_1_1_4, 7}, /* 0x34 */
+ {SNOR_PINDEX_1_4_4, 8}, /* 0x3e */
+ };
+ static const struct sfdp_4bait erases[SNOR_MAX_ERASE_TYPES] = {
+ {SNOR_PINDEX_1_1_1, 9},
+ {SNOR_PINDEX_1_1_1, 10},
+ {SNOR_PINDEX_1_1_1, 11},
+ {SNOR_PINDEX_1_1_1, 12},
+ };
+ u32 word[2], addr, rd_modes, wr_modes, erase_modes;
+ int i, err;
+
+ if (param_header->major != SFDP_JESD216_MAJOR ||
+ param_header->length < 2)
+ return -EINVAL;
+
+ /* Read the 4-byte Address Instruction Table. */
+ addr = SFDP_PARAM_HEADER_PTP(param_header);
+ err = spi_nor_read_sfdp(nor, addr, sizeof(word), word);
+ if (err)
+ return err;
+
+ for (i = 0; i < 2; ++i)
+ word[i] = le32_to_cpu(word[i]);
+
+ /*
+ * Compute the subset of (Fast) Read commands for which the 4-byte
+ * version is supported.
+ */
+ rd_modes = 0;
+ for (i = 0; i < ARRAY_SIZE(reads); ++i) {
+ const struct sfdp_4bait *read = &reads[i];
+
+ if ((params->rd_modes & BIT(read->pindex)) &&
+ (word[0] & BIT(read->wbit)))
+ rd_modes |= BIT(read->pindex);
+ }
+
+ /*
+ * Compute the subset of Page Program commands for which the 4-byte
+ * version is supported.
+ */
+ wr_modes = 0;
+ for (i = 0; i < ARRAY_SIZE(programs); ++i) {
+ const struct sfdp_4bait *program = &programs[i];
+
+ if ((params->wr_modes & BIT(program->pindex)) &&
+ (word[0] & BIT(program->wbit)))
+ wr_modes |= BIT(program->pindex);
+ }
+
+ /*
+ * Compute the subet of Sector Erase commands for which the 4-byte
+ * version is supported.
+ */
+ erase_modes = 0;
+ for (i = 0; i < SNOR_MAX_ERASE_TYPES; ++i) {
+ const struct sfdp_4bait *erase = &erases[i];
+
+ if ((params->erase_types[i].size > 0) &&
+ (word[0] & BIT(erase->wbit)))
+ erase_modes |= BIT(i);
+ }
+
+ /*
+ * We need at least one 4-byte op code per read, program and erase
+ * operation; the .read(), .write() and .erase() hooks share the
+ * nor->addr_width value.
+ */
+ if (!rd_modes || !wr_modes || !erase_modes)
+ return 0;
+
+ /*
+ * Discard all operations from the 4-byte instruction set which are
+ * not supported by this memory.
+ */
+ params->rd_modes = rd_modes;
+ params->wr_modes = wr_modes;
+ for (i = 0; i < SNOR_MAX_ERASE_TYPES; ++i)
+ if (!(erase_modes & BIT(i)))
+ params->erase_types[i].size = 0;
+
+ /* Use the 4-byte address instruction set. */
+ params->reads[SNOR_PINDEX_SLOW].opcode = SPINOR_OP_READ_4B;
+ params->reads[SNOR_PINDEX_1_1_1].opcode = SPINOR_OP_READ_FAST_4B;
+ params->reads[SNOR_PINDEX_1_1_2].opcode = SPINOR_OP_READ_1_1_2_4B;
+ params->reads[SNOR_PINDEX_1_2_2].opcode = SPINOR_OP_READ_1_2_2_4B;
+ params->reads[SNOR_PINDEX_1_1_4].opcode = SPINOR_OP_READ_1_1_4_4B;
+ params->reads[SNOR_PINDEX_1_4_4].opcode = SPINOR_OP_READ_1_4_4_4B;
+ params->page_programs[SNOR_PINDEX_1_1_1] = SPINOR_OP_PP_4B;
+ params->page_programs[SNOR_PINDEX_1_1_4] = SPINOR_OP_PP_1_1_4_4B;
+ params->page_programs[SNOR_PINDEX_1_4_4] = SPINOR_OP_PP_1_4_4_4B;
+ for (i = 0; i < SNOR_MAX_ERASE_TYPES; ++i)
+ params->erase_types[i].opcode = (word[1] >> (i * 8)) & 0xff;
+
+ nor->addr_width = 4;
+ return 0;
+}
+
static int spi_nor_parse_sfdp(struct spi_nor *nor,
struct spi_nor_basic_flash_parameter *params)
{
@@ -1795,6 +1914,23 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
if (err)
goto exit;
+ /* Parse other parameter headers. */
+ for (i = 0; i < header.nph; ++i) {
+ param_header = ¶m_headers[i];
+
+ switch (SFDP_PARAM_HEADER_ID(param_header)) {
+ case SFDP_4BAIT_ID:
+ err = spi_nor_parse_4bait(nor, param_header, params);
+ break;
+
+ default:
+ break;
+ }
+
+ if (err)
+ goto exit;
+ }
+
exit:
kfree(param_headers);
return (err) ? err : bfpt_header->minor;
@@ -2149,7 +2285,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
if (ret)
return ret;
- if (info->addr_width)
+ if (nor->addr_width)
+ ; /* already configured by spi_nor_setup(). */
+ else if (info->addr_width)
nor->addr_width = info->addr_width;
else if (mtd->size > 0x1000000) {
/* enable 4-byte addressing if the device exceeds 16MiB */
--
2.7.4
This patch adds an entry in the spi_nor_ids[] table to add support
to the Macronix mx66l1g45g.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 879b98ef1d80..031c6792a3fe 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -937,6 +937,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
+ { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
/* Micron */
--
2.7.4
This patch adds support to the SST sst26* QSPI memories.
It also adds a new SST_BLOCK_PROTECT flag so spi_nor_scan() sends
a SST Global Block Protection Unlock (98h) command once for all
otherwise later Sector Erase and Page Program commands would fail.
It was tested with sst26vf016b, sst26vf032b, sst26vf032ba and sst26vf064b
on a sama5d2 xplained board at 55.3MHz and 3.3V.
sst26wf040b and sst26wf080b were not tested since they are 1.8V memories
hence don't fit the sama5d2 xplained board requirements.
Signed-off-by: Cyrille Pitchen <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 20 ++++++++++++++++++++
include/linux/mtd/spi-nor.h | 1 +
2 files changed, 21 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 031c6792a3fe..355824bd3587 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -81,6 +81,7 @@ struct flash_info {
* to support memory size above 128Mib.
*/
#define SPI_NOR_SKIP_SFDP BIT(11) /* Skip read of SFDP tables */
+#define SST_BLOCK_PROTECT BIT(12) /* use SST Unlock Block-Protection */
};
#define JEDEC_MFR(info) ((info)->id[0])
@@ -999,6 +1000,11 @@ static const struct flash_info spi_nor_ids[] = {
{ "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
{ "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
+ { "sst26vf016b", INFO(0xbf2641, 0, 64 * 1024, 32, SECT_4K | SST_BLOCK_PROTECT) },
+ { "sst26vf032b", INFO(0xbf2642, 0, 64 * 1024, 64, SECT_4K | SST_BLOCK_PROTECT) },
+ { "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SST_BLOCK_PROTECT) },
+ { "sst26wf040b", INFO(0xbf2654, 0, 64 * 1024, 8, SECT_4K | SST_BLOCK_PROTECT) },
+ { "sst26wf080b", INFO(0xbf2658, 0, 64 * 1024, 16, SECT_4K | SST_BLOCK_PROTECT) },
/* ST Microelectronics -- newer production may have feature updates */
{ "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
@@ -1135,6 +1141,14 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
return ret;
}
+static int sst_unlock_block_protection(struct spi_nor *nor)
+{
+ int ret;
+
+ ret = write_enable(nor);
+ return ret ? ret : nor->write_reg(nor, SPINOR_OP_ULBPR, NULL, 0);
+}
+
static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
size_t *retlen, const u_char *buf)
{
@@ -2308,6 +2322,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
return -EINVAL;
}
+ if (info->flags & SST_BLOCK_PROTECT) {
+ ret = sst_unlock_block_protection(nor);
+ if (ret)
+ return ret;
+ }
+
dev_info(dev, "%s (%lld Kbytes)\n", info->name,
(long long)mtd->size >> 10);
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index ede7ad83c9c5..016b6c51e854 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -80,6 +80,7 @@
#define SPINOR_OP_BP 0x02 /* Byte program */
#define SPINOR_OP_WRDI 0x04 /* Write disable */
#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
+#define SPINOR_OP_ULBPR 0x98 /* Global Block Protection Unlock */
/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
--
2.7.4
On Wednesday 05 October 2016 05:30 PM, Cyrille Pitchen wrote:
> This patch provides an alternative mean to support memory above 16MiB
> (128Mib) by replacing 3byte address op codes by their associated 4byte
> address versions.
>
> Using the dedicated 4byte address op codes doesn't change the internal
> state of the SPI NOR memory as opposed to using other means such as
> updating a Base Address Register (BAR) and sending command to enter/leave
> the 4byte mode.
>
> Hence when a CPU reset occurs, early bootloaders don't need to be aware
> of BAR value or 4byte mode being enabled: they can still access the first
> 16MiB of the SPI NOR memory using the regular 3byte address op codes.
>
I am facing a similar issue on my am437x-idk board with mx66l51235l
flash and bootloader failed to access flash due to 4byte mode being
enabled. With SPI_NOR_4B_OPCODES flag set in mx66l51235l flash info and
this series applied, I can see that bootloader can now access flash.
Thanks for the patch!
FWIW, Tested-by: Vignesh R <[email protected]>
> Signed-off-by: Cyrille Pitchen <[email protected]>
> ---
> drivers/mtd/devices/serial_flash_cmds.h | 7 ---
> drivers/mtd/devices/st_spi_fsm.c | 28 ++++-----
> drivers/mtd/spi-nor/spi-nor.c | 104 +++++++++++++++++++++++++-------
> include/linux/mtd/spi-nor.h | 22 +++++--
> 4 files changed, 113 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/mtd/devices/serial_flash_cmds.h b/drivers/mtd/devices/serial_flash_cmds.h
> index f59a125295d0..8b81e15105dd 100644
> --- a/drivers/mtd/devices/serial_flash_cmds.h
> +++ b/drivers/mtd/devices/serial_flash_cmds.h
> @@ -18,19 +18,12 @@
> #define SPINOR_OP_RDVCR 0x85
>
> /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
> -#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */
> -#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */
> -
> #define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
> #define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
> #define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
> #define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
> #define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
>
> -/* READ commands with 32-bit addressing */
> -#define SPINOR_OP_READ4_1_2_2 0xbc
> -#define SPINOR_OP_READ4_1_4_4 0xec
> -
> /* Configuration flags */
> #define FLASH_FLAG_SINGLE 0x000000ff
> #define FLASH_FLAG_READ_WRITE 0x00000001
> diff --git a/drivers/mtd/devices/st_spi_fsm.c b/drivers/mtd/devices/st_spi_fsm.c
> index 5454b4113589..804313a33f2b 100644
> --- a/drivers/mtd/devices/st_spi_fsm.c
> +++ b/drivers/mtd/devices/st_spi_fsm.c
> @@ -507,13 +507,13 @@ static struct seq_rw_config n25q_read3_configs[] = {
> * - 'FAST' variants configured for 8 dummy cycles (see note above.)
> */
> static struct seq_rw_config n25q_read4_configs[] = {
> - {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
> - {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
> - {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
> - {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
> - {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
> - {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
> - {0x00, 0, 0, 0, 0, 0x00, 0, 0},
> + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8},
> + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
> + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8},
> + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
> + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
> + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
> + {0x00, 0, 0, 0, 0, 0x00, 0, 0},
> };
>
> /*
> @@ -553,13 +553,13 @@ static int stfsm_mx25_en_32bit_addr_seq(struct stfsm_seq *seq)
> * entering a state that is incompatible with the SPIBoot Controller.
> */
> static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
> - {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
> - {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
> - {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
> - {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
> - {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
> - {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
> - {0x00, 0, 0, 0, 0, 0x00, 0, 0},
> + {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 2, 4},
> + {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
> + {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 4, 0},
> + {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
> + {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
> + {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
> + {0x00, 0, 0, 0, 0, 0x00, 0, 0},
> };
>
> static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 5c87b2d99507..423448c1c7a8 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -75,6 +75,10 @@ struct flash_info {
> * bit. Must be used with
> * SPI_NOR_HAS_LOCK.
> */
> +#define SPI_NOR_4B_OPCODES BIT(10) /*
> + * Use dedicated 4byte address op codes
> + * to support memory size above 128Mib.
> + */
> };
>
> #define JEDEC_MFR(info) ((info)->id[0])
> @@ -188,6 +192,81 @@ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
> return mtd->priv;
> }
>
> +
> +struct spi_nor_address_entry {
> + u8 src_opcode;
> + u8 dst_opcode;
> +};
> +
> +static u8 spi_nor_convert_opcode(u8 opcode,
> + const struct spi_nor_address_entry *entries,
> + size_t num_entries)
> +{
> + int min, max;
> +
> + min = 0;
> + max = num_entries - 1;
> + while (min <= max) {
> + int mid = (min + max) >> 1;
> + const struct spi_nor_address_entry *entry = &entries[mid];
> +
> + if (opcode == entry->src_opcode)
> + return entry->dst_opcode;
> +
> + if (opcode < entry->src_opcode)
> + max = mid - 1;
> + else
> + min = mid + 1;
> + }
> +
> + /* No conversion found */
> + return opcode;
> +}
> +
> +static u8 spi_nor_3to4_opcode(u8 opcode)
> +{
> + /* MUST be sorted by 3byte opcode */
> +#define ENTRY_3TO4(_opcode) { _opcode, _opcode##_4B }
> + static const struct spi_nor_address_entry spi_nor_3to4_table[] = {
> + ENTRY_3TO4(SPINOR_OP_PP), /* 0x02 */
> + ENTRY_3TO4(SPINOR_OP_READ), /* 0x03 */
> + ENTRY_3TO4(SPINOR_OP_READ_FAST), /* 0x0b */
> + ENTRY_3TO4(SPINOR_OP_BE_4K), /* 0x20 */
> + ENTRY_3TO4(SPINOR_OP_PP_1_1_4), /* 0x32 */
> + ENTRY_3TO4(SPINOR_OP_PP_1_4_4), /* 0x38 */
> + ENTRY_3TO4(SPINOR_OP_READ_1_1_2), /* 0x3b */
> + ENTRY_3TO4(SPINOR_OP_BE_32K), /* 0x52 */
> + ENTRY_3TO4(SPINOR_OP_READ_1_1_4), /* 0x6b */
> + ENTRY_3TO4(SPINOR_OP_READ_1_2_2), /* 0xbb */
> + ENTRY_3TO4(SPINOR_OP_SE), /* 0xd8 */
> + ENTRY_3TO4(SPINOR_OP_READ_1_4_4), /* 0xeb */
> + };
> +#undef ENTRY_3TO4
> +
> + return spi_nor_convert_opcode(opcode, spi_nor_3to4_table,
> + ARRAY_SIZE(spi_nor_3to4_table));
> +}
> +
> +static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
> + const struct flash_info *info)
> +{
> + /* Do some manufacturer fixups first */
> + switch (JEDEC_MFR(info)) {
> + case SNOR_MFR_SPANSION:
> + /* No small sector erase for 4-byte command set */
> + nor->erase_opcode = SPINOR_OP_SE;
> + nor->mtd.erasesize = info->sector_size;
> + break;
> +
> + default:
> + break;
> + }
> +
> + nor->read_opcode = spi_nor_3to4_opcode(nor->read_opcode);
> + nor->program_opcode = spi_nor_3to4_opcode(nor->program_opcode);
> + nor->erase_opcode = spi_nor_3to4_opcode(nor->erase_opcode);
> +}
> +
> /* Enable/disable 4-byte addressing mode. */
> static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
> int enable)
> @@ -1476,27 +1555,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
> else if (mtd->size > 0x1000000) {
> /* enable 4-byte addressing if the device exceeds 16MiB */
> nor->addr_width = 4;
> - if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
> - /* Dedicated 4-byte command set */
> - switch (nor->flash_read) {
> - case SPI_NOR_QUAD:
> - nor->read_opcode = SPINOR_OP_READ4_1_1_4;
> - break;
> - case SPI_NOR_DUAL:
> - nor->read_opcode = SPINOR_OP_READ4_1_1_2;
> - break;
> - case SPI_NOR_FAST:
> - nor->read_opcode = SPINOR_OP_READ4_FAST;
> - break;
> - case SPI_NOR_NORMAL:
> - nor->read_opcode = SPINOR_OP_READ4;
> - break;
> - }
> - nor->program_opcode = SPINOR_OP_PP_4B;
> - /* No small sector erase for 4-byte command set */
> - nor->erase_opcode = SPINOR_OP_SE_4B;
> - mtd->erasesize = info->sector_size;
> - } else
> + if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
> + info->flags & SPI_NOR_4B_OPCODES)
> + spi_nor_set_4byte_opcodes(nor, info);
> + else
> set_4byte(nor, info, 1);
> } else {
> nor->addr_width = 3;
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index c425c7b4c2a0..8b02fd7864d0 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -43,9 +43,13 @@
> #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
> #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
> #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
> -#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
> -#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
> +#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
> +#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
> +#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
> +#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
> #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
> +#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
> +#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
> #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
> #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
> #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
> @@ -56,11 +60,17 @@
> #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
>
> /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
> -#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
> -#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
> -#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
> -#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
> +#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
> +#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
> +#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
> +#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
> +#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
> +#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
> #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
> +#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
> +#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
> +#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
> +#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
> #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
>
> /* Used for SST flashes only. */
>
--
Regards
Vignesh
On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
<[email protected]> wrote:
> Hi all,
>
> This series extends support of SPI protocols to new protocols such as
> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
> op codes, timing parameters (number of mode and dummy cycles) and erase
> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
> tables, when available, as defined in the JEDEC JESD216 specifications.
>
> When SFDP tables are not available, legacy settings are still used for
> backward compatibility (SPI and earlier QSPI memories).
>
> Support of SPI memories >128Mbits is also improved by using the 4byte
> address instruction set, when available. Using those dedicated op codes
> is stateless as opposed to enter the 4byte address mode, hence a better
> compatibility with some boot loaders which expect to use 3byte address
> op codes.
The memories which are > 128Mbits should have 4-bytes addressing
support based on my experience, do you think BAR is also required
atleast from spi-nor side?
thanks!
--
Jagan Teki
Free Software Engineer | http://www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
On 10/22/2016 01:00 PM, Jagan Teki wrote:
> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
> <[email protected]> wrote:
>> Hi all,
>>
>> This series extends support of SPI protocols to new protocols such as
>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
>> op codes, timing parameters (number of mode and dummy cycles) and erase
>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
>> tables, when available, as defined in the JEDEC JESD216 specifications.
>>
>> When SFDP tables are not available, legacy settings are still used for
>> backward compatibility (SPI and earlier QSPI memories).
>>
>> Support of SPI memories >128Mbits is also improved by using the 4byte
>> address instruction set, when available. Using those dedicated op codes
>> is stateless as opposed to enter the 4byte address mode, hence a better
>> compatibility with some boot loaders which expect to use 3byte address
>> op codes.
>
> The memories which are > 128Mbits should have 4-bytes addressing
> support based on my experience, do you think BAR is also required
> atleast from spi-nor side?
Yes, I believe BAR is still required for broken/dumb flash chips.
Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-(
--
Best regards,
Marek Vasut
On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
<[email protected]> wrote:
> The patch checks whether the Quad Enable bit is already set in the Status
> Register. If so, the function exits immediately with a successful return
> code. Otherwise, a message is now printed telling we're setting the
> non-volatile bit.
>
> Signed-off-by: Cyrille Pitchen <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index d0fc165d7d66..5c87b2d99507 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1211,6 +1211,11 @@ static int macronix_quad_enable(struct spi_nor *nor)
> val = read_sr(nor);
> if (val < 0)
> return val;
> + if (val & SR_QUAD_EN_MX)
> + return 0;
> +
> + /* Update the Quad Enable bit. */
> + dev_info(nor->dev, "setting Macronix Quad Enable (non-volatile) bit\n");
> write_enable(nor);
>
> write_sr(nor, val | SR_QUAD_EN_MX);
Safe to save ret and check the same as well.
thanks!
--
Jagan Teki
Free Software Engineer | http://www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut <[email protected]> wrote:
> On 10/22/2016 01:00 PM, Jagan Teki wrote:
>> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
>> <[email protected]> wrote:
>>> Hi all,
>>>
>>> This series extends support of SPI protocols to new protocols such as
>>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
>>> op codes, timing parameters (number of mode and dummy cycles) and erase
>>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
>>> tables, when available, as defined in the JEDEC JESD216 specifications.
>>>
>>> When SFDP tables are not available, legacy settings are still used for
>>> backward compatibility (SPI and earlier QSPI memories).
>>>
>>> Support of SPI memories >128Mbits is also improved by using the 4byte
>>> address instruction set, when available. Using those dedicated op codes
>>> is stateless as opposed to enter the 4byte address mode, hence a better
>>> compatibility with some boot loaders which expect to use 3byte address
>>> op codes.
>>
>> The memories which are > 128Mbits should have 4-bytes addressing
>> support based on my experience, do you think BAR is also required
>> atleast from spi-nor side?
>
> Yes, I believe BAR is still required for broken/dumb flash chips.
> Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-(
Do you have list for those broken chips? because I never find any
chips which has > 16 MiB with not support of 4-byte address opcodes
and I've seen the controller has dependable with BAR though it can
access > 16MiB ex: zynq qspi/
thanks!
--
Jagan Teki
Free Software Engineer | http://www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
On 10/24/2016 09:41 AM, Jagan Teki wrote:
> On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut <[email protected]> wrote:
>> On 10/22/2016 01:00 PM, Jagan Teki wrote:
>>> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
>>> <[email protected]> wrote:
>>>> Hi all,
>>>>
>>>> This series extends support of SPI protocols to new protocols such as
>>>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
>>>> op codes, timing parameters (number of mode and dummy cycles) and erase
>>>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
>>>> tables, when available, as defined in the JEDEC JESD216 specifications.
>>>>
>>>> When SFDP tables are not available, legacy settings are still used for
>>>> backward compatibility (SPI and earlier QSPI memories).
>>>>
>>>> Support of SPI memories >128Mbits is also improved by using the 4byte
>>>> address instruction set, when available. Using those dedicated op codes
>>>> is stateless as opposed to enter the 4byte address mode, hence a better
>>>> compatibility with some boot loaders which expect to use 3byte address
>>>> op codes.
>>>
>>> The memories which are > 128Mbits should have 4-bytes addressing
>>> support based on my experience, do you think BAR is also required
>>> atleast from spi-nor side?
>>
>> Yes, I believe BAR is still required for broken/dumb flash chips.
>> Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-(
>
> Do you have list for those broken chips?
No.
> because I never find any
> chips which has > 16 MiB with not support of 4-byte address opcodes
> and I've seen the controller has dependable with BAR though it can
> access > 16MiB ex: zynq qspi/
IIRC some of the 32 MiB micron chips were pretty flaky in that aspect,
they used the same opcodes for 4byte access as for 3byte access and
their behavior was switched by writing some non-volatile bit.
--
Best regards,
Marek Vasut
Hi Jagan,
Le 24/10/2016 à 09:41, Jagan Teki a écrit :
> On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut <[email protected]> wrote:
>> On 10/22/2016 01:00 PM, Jagan Teki wrote:
>>> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
>>> <[email protected]> wrote:
>>>> Hi all,
>>>>
>>>> This series extends support of SPI protocols to new protocols such as
>>>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
>>>> op codes, timing parameters (number of mode and dummy cycles) and erase
>>>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
>>>> tables, when available, as defined in the JEDEC JESD216 specifications.
>>>>
>>>> When SFDP tables are not available, legacy settings are still used for
>>>> backward compatibility (SPI and earlier QSPI memories).
>>>>
>>>> Support of SPI memories >128Mbits is also improved by using the 4byte
>>>> address instruction set, when available. Using those dedicated op codes
>>>> is stateless as opposed to enter the 4byte address mode, hence a better
>>>> compatibility with some boot loaders which expect to use 3byte address
>>>> op codes.
>>>
>>> The memories which are > 128Mbits should have 4-bytes addressing
>>> support based on my experience, do you think BAR is also required
>>> atleast from spi-nor side?
>>
>> Yes, I believe BAR is still required for broken/dumb flash chips.
>> Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-(
>
> Do you have list for those broken chips? because I never find any
> chips which has > 16 MiB with not support of 4-byte address opcodes
> and I've seen the controller has dependable with BAR though it can
> access > 16MiB ex: zynq qspi/
>
> thanks!
>
Let's take the case of Micron n25q256* memories. Depending of the part number,
the 12h op code is associated with either 4-byte address Page Program 1-1-1
or 3-byte address Page Program 1-4-4.
Then considering parts where the 12h op code is used for 3-byte address Page
Program 1-4-4, there is no op code for a 4-byte address Page Program 1-1-1.
Note 15, extracted from the Micron n25q_256mb_3v_65nm.pdf datasheet, about
the 3-byte address Page Program 1-4-4 (Extended Quad Input Fast Program):
The code 38h is valid only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x
and N25Q256A83ESFA0F; the code 12h is valid for the other part numbers.
Hence most of the Micron n25q256* memories has no op code for 4-byte address
Page Program 1-1-1.
Then we could use the 34h op code instead to perform 4-byte address Page
Program 1-1-4 but some SPI controllers might not support the SPI 1-1-4 protocol
for Page Program operations. Sp entering the 4-byte address mode or using
the BAR might still be the only solutions in those cases.
Also, I'm pretty sure some other SPI NOR memories support 4-byte address Fast
Read op codes but only 3-byte address op codes for Page Program and Sector
Erase. I will look at the datasheets I have to find and provide an example.
Best regards,
Cyrille
Le 24/10/2016 à 14:09, Cyrille Pitchen a écrit :
> Hi Jagan,
>
> Le 24/10/2016 à 09:41, Jagan Teki a écrit :
>> On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut <[email protected]> wrote:
>>> On 10/22/2016 01:00 PM, Jagan Teki wrote:
>>>> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
>>>> <[email protected]> wrote:
>>>>> Hi all,
>>>>>
>>>>> This series extends support of SPI protocols to new protocols such as
>>>>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
>>>>> op codes, timing parameters (number of mode and dummy cycles) and erase
>>>>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
>>>>> tables, when available, as defined in the JEDEC JESD216 specifications.
>>>>>
>>>>> When SFDP tables are not available, legacy settings are still used for
>>>>> backward compatibility (SPI and earlier QSPI memories).
>>>>>
>>>>> Support of SPI memories >128Mbits is also improved by using the 4byte
>>>>> address instruction set, when available. Using those dedicated op codes
>>>>> is stateless as opposed to enter the 4byte address mode, hence a better
>>>>> compatibility with some boot loaders which expect to use 3byte address
>>>>> op codes.
>>>>
>>>> The memories which are > 128Mbits should have 4-bytes addressing
>>>> support based on my experience, do you think BAR is also required
>>>> atleast from spi-nor side?
>>>
>>> Yes, I believe BAR is still required for broken/dumb flash chips.
>>> Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-(
>>
>> Do you have list for those broken chips? because I never find any
>> chips which has > 16 MiB with not support of 4-byte address opcodes
>> and I've seen the controller has dependable with BAR though it can
>> access > 16MiB ex: zynq qspi/
>>
>> thanks!
>>
>
> Let's take the case of Micron n25q256* memories. Depending of the part number,
> the 12h op code is associated with either 4-byte address Page Program 1-1-1
> or 3-byte address Page Program 1-4-4.
> Then considering parts where the 12h op code is used for 3-byte address Page
> Program 1-4-4, there is no op code for a 4-byte address Page Program 1-1-1.
>
> Note 15, extracted from the Micron n25q_256mb_3v_65nm.pdf datasheet, about
> the 3-byte address Page Program 1-4-4 (Extended Quad Input Fast Program):
> The code 38h is valid only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x
> and N25Q256A83ESFA0F; the code 12h is valid for the other part numbers.
>
> Hence most of the Micron n25q256* memories has no op code for 4-byte address
> Page Program 1-1-1.
> Then we could use the 34h op code instead to perform 4-byte address Page
> Program 1-1-4 but some SPI controllers might not support the SPI 1-1-4 protocol
> for Page Program operations. Sp entering the 4-byte address mode or using
> the BAR might still be the only solutions in those cases.
>
> Also, I'm pretty sure some other SPI NOR memories support 4-byte address Fast
> Read op codes but only 3-byte address op codes for Page Program and Sector
> Erase. I will look at the datasheets I have to find and provide an example.
>
>
Even worse, let's take the example for Macronix MX25L25635* and MX25L25673*:
they both share the very same JEDEC ID. The older part (35) doesn't support
the 4-byte address instruction set at all whereas the newer part (73) does.
> Best regards,
>
> Cyrille
>
On Mon, Oct 24, 2016 at 7:37 PM, Cyrille Pitchen
<[email protected]> wrote:
> Le 24/10/2016 à 14:09, Cyrille Pitchen a écrit :
>> Hi Jagan,
>>
>> Le 24/10/2016 à 09:41, Jagan Teki a écrit :
>>> On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut <[email protected]> wrote:
>>>> On 10/22/2016 01:00 PM, Jagan Teki wrote:
>>>>> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
>>>>> <[email protected]> wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> This series extends support of SPI protocols to new protocols such as
>>>>>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
>>>>>> op codes, timing parameters (number of mode and dummy cycles) and erase
>>>>>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
>>>>>> tables, when available, as defined in the JEDEC JESD216 specifications.
>>>>>>
>>>>>> When SFDP tables are not available, legacy settings are still used for
>>>>>> backward compatibility (SPI and earlier QSPI memories).
>>>>>>
>>>>>> Support of SPI memories >128Mbits is also improved by using the 4byte
>>>>>> address instruction set, when available. Using those dedicated op codes
>>>>>> is stateless as opposed to enter the 4byte address mode, hence a better
>>>>>> compatibility with some boot loaders which expect to use 3byte address
>>>>>> op codes.
>>>>>
>>>>> The memories which are > 128Mbits should have 4-bytes addressing
>>>>> support based on my experience, do you think BAR is also required
>>>>> atleast from spi-nor side?
>>>>
>>>> Yes, I believe BAR is still required for broken/dumb flash chips.
>>>> Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-(
>>>
>>> Do you have list for those broken chips? because I never find any
>>> chips which has > 16 MiB with not support of 4-byte address opcodes
>>> and I've seen the controller has dependable with BAR though it can
>>> access > 16MiB ex: zynq qspi/
>>>
>>> thanks!
>>>
>>
>> Let's take the case of Micron n25q256* memories. Depending of the part number,
>> the 12h op code is associated with either 4-byte address Page Program 1-1-1
>> or 3-byte address Page Program 1-4-4.
>> Then considering parts where the 12h op code is used for 3-byte address Page
>> Program 1-4-4, there is no op code for a 4-byte address Page Program 1-1-1.
>>
>> Note 15, extracted from the Micron n25q_256mb_3v_65nm.pdf datasheet, about
>> the 3-byte address Page Program 1-4-4 (Extended Quad Input Fast Program):
>> The code 38h is valid only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x
>> and N25Q256A83ESFA0F; the code 12h is valid for the other part numbers.
>>
>> Hence most of the Micron n25q256* memories has no op code for 4-byte address
>> Page Program 1-1-1.
>> Then we could use the 34h op code instead to perform 4-byte address Page
>> Program 1-1-4 but some SPI controllers might not support the SPI 1-1-4 protocol
>> for Page Program operations. Sp entering the 4-byte address mode or using
>> the BAR might still be the only solutions in those cases.
>>
>> Also, I'm pretty sure some other SPI NOR memories support 4-byte address Fast
>> Read op codes but only 3-byte address op codes for Page Program and Sector
>> Erase. I will look at the datasheets I have to find and provide an example.
>>
>>
>
> Even worse, let's take the example for Macronix MX25L25635* and MX25L25673*:
> they both share the very same JEDEC ID. The older part (35) doesn't support
> the 4-byte address instruction set at all whereas the newer part (73) does.
So, though we have a support of 4-byte opcode, few of the reads will
still way back to use 3-byte opcode is it?
If ie the case may be we can directly rely on 4-byte opcode page
program or reads instead of creating check for which opcode support
which bytes address, IMHO.
thanks!
--
Jagan Teki
Free Software Engineer | http://www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
Hi Cyrille,
On Tue, Oct 25, 2016 at 2:38 PM, Jagan Teki <[email protected]> wrote:
> On Mon, Oct 24, 2016 at 7:37 PM, Cyrille Pitchen
> <[email protected]> wrote:
>> Le 24/10/2016 à 14:09, Cyrille Pitchen a écrit :
>>> Hi Jagan,
>>>
>>> Le 24/10/2016 à 09:41, Jagan Teki a écrit :
>>>> On Sun, Oct 23, 2016 at 2:03 AM, Marek Vasut <[email protected]> wrote:
>>>>> On 10/22/2016 01:00 PM, Jagan Teki wrote:
>>>>>> On Wed, Oct 5, 2016 at 5:30 PM, Cyrille Pitchen
>>>>>> <[email protected]> wrote:
>>>>>>> Hi all,
>>>>>>>
>>>>>>> This series extends support of SPI protocols to new protocols such as
>>>>>>> SPI x-2-2 and SPI x-4-4. Also spi_nor_scan() tries now to select the right
>>>>>>> op codes, timing parameters (number of mode and dummy cycles) and erase
>>>>>>> sector size by parsing the Serial Flash Discoverable Parameter (SFDP)
>>>>>>> tables, when available, as defined in the JEDEC JESD216 specifications.
>>>>>>>
>>>>>>> When SFDP tables are not available, legacy settings are still used for
>>>>>>> backward compatibility (SPI and earlier QSPI memories).
>>>>>>>
>>>>>>> Support of SPI memories >128Mbits is also improved by using the 4byte
>>>>>>> address instruction set, when available. Using those dedicated op codes
>>>>>>> is stateless as opposed to enter the 4byte address mode, hence a better
>>>>>>> compatibility with some boot loaders which expect to use 3byte address
>>>>>>> op codes.
>>>>>>
>>>>>> The memories which are > 128Mbits should have 4-bytes addressing
>>>>>> support based on my experience, do you think BAR is also required
>>>>>> atleast from spi-nor side?
>>>>>
>>>>> Yes, I believe BAR is still required for broken/dumb flash chips.
>>>>> Not all chips > 16 MiB support dedicated 4-byte addressing opcodes :-(
>>>>
>>>> Do you have list for those broken chips? because I never find any
>>>> chips which has > 16 MiB with not support of 4-byte address opcodes
>>>> and I've seen the controller has dependable with BAR though it can
>>>> access > 16MiB ex: zynq qspi/
>>>>
>>>> thanks!
>>>>
>>>
>>> Let's take the case of Micron n25q256* memories. Depending of the part number,
>>> the 12h op code is associated with either 4-byte address Page Program 1-1-1
>>> or 3-byte address Page Program 1-4-4.
>>> Then considering parts where the 12h op code is used for 3-byte address Page
>>> Program 1-4-4, there is no op code for a 4-byte address Page Program 1-1-1.
>>>
>>> Note 15, extracted from the Micron n25q_256mb_3v_65nm.pdf datasheet, about
>>> the 3-byte address Page Program 1-4-4 (Extended Quad Input Fast Program):
>>> The code 38h is valid only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x
>>> and N25Q256A83ESFA0F; the code 12h is valid for the other part numbers.
I am trying to understand the conflict more clearly with an example of
Micron, so on Table 18 from Micron n25q_256mb_3v_65nm.pdf datasheet,
Page program 3-byte has 02h and Quad page program 3-byte has 32h but
for 4-byte addressing only quad page program (no support of page
program) can be either 02h/32h/12h and indeed these can change based
on the n25q256* parts so why can't we rely on Quad page program for
4-byte addressing? and so there is no necessity for BAR here.
And also other than the un-supported-controller can't we rely directly
on supported page program opcodes for 4-byte addressing? say if it is
supporting QPP on 4-byte then use it as it is and no need to take care
of PP here.
thanks!
--
Jagan Teki
Free Software Engineer | http://www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.