Hi,

Dne ponedeljek, 21. maj 2018 ob 10:12:53 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:24PM +0200, Jernej Skrabec wrote:
> > Expand HDMI PHY clock driver to support second clock parent.
> >
> > Signed-off-by: Jernej Skrabec <[email protected]>
> > ---
> >
> > drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 6 +-
> > drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 29 ++++++-
> > drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 90 ++++++++++++++++------
> > 3 files changed, 98 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index 801a17222762..aadbe0a10b0c
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
> > @@ -98,7 +98,8 @@
> >
> > #define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29)
> > #define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28)
> > #define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27)
> >
> > -#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL BIT(26)
> > +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
> > +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
> >
> > #define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25)
> > #define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22)
> > #define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
> >
> > @@ -190,6 +191,7 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi
> > *hdmi);
> >
> > void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
> > const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void);
> >
> > -int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev);
> > +int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
> > + bool second_parent);
> >
> > #endif /* _SUN8I_DW_HDMI_H_ */
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c index deba47ed69d8..7a911f0a3ae3
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
> > @@ -183,7 +183,13 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi
> > *hdmi,>
> > regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
> >
> > SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
> >
> > - regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
> > + /*
> > + * NOTE: We have to be careful not to overwrite PHY parent
> > + * clock selection bit and clock divider.
> > + */
> > + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
> > + ~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
> > + pll_cfg1_init);
>
> It feels like it belongs in a separate patch.

Why? clk_set_rate() on HDMI PHY clock is called before this function, so
SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL bit is already set to correct value. Original
code doesn't take this into account and sets it to 0 here in all cases, which
obviously is not right.

If you insist on splitting this in new patch, it has to be applied before
clock changes. It would also need to include "reset PLL clock configuration"
chunk (next change in this patch), otherwise other SoCs with only one parent
could get 1 there, which is obviously wrong. Note that I didn't really tested
if default value of this bit is 0 or 1, but I wouldn't really like to depend
on default values.

>
> > regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
> >
> > (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
> > pll_cfg2_init);
> >
> > @@ -352,6 +358,10 @@ static void sun8i_hdmi_phy_init_h3(struct
> > sun8i_hdmi_phy *phy)>
> > SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
> > SUN8I_HDMI_PHY_ANA_CFG3_SDAEN);
> >
> > + /* reset PLL clock configuration */
> > + regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
> > + regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, 0);
> > +
>
> Ditto,
>
> > +
> > + /*
> > + * Even though HDMI PHY clock doesn't have enable/disable
> > + * handlers, we have to enable it. Otherwise it could happen
> > + * that parent PLL is not enabled by clock framework in a
> > + * highly unlikely event when parent PLL is used solely for
> > + * HDMI PHY clock.
> > + */
> > + clk_prepare_enable(phy->clk_phy);
>
> The implementation of the clock doesn't really matter in our API
> usage. If we're using a clock, we have to call
> clk_prepare_enable. That's documented everywhere, and mentionning how
> the clock is implemented is an abstraction leakage and it's
> irrelevant. I'd simply remove the comment here.
>
> And it should be in a separate patch as well.

OK. Should I add Fixes tag, since current code obviously is not by the specs?
It could still get in 4.17...

Best regards,
Jernej

2018-05-21 15:12:55

by Jernej Skrabec

[permalink] [raw]

Subject: Re: [PATCH 04/15] dt-bindings: display: sunxi-drm: Add TCON TOP description

Hi,

Dne ponedeljek, 21. maj 2018 ob 10:01:47 CEST je Maxime Ripard napisal(a):
> Hi,
>
> On Sat, May 19, 2018 at 08:31:16PM +0200, Jernej Skrabec wrote:
> > TCON TOP main purpose is to configure whole display pipeline. It
> > determines relationships between mixers and TCONs, selects source TCON
> > for HDMI, muxes LCD and TV encoder GPIO output,
>
> I'm not sure you mean GPIO here, but rather pin?

Right, I'll fix that.

>
> > selects TV encoder clock source and contains additional TV TCON and
> > DSI gates.
> >
> > Signed-off-by: Jernej Skrabec <[email protected]>
> > ---
> >
> > .../bindings/display/sunxi/sun4i-drm.txt | 20 +++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> > 3346c1e2a7a0..a099957ab62a 100644
> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> > @@ -187,6 +187,26 @@ And on the A23, A31, A31s and A33, you need one more
clock line:
> > - 'lvds-alt': An alternative clock source, separate from the TCON
> > channel 0
> >
> > clock, that can be used to drive the LVDS clock
> >
> > +TCON TOP
> > +--------
> > +
> > +TCON TOPs main purpose is to configure whole display pipeline. It
> > determines +relationships between mixers and TCONs, selects source TCON
> > for HDMI, muxes +LCD and TV encoder GPIO output, selects TV encoder clock
> > source and contains +additional TV TCON and DSI gates.
> > +
> > +Required properties:
> > + - compatible: value must be one of:
> > + * allwinner,sun8i-r40-tcon-top
> > + - reg: base address and size of the memory-mapped region.
> > + - clocks: phandle to the clocks feeding the TCON TOP
> > + * bus: TCON TOP interface clock
> > + - clock-names: clock name mentioned above
> > + - resets: phandle to the reset line driving the DRC
> > + * rst: TCON TOP reset line
> > + - reset-names: reset name mentioned above
> > + - #clock-cells : must contain 1
> > +
>
> I guess you should better describe the OF-graph endpoints, and the
> clocks output. Just using the binding additions here doesn't allow to
> get a clear idea of how the DT should look like.

With my idea of implementation, OF graph is the same as before, so I didn't
mention anything about it.

My idea of dependencies (you should view it in fixed width font):
TCON-TOP
^
|
mixer <-> TCON <-> HDMI

I'll explain my design decision as response to other mail.

Best regards,
Jernej

2018-05-21 15:16:43

by Jernej Skrabec

[permalink] [raw]

Subject: Re: [PATCH 05/15] drm/sun4i: Add TCON TOP driver

Hi,

Dne ponedeljek, 21. maj 2018 ob 10:05:17 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:17PM +0200, Jernej Skrabec wrote:
> > As already described in DT binding, TCON TOP is responsible for
> > configuring display pipeline. In this initial driver focus is on HDMI
> > pipeline, so TVE and LCD configuration is not implemented.
> >
> > Implemented features:
> > - HDMI source selection
> > - clock driver (TCON and DSI gating)
> > - connecting mixers and TCONS
> >
> > Something similar also existed in previous SoCs, except that it was part
> > of first TCON.
> >
> > Signed-off-by: Jernej Skrabec <[email protected]>
> > ---
> >
> > drivers/gpu/drm/sun4i/Makefile | 3 +-
> > drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 256 +++++++++++++++++++++
> > drivers/gpu/drm/sun4i/sun8i_tcon_top.h | 20 ++
> > include/dt-bindings/clock/sun8i-tcon-top.h | 11 +
> > 4 files changed, 289 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.h
> > create mode 100644 include/dt-bindings/clock/sun8i-tcon-top.h
> >
> > diff --git a/drivers/gpu/drm/sun4i/Makefile
> > b/drivers/gpu/drm/sun4i/Makefile index 2589f4acd5ae..09fbfd6304ba 100644
> > --- a/drivers/gpu/drm/sun4i/Makefile
> > +++ b/drivers/gpu/drm/sun4i/Makefile
> > @@ -16,7 +16,8 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o
> >
> > sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \
> >
> > sun8i_vi_layer.o sun8i_ui_scaler.o \
> >
> > - sun8i_vi_scaler.o sun8i_csc.o
> > + sun8i_vi_scaler.o sun8i_csc.o \
> > + sun8i_tcon_top.o
> >
> > sun4i-tcon-y += sun4i_crtc.o
> > sun4i-tcon-y += sun4i_dotclock.o
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c new file mode 100644
> > index 000000000000..075a356a6dfa
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
> > @@ -0,0 +1,256 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2018 Jernej Skrabec <[email protected]> */
> > +
> > +#include <drm/drmP.h>
> > +
> > +#include <dt-bindings/clock/sun8i-tcon-top.h>
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include "sun8i_tcon_top.h"
> > +
> > +#define TCON_TOP_PORT_SEL_REG 0x1C
> > +#define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0)
> > +#define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4)
> > +#define TCON_TOP_PORT_TCON_LCD0 0
> > +#define TCON_TOP_PORT_TCON_LCD1 1
> > +#define TCON_TOP_PORT_TCON_TV0 2
> > +#define TCON_TOP_PORT_TCON_TV1 3
> > +
> > +#define TCON_TOP_GATE_SRC_REG 0x20
> > +#define TCON_TOP_HDMI_SRC_MSK GENMASK(29, 28)
> > +#define TCON_TOP_HDMI_SRC_NONE 0
> > +#define TCON_TOP_HDMI_SRC_TCON_TV0 1
> > +#define TCON_TOP_HDMI_SRC_TCON_TV1 2
> > +#define TCON_TOP_TCON_TV1_GATE 24
> > +#define TCON_TOP_TCON_TV0_GATE 20
> > +#define TCON_TOP_TCON_DSI_GATE 16
> > +
> > +#define CLK_NUM 3
> > +
> > +struct sun8i_tcon_top {
> > + struct clk *bus;
> > + void __iomem *regs;
> > + struct reset_control *rst;
> > +
> > + /*
> > + * spinlock is used for locking access to registers from different
> > + * places - tcon driver and clk subsystem.
> > + */
> > + spinlock_t reg_lock;
> > +};
> > +
> > +struct sun8i_tcon_top_gate {
> > + const char *name;
> > + u8 bit;
> > + int index;
> > +};
> > +
> > +static const struct sun8i_tcon_top_gate gates[] = {
> > + {"bus-tcon-top-dsi", TCON_TOP_TCON_DSI_GATE, CLK_BUS_TCON_TOP_DSI},
> > + {"bus-tcon-top-tv0", TCON_TOP_TCON_TV0_GATE, CLK_BUS_TCON_TOP_TV0},
> > + {"bus-tcon-top-tv1", TCON_TOP_TCON_TV1_GATE, CLK_BUS_TCON_TOP_TV1},
> > +};
> > +
> > +void sun8i_tcon_top_set_hdmi_src(struct sun8i_tcon_top *tcon_top, int
> > tcon) +{
> > + unsigned long flags;
> > + u32 val;
> > +
> > + if (tcon > 1) {
> > + DRM_ERROR("TCON index is too high!\n");
> > + return;
> > + }
> > +
> > + spin_lock_irqsave(&tcon_top->reg_lock, flags);
> > +
> > + val = readl(tcon_top->regs + TCON_TOP_GATE_SRC_REG);
> > + val &= ~TCON_TOP_HDMI_SRC_MSK;
> > + val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK,
> > + TCON_TOP_HDMI_SRC_TCON_TV0 + tcon);
> > + writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
> > +
> > + spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
> > +}
> > +
> > +void sun8i_tcon_top_de_config(struct sun8i_tcon_top *tcon_top,
> > + int mixer, enum tcon_type tcon_type, int tcon)
> > +{
> > + unsigned long flags;
> > + u32 val, reg;
> > +
> > + if (mixer > 1) {
> > + DRM_ERROR("Mixer index is too high!\n");
> > + return;
> > + }
> > +
> > + if (tcon > 1) {
> > + DRM_ERROR("TCON index is too high!\n");
> > + return;
> > + }
> > +
> > + switch (tcon_type) {
> > + case tcon_type_lcd:
> > + val = TCON_TOP_PORT_TCON_LCD0 + tcon;
> > + break;
> > + case tcon_type_tv:
> > + val = TCON_TOP_PORT_TCON_TV0 + tcon;
> > + break;
> > + default:
> > + DRM_ERROR("Invalid TCON type!\n");
> > + return;
> > + }
> > +
> > + spin_lock_irqsave(&tcon_top->reg_lock, flags);
> > +
> > + reg = readl(tcon_top->regs + TCON_TOP_PORT_SEL_REG);
> > + if (mixer == 0) {
> > + reg &= ~TCON_TOP_PORT_DE0_MSK;
> > + reg |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, val);
> > + } else {
> > + reg &= ~TCON_TOP_PORT_DE1_MSK;
> > + reg |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, val);
> > + }
> > + writel(reg, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
> > +
> > + spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
> > +}
> > +
> > +static int sun8i_tcon_top_probe(struct platform_device *pdev)
> > +{
> > + struct clk_hw_onecell_data *clk_data;
> > + struct sun8i_tcon_top *tcon_top;
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + int ret, i;
> > +
> > + tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
> > + if (!tcon_top)
> > + return -ENOMEM;
> > +
> > + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data) +
> > + sizeof(*clk_data->hws) * CLK_NUM,
> > + GFP_KERNEL);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + spin_lock_init(&tcon_top->reg_lock);
> > +
> > + tcon_top->rst = devm_reset_control_get(dev, "rst");
> > + if (IS_ERR(tcon_top->rst)) {
> > + dev_err(dev, "Couldn't get our reset line\n");
> > + return PTR_ERR(tcon_top->rst);
> > + }
> > +
> > + tcon_top->bus = devm_clk_get(dev, "bus");
> > + if (IS_ERR(tcon_top->bus)) {
> > + dev_err(dev, "Couldn't get the bus clock\n");
> > + return PTR_ERR(tcon_top->bus);
> > + }
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + tcon_top->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(tcon_top->regs))
> > + return PTR_ERR(tcon_top->regs);
> > +
> > + ret = reset_control_deassert(tcon_top->rst);
> > + if (ret) {
> > + dev_err(dev, "Could not deassert ctrl reset control\n");
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(tcon_top->bus);
> > + if (ret) {
> > + dev_err(dev, "Could not enable bus clock\n");
> > + goto err_assert_reset;
> > + }
> > +
> > + /*
> > + * Default register values might have some reserved bits set, which
> > + * prevents TCON TOP from working properly. Set them to 0 here.
> > + */
> > + writel(0, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
> > + writel(0, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
> > +
> > + for (i = 0; i < CLK_NUM; i++) {
> > + const char *parent_name = "bus-tcon-top";
>
> I guess retrieving the parent's clock name at runtime would be more
> flexible.
>

It is, but will it ever be anything else?

> > + struct clk_init_data init;
> > + struct clk_gate *gate;
> > +
> > + gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
> > + if (!gate) {
> > + ret = -ENOMEM;
> > + goto err_disable_clock;
> > + }
> > +
> > + init.name = gates[i].name;
> > + init.ops = &clk_gate_ops;
> > + init.flags = CLK_IS_BASIC;
> > + init.parent_names = &parent_name;
> > + init.num_parents = 1;
> > +
> > + gate->reg = tcon_top->regs + TCON_TOP_GATE_SRC_REG;
> > + gate->bit_idx = gates[i].bit;
> > + gate->lock = &tcon_top->reg_lock;
> > + gate->hw.init = &init;
> > +
> > + ret = devm_clk_hw_register(dev, &gate->hw);
> > + if (ret)
> > + goto err_disable_clock;
>
> Isn't it what clk_hw_register_gate is doing?
>

Almost, but not exactly. My goal was to use devm_* functions, so there is no
need to do any special cleanup.

> > + clk_data->hws[gates[i].index] = &gate->hw;
> > + }
> > +
> > + clk_data->num = CLK_NUM;
> > +
> > + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
clk_data);
> > + if (ret)
> > + goto err_disable_clock;
> > +
> > + platform_set_drvdata(pdev, tcon_top);
> > +
> > + return 0;
> > +
> > +err_disable_clock:
> > + clk_disable_unprepare(tcon_top->bus);
> > +err_assert_reset:
> > + reset_control_assert(tcon_top->rst);
> > +
> > + return ret;
> > +}
> > +
> > +static int sun8i_tcon_top_remove(struct platform_device *pdev)
> > +{
> > + struct sun8i_tcon_top *tcon_top = platform_get_drvdata(pdev);
> > +
> > + clk_disable_unprepare(tcon_top->bus);
> > + reset_control_assert(tcon_top->rst);
> > +
> > + return 0;
> > +}
> > +
> > +const struct of_device_id sun8i_tcon_top_of_table[] = {
> > + { .compatible = "allwinner,sun8i-r40-tcon-top" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
> > +
> > +static struct platform_driver sun8i_tcon_top_platform_driver = {
> > + .probe = sun8i_tcon_top_probe,
> > + .remove = sun8i_tcon_top_remove,
> > + .driver = {
> > + .name = "sun8i-tcon-top",
> > + .of_match_table = sun8i_tcon_top_of_table,
> > + },
> > +};
> > +module_platform_driver(sun8i_tcon_top_platform_driver);
> > +
> > +MODULE_AUTHOR("Jernej Skrabec <[email protected]>");
> > +MODULE_DESCRIPTION("Allwinner R40 TCON TOP driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
> > b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h new file mode 100644
> > index 000000000000..19126e07d2a6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
> > @@ -0,0 +1,20 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/* Copyright (c) 2018 Jernej Skrabec <[email protected]> */
> > +
> > +#ifndef _SUN8I_TCON_TOP_H_
> > +#define _SUN8I_TCON_TOP_H_
> > +
> > +#include <linux/device.h>
> > +
> > +struct sun8i_tcon_top;
> > +
> > +enum tcon_type {
> > + tcon_type_lcd,
> > + tcon_type_tv,
>
> The usual practice is to have the enum values upper-case.

Ok.

Best regards,
Jernej

2018-05-21 17:30:19

by Jernej Skrabec

[permalink] [raw]

Subject: Re: [PATCH 06/15] drm/sun4i: tcon: Add support for tcon-top

Hi,

Dne ponedeljek, 21. maj 2018 ob 10:07:59 CEST je Maxime Ripard napisal(a):
> On Sat, May 19, 2018 at 08:31:18PM +0200, Jernej Skrabec wrote:
> > If SoC has TCON TOP unit, it has to be configured from TCON, since it
> > has all information needed. Additionally, if it is TCON TV, it must also
> > enable bus gate inside TCON TOP unit.
>
> Why?

I'll explain my design decision below.

>
> > Add support for such TCONs.
> >
> > Signed-off-by: Jernej Skrabec <[email protected]>
> > ---
> >
> > drivers/gpu/drm/sun4i/sun4i_tcon.c | 28 ++++++++++++++++++++++++++++
> > drivers/gpu/drm/sun4i/sun4i_tcon.h | 8 ++++++++
> > 2 files changed, 36 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 08747fc3ee71..e0c562ce1c22
> > 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > @@ -688,6 +688,16 @@ static int sun4i_tcon_init_clocks(struct device *dev,
> >
> > dev_err(dev, "Couldn't get the TCON bus clock\n");
> > return PTR_ERR(tcon->clk);
> >
> > }
> >
> > +
> > + if (tcon->quirks->needs_tcon_top && tcon->quirks->has_channel_1) {
> > + tcon->top_clk = devm_clk_get(dev, "tcon-top");
> > + if (IS_ERR(tcon->top_clk)) {
> > + dev_err(dev, "Couldn't get the TCON TOP bus clock\n");
> > + return PTR_ERR(tcon->top_clk);
> > + }
> > + clk_prepare_enable(tcon->top_clk);
> > + }
> > +
> >
> > clk_prepare_enable(tcon->clk);
> >
> > if (tcon->quirks->has_channel_0) {
> >
> > @@ -712,6 +722,7 @@ static int sun4i_tcon_init_clocks(struct device *dev,
> >
> > static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
> > {
> >
> > clk_disable_unprepare(tcon->clk);
> >
> > + clk_disable_unprepare(tcon->top_clk);
> >
> > }
> >
> > static int sun4i_tcon_init_irq(struct device *dev,
> >
> > @@ -980,6 +991,23 @@ static int sun4i_tcon_bind(struct device *dev, struct
> > device *master,>
> > tcon->id = engine->id;
> > tcon->quirks = of_device_get_match_data(dev);
> >
> > + if (tcon->quirks->needs_tcon_top) {
> > + struct device_node *np;
> > +
> > + np = of_parse_phandle(dev->of_node, "allwinner,tcon-top", 0);
> > + if (np) {
> > + struct platform_device *pdev;
> > +
> > + pdev = of_find_device_by_node(np);
> > + if (pdev)
> > + tcon->tcon_top = platform_get_drvdata(pdev);
> > + of_node_put(np);
> > +
> > + if (!tcon->tcon_top)
> > + return -EPROBE_DEFER;
> > + }
> > + }
> > +
>
> I might have missed it, but I've not seen the bindings additions for
> that property. This shouldn't really be done that way anyway, instead
> of using a direct phandle, you should be using the of-graph, with the
> TCON-top sitting where it belongs in the flow of data.

Just to answer to the first question, it did describe it in "[PATCH 07/15] dt-
bindings: display: sun4i-drm: Add R40 HDMI pipeline".

As why I designed it that way - HW representation could be described that way
(ASCII art makes sense when fixed width font is used to view it):

/ LCD0/LVDS0
/ TCON-LCD0
| \ MIPI DSI
mixer0 |
\ / TCON-LCD1 - LCD1/LVDS1
TCON-TOP
/ \ TCON-TV0 - TVE0/RGB
mixer1 | \
| TCON-TOP - HDMI
| /
\ TCON-TV1 - TVE1/RGB

This is a bit simplified, since there is also TVE-TOP, which is responsible
for sharing 4 DACs between both TVE encoders. You can have two TV outs (PAL/
NTSC) or TVE0 as TV out and TVE1 as RGB or vice versa. It even seems that you
can arbitrarly choose which DAC is responsible for which signal, so there is a
ton of possible end combinations, but I'm not 100% sure.

Even though I wrote TCON-TOP twice, this is same unit in HW. R40 manual
suggest more possibilities, although some of them seem wrong, like RGB feeding
from LCD TCON. That is confirmed to be wrong when checking BSP code.

Additionally, TCON-TOP comes in the middle of TVE0 and LCD0, TVE1 and LCD1 for
pin muxing, although I'm not sure why is that needed at all, since according
to R40 datasheet, TVE0 and TVE1 pins are dedicated and not on PORT D and PORT
H, respectively, as TCON-TOP documentation suggest. However, HSYNC and PSYNC
lines might be shared between TVE (when it works in RGB mode) and LCD. But
that is just my guess since I'm not really familiar with RGB and LCD
interfaces.

I'm really not sure what would be the best representation in OF-graph. Can you
suggest one?

On the other hand, mux callback in TCON driver has all available informations
at hand. It knows mixer ID, TCON ID and most importantly, encoder type. Based
on all that informations, it's easy to configure TCON TOP.

I hope you understand. If you have better idea, I'm all ears, since phandle
seems a bit weird to me too, but I think it's the only future proof, when
adding LVDS, RGB, TVE or LCD support.

Best regards,
Jernej

2018-05-22 02:26:43

by Jernej Škrabec

[permalink] [raw]

Subject: Re: [linux-sunxi] Re: [PATCH 06/15] drm/sun4i: tcon: Add support for tcon-top

Dne četrtek, 07. junij 2018 ob 00:30:24 CEST je Jernej Škrabec napisal(a):
> Dne ponedeljek, 04. junij 2018 ob 18:23:57 CEST je Maxime Ripard napisal(a):
> > On Mon, Jun 04, 2018 at 05:09:56PM +0200, Jernej Škrabec wrote:
> > > Dne ponedeljek, 04. junij 2018 ob 13:50:34 CEST je Maxime Ripard
>
> napisal(a):
> > > > On Fri, Jun 01, 2018 at 09:19:43AM -0700, Chen-Yu Tsai wrote:
> > > > > On Fri, Jun 1, 2018 at 8:29 AM, Maxime Ripard
> > > > > <[email protected]>
> > >
> > > wrote:
> > > > > > On Thu, May 31, 2018 at 07:54:08PM +0200, Jernej Škrabec wrote:
> > > > > >> Dne četrtek, 31. maj 2018 ob 11:21:33 CEST je Maxime Ripard
>
> napisal(a):
> > > > > >> > On Thu, May 24, 2018 at 03:01:09PM -0700, Chen-Yu Tsai wrote:
> > > > > >> > > >> > > + if (tcon->quirks->needs_tcon_top) {
> > > > > >> > > >> > > + struct device_node *np;
> > > > > >> > > >> > > +
> > > > > >> > > >> > > + np = of_parse_phandle(dev->of_node,
> > > > > >> > > >> > > "allwinner,tcon-top",
> > > > > >> > > >> > > 0);
> > > > > >> > > >> > > + if (np) {
> > > > > >> > > >> > > + struct platform_device *pdev;
> > > > > >> > > >> > > +
> > > > > >> > > >> > > + pdev = of_find_device_by_node(np);
> > > > > >> > > >> > > + if (pdev)
> > > > > >> > > >> > > + tcon->tcon_top =
> > > > > >> > > >> > > platform_get_drvdata(pdev);
> > > > > >> > > >> > > + of_node_put(np);
> > > > > >> > > >> > > +
> > > > > >> > > >> > > + if (!tcon->tcon_top)
> > > > > >> > > >> > > + return -EPROBE_DEFER;
> > > > > >> > > >> > > + }
> > > > > >> > > >> > > + }
> > > > > >> > > >> > > +
> > > > > >> > > >> >
> > > > > >> > > >> > I might have missed it, but I've not seen the bindings
> > > > > >> > > >> > additions for
> > > > > >> > > >> > that property. This shouldn't really be done that way
> > > > > >> > > >> > anyway,
> > > > > >> > > >> > instead
> > > > > >> > > >> > of using a direct phandle, you should be using the
> > > > > >> > > >> > of-graph,
> > > > > >> > > >> > with the
> > > > > >> > > >> > TCON-top sitting where it belongs in the flow of data.
> > > > > >> > > >>
> > > > > >> > > >> Just to answer to the first question, it did describe it
> > > > > >> > > >> in
> > > > > >> > > >> "[PATCH
> > > > > >> > > >> 07/15] dt- bindings: display: sun4i-drm: Add R40 HDMI
> > > > > >> > > >> pipeline".
> > > > > >> > > >>
> > > > > >> > > >> As why I designed it that way - HW representation could be
> > > > > >> > > >> described
> > > > > >> > > >> that way> >>
> > > > > >> > > >>
> > > > > >> > > >> (ASCII art makes sense when fixed width font is used to
> > > > > >> > > >> view
> > >
> > > it):
> > > > > >> > > >> / LCD0/LVDS0
> > > > > >> > > >>
> > > > > >> > > >> / TCON-LCD0
> > > > > >> > > >>
> > > > > >> > > >> | \ MIPI DSI
> > > > > >> > > >>
> > > > > >> > > >> mixer0 |
> > > > > >> > > >>
> > > > > >> > > >> \ / TCON-LCD1 - LCD1/LVDS1
> > > > > >> > > >>
> > > > > >> > > >> TCON-TOP
> > > > > >> > > >>
> > > > > >> > > >> / \ TCON-TV0 - TVE0/RGB
> > > > > >> > > >>
> > > > > >> > > >> mixer1 | \
> > > > > >> > > >>
> > > > > >> > > >> | TCON-TOP - HDMI
> > > > > >> > > >> |
> > > > > >> > > >> | /
> > > > > >> > > >>
> > > > > >> > > >> \ TCON-TV1 - TVE1/RGB
> > > > > >> > > >>
> > > > > >> > > >> This is a bit simplified, since there is also TVE-TOP,
> > > > > >> > > >> which
> > > > > >> > > >> is
> > > > > >> > > >> responsible
> > > > > >> > > >> for sharing 4 DACs between both TVE encoders. You can have
> > > > > >> > > >> two
> > > > > >> > > >> TV outs
> > > > > >> > > >> (PAL/ NTSC) or TVE0 as TV out and TVE1 as RGB or vice
> > > > > >> > > >> versa.
> > > > > >> > > >> It
> > > > > >> > > >> even
> > > > > >> > > >> seems that you can arbitrarly choose which DAC is
> > > > > >> > > >> responsible
> > > > > >> > > >> for
> > > > > >> > > >> which signal, so there is a ton of possible end
> > > > > >> > > >> combinations,
> > > > > >> > > >> but I'm
> > > > > >> > > >> not 100% sure.
> > > > > >> > > >>
> > > > > >> > > >> Even though I wrote TCON-TOP twice, this is same unit in
> > > > > >> > > >> HW.
> > > > > >> > > >> R40
> > > > > >> > > >> manual
> > > > > >> > > >> suggest more possibilities, although some of them seem
> > > > > >> > > >> wrong,
> > > > > >> > > >> like RGB
> > > > > >> > > >> feeding from LCD TCON. That is confirmed to be wrong when
> > > > > >> > > >> checking BSP
> > > > > >> > > >> code.
> > > > > >> > > >>
> > > > > >> > > >> Additionally, TCON-TOP comes in the middle of TVE0 and
> > > > > >> > > >> LCD0,
> > > > > >> > > >> TVE1 and
> > > > > >> > > >> LCD1 for pin muxing, although I'm not sure why is that
> > > > > >> > > >> needed at
> > > > > >> > > >> all,
> > > > > >> > > >> since according to R40 datasheet, TVE0 and TVE1 pins are
> > > > > >> > > >> dedicated and
> > > > > >> > > >> not on PORT D and PORT H, respectively, as TCON-TOP
> > > > > >> > > >> documentation
> > > > > >> > > >> suggest. However, HSYNC and PSYNC lines might be shared
> > > > > >> > > >> between
> > > > > >> > > >> TVE
> > > > > >> > > >> (when it works in RGB mode) and LCD. But that is just my
> > > > > >> > > >> guess
> > > > > >> > > >> since
> > > > > >> > > >> I'm not really familiar with RGB and LCD interfaces.
> > > > > >> > > >>
> > > > > >> > > >> I'm really not sure what would be the best representation
> > > > > >> > > >> in
> > > > > >> > > >> OF-graph.
> > > > > >> > > >> Can you suggest one?
> > > > > >> > > >
> > > > > >> > > > Rob might disagree on this one, but I don't see anything
> > > > > >> > > > wrong
> > > > > >> > > > with
> > > > > >> > > > having loops in the graph. If the TCON-TOP can be both the
> > > > > >> > > > input
> > > > > >> > > > and
> > > > > >> > > > output of the TCONs, then so be it, and have it described
> > > > > >> > > > that
> > > > > >> > > > way in
> > > > > >> > > > the graph.
> > > > > >> > > >
> > > > > >> > > > The code is already able to filter out nodes that have
> > > > > >> > > > already
> > > > > >> > > > been
> > > > > >> > > > added to the list of devices we need to wait for in the
> > > > > >> > > > component
> > > > > >> > > > framework, so that should work as well.
> > > > > >> > > >
> > > > > >> > > > And we'd need to describe TVE-TOP as well, even though we
> > > > > >> > > > don't
> > > > > >> > > > have a
> > > > > >> > > > driver for it yet. That will simplify the backward
> > > > > >> > > > compatibility
> > > > > >> > > > later
> > > > > >> > > > on.
> > > > > >> > >
> > > > > >> > > I'm getting the feeling that TCON-TOP / TVE-TOP is the glue
> > > > > >> > > layer
> > > > > >> > > that
> > > > > >> > > binds everything together, and provides signal routing, kind
> > > > > >> > > of
> > > > > >> > > like
> > > > > >> > > DE-TOP on A64. So the signal mux controls that were
> > > > > >> > > originally
> > > > > >> > > found
> > > > > >> > > in TCON0 and TVE0 were moved out.
> > > > > >> > >
> > > > > >> > > The driver needs to know about that, but the graph about
> > > > > >> > > doesn't
> > > > > >> > > make
> > > > > >> > > much sense directly. Without looking at the manual, I
> > > > > >> > > understand it
> > > > > >> > > to
> > > > > >> > > likely be one mux between the mixers and TCONs, and one
> > > > > >> > > between
> > > > > >> > > the
> > > > > >> > > TCON-TVs and HDMI. Would it make more sense to just have the
> > > > > >> > > graph
> > > > > >> > > connections between the muxed components, and remove TCON-TOP
> > > > > >> > > from
> > > > > >> > > it, like we had in the past? A phandle could be used to
> > > > > >> > > reference
> > > > > >> > > the TCON-TOP for mux controls, in addition to the clocks and
> > > > > >> > > resets.
> > > > > >> > >
> > > > > >> > > For TVE, we would need something to represent each of the
> > > > > >> > > output
> > > > > >> > > pins,
> > > > > >> > > so the device tree can actually describe what kind of signal,
> > > > > >> > > be it
> > > > > >> > > each component of RGB/YUV or composite video, is wanted on
> > > > > >> > > each
> > > > > >> > > pin,
> > > > > >> > > if any. This is also needed on the A20 for the Cubietruck, so
> > > > > >> > > we
> > > > > >> > > can
> > > > > >> > > describe which pins are tied to the VGA connector, and which
> > > > > >> > > one
> > > > > >> > > does
> > > > > >> > > R, G, or B.
> > > > > >> >
> > > > > >> > I guess we'll see how the DT maintainers feel about this, but
> > > > > >> > my
> > > > > >> > impression is that the OF graph should model the flow of data
> > > > > >> > between
> > > > > >> > the devices. If there's a mux somewhere, then the data is
> > > > > >> > definitely
> > > > > >> > going through it, and as such it should be part of the graph.
> > > > > >>
> > > > > >> I concur, but I spent few days thinking how to represent this
> > > > > >> sanely in
> > > > > >> graph, but I didn't find any good solution. I'll represent here
> > > > > >> my
> > > > > >> idea and please tell your opinion before I start implementing it.
> > > > > >>
> > > > > >> First, let me be clear that mixer0 and mixer1 don't have same
> > > > > >> capabilities
> > > > > >> (different number of planes, mixer0 supports writeback, mixer1
> > > > > >> does
> > > > > >> not,
> > > > > >> etc.). Thus, it does matter which mixer is connected to which
> > > > > >> TCON/encoder.
> > > > > >> mixer0 is meant to be connected to main display and mixer1 to
> > > > > >> auxiliary. That obviously depends on end system.
> > > > > >>
> > > > > >> So, TCON TOP has 3 muxes, which have to be represented in graph.
> > > > > >> Two of
> > > > > >> them are for mixer/TCON relationship (each of them 1 input and 4
> > > > > >> possible outputs) and one for TV TCON/HDMI pair selection (2
> > > > > >> possible
> > > > > >> inputs, 1 output).
> > > > > >>
> > > > > >> According to current practice in sun4i-drm driver, graph has to
> > > > > >> have
> > > > > >> port 0, representing input and port 1, representing output. This
> > > > > >> would
> > > > > >> mean that graph looks something like that:
> > > > > >>
> > > > > >> tcon_top: tcon-top@1c70000 {
> > > > > >>
> > > > > >> compatible = "allwinner,sun8i-r40-tcon-top";
> > > > > >> ...
> > > > > >> ports {
> > > > > >>
> > > > > >> #address-cells = <1>;
> > > > > >> #size-cells = <0>;
> > > > > >>
> > > > > >> tcon_top_in: port@0 {
> > > > > >>
> > > > > >> #address-cells = <1>;
> > > > > >> #size-cells = <0>;
> > > > > >> reg = <0>;
> > > > > >>
> > > > > >> tcon_top_in_mixer0: endpoint@0 {
> > > > > >>
> > > > > >> reg = <0>;
> > > > > >> remote-endpoint =
> > > > > >> <&mixer0_out_tcon_top>;
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> tcon_top_in_mixer1: endpoint@1 {
> > > > > >>
> > > > > >> reg = <1>;
> > > > > >> remote-endpoint =
> > > > > >> <&mixer1_out_tcon_top>;
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> tcon_top_in_tcon_tv: endpoint@2 {
> > > > > >>
> > > > > >> reg = <2>;
> > > > > >> // here is HDMI input connection,
> > > > > >> part of
> > > > > >> board DTS
> > > > > >> remote-endpoint = <board specific
> > > > > >> phandle
> > > > > >> to TV TCON output>;
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> tcon_top_out: port@1 {
> > > > > >>
> > > > > >> #address-cells = <1>;
> > > > > >> #size-cells = <0>;
> > > > > >> reg = <1>;
> > > > > >>
> > > > > >> tcon_top_out_tcon0: endpoint@0 {
> > > > > >>
> > > > > >> reg = <0>;
> > > > > >> // here is mixer0 output
> > > > > >> connection,
> > > > > >> part
> > > > > >> of board DTS
> > > > > >> remote-endpoint = <board specific
> > > > > >> phandle
> > > > > >> to TCON>;
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> tcon_top_out_tcon1: endpoint@1 {
> > > > > >>
> > > > > >> reg = <1>;
> > > > > >> // here is mixer1 output
> > > > > >> connection,
> > > > > >> part
> > > > > >> of board DTS
> > > > > >> remote-endpoint = <board specific
> > > > > >> phandle
> > > > > >> to TCON>;
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> tcon_top_out_hdmi: endpoint@2 {
> > > > > >>
> > > > > >> reg = <2>;
> > > > > >> remote-endpoint =
> > > > > >> <&hdmi_in_tcon_top>;
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> };
> > > > > >>
> > > > > >> };
> > > > > >
> > > > > > IIRC, each port is supposed to be one route for the data, so we
> > > > > > would
> > > > > > have multiple ports, one for the mixers in input and for the tcon
> > > > > > in
> > > > > > output, and one for the TCON in input and for the HDMI/TV in
> > > > > > output. Rob might correct me here.
> > >
> > > Ok, that seems more clean approach. I'll have to extend graph traversing
> > > algorithm in sun4i_drv.c, but that's no problem.
> > >
> > > Just to be clear, you have in mind 3 pairs of ports (0/1 for mixer0 mux,
> > > 2/3 for mixer1 and 4/5 for HDMI input), right? That way each mux is
> > > represented with one pair of ports, even numbered for input and odd
> > > numbered for output.
> >
> > Yep, unless Rob feels otherwise.
>
> I found an issue with this concept.
>
> HDMI driver (sun8i_dw_hdmi.c) uses drm_of_find_possible_crtcs() to find
> connected crtcs (TCONs) to HDMI. This function assumes that crtc and encoder
> are directly connected through of_graph, but that is not the case with TCON
> TOP HDMI mux anymore.
> I could give TCON TOP node as an input to this function, but that won't
> work, since TCON TOP can have connections to other crtcs, not only that of
> HDMI and they will also be picked up by drm_of_find_possible_crtcs().
>
> Any suggestion how to solve this nicely? I think creating my own version of
> drm_of_find_possible_crtcs() which considers that case is one way, but not
> very nice solution. Alternatively, we can fix possible_crtcs to BIT(0),

This doesn't seem like a good solution, since it doesn't work in dual head
system. I'll take first approach.

Best regards,
Jernej

> since it always has only one input. This is done in meson_dw_hdmi.c for
> example.