The outbound iATU programming functions are similar, so PATCH1 consolidates
them into one.
Most transactions' type are cfg0 and MEM, so current iATU usage is not
balanced. PATCH2 adopts idea from Minghuan Lian <[email protected]>:
http://www.spinics.net/lists/linux-pci/msg40440.html
to change the iATU allocation: iATU0 for cfg and IO, iATU1 for MEM.
Changes since v1:
- remove outbound iATU programming for IO in dw_pcie_host_init, since it can
be done by berlin_pcie_{rd|wr}_other_conf() latter.
- only do outbound iATU programming for MEM if pp->ops->rd_other_conf is not
set. Thank Fabrice Gasnier to point out "some platforms doesn't have support
for ATU"
Jisheng Zhang (2):
PCI: designware: consolidate outbound iATU programming functions
PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM
drivers/pci/host/pcie-designware.c | 142 ++++++++++++++++---------------------
1 file changed, 60 insertions(+), 82 deletions(-)
--
2.1.4
Currently, the outbound iATU programming functions are similar, the only
difference is index, type, addr and size. This patch tries to consolidate
these functions into one. One side effect is it saves around 1700 bytes in
text:
text data bss dec hex filename
9276 204 4 9484 250c pcie-designware.o-before
7532 204 4 7740 1e3c pcie-designware.o
Signed-off-by: Jisheng Zhang <[email protected]>
---
drivers/pci/host/pcie-designware.c | 109 +++++++++++++------------------------
1 file changed, 39 insertions(+), 70 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 2e9f84f..1da1446 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -150,6 +150,21 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
return ret;
}
+static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
+ int type, u64 cpu_addr, u64 pci_addr, u32 size)
+{
+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
+ PCIE_ATU_VIEWPORT);
+ dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
+ dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
+ dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
+ PCIE_ATU_LIMIT);
+ dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
+ dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+}
+
static struct irq_chip dw_msi_irq_chip = {
.name = "PCI-MSI",
.irq_enable = pci_msi_unmask_irq,
@@ -515,68 +530,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
return 0;
}
-static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
-{
- /* Program viewport 0 : OUTBOUND : CFG0 */
- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
- PCIE_ATU_LIMIT);
- dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
- dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
-static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
-{
- /* Program viewport 1 : OUTBOUND : CFG1 */
- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
- PCIE_ATU_LIMIT);
- dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
- dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
-static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
-{
- /* Program viewport 0 : OUTBOUND : MEM */
- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
- PCIE_ATU_LIMIT);
- dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
- dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
- PCIE_ATU_UPPER_TARGET);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
-static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
-{
- /* Program viewport 1 : OUTBOUND : IO */
- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
- dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
- dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
- PCIE_ATU_LIMIT);
- dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
- dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
- PCIE_ATU_UPPER_TARGET);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
-}
-
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val)
{
@@ -588,15 +541,23 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
address = where & ~0x3;
if (bus->parent->number == pp->root_bus_nr) {
- dw_pcie_prog_viewport_cfg0(pp, busdev);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
+ busdev, pp->cfg0_size);
ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
val);
- dw_pcie_prog_viewport_mem_outbound(pp);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
+ pp->mem_bus_addr, pp->mem_size);
} else {
- dw_pcie_prog_viewport_cfg1(pp, busdev);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
+ busdev, pp->cfg1_size);
ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
val);
- dw_pcie_prog_viewport_io_outbound(pp);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_IO, pp->io_mod_base,
+ pp->io_bus_addr, pp->io_size);
}
return ret;
@@ -613,15 +574,23 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
address = where & ~0x3;
if (bus->parent->number == pp->root_bus_nr) {
- dw_pcie_prog_viewport_cfg0(pp, busdev);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
+ busdev, pp->cfg0_size);
ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
val);
- dw_pcie_prog_viewport_mem_outbound(pp);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
+ pp->mem_bus_addr, pp->mem_size);
} else {
- dw_pcie_prog_viewport_cfg1(pp, busdev);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
+ busdev, pp->cfg1_size);
ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
val);
- dw_pcie_prog_viewport_io_outbound(pp);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_IO, pp->io_mod_base,
+ pp->io_bus_addr, pp->io_size);
}
return ret;
--
2.1.4
Most transactions' type are cfg0 and MEM, so the Current iATU usage is not
balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors
the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation
ideas comes from Minghuan Lian <[email protected]>:
http://www.spinics.net/lists/linux-pci/msg40440.html
Signed-off-by: Jisheng Zhang <[email protected]>
---
drivers/pci/host/pcie-designware.c | 81 +++++++++++++++++++++-----------------
1 file changed, 45 insertions(+), 36 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 1da1446..40a0db1 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -508,6 +508,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (pp->ops->host_init)
pp->ops->host_init(pp);
+ if (!pp->ops->rd_other_conf)
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
+ pp->mem_bus_addr, pp->mem_size);
+
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
/* program correct class for RC */
@@ -533,66 +538,70 @@ int dw_pcie_host_init(struct pcie_port *pp)
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val)
{
- int ret = PCIBIOS_SUCCESSFUL;
- u32 address, busdev;
+ int ret, type;
+ u32 address, busdev, cfg_size;
+ u64 cpu_addr;
+ void __iomem *va_cfg_base;
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
address = where & ~0x3;
if (bus->parent->number == pp->root_bus_nr) {
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
- busdev, pp->cfg0_size);
- ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
- val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
- pp->mem_bus_addr, pp->mem_size);
+ type = PCIE_ATU_TYPE_CFG0;
+ cpu_addr = pp->cfg0_mod_base;
+ cfg_size = pp->cfg0_size;
+ va_cfg_base = pp->va_cfg0_base;
} else {
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
- busdev, pp->cfg1_size);
- ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
- val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_IO, pp->io_mod_base,
- pp->io_bus_addr, pp->io_size);
+ type = PCIE_ATU_TYPE_CFG1;
+ cpu_addr = pp->cfg1_mod_base;
+ cfg_size = pp->cfg1_size;
+ va_cfg_base = pp->va_cfg1_base;
}
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ type, cpu_addr,
+ busdev, cfg_size);
+ ret = dw_pcie_cfg_read(va_cfg_base + address, where, size, val);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO, pp->io_mod_base,
+ pp->io_bus_addr, pp->io_size);
+
return ret;
}
static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 devfn, int where, int size, u32 val)
{
- int ret = PCIBIOS_SUCCESSFUL;
- u32 address, busdev;
+ int ret, type;
+ u32 address, busdev, cfg_size;
+ u64 cpu_addr;
+ void __iomem *va_cfg_base;
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
address = where & ~0x3;
if (bus->parent->number == pp->root_bus_nr) {
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_CFG0, pp->cfg0_mod_base,
- busdev, pp->cfg0_size);
- ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
- val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_MEM, pp->mem_mod_base,
- pp->mem_bus_addr, pp->mem_size);
+ type = PCIE_ATU_TYPE_CFG0;
+ cpu_addr = pp->cfg0_mod_base;
+ cfg_size = pp->cfg0_size;
+ va_cfg_base = pp->va_cfg0_base;
} else {
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_CFG1, pp->cfg1_mod_base,
- busdev, pp->cfg1_size);
- ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
- val);
- dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_IO, pp->io_mod_base,
- pp->io_bus_addr, pp->io_size);
+ type = PCIE_ATU_TYPE_CFG1;
+ cpu_addr = pp->cfg1_mod_base;
+ cfg_size = pp->cfg1_size;
+ va_cfg_base = pp->va_cfg1_base;
}
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ type, cpu_addr,
+ busdev, cfg_size);
+ ret = dw_pcie_cfg_write(va_cfg_base + address, where, size, val);
+ dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO, pp->io_mod_base,
+ pp->io_bus_addr, pp->io_size);
+
return ret;
}
--
2.1.4
[+cc Mohit]
On Thu, Apr 30, 2015 at 04:22:27PM +0800, Jisheng Zhang wrote:
> The outbound iATU programming functions are similar, so PATCH1 consolidates
> them into one.
>
> Most transactions' type are cfg0 and MEM, so current iATU usage is not
> balanced. PATCH2 adopts idea from Minghuan Lian <[email protected]>:
>
> http://www.spinics.net/lists/linux-pci/msg40440.html
>
> to change the iATU allocation: iATU0 for cfg and IO, iATU1 for MEM.
>
> Changes since v1:
> - remove outbound iATU programming for IO in dw_pcie_host_init, since it can
> be done by berlin_pcie_{rd|wr}_other_conf() latter.
> - only do outbound iATU programming for MEM if pp->ops->rd_other_conf is not
> set. Thank Fabrice Gasnier to point out "some platforms doesn't have support
> for ATU"
>
> Jisheng Zhang (2):
> PCI: designware: consolidate outbound iATU programming functions
> PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM
>
> drivers/pci/host/pcie-designware.c | 142 ++++++++++++++++---------------------
These need acks from Jingoo and/or Mohit. Any opinions?
Bjorn
[-cc Mohit, +cc Pratyush]
On Tue, May 19, 2015 at 6:05 PM, Bjorn Helgaas <[email protected]> wrote:
> [+cc Mohit]
>
> On Thu, Apr 30, 2015 at 04:22:27PM +0800, Jisheng Zhang wrote:
>> The outbound iATU programming functions are similar, so PATCH1 consolidates
>> them into one.
>>
>> Most transactions' type are cfg0 and MEM, so current iATU usage is not
>> balanced. PATCH2 adopts idea from Minghuan Lian <[email protected]>:
>>
>> http://www.spinics.net/lists/linux-pci/msg40440.html
>>
>> to change the iATU allocation: iATU0 for cfg and IO, iATU1 for MEM.
>>
>> Changes since v1:
>> - remove outbound iATU programming for IO in dw_pcie_host_init, since it can
>> be done by berlin_pcie_{rd|wr}_other_conf() latter.
>> - only do outbound iATU programming for MEM if pp->ops->rd_other_conf is not
>> set. Thank Fabrice Gasnier to point out "some platforms doesn't have support
>> for ATU"
>>
>> Jisheng Zhang (2):
>> PCI: designware: consolidate outbound iATU programming functions
>> PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM
>>
>> drivers/pci/host/pcie-designware.c | 142 ++++++++++++++++---------------------
>
> These need acks from Jingoo and/or Mohit. Any opinions?
Oops, sorry, forgot about the recent addition of Pratyush.
Bjorn
On Thu, Apr 30, 2015 at 1:52 PM, Jisheng Zhang <[email protected]> wrote:
> Currently, the outbound iATU programming functions are similar, the only
> difference is index, type, addr and size. This patch tries to consolidate
> these functions into one. One side effect is it saves around 1700 bytes in
> text:
>
> text data bss dec hex filename
> 9276 204 4 9484 250c pcie-designware.o-before
> 7532 204 4 7740 1e3c pcie-designware.o
>
> Signed-off-by: Jisheng Zhang <[email protected]>
looks fine to me.
Acked-by: Pratyush Anand <[email protected]>
On Thu, Apr 30, 2015 at 1:52 PM, Jisheng Zhang <[email protected]> wrote:
> Most transactions' type are cfg0 and MEM, so the Current iATU usage is not
> balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors
> the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation
> ideas comes from Minghuan Lian <[email protected]>:
>
> http://www.spinics.net/lists/linux-pci/msg40440.html
>
> Signed-off-by: Jisheng Zhang <[email protected]>
Nice optimization of resources. Thanks :)
Acked-by: Pratyush Anand <[email protected]>
[+cc Pratyush]
On Thu, Apr 30, 2015 at 04:22:27PM +0800, Jisheng Zhang wrote:
> The outbound iATU programming functions are similar, so PATCH1 consolidates
> them into one.
>
> Most transactions' type are cfg0 and MEM, so current iATU usage is not
> balanced. PATCH2 adopts idea from Minghuan Lian <[email protected]>:
>
> http://www.spinics.net/lists/linux-pci/msg40440.html
>
> to change the iATU allocation: iATU0 for cfg and IO, iATU1 for MEM.
>
> Changes since v1:
> - remove outbound iATU programming for IO in dw_pcie_host_init, since it can
> be done by berlin_pcie_{rd|wr}_other_conf() latter.
> - only do outbound iATU programming for MEM if pp->ops->rd_other_conf is not
> set. Thank Fabrice Gasnier to point out "some platforms doesn't have support
> for ATU"
>
> Jisheng Zhang (2):
> PCI: designware: consolidate outbound iATU programming functions
> PCI: designware: use iATU0 for cfg and IO, iATU1 for MEM
>
> drivers/pci/host/pcie-designware.c | 142 ++++++++++++++++---------------------
Applied both with Pratyush's ack to pci/host-designware for v4.2, thanks!