This patch series adds ethernet support for the StarFive JH7100 SoC and
makes it available for the StarFive VisionFive V1 and BeagleV Starlight
boards, although I could only validate on the former SBC. Thank you Emil
and Geert for helping with tests on BeagleV!
The work is heavily based on the reference implementation [1] and depends
on the SiFive Composable Cache controller and non-coherent DMA support
provided by Emil via [2] and [3].
*Update 1*: As of next-20231214, dependencies [2] & [3] have been merged.
*Update 2*: Since v5, the dwmac patches will be handled via [4], while the
clock patches subset via [5].
[1] https://github.com/starfive-tech/linux/commits/visionfive
[2] https://lore.kernel.org/all/CAJM55Z_pdoGxRXbmBgJ5GbVWyeM1N6+LHihbNdT26Oo_qA5VYA@mail.gmail.com/
[3] https://lore.kernel.org/all/[email protected]/
[4] https://lore.kernel.org/lkml/[email protected]/
[5] https://lore.kernel.org/lkml/[email protected]/
Changes in v5:
- Collected R-b tags from Jacob and Andrew
- Squashed PATCH 2 into PATCH 1 per Krzysztof's review
- Split series into patch sets per subsystem, as described in "Update 2"
section above (per Andrew's review)
- v4:
https://lore.kernel.org/lkml/[email protected]/
Changes in v4:
- Restricted double usage of 'ahb' reset name in PATCH 2 (Jessica, Samuel)
- Moved phy reference from PATCH 5 to both PATCH 6 & 7 where the node is
actually defined (Emil, Conor)
- Drop unnecessary gpio include in PATCH 6; also added a DTS comment
describing the rational behind RX internal delay adjustment (Andrew)
- v3:
https://lore.kernel.org/lkml/[email protected]/
Changes in v3:
- Rebased series onto next-20231214 and dropped the ccache & DMA coherency
related patches (v2 06-08/12) handled by Emil via [3]
- Squashed PATCH v2 01/12 into PATCH v3 2/9, per Krzysztof's review
- Dropped incorrect PATCH v2 02/12
- Incorporated Emil's feedback; also added his Co-developed-by on all dts
patches
- Documented the need of adjusting RX internal delay in PATCH v3 8/9, per
Andrew's request
- Added clock fixes from Emil (PATCH v3 8-9/9) required to support
10/100Mb link speeds
- v2:
https://lore.kernel.org/lkml/[email protected]/
Changes in v2:
- Dropped ccache PATCH 01-05 reworked by Emil via [2]
- Dropped already applied PATCH 06/12
- Added PATCH v2 01 to prepare snps-dwmac binding for JH7100 support
- Added PATCH v2 02-03 to provide some jh7110-dwmac binding optimizations
- Handled JH7110 conflicting work in PATCH 07 via PATCH v2 04
- Reworked PATCH 8 via PATCH v2 05, adding JH7100 quirk and dropped
starfive,gtxclk-dlychain DT property; also fixed register naming
- Added PATCH v2 08 providing DMA coherency related DT changes
- Updated PATCH 9 commit msg:
s/OF_DMA_DEFAULT_COHERENT/ARCH_DMA_DEFAULT_COHERENT/
- Replaced 'uncached-offset' property with 'sifive,cache-ops' in PATCH
10/12 and dropped 'sideband' reg
- Add new patch providing coherent DMA memory pool (PATCH v2 10)
- Updated PATCH 11/12 according to the stmmac glue layer changes in
upstream
- Split PATCH 12/12 into PATCH v2 10-12 to handle individual gmac setup of
VisionFive v1 and BeagleV boards as they use different PHYs; also
switched phy-mode from "rgmii-tx" to "rgmii-id" (requires a reduction of
rx-internal-delay-ps by ~50%)
- Rebased series onto next-20231024
- v1:
https://lore.kernel.org/lkml/[email protected]/
Cristian Ciocaltea (4):
riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes
riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac
riscv: dts: starfive: visionfive-v1: Setup ethernet phy
riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio
.../dts/starfive/jh7100-beaglev-starlight.dts | 11 +++
.../boot/dts/starfive/jh7100-common.dtsi | 84 +++++++++++++++++++
.../jh7100-starfive-visionfive-v1.dts | 22 ++++-
arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++
4 files changed, 152 insertions(+), 1 deletion(-)
--
2.43.0
Provide the sysmain and gmac DT nodes supporting the DWMAC found on the
StarFive JH7100 SoC.
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Jacob Keller <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index c216aaecac53..2ebdebe6a81c 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -204,6 +204,37 @@ sdio1: mmc@10010000 {
status = "disabled";
};
+ gmac: ethernet@10020000 {
+ compatible = "starfive,jh7100-dwmac", "snps,dwmac";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
+ <&clkgen JH7100_CLK_GMAC_AHB>,
+ <&clkgen JH7100_CLK_GMAC_PTP_REF>,
+ <&clkgen JH7100_CLK_GMAC_TX_INV>,
+ <&clkgen JH7100_CLK_GMAC_GTX>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
+ resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
+ reset-names = "ahb";
+ interrupts = <6>, <7>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ max-frame-size = <9000>;
+ snps,multicast-filter-bins = <32>;
+ snps,perfect-filter-entries = <128>;
+ starfive,syscon = <&sysmain 0x70 0>;
+ rx-fifo-depth = <32768>;
+ tx-fifo-depth = <16384>;
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,fixed-burst;
+ snps,force_thresh_dma_mode;
+ status = "disabled";
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <16>;
+ snps,rd_osr_lmt = <16>;
+ snps,blen = <256 128 64 32 0 0 0>;
+ };
+ };
+
clkgen: clock-controller@11800000 {
compatible = "starfive,jh7100-clkgen";
reg = <0x0 0x11800000 0x0 0x10000>;
@@ -218,6 +249,11 @@ rstgen: reset-controller@11840000 {
#reset-cells = <1>;
};
+ sysmain: syscon@11850000 {
+ compatible = "starfive,jh7100-sysmain", "syscon";
+ reg = <0x0 0x11850000 0x0 0x10000>;
+ };
+
i2c0: i2c@118b0000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x118b0000 0x0 0x10000>;
--
2.43.0
Add pinmux configuration for DWMAC found on the JH7100 based boards and
enable the related DT node, providing a basic PHY configuration.
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Jacob Keller <[email protected]>
---
.../boot/dts/starfive/jh7100-common.dtsi | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index 42fb61c36068..bcba08e5bdf2 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -72,7 +72,91 @@ wifi_pwrseq: wifi-pwrseq {
};
};
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
&gpio {
+ gmac_pins: gmac-0 {
+ gtxclk-pins {
+ pins = <PAD_FUNC_SHARE(115)>;
+ bias-pull-up;
+ drive-strength = <35>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ miitxclk-pins {
+ pins = <PAD_FUNC_SHARE(116)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ tx-pins {
+ pins = <PAD_FUNC_SHARE(117)>,
+ <PAD_FUNC_SHARE(119)>,
+ <PAD_FUNC_SHARE(120)>,
+ <PAD_FUNC_SHARE(121)>,
+ <PAD_FUNC_SHARE(122)>,
+ <PAD_FUNC_SHARE(123)>,
+ <PAD_FUNC_SHARE(124)>,
+ <PAD_FUNC_SHARE(125)>,
+ <PAD_FUNC_SHARE(126)>;
+ bias-pull-up;
+ drive-strength = <35>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ rxclk-pins {
+ pins = <PAD_FUNC_SHARE(127)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <6>;
+ };
+ rxer-pins {
+ pins = <PAD_FUNC_SHARE(129)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ rx-pins {
+ pins = <PAD_FUNC_SHARE(128)>,
+ <PAD_FUNC_SHARE(130)>,
+ <PAD_FUNC_SHARE(131)>,
+ <PAD_FUNC_SHARE(132)>,
+ <PAD_FUNC_SHARE(133)>,
+ <PAD_FUNC_SHARE(134)>,
+ <PAD_FUNC_SHARE(135)>,
+ <PAD_FUNC_SHARE(136)>,
+ <PAD_FUNC_SHARE(137)>,
+ <PAD_FUNC_SHARE(138)>,
+ <PAD_FUNC_SHARE(139)>,
+ <PAD_FUNC_SHARE(140)>,
+ <PAD_FUNC_SHARE(141)>;
+ bias-pull-up;
+ drive-strength = <14>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
i2c0_pins: i2c0-0 {
i2c-pins {
pinmux = <GPIOMUX(62, GPO_LOW,
--
2.43.0
The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting
RGMII-ID, but requires manual adjustment of the RX internal delay to
work properly.
The default RX delay provided by the driver is 1.95 ns, which proves to
be too high. Applying a 50% reduction seems to mitigate the issue.
Also note this adjustment is not necessary on BeagleV Starlight SBC,
which uses a Microchip PHY. Hence, there is no indication of a
misbehaviour on the GMAC side, but most likely the issue stems from
the Motorcomm PHY.
While at it, drop the redundant gpio include, which is already provided
by jh7100-common.dtsi.
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Jacob Keller <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
.../jh7100-starfive-visionfive-v1.dts | 22 ++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
index e82af72f1aaf..4e396f820660 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include "jh7100-common.dtsi"
-#include <dt-bindings/gpio/gpio.h>
/ {
model = "StarFive VisionFive V1";
@@ -18,3 +17,24 @@ gpio-restart {
priority = <224>;
};
};
+
+/*
+ * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
+ * manual adjustment of the RX internal delay to work properly. The default
+ * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
+ * reduction seems to mitigate the issue.
+ *
+ * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
+ * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
+ * responsible for the misbehaviour, not the GMAC.
+ */
+&mdio {
+ phy: ethernet-phy@0 {
+ reg = <0>;
+ rx-internal-delay-ps = <900>;
+ };
+};
+
+&gmac {
+ phy-handle = <&phy>;
+};
--
2.43.0
The BeagleV Starlight SBC uses a Microchip KSZ9031RNXCA PHY supporting
RGMII-ID which doesn't require any particular setup, other than defining
a reset gpio, as opposed to VisionFive V1 for which the RX internal
delay had to be adjusted.
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Cristian Ciocaltea <[email protected]>
Reviewed-by: Jacob Keller <[email protected]>
---
.../boot/dts/starfive/jh7100-beaglev-starlight.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
index 7cda3a89020a..b79426935bfd 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
@@ -11,3 +11,14 @@ / {
model = "BeagleV Starlight Beta";
compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
};
+
+&mdio {
+ phy: ethernet-phy@7 {
+ reg = <7>;
+ reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gmac {
+ phy-handle = <&phy>;
+};
--
2.43.0
Cristian Ciocaltea wrote:
> Provide the sysmain and gmac DT nodes supporting the DWMAC found on the
> StarFive JH7100 SoC.
>
> Co-developed-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> Reviewed-by: Jacob Keller <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> index c216aaecac53..2ebdebe6a81c 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> @@ -204,6 +204,37 @@ sdio1: mmc@10010000 {
> status = "disabled";
> };
>
> + gmac: ethernet@10020000 {
> + compatible = "starfive,jh7100-dwmac", "snps,dwmac";
> + reg = <0x0 0x10020000 0x0 0x10000>;
> + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
> + <&clkgen JH7100_CLK_GMAC_AHB>,
> + <&clkgen JH7100_CLK_GMAC_PTP_REF>,
> + <&clkgen JH7100_CLK_GMAC_TX_INV>,
> + <&clkgen JH7100_CLK_GMAC_GTX>;
> + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
> + resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
> + reset-names = "ahb";
> + interrupts = <6>, <7>;
> + interrupt-names = "macirq", "eth_wake_irq";
> + max-frame-size = <9000>;
> + snps,multicast-filter-bins = <32>;
> + snps,perfect-filter-entries = <128>;
> + starfive,syscon = <&sysmain 0x70 0>;
> + rx-fifo-depth = <32768>;
> + tx-fifo-depth = <16384>;
> + snps,axi-config = <&stmmac_axi_setup>;
> + snps,fixed-burst;
> + snps,force_thresh_dma_mode;
Compared to v4 you're missing a
snps,no-pbl-x8;
here. It might be the right thing to do, but then I would have expected
it to me mentioned in the cover letter version history.
> + status = "disabled";
> +
> + stmmac_axi_setup: stmmac-axi-config {
> + snps,wr_osr_lmt = <16>;
> + snps,rd_osr_lmt = <16>;
> + snps,blen = <256 128 64 32 0 0 0>;
> + };
> + };
> +
> clkgen: clock-controller@11800000 {
> compatible = "starfive,jh7100-clkgen";
> reg = <0x0 0x11800000 0x0 0x10000>;
> @@ -218,6 +249,11 @@ rstgen: reset-controller@11840000 {
> #reset-cells = <1>;
> };
>
> + sysmain: syscon@11850000 {
> + compatible = "starfive,jh7100-sysmain", "syscon";
> + reg = <0x0 0x11850000 0x0 0x10000>;
> + };
> +
> i2c0: i2c@118b0000 {
> compatible = "snps,designware-i2c";
> reg = <0x0 0x118b0000 0x0 0x10000>;
> --
> 2.43.0
>
Cristian Ciocaltea wrote:
> The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting
> RGMII-ID, but requires manual adjustment of the RX internal delay to
> work properly.
>
> The default RX delay provided by the driver is 1.95 ns, which proves to
> be too high. Applying a 50% reduction seems to mitigate the issue.
>
> Also note this adjustment is not necessary on BeagleV Starlight SBC,
> which uses a Microchip PHY. Hence, there is no indication of a
> misbehaviour on the GMAC side, but most likely the issue stems from
> the Motorcomm PHY.
>
> While at it, drop the redundant gpio include, which is already provided
> by jh7100-common.dtsi.
>
> Co-developed-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> Reviewed-by: Jacob Keller <[email protected]>
> Reviewed-by: Andrew Lunn <[email protected]>
> ---
> .../jh7100-starfive-visionfive-v1.dts | 22 ++++++++++++++++++-
> 1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
> index e82af72f1aaf..4e396f820660 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
> @@ -6,7 +6,6 @@
>
> /dts-v1/;
> #include "jh7100-common.dtsi"
> -#include <dt-bindings/gpio/gpio.h>
>
> / {
> model = "StarFive VisionFive V1";
> @@ -18,3 +17,24 @@ gpio-restart {
> priority = <224>;
> };
> };
> +
> +/*
> + * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
> + * manual adjustment of the RX internal delay to work properly. The default
> + * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
> + * reduction seems to mitigate the issue.
> + *
> + * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
> + * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
> + * responsible for the misbehaviour, not the GMAC.
> + */
> +&mdio {
> + phy: ethernet-phy@0 {
> + reg = <0>;
> + rx-internal-delay-ps = <900>;
> + };
> +};
> +
> +&gmac {
> + phy-handle = <&phy>;
> +};
Alphabetical ordering here, please.
/Emil
Cristian Ciocaltea wrote:
> The BeagleV Starlight SBC uses a Microchip KSZ9031RNXCA PHY supporting
> RGMII-ID which doesn't require any particular setup, other than defining
> a reset gpio, as opposed to VisionFive V1 for which the RX internal
> delay had to be adjusted.
>
> Co-developed-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Cristian Ciocaltea <[email protected]>
> Reviewed-by: Jacob Keller <[email protected]>
> ---
> .../boot/dts/starfive/jh7100-beaglev-starlight.dts | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
> index 7cda3a89020a..b79426935bfd 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
> +++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
> @@ -11,3 +11,14 @@ / {
> model = "BeagleV Starlight Beta";
> compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
> };
> +
> +&mdio {
> + phy: ethernet-phy@7 {
> + reg = <7>;
> + reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&gmac {
> + phy-handle = <&phy>;
> +};
..and here.
On 12/20/23 15:43, Emil Renner Berthing wrote:
> Cristian Ciocaltea wrote:
>> Provide the sysmain and gmac DT nodes supporting the DWMAC found on the
>> StarFive JH7100 SoC.
>>
>> Co-developed-by: Emil Renner Berthing <[email protected]>
>> Signed-off-by: Emil Renner Berthing <[email protected]>
>> Signed-off-by: Cristian Ciocaltea <[email protected]>
>> Reviewed-by: Jacob Keller <[email protected]>
>> ---
>> arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++
>> 1 file changed, 36 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> index c216aaecac53..2ebdebe6a81c 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> @@ -204,6 +204,37 @@ sdio1: mmc@10010000 {
>> status = "disabled";
>> };
>>
>> + gmac: ethernet@10020000 {
>> + compatible = "starfive,jh7100-dwmac", "snps,dwmac";
>> + reg = <0x0 0x10020000 0x0 0x10000>;
>> + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
>> + <&clkgen JH7100_CLK_GMAC_AHB>,
>> + <&clkgen JH7100_CLK_GMAC_PTP_REF>,
>> + <&clkgen JH7100_CLK_GMAC_TX_INV>,
>> + <&clkgen JH7100_CLK_GMAC_GTX>;
>> + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
>> + resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
>> + reset-names = "ahb";
>> + interrupts = <6>, <7>;
>> + interrupt-names = "macirq", "eth_wake_irq";
>> + max-frame-size = <9000>;
>> + snps,multicast-filter-bins = <32>;
>> + snps,perfect-filter-entries = <128>;
>> + starfive,syscon = <&sysmain 0x70 0>;
>> + rx-fifo-depth = <32768>;
>> + tx-fifo-depth = <16384>;
>> + snps,axi-config = <&stmmac_axi_setup>;
>> + snps,fixed-burst;
>> + snps,force_thresh_dma_mode;
>
> Compared to v4 you're missing a
>
> snps,no-pbl-x8;
>
> here. It might be the right thing to do, but then I would have expected
> it to me mentioned in the cover letter version history.
Oh yes, I missed to add this to the changelog, sorry! I dropped that
because the property is only valid for snps,dwmac-{3.50a, 4.10a, 4.20a,
5.20} compatibles, while we have plain snps,dwmac to handle 3.7x.
We could have probably used snps,dwmac-3.70a or snps,dwmac-3.710, but
I'm not sure which is the exact chip revision and it wouldn't really
change anything as there is no special handling for them in the
snps,dwmac.yaml binding.
>> + status = "disabled";
>> +
>> + stmmac_axi_setup: stmmac-axi-config {
>> + snps,wr_osr_lmt = <16>;
>> + snps,rd_osr_lmt = <16>;
>> + snps,blen = <256 128 64 32 0 0 0>;
>> + };
>> + };
>> +
>> clkgen: clock-controller@11800000 {
>> compatible = "starfive,jh7100-clkgen";
>> reg = <0x0 0x11800000 0x0 0x10000>;
>> @@ -218,6 +249,11 @@ rstgen: reset-controller@11840000 {
>> #reset-cells = <1>;
>> };
>>
>> + sysmain: syscon@11850000 {
>> + compatible = "starfive,jh7100-sysmain", "syscon";
>> + reg = <0x0 0x11850000 0x0 0x10000>;
>> + };
>> +
>> i2c0: i2c@118b0000 {
>> compatible = "snps,designware-i2c";
>> reg = <0x0 0x118b0000 0x0 0x10000>;
>> --
>> 2.43.0
>>
On 12/20/23 15:48, Emil Renner Berthing wrote:
> Cristian Ciocaltea wrote:
>> The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting
>> RGMII-ID, but requires manual adjustment of the RX internal delay to
>> work properly.
>>
>> The default RX delay provided by the driver is 1.95 ns, which proves to
>> be too high. Applying a 50% reduction seems to mitigate the issue.
>>
>> Also note this adjustment is not necessary on BeagleV Starlight SBC,
>> which uses a Microchip PHY. Hence, there is no indication of a
>> misbehaviour on the GMAC side, but most likely the issue stems from
>> the Motorcomm PHY.
>>
>> While at it, drop the redundant gpio include, which is already provided
>> by jh7100-common.dtsi.
>>
>> Co-developed-by: Emil Renner Berthing <[email protected]>
>> Signed-off-by: Emil Renner Berthing <[email protected]>
>> Signed-off-by: Cristian Ciocaltea <[email protected]>
>> Reviewed-by: Jacob Keller <[email protected]>
>> Reviewed-by: Andrew Lunn <[email protected]>
>> ---
>> .../jh7100-starfive-visionfive-v1.dts | 22 ++++++++++++++++++-
>> 1 file changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
>> index e82af72f1aaf..4e396f820660 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
>> +++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
>> @@ -6,7 +6,6 @@
>>
>> /dts-v1/;
>> #include "jh7100-common.dtsi"
>> -#include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> model = "StarFive VisionFive V1";
>> @@ -18,3 +17,24 @@ gpio-restart {
>> priority = <224>;
>> };
>> };
>> +
>> +/*
>> + * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
>> + * manual adjustment of the RX internal delay to work properly. The default
>> + * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
>> + * reduction seems to mitigate the issue.
>> + *
>> + * It is worth noting the adjustment is not necessary on BeagleV Starlight SBC,
>> + * which uses a Microchip PHY. Hence, most likely the Motorcomm PHY is the one
>> + * responsible for the misbehaviour, not the GMAC.
>> + */
>> +&mdio {
>> + phy: ethernet-phy@0 {
>> + reg = <0>;
>> + rx-internal-delay-ps = <900>;
>> + };
>> +};
>> +
>> +&gmac {
>> + phy-handle = <&phy>;
>> +};
>
> Alphabetical ordering here, please.
Yeah, I wasn't sure if the ordering is more important than having the
referenced nodes added before. I suppose there's a need for v6. :-)
> /Emil
Cristian Ciocaltea wrote:
> On 12/20/23 15:43, Emil Renner Berthing wrote:
> > Cristian Ciocaltea wrote:
> >> Provide the sysmain and gmac DT nodes supporting the DWMAC found on the
> >> StarFive JH7100 SoC.
> >>
> >> Co-developed-by: Emil Renner Berthing <[email protected]>
> >> Signed-off-by: Emil Renner Berthing <[email protected]>
> >> Signed-off-by: Cristian Ciocaltea <[email protected]>
> >> Reviewed-by: Jacob Keller <[email protected]>
> >> ---
> >> arch/riscv/boot/dts/starfive/jh7100.dtsi | 36 ++++++++++++++++++++++++
> >> 1 file changed, 36 insertions(+)
> >>
> >> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> >> index c216aaecac53..2ebdebe6a81c 100644
> >> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> >> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> >> @@ -204,6 +204,37 @@ sdio1: mmc@10010000 {
> >> status = "disabled";
> >> };
> >>
> >> + gmac: ethernet@10020000 {
> >> + compatible = "starfive,jh7100-dwmac", "snps,dwmac";
> >> + reg = <0x0 0x10020000 0x0 0x10000>;
> >> + clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
> >> + <&clkgen JH7100_CLK_GMAC_AHB>,
> >> + <&clkgen JH7100_CLK_GMAC_PTP_REF>,
> >> + <&clkgen JH7100_CLK_GMAC_TX_INV>,
> >> + <&clkgen JH7100_CLK_GMAC_GTX>;
> >> + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
> >> + resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
> >> + reset-names = "ahb";
> >> + interrupts = <6>, <7>;
> >> + interrupt-names = "macirq", "eth_wake_irq";
> >> + max-frame-size = <9000>;
> >> + snps,multicast-filter-bins = <32>;
> >> + snps,perfect-filter-entries = <128>;
> >> + starfive,syscon = <&sysmain 0x70 0>;
> >> + rx-fifo-depth = <32768>;
> >> + tx-fifo-depth = <16384>;
> >> + snps,axi-config = <&stmmac_axi_setup>;
> >> + snps,fixed-burst;
> >> + snps,force_thresh_dma_mode;
> >
> > Compared to v4 you're missing a
> >
> > snps,no-pbl-x8;
> >
> > here. It might be the right thing to do, but then I would have expected
> > it to me mentioned in the cover letter version history.
>
> Oh yes, I missed to add this to the changelog, sorry! I dropped that
> because the property is only valid for snps,dwmac-{3.50a, 4.10a, 4.20a,
> 5.20} compatibles, while we have plain snps,dwmac to handle 3.7x.
>
> We could have probably used snps,dwmac-3.70a or snps,dwmac-3.710, but
> I'm not sure which is the exact chip revision and it wouldn't really
> change anything as there is no special handling for them in the
> snps,dwmac.yaml binding.
I see, makes sense. This way works fine for me.
/Emil