Add CRG driver for Hi3798CV200 and Hi3516CV200 SoCs.
Jiancheng Xue (2):
clk: hisilicon: add CRG driver for Hi3798CV200 SoC
clk: hisilicon: add CRG driver for Hi3516CV300 SoC
.../clock/{hi3519-crg.txt => hisi-crg.txt} | 12 +-
drivers/clk/hisilicon/Kconfig | 16 +
drivers/clk/hisilicon/Makefile | 2 +
drivers/clk/hisilicon/crg-hi3516cv300.c | 330 ++++++++++++++++++++
drivers/clk/hisilicon/crg-hi3798cv200.c | 337 +++++++++++++++++++++
drivers/clk/hisilicon/crg.h | 34 +++
include/dt-bindings/clock/hi3516cv300-clock.h | 48 +++
include/dt-bindings/clock/histb-clock.h | 66 ++++
8 files changed, 841 insertions(+), 4 deletions(-)
rename Documentation/devicetree/bindings/clock/{hi3519-crg.txt => hisi-crg.txt} (80%)
create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c
create mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c
create mode 100644 drivers/clk/hisilicon/crg.h
create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h
create mode 100644 include/dt-bindings/clock/histb-clock.h
--
1.9.1
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Pan Wen <[email protected]>
---
drivers/clk/hisilicon/Kconfig | 8 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/crg-hi3516cv300.c | 330 ++++++++++++++++++++++++++
include/dt-bindings/clock/hi3516cv300-clock.h | 48 ++++
4 files changed, 387 insertions(+)
create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c
create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index c41b6d2..f80773b 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -1,3 +1,11 @@
+config COMMON_CLK_HI3516CV300
+ tristate "HI3516CV300 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ select RESET_HISI
+ default ARCH_HISI
+ help
+ Build the clock driver for hi3516cv300.
+
config COMMON_CLK_HI3519
tristate "Hi3519 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 5819891..4eec5e5 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -7,6 +7,7 @@ obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
+obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c
new file mode 100644
index 0000000..2007123
--- /dev/null
+++ b/drivers/clk/hisilicon/crg-hi3516cv300.c
@@ -0,0 +1,330 @@
+/*
+ * Hi3516CV300 Clock and Reset Generator Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/hi3516cv300-clock.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "clk.h"
+#include "crg.h"
+#include "reset.h"
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_INNER_CLK_OFFSET 64
+#define HI3516CV300_FIXED_3M 65
+#define HI3516CV300_FIXED_6M 66
+#define HI3516CV300_FIXED_24M 67
+#define HI3516CV300_FIXED_49P5 68
+#define HI3516CV300_FIXED_50M 69
+#define HI3516CV300_FIXED_83P3M 70
+#define HI3516CV300_FIXED_99M 71
+#define HI3516CV300_FIXED_100M 72
+#define HI3516CV300_FIXED_148P5M 73
+#define HI3516CV300_FIXED_198M 74
+#define HI3516CV300_FIXED_297M 75
+#define HI3516CV300_UART_MUX 76
+#define HI3516CV300_FMC_MUX 77
+#define HI3516CV300_MMC0_MUX 78
+#define HI3516CV300_MMC1_MUX 79
+#define HI3516CV300_MMC2_MUX 80
+#define HI3516CV300_MMC3_MUX 81
+#define HI3516CV300_PWM_MUX 82
+#define HI3516CV300_CRG_NR_CLKS 128
+
+static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = {
+ { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
+ { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
+ { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
+ { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
+ { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
+ { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
+ { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
+ { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
+ { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
+ { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
+ { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
+ { HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, },
+};
+
+static const char *const uart_mux_p[] = {"24m", "6m"};
+static const char *const fmc_mux_p[] = {
+ "24m", "83.3m", "148.5m", "198m", "297m"
+};
+static const char *const mmc_mux_p[] = {"49.5m"};
+static const char *const mmc2_mux_p[] = {"99m", "49.5m"};
+static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"};
+
+static u32 uart_mux_table[] = {0, 1};
+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4};
+static u32 mmc_mux_table[] = {0};
+static u32 mmc2_mux_table[] = {0, 2};
+static u32 pwm_mux_table[] = {0, 1, 2, 3};
+
+static const struct hisi_mux_clock hi3516cv300_mux_clks[] = {
+ { HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
+ CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
+ { HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
+ { HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
+ { HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
+ { HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p),
+ CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
+ { HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
+ { HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p),
+ CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
+
+ { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
+ 0xe4, 15, 0, },
+ { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
+ 0xe4, 16, 0, },
+ { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
+ 0xe4, 17, 0, },
+
+ { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
+ 0xe4, 13, 0, },
+ { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
+ 0xe4, 14, 0, },
+
+ { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
+ 0xc0, 1, 0, },
+ { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
+ 0xc4, 1, 0, },
+ { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
+ 0xc4, 9, 0, },
+ { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
+ 0xc4, 17, 0, },
+ { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
+ 0xc8, 1, 0, },
+
+ { HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, },
+
+ { HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, },
+ { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
+ 0x38, 1, 0, },
+
+ { HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, },
+ { HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0,
+ 0xb8, 1, 0, },
+ { HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0,
+ 0xb8, 2, 0, },
+ { HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0,
+ 0xb8, 3, 0, },
+ { HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0,
+ 0xb8, 4, 0, },
+ { HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, },
+ { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
+};
+
+static struct hisi_clock_data *hi3516cv300_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
+ ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
+ ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
+ ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3516cv300_gate_clks,
+ ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
+unregister_mux:
+ hisi_clk_unregister_mux(hi3516cv300_mux_clks,
+ ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
+ ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3516cv300_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3516cv300_gate_clks,
+ ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
+ hisi_clk_unregister_mux(hi3516cv300_mux_clks,
+ ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
+ hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
+ ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
+ .register_clks = hi3516cv300_clk_register,
+ .unregister_clks = hi3516cv300_clk_unregister,
+};
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_SYSCTRL_NR_CLKS 16
+
+static const char *wdt_mux_p[] __initconst = { "3m", "apb" };
+static u32 wdt_mux_table[] = {0, 1};
+
+static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
+ { HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p),
+ CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
+};
+
+static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
+ ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ return clk_data;
+
+unregister_mux:
+ hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
+ ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
+ ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
+ crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
+ .register_clks = hi3516cv300_sysctrl_clk_register,
+ .unregister_clks = hi3516cv300_sysctrl_clk_unregister,
+};
+
+static const struct of_device_id hi3516cv300_crg_match_table[] = {
+ {
+ .compatible = "hisilicon,hi3516cv300-crg",
+ .data = &hi3516cv300_crg_funcs
+ },
+ {
+ .compatible = "hisilicon,hi3516cv300-sysctrl",
+ .data = &hi3516cv300_sysctrl_funcs
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
+
+static int hi3516cv300_crg_probe(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg;
+
+ crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
+ if (!crg)
+ return -ENOMEM;
+
+ crg->funcs = of_device_get_match_data(&pdev->dev);
+ if (!crg->funcs)
+ return -ENOENT;
+
+ crg->rstc = hisi_reset_init(pdev);
+ if (!crg->rstc)
+ return -ENOMEM;
+
+ crg->clk_data = crg->funcs->register_clks(pdev);
+ if (IS_ERR(crg->clk_data)) {
+ hisi_reset_exit(crg->rstc);
+ return PTR_ERR(crg->clk_data);
+ }
+
+ platform_set_drvdata(pdev, crg);
+ return 0;
+}
+
+static int hi3516cv300_crg_remove(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ hisi_reset_exit(crg->rstc);
+ crg->funcs->unregister_clks(pdev);
+ return 0;
+}
+
+static struct platform_driver hi3516cv300_crg_driver = {
+ .probe = hi3516cv300_crg_probe,
+ .remove = hi3516cv300_crg_remove,
+ .driver = {
+ .name = "hi3516cv300-crg",
+ .of_match_table = hi3516cv300_crg_match_table,
+ },
+};
+
+static int __init hi3516cv300_crg_init(void)
+{
+ return platform_driver_register(&hi3516cv300_crg_driver);
+}
+core_initcall(hi3516cv300_crg_init);
+
+static void __exit hi3516cv300_crg_exit(void)
+{
+ platform_driver_unregister(&hi3516cv300_crg_driver);
+}
+module_exit(hi3516cv300_crg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");
diff --git a/include/dt-bindings/clock/hi3516cv300-clock.h b/include/dt-bindings/clock/hi3516cv300-clock.h
new file mode 100644
index 0000000..5ba51b8
--- /dev/null
+++ b/include/dt-bindings/clock/hi3516cv300-clock.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HI3516CV300_CLOCK_H
+#define __DTS_HI3516CV300_CLOCK_H
+
+/* hi3516CV300 core CRG */
+#define HI3516CV300_APB_CLK 0
+#define HI3516CV300_UART0_CLK 1
+#define HI3516CV300_UART1_CLK 2
+#define HI3516CV300_UART2_CLK 3
+#define HI3516CV300_SPI0_CLK 4
+#define HI3516CV300_SPI1_CLK 5
+#define HI3516CV300_FMC_CLK 6
+#define HI3516CV300_MMC0_CLK 7
+#define HI3516CV300_MMC1_CLK 8
+#define HI3516CV300_MMC2_CLK 9
+#define HI3516CV300_MMC3_CLK 10
+#define HI3516CV300_ETH_CLK 11
+#define HI3516CV300_ETH_MACIF_CLK 12
+#define HI3516CV300_DMAC_CLK 13
+#define HI3516CV300_PWM_CLK 14
+#define HI3516CV300_USB2_BUS_CLK 15
+#define HI3516CV300_USB2_OHCI48M_CLK 16
+#define HI3516CV300_USB2_OHCI12M_CLK 17
+#define HI3516CV300_USB2_OTG_UTMI_CLK 18
+#define HI3516CV300_USB2_HST_PHY_CLK 19
+#define HI3516CV300_USB2_UTMI0_CLK 20
+#define HI3516CV300_USB2_PHY_CLK 21
+
+/* hi3516CV300 sysctrl CRG */
+#define HI3516CV300_WDT_CLK 1
+
+#endif /* __DTS_HI3516CV300_CLOCK_H */
--
1.9.1
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Jiancheng Xue <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
change log
v3:
- Added ethernet and combo-phy clocks.
v2:
- Fixed compiling error when compiled as a module.
- Fixed issues pointed by Stephen Boyd.
- Added prefix HISTB for clock index macro definitions.
.../clock/{hi3519-crg.txt => hisi-crg.txt} | 12 +-
drivers/clk/hisilicon/Kconfig | 8 +
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/crg-hi3798cv200.c | 337 +++++++++++++++++++++
drivers/clk/hisilicon/crg.h | 34 +++
include/dt-bindings/clock/histb-clock.h | 66 ++++
6 files changed, 454 insertions(+), 4 deletions(-)
rename Documentation/devicetree/bindings/clock/{hi3519-crg.txt => hisi-crg.txt} (80%)
create mode 100644 drivers/clk/hisilicon/crg-hi3798cv200.c
create mode 100644 drivers/clk/hisilicon/crg.h
create mode 100644 include/dt-bindings/clock/histb-clock.h
diff --git a/Documentation/devicetree/bindings/clock/hi3519-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt
similarity index 80%
rename from Documentation/devicetree/bindings/clock/hi3519-crg.txt
rename to Documentation/devicetree/bindings/clock/hisi-crg.txt
index acd1f23..cc60b3d 100644
--- a/Documentation/devicetree/bindings/clock/hi3519-crg.txt
+++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt
@@ -1,7 +1,7 @@
-* Hisilicon Hi3519 Clock and Reset Generator(CRG)
+* HiSilicon Clock and Reset Generator(CRG)
-The Hi3519 CRG module provides clock and reset signals to various
-controllers within the SoC.
+The CRG module provides clock and reset signals to various
+modules within the SoC.
This binding uses the following bindings:
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -10,7 +10,11 @@ This binding uses the following bindings:
Required Properties:
- compatible: should be one of the following.
- - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
+ - "hisilicon,hi3516cv300-crg"
+ - "hisilicon,hi3516cv300-sysctrl"
+ - "hisilicon,hi3519-crg"
+ - "hisilicon,hi3798cv200-crg"
+ - "hisilicon,hi3798cv200-sysctrl"
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 3f537a0..c41b6d2 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -6,6 +6,14 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3798CV200
+ tristate "Hi3798CV200 Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ select RESET_HISI
+ default ARCH_HISI
+ help
+ Build the clock driver for hi3798cv200.
+
config COMMON_CLK_HI6220
bool "Hi6220 Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index e169ec7..5819891 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
+obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
new file mode 100644
index 0000000..fc8b5bc
--- /dev/null
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -0,0 +1,337 @@
+/*
+ * Hi3798CV200 Clock and Reset Generator Driver
+ *
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/clock/histb-clock.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include "clk.h"
+#include "crg.h"
+#include "reset.h"
+
+/* hi3798CV200 core CRG */
+#define HI3798CV200_INNER_CLK_OFFSET 64
+#define HI3798CV200_FIXED_24M 65
+#define HI3798CV200_FIXED_25M 66
+#define HI3798CV200_FIXED_50M 67
+#define HI3798CV200_FIXED_75M 68
+#define HI3798CV200_FIXED_100M 69
+#define HI3798CV200_FIXED_150M 70
+#define HI3798CV200_FIXED_200M 71
+#define HI3798CV200_FIXED_250M 72
+#define HI3798CV200_FIXED_300M 73
+#define HI3798CV200_FIXED_400M 74
+#define HI3798CV200_MMC_MUX 75
+#define HI3798CV200_ETH_PUB_CLK 76
+#define HI3798CV200_ETH_BUS_CLK 77
+#define HI3798CV200_ETH_BUS0_CLK 78
+#define HI3798CV200_ETH_BUS1_CLK 79
+#define HI3798CV200_COMBPHY1_MUX 80
+
+#define HI3798CV200_CRG_NR_CLKS 128
+
+static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
+ { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
+ { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
+ { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
+ { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
+ { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
+ { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
+ { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
+ { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
+ { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
+ { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
+ { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
+};
+
+static const char *const mmc_mux_p[] = {
+ "100m", "50m", "25m", "200m", "150m" };
+static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
+
+static const char *const comphy1_mux_p[] = {
+ "100m", "25m"};
+static u32 comphy1_mux_table[] = {2, 3};
+
+static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
+ { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
+ CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
+ { HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
+ comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),
+ CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
+ /* UART */
+ { HISTB_UART2_CLK, "clk_uart2", "75m",
+ CLK_SET_RATE_PARENT, 0x68, 4, 0, },
+ /* I2C */
+ { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
+ { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
+ { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
+ { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
+ { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
+ /* SPI */
+ { HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
+ CLK_SET_RATE_PARENT, 0x70, 0, 0, },
+ /* SDIO */
+ { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
+ CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
+ { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux",
+ CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
+ /* EMMC */
+ { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
+ CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
+ { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
+ CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
+ /* PCIE*/
+ { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
+ CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
+ { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
+ CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
+ { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
+ CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
+ { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
+ CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
+ /* Ethernet */
+ { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
+ CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
+ { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
+ CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
+ { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
+ CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
+ { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
+ CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
+ { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
+ CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
+ { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0",
+ CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
+ { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1",
+ CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
+ { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
+ CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
+ /* COMBPHY1 */
+ { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
+ CLK_SET_RATE_PARENT, 0x188, 8, 0, },
+};
+
+static struct hisi_clock_data *hi3798cv200_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
+ ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+ clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
+ ARRAY_SIZE(hi3798cv200_mux_clks),
+ clk_data);
+ if (ret)
+ goto unregister_fixed_rate;
+
+ ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
+ ARRAY_SIZE(hi3798cv200_gate_clks),
+ clk_data);
+ if (ret)
+ goto unregister_mux;
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_fixed_rate:
+ hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
+ ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+ clk_data);
+
+unregister_mux:
+ hisi_clk_unregister_mux(hi3798cv200_mux_clks,
+ ARRAY_SIZE(hi3798cv200_mux_clks),
+ clk_data);
+unregister_gate:
+ hisi_clk_unregister_gate(hi3798cv200_gate_clks,
+ ARRAY_SIZE(hi3798cv200_gate_clks),
+ clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3798cv200_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3798cv200_gate_clks,
+ ARRAY_SIZE(hi3798cv200_gate_clks),
+ crg->clk_data);
+ hisi_clk_unregister_mux(hi3798cv200_mux_clks,
+ ARRAY_SIZE(hi3798cv200_mux_clks),
+ crg->clk_data);
+ hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
+ ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
+ crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
+ .register_clks = hi3798cv200_clk_register,
+ .unregister_clks = hi3798cv200_clk_unregister,
+};
+
+/* hi3798CV200 sysctrl CRG */
+
+#define HI3798CV200_SYSCTRL_NR_CLKS 16
+
+static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
+ { HISTB_IR_CLK, "clk_ir", "100m",
+ CLK_SET_RATE_PARENT, 0x48, 4, 0, },
+ { HISTB_TIMER01_CLK, "clk_timer01", "24m",
+ CLK_SET_RATE_PARENT, 0x48, 6, 0, },
+ { HISTB_UART0_CLK, "clk_uart0", "75m",
+ CLK_SET_RATE_PARENT, 0x48, 10, 0, },
+};
+
+static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
+ struct platform_device *pdev)
+{
+ struct hisi_clock_data *clk_data;
+ int ret;
+
+ clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
+ if (!clk_data)
+ return ERR_PTR(-ENOMEM);
+
+ ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
+ ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+ clk_data);
+ if (ret)
+ return ERR_PTR(ret);
+
+ ret = of_clk_add_provider(pdev->dev.of_node,
+ of_clk_src_onecell_get, &clk_data->clk_data);
+ if (ret)
+ goto unregister_gate;
+
+ return clk_data;
+
+unregister_gate:
+ hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
+ ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+ clk_data);
+ return ERR_PTR(ret);
+}
+
+static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
+ ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
+ crg->clk_data);
+}
+
+static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
+ .register_clks = hi3798cv200_sysctrl_clk_register,
+ .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
+};
+
+static const struct of_device_id hi3798cv200_crg_match_table[] = {
+ { .compatible = "hisilicon,hi3798cv200-crg",
+ .data = &hi3798cv200_crg_funcs },
+ { .compatible = "hisilicon,hi3798cv200-sysctrl",
+ .data = &hi3798cv200_sysctrl_funcs },
+ { }
+};
+MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
+
+static int hi3798cv200_crg_probe(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg;
+
+ crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
+ if (!crg)
+ return -ENOMEM;
+
+ crg->funcs = of_device_get_match_data(&pdev->dev);
+ if (!crg->funcs)
+ return -ENOENT;
+
+ crg->rstc = hisi_reset_init(pdev);
+ if (!crg->rstc)
+ return -ENOMEM;
+
+ crg->clk_data = crg->funcs->register_clks(pdev);
+ if (IS_ERR(crg->clk_data)) {
+ hisi_reset_exit(crg->rstc);
+ return PTR_ERR(crg->clk_data);
+ }
+
+ platform_set_drvdata(pdev, crg);
+ return 0;
+}
+
+static int hi3798cv200_crg_remove(struct platform_device *pdev)
+{
+ struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
+
+ hisi_reset_exit(crg->rstc);
+ crg->funcs->unregister_clks(pdev);
+ return 0;
+}
+
+static struct platform_driver hi3798cv200_crg_driver = {
+ .probe = hi3798cv200_crg_probe,
+ .remove = hi3798cv200_crg_remove,
+ .driver = {
+ .name = "hi3798cv200-crg",
+ .of_match_table = hi3798cv200_crg_match_table,
+ },
+};
+
+static int __init hi3798cv200_crg_init(void)
+{
+ return platform_driver_register(&hi3798cv200_crg_driver);
+}
+core_initcall(hi3798cv200_crg_init);
+
+static void __exit hi3798cv200_crg_exit(void)
+{
+ platform_driver_unregister(&hi3798cv200_crg_driver);
+}
+module_exit(hi3798cv200_crg_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");
diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
new file mode 100644
index 0000000..e073971
--- /dev/null
+++ b/drivers/clk/hisilicon/crg.h
@@ -0,0 +1,34 @@
+/*
+ * HiSilicon Clock and Reset Driver Header
+ *
+ * Copyright (c) 2016 HiSilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HISI_CRG_H
+#define __HISI_CRG_H
+
+struct hisi_clock_data;
+struct hisi_reset_controller;
+
+struct hisi_crg_funcs {
+ struct hisi_clock_data* (*register_clks)(struct platform_device *pdev);
+ void (*unregister_clks)(struct platform_device *pdev);
+};
+
+struct hisi_crg_dev {
+ struct hisi_clock_data *clk_data;
+ struct hisi_reset_controller *rstc;
+ const struct hisi_crg_funcs *funcs;
+};
+
+#endif /* __HISI_CRG_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
new file mode 100644
index 0000000..181c0f0
--- /dev/null
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DTS_HISTB_CLOCK_H
+#define __DTS_HISTB_CLOCK_H
+
+/* clocks provided by core CRG */
+#define HISTB_OSC_CLK 0
+#define HISTB_APB_CLK 1
+#define HISTB_AHB_CLK 2
+#define HISTB_UART1_CLK 3
+#define HISTB_UART2_CLK 4
+#define HISTB_UART3_CLK 5
+#define HISTB_I2C0_CLK 6
+#define HISTB_I2C1_CLK 7
+#define HISTB_I2C2_CLK 8
+#define HISTB_I2C3_CLK 9
+#define HISTB_I2C4_CLK 10
+#define HISTB_I2C5_CLK 11
+#define HISTB_SPI0_CLK 12
+#define HISTB_SPI1_CLK 13
+#define HISTB_SPI2_CLK 14
+#define HISTB_SCI_CLK 15
+#define HISTB_FMC_CLK 16
+#define HISTB_MMC_BIU_CLK 17
+#define HISTB_MMC_CIU_CLK 18
+#define HISTB_MMC_DRV_CLK 19
+#define HISTB_MMC_SAMPLE_CLK 20
+#define HISTB_SDIO0_BIU_CLK 21
+#define HISTB_SDIO0_CIU_CLK 22
+#define HISTB_SDIO0_DRV_CLK 23
+#define HISTB_SDIO0_SAMPLE_CLK 24
+#define HISTB_PCIE_AUX_CLK 25
+#define HISTB_PCIE_PIPE_CLK 26
+#define HISTB_PCIE_SYS_CLK 27
+#define HISTB_PCIE_BUS_CLK 28
+#define HISTB_ETH0_MAC_CLK 29
+#define HISTB_ETH0_MACIF_CLK 30
+#define HISTB_ETH1_MAC_CLK 31
+#define HISTB_ETH1_MACIF_CLK 32
+#define HISTB_COMBPHY1_CLK 33
+
+
+/* clocks provided by mcu CRG */
+#define HISTB_MCE_CLK 1
+#define HISTB_IR_CLK 2
+#define HISTB_TIMER01_CLK 3
+#define HISTB_LEDC_CLK 4
+#define HISTB_UART0_CLK 5
+#define HISTB_LSADC_CLK 6
+
+#endif /* __DTS_HISTB_CLOCK_H */
--
1.9.1
Hi, is there any mainline kernel or uboot for hisilicon hi3520dv200 or
hi3520dv300? just want some base support to boot , anything close to
mainline is ok :)
2016-10-29 14:13 GMT+08:00 Jiancheng Xue <[email protected]>:
> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
> Generator) module generates clock and reset signals used
> by other module blocks on SoC.
>
> Signed-off-by: Pan Wen <[email protected]>
> ---
> drivers/clk/hisilicon/Kconfig | 8 +
> drivers/clk/hisilicon/Makefile | 1 +
> drivers/clk/hisilicon/crg-hi3516cv300.c | 330 ++++++++++++++++++++++++++
> include/dt-bindings/clock/hi3516cv300-clock.h | 48 ++++
> 4 files changed, 387 insertions(+)
> create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c
> create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h
>
> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
> index c41b6d2..f80773b 100644
> --- a/drivers/clk/hisilicon/Kconfig
> +++ b/drivers/clk/hisilicon/Kconfig
> @@ -1,3 +1,11 @@
> +config COMMON_CLK_HI3516CV300
> + tristate "HI3516CV300 Clock Driver"
> + depends on ARCH_HISI || COMPILE_TEST
> + select RESET_HISI
> + default ARCH_HISI
> + help
> + Build the clock driver for hi3516cv300.
> +
> config COMMON_CLK_HI3519
> tristate "Hi3519 Clock Driver"
> depends on ARCH_HISI || COMPILE_TEST
> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
> index 5819891..4eec5e5 100644
> --- a/drivers/clk/hisilicon/Makefile
> +++ b/drivers/clk/hisilicon/Makefile
> @@ -7,6 +7,7 @@ obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
> obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
> +obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
> obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
> obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
> diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c
> new file mode 100644
> index 0000000..2007123
> --- /dev/null
> +++ b/drivers/clk/hisilicon/crg-hi3516cv300.c
> @@ -0,0 +1,330 @@
> +/*
> + * Hi3516CV300 Clock and Reset Generator Driver
> + *
> + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <dt-bindings/clock/hi3516cv300-clock.h>
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include "clk.h"
> +#include "crg.h"
> +#include "reset.h"
> +
> +/* hi3516CV300 core CRG */
> +#define HI3516CV300_INNER_CLK_OFFSET 64
> +#define HI3516CV300_FIXED_3M 65
> +#define HI3516CV300_FIXED_6M 66
> +#define HI3516CV300_FIXED_24M 67
> +#define HI3516CV300_FIXED_49P5 68
> +#define HI3516CV300_FIXED_50M 69
> +#define HI3516CV300_FIXED_83P3M 70
> +#define HI3516CV300_FIXED_99M 71
> +#define HI3516CV300_FIXED_100M 72
> +#define HI3516CV300_FIXED_148P5M 73
> +#define HI3516CV300_FIXED_198M 74
> +#define HI3516CV300_FIXED_297M 75
> +#define HI3516CV300_UART_MUX 76
> +#define HI3516CV300_FMC_MUX 77
> +#define HI3516CV300_MMC0_MUX 78
> +#define HI3516CV300_MMC1_MUX 79
> +#define HI3516CV300_MMC2_MUX 80
> +#define HI3516CV300_MMC3_MUX 81
> +#define HI3516CV300_PWM_MUX 82
> +#define HI3516CV300_CRG_NR_CLKS 128
> +
> +static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = {
> + { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
> + { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
> + { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
> + { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
> + { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
> + { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
> + { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
> + { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
> + { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
> + { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
> + { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
> + { HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, },
> +};
> +
> +static const char *const uart_mux_p[] = {"24m", "6m"};
> +static const char *const fmc_mux_p[] = {
> + "24m", "83.3m", "148.5m", "198m", "297m"
> +};
> +static const char *const mmc_mux_p[] = {"49.5m"};
> +static const char *const mmc2_mux_p[] = {"99m", "49.5m"};
> +static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"};
> +
> +static u32 uart_mux_table[] = {0, 1};
> +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4};
> +static u32 mmc_mux_table[] = {0};
> +static u32 mmc2_mux_table[] = {0, 2};
> +static u32 pwm_mux_table[] = {0, 1, 2, 3};
> +
> +static const struct hisi_mux_clock hi3516cv300_mux_clks[] = {
> + { HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
> + CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
> + { HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
> + CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
> + { HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
> + CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
> + { HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
> + CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
> + { HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p),
> + CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
> + { HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
> + CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
> + { HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p),
> + CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
> +};
> +
> +static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
> +
> + { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
> + 0xe4, 15, 0, },
> + { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
> + 0xe4, 16, 0, },
> + { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
> + 0xe4, 17, 0, },
> +
> + { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
> + 0xe4, 13, 0, },
> + { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
> + 0xe4, 14, 0, },
> +
> + { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
> + 0xc0, 1, 0, },
> + { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
> + 0xc4, 1, 0, },
> + { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
> + 0xc4, 9, 0, },
> + { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
> + 0xc4, 17, 0, },
> + { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
> + 0xc8, 1, 0, },
> +
> + { HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, },
> +
> + { HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, },
> + { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
> + 0x38, 1, 0, },
> +
> + { HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, },
> + { HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0,
> + 0xb8, 1, 0, },
> + { HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0,
> + 0xb8, 2, 0, },
> + { HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0,
> + 0xb8, 3, 0, },
> + { HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0,
> + 0xb8, 4, 0, },
> + { HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, },
> + { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
> +};
> +
> +static struct hisi_clock_data *hi3516cv300_clk_register(
> + struct platform_device *pdev)
> +{
> + struct hisi_clock_data *clk_data;
> + int ret;
> +
> + clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
> + if (!clk_data)
> + return ERR_PTR(-ENOMEM);
> +
> + ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
> + ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
> + ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
> + if (ret)
> + goto unregister_fixed_rate;
> +
> + ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
> + ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
> + if (ret)
> + goto unregister_mux;
> +
> + ret = of_clk_add_provider(pdev->dev.of_node,
> + of_clk_src_onecell_get, &clk_data->clk_data);
> + if (ret)
> + goto unregister_gate;
> +
> + return clk_data;
> +
> +unregister_gate:
> + hisi_clk_unregister_gate(hi3516cv300_gate_clks,
> + ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
> +unregister_mux:
> + hisi_clk_unregister_mux(hi3516cv300_mux_clks,
> + ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
> +unregister_fixed_rate:
> + hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
> + ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
> + return ERR_PTR(ret);
> +}
> +
> +static void hi3516cv300_clk_unregister(struct platform_device *pdev)
> +{
> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
> +
> + of_clk_del_provider(pdev->dev.of_node);
> +
> + hisi_clk_unregister_gate(hi3516cv300_gate_clks,
> + ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
> + hisi_clk_unregister_mux(hi3516cv300_mux_clks,
> + ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
> + hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
> + ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
> +}
> +
> +static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
> + .register_clks = hi3516cv300_clk_register,
> + .unregister_clks = hi3516cv300_clk_unregister,
> +};
> +
> +/* hi3516CV300 sysctrl CRG */
> +#define HI3516CV300_SYSCTRL_NR_CLKS 16
> +
> +static const char *wdt_mux_p[] __initconst = { "3m", "apb" };
> +static u32 wdt_mux_table[] = {0, 1};
> +
> +static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
> + { HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p),
> + CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
> +};
> +
> +static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
> + struct platform_device *pdev)
> +{
> + struct hisi_clock_data *clk_data;
> + int ret;
> +
> + clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
> + if (!clk_data)
> + return ERR_PTR(-ENOMEM);
> +
> + ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
> + ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
> + if (ret)
> + return ERR_PTR(ret);
> +
> +
> + ret = of_clk_add_provider(pdev->dev.of_node,
> + of_clk_src_onecell_get, &clk_data->clk_data);
> + if (ret)
> + goto unregister_mux;
> +
> + return clk_data;
> +
> +unregister_mux:
> + hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
> + ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
> + return ERR_PTR(ret);
> +}
> +
> +static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
> +{
> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
> +
> + of_clk_del_provider(pdev->dev.of_node);
> +
> + hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
> + ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
> + crg->clk_data);
> +}
> +
> +static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
> + .register_clks = hi3516cv300_sysctrl_clk_register,
> + .unregister_clks = hi3516cv300_sysctrl_clk_unregister,
> +};
> +
> +static const struct of_device_id hi3516cv300_crg_match_table[] = {
> + {
> + .compatible = "hisilicon,hi3516cv300-crg",
> + .data = &hi3516cv300_crg_funcs
> + },
> + {
> + .compatible = "hisilicon,hi3516cv300-sysctrl",
> + .data = &hi3516cv300_sysctrl_funcs
> + },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
> +
> +static int hi3516cv300_crg_probe(struct platform_device *pdev)
> +{
> + struct hisi_crg_dev *crg;
> +
> + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
> + if (!crg)
> + return -ENOMEM;
> +
> + crg->funcs = of_device_get_match_data(&pdev->dev);
> + if (!crg->funcs)
> + return -ENOENT;
> +
> + crg->rstc = hisi_reset_init(pdev);
> + if (!crg->rstc)
> + return -ENOMEM;
> +
> + crg->clk_data = crg->funcs->register_clks(pdev);
> + if (IS_ERR(crg->clk_data)) {
> + hisi_reset_exit(crg->rstc);
> + return PTR_ERR(crg->clk_data);
> + }
> +
> + platform_set_drvdata(pdev, crg);
> + return 0;
> +}
> +
> +static int hi3516cv300_crg_remove(struct platform_device *pdev)
> +{
> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
> +
> + hisi_reset_exit(crg->rstc);
> + crg->funcs->unregister_clks(pdev);
> + return 0;
> +}
> +
> +static struct platform_driver hi3516cv300_crg_driver = {
> + .probe = hi3516cv300_crg_probe,
> + .remove = hi3516cv300_crg_remove,
> + .driver = {
> + .name = "hi3516cv300-crg",
> + .of_match_table = hi3516cv300_crg_match_table,
> + },
> +};
> +
> +static int __init hi3516cv300_crg_init(void)
> +{
> + return platform_driver_register(&hi3516cv300_crg_driver);
> +}
> +core_initcall(hi3516cv300_crg_init);
> +
> +static void __exit hi3516cv300_crg_exit(void)
> +{
> + platform_driver_unregister(&hi3516cv300_crg_driver);
> +}
> +module_exit(hi3516cv300_crg_exit);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");
> diff --git a/include/dt-bindings/clock/hi3516cv300-clock.h b/include/dt-bindings/clock/hi3516cv300-clock.h
> new file mode 100644
> index 0000000..5ba51b8
> --- /dev/null
> +++ b/include/dt-bindings/clock/hi3516cv300-clock.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef __DTS_HI3516CV300_CLOCK_H
> +#define __DTS_HI3516CV300_CLOCK_H
> +
> +/* hi3516CV300 core CRG */
> +#define HI3516CV300_APB_CLK 0
> +#define HI3516CV300_UART0_CLK 1
> +#define HI3516CV300_UART1_CLK 2
> +#define HI3516CV300_UART2_CLK 3
> +#define HI3516CV300_SPI0_CLK 4
> +#define HI3516CV300_SPI1_CLK 5
> +#define HI3516CV300_FMC_CLK 6
> +#define HI3516CV300_MMC0_CLK 7
> +#define HI3516CV300_MMC1_CLK 8
> +#define HI3516CV300_MMC2_CLK 9
> +#define HI3516CV300_MMC3_CLK 10
> +#define HI3516CV300_ETH_CLK 11
> +#define HI3516CV300_ETH_MACIF_CLK 12
> +#define HI3516CV300_DMAC_CLK 13
> +#define HI3516CV300_PWM_CLK 14
> +#define HI3516CV300_USB2_BUS_CLK 15
> +#define HI3516CV300_USB2_OHCI48M_CLK 16
> +#define HI3516CV300_USB2_OHCI12M_CLK 17
> +#define HI3516CV300_USB2_OTG_UTMI_CLK 18
> +#define HI3516CV300_USB2_HST_PHY_CLK 19
> +#define HI3516CV300_USB2_UTMI0_CLK 20
> +#define HI3516CV300_USB2_PHY_CLK 21
> +
> +/* hi3516CV300 sysctrl CRG */
> +#define HI3516CV300_WDT_CLK 1
> +
> +#endif /* __DTS_HI3516CV300_CLOCK_H */
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
在 2016/10/29 19:36, Hao Zhang 写道:
> Hi, is there any mainline kernel or uboot for hisilicon hi3520dv200 or
> hi3520dv300? just want some base support to boot , anything close to
> mainline is ok :)
>
Sorry. I wasn't engaged in hi3520d project. I have no detailed information about it.
As far as I know, most of HiSilicon products include a written offer document. You
can check it out and apply for the source code following the instructions.
Regards,
Jiancheng
> 2016-10-29 14:13 GMT+08:00 Jiancheng Xue <[email protected]>:
>> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
>> Generator) module generates clock and reset signals used
>> by other module blocks on SoC.
>>
>> Signed-off-by: Pan Wen <[email protected]>
>> ---
>> drivers/clk/hisilicon/Kconfig | 8 +
>> drivers/clk/hisilicon/Makefile | 1 +
>> drivers/clk/hisilicon/crg-hi3516cv300.c | 330 ++++++++++++++++++++++++++
>> include/dt-bindings/clock/hi3516cv300-clock.h | 48 ++++
>> 4 files changed, 387 insertions(+)
>> create mode 100644 drivers/clk/hisilicon/crg-hi3516cv300.c
>> create mode 100644 include/dt-bindings/clock/hi3516cv300-clock.h
>>
>> diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
>> index c41b6d2..f80773b 100644
>> --- a/drivers/clk/hisilicon/Kconfig
>> +++ b/drivers/clk/hisilicon/Kconfig
>> @@ -1,3 +1,11 @@
>> +config COMMON_CLK_HI3516CV300
>> + tristate "HI3516CV300 Clock Driver"
>> + depends on ARCH_HISI || COMPILE_TEST
>> + select RESET_HISI
>> + default ARCH_HISI
>> + help
>> + Build the clock driver for hi3516cv300.
>> +
>> config COMMON_CLK_HI3519
>> tristate "Hi3519 Clock Driver"
>> depends on ARCH_HISI || COMPILE_TEST
>> diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
>> index 5819891..4eec5e5 100644
>> --- a/drivers/clk/hisilicon/Makefile
>> +++ b/drivers/clk/hisilicon/Makefile
>> @@ -7,6 +7,7 @@ obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
>> obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
>> obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
>> obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
>> +obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
>> obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
>> obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
>> obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
>> diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c
>> new file mode 100644
>> index 0000000..2007123
>> --- /dev/null
>> +++ b/drivers/clk/hisilicon/crg-hi3516cv300.c
>> @@ -0,0 +1,330 @@
>> +/*
>> + * Hi3516CV300 Clock and Reset Generator Driver
>> + *
>> + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <dt-bindings/clock/hi3516cv300-clock.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include "clk.h"
>> +#include "crg.h"
>> +#include "reset.h"
>> +
>> +/* hi3516CV300 core CRG */
>> +#define HI3516CV300_INNER_CLK_OFFSET 64
>> +#define HI3516CV300_FIXED_3M 65
>> +#define HI3516CV300_FIXED_6M 66
>> +#define HI3516CV300_FIXED_24M 67
>> +#define HI3516CV300_FIXED_49P5 68
>> +#define HI3516CV300_FIXED_50M 69
>> +#define HI3516CV300_FIXED_83P3M 70
>> +#define HI3516CV300_FIXED_99M 71
>> +#define HI3516CV300_FIXED_100M 72
>> +#define HI3516CV300_FIXED_148P5M 73
>> +#define HI3516CV300_FIXED_198M 74
>> +#define HI3516CV300_FIXED_297M 75
>> +#define HI3516CV300_UART_MUX 76
>> +#define HI3516CV300_FMC_MUX 77
>> +#define HI3516CV300_MMC0_MUX 78
>> +#define HI3516CV300_MMC1_MUX 79
>> +#define HI3516CV300_MMC2_MUX 80
>> +#define HI3516CV300_MMC3_MUX 81
>> +#define HI3516CV300_PWM_MUX 82
>> +#define HI3516CV300_CRG_NR_CLKS 128
>> +
>> +static const struct hisi_fixed_rate_clock hi3516cv300_fixed_rate_clks[] = {
>> + { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
>> + { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
>> + { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
>> + { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
>> + { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
>> + { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
>> + { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
>> + { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
>> + { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
>> + { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
>> + { HI3516CV300_FIXED_297M, "297m", NULL, 0, 297000000, },
>> + { HI3516CV300_APB_CLK, "apb", NULL, 0, 50000000, },
>> +};
>> +
>> +static const char *const uart_mux_p[] = {"24m", "6m"};
>> +static const char *const fmc_mux_p[] = {
>> + "24m", "83.3m", "148.5m", "198m", "297m"
>> +};
>> +static const char *const mmc_mux_p[] = {"49.5m"};
>> +static const char *const mmc2_mux_p[] = {"99m", "49.5m"};
>> +static const char *const pwm_mux_p[] = {"3m", "50m", "24m", "24m"};
>> +
>> +static u32 uart_mux_table[] = {0, 1};
>> +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4};
>> +static u32 mmc_mux_table[] = {0};
>> +static u32 mmc2_mux_table[] = {0, 2};
>> +static u32 pwm_mux_table[] = {0, 1, 2, 3};
>> +
>> +static const struct hisi_mux_clock hi3516cv300_mux_clks[] = {
>> + { HI3516CV300_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
>> + CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
>> + { HI3516CV300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
>> + CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
>> + { HI3516CV300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
>> + CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
>> + { HI3516CV300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
>> + CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
>> + { HI3516CV300_MMC2_MUX, "mmc2_mux", mmc2_mux_p, ARRAY_SIZE(mmc2_mux_p),
>> + CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
>> + { HI3516CV300_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
>> + CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
>> + { HI3516CV300_PWM_MUX, "pwm_mux", pwm_mux_p, ARRAY_SIZE(pwm_mux_p),
>> + CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
>> +};
>> +
>> +static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
>> +
>> + { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
>> + 0xe4, 15, 0, },
>> + { HI3516CV300_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
>> + 0xe4, 16, 0, },
>> + { HI3516CV300_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
>> + 0xe4, 17, 0, },
>> +
>> + { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
>> + 0xe4, 13, 0, },
>> + { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
>> + 0xe4, 14, 0, },
>> +
>> + { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
>> + 0xc0, 1, 0, },
>> + { HI3516CV300_MMC0_CLK, "clk_mmc0", "mmc0_mux", CLK_SET_RATE_PARENT,
>> + 0xc4, 1, 0, },
>> + { HI3516CV300_MMC1_CLK, "clk_mmc1", "mmc1_mux", CLK_SET_RATE_PARENT,
>> + 0xc4, 9, 0, },
>> + { HI3516CV300_MMC2_CLK, "clk_mmc2", "mmc2_mux", CLK_SET_RATE_PARENT,
>> + 0xc4, 17, 0, },
>> + { HI3516CV300_MMC3_CLK, "clk_mmc3", "mmc3_mux", CLK_SET_RATE_PARENT,
>> + 0xc8, 1, 0, },
>> +
>> + { HI3516CV300_ETH_CLK, "clk_eth", NULL, 0, 0xec, 1, 0, },
>> +
>> + { HI3516CV300_DMAC_CLK, "clk_dmac", NULL, 0, 0xd8, 5, 0, },
>> + { HI3516CV300_PWM_CLK, "clk_pwm", "pwm_mux", CLK_SET_RATE_PARENT,
>> + 0x38, 1, 0, },
>> +
>> + { HI3516CV300_USB2_BUS_CLK, "clk_usb2_bus", NULL, 0, 0xb8, 0, 0, },
>> + { HI3516CV300_USB2_OHCI48M_CLK, "clk_usb2_ohci48m", NULL, 0,
>> + 0xb8, 1, 0, },
>> + { HI3516CV300_USB2_OHCI12M_CLK, "clk_usb2_ohci12m", NULL, 0,
>> + 0xb8, 2, 0, },
>> + { HI3516CV300_USB2_OTG_UTMI_CLK, "clk_usb2_otg_utmi", NULL, 0,
>> + 0xb8, 3, 0, },
>> + { HI3516CV300_USB2_HST_PHY_CLK, "clk_usb2_hst_phy", NULL, 0,
>> + 0xb8, 4, 0, },
>> + { HI3516CV300_USB2_UTMI0_CLK, "clk_usb2_utmi0", NULL, 0, 0xb8, 5, 0, },
>> + { HI3516CV300_USB2_PHY_CLK, "clk_usb2_phy", NULL, 0, 0xb8, 7, 0, },
>> +};
>> +
>> +static struct hisi_clock_data *hi3516cv300_clk_register(
>> + struct platform_device *pdev)
>> +{
>> + struct hisi_clock_data *clk_data;
>> + int ret;
>> +
>> + clk_data = hisi_clk_alloc(pdev, HI3516CV300_CRG_NR_CLKS);
>> + if (!clk_data)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks,
>> + ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
>> + if (ret)
>> + return ERR_PTR(ret);
>> +
>> + ret = hisi_clk_register_mux(hi3516cv300_mux_clks,
>> + ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
>> + if (ret)
>> + goto unregister_fixed_rate;
>> +
>> + ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
>> + ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
>> + if (ret)
>> + goto unregister_mux;
>> +
>> + ret = of_clk_add_provider(pdev->dev.of_node,
>> + of_clk_src_onecell_get, &clk_data->clk_data);
>> + if (ret)
>> + goto unregister_gate;
>> +
>> + return clk_data;
>> +
>> +unregister_gate:
>> + hisi_clk_unregister_gate(hi3516cv300_gate_clks,
>> + ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
>> +unregister_mux:
>> + hisi_clk_unregister_mux(hi3516cv300_mux_clks,
>> + ARRAY_SIZE(hi3516cv300_mux_clks), clk_data);
>> +unregister_fixed_rate:
>> + hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
>> + ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data);
>> + return ERR_PTR(ret);
>> +}
>> +
>> +static void hi3516cv300_clk_unregister(struct platform_device *pdev)
>> +{
>> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
>> +
>> + of_clk_del_provider(pdev->dev.of_node);
>> +
>> + hisi_clk_unregister_gate(hi3516cv300_gate_clks,
>> + ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);
>> + hisi_clk_unregister_mux(hi3516cv300_mux_clks,
>> + ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data);
>> + hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks,
>> + ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data);
>> +}
>> +
>> +static const struct hisi_crg_funcs hi3516cv300_crg_funcs = {
>> + .register_clks = hi3516cv300_clk_register,
>> + .unregister_clks = hi3516cv300_clk_unregister,
>> +};
>> +
>> +/* hi3516CV300 sysctrl CRG */
>> +#define HI3516CV300_SYSCTRL_NR_CLKS 16
>> +
>> +static const char *wdt_mux_p[] __initconst = { "3m", "apb" };
>> +static u32 wdt_mux_table[] = {0, 1};
>> +
>> +static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = {
>> + { HI3516CV300_WDT_CLK, "wdt", wdt_mux_p, ARRAY_SIZE(wdt_mux_p),
>> + CLK_SET_RATE_PARENT, 0x0, 23, 1, 0, wdt_mux_table, },
>> +};
>> +
>> +static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register(
>> + struct platform_device *pdev)
>> +{
>> + struct hisi_clock_data *clk_data;
>> + int ret;
>> +
>> + clk_data = hisi_clk_alloc(pdev, HI3516CV300_SYSCTRL_NR_CLKS);
>> + if (!clk_data)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks,
>> + ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
>> + if (ret)
>> + return ERR_PTR(ret);
>> +
>> +
>> + ret = of_clk_add_provider(pdev->dev.of_node,
>> + of_clk_src_onecell_get, &clk_data->clk_data);
>> + if (ret)
>> + goto unregister_mux;
>> +
>> + return clk_data;
>> +
>> +unregister_mux:
>> + hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
>> + ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data);
>> + return ERR_PTR(ret);
>> +}
>> +
>> +static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev)
>> +{
>> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
>> +
>> + of_clk_del_provider(pdev->dev.of_node);
>> +
>> + hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks,
>> + ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks),
>> + crg->clk_data);
>> +}
>> +
>> +static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = {
>> + .register_clks = hi3516cv300_sysctrl_clk_register,
>> + .unregister_clks = hi3516cv300_sysctrl_clk_unregister,
>> +};
>> +
>> +static const struct of_device_id hi3516cv300_crg_match_table[] = {
>> + {
>> + .compatible = "hisilicon,hi3516cv300-crg",
>> + .data = &hi3516cv300_crg_funcs
>> + },
>> + {
>> + .compatible = "hisilicon,hi3516cv300-sysctrl",
>> + .data = &hi3516cv300_sysctrl_funcs
>> + },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, hi3516cv300_crg_match_table);
>> +
>> +static int hi3516cv300_crg_probe(struct platform_device *pdev)
>> +{
>> + struct hisi_crg_dev *crg;
>> +
>> + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
>> + if (!crg)
>> + return -ENOMEM;
>> +
>> + crg->funcs = of_device_get_match_data(&pdev->dev);
>> + if (!crg->funcs)
>> + return -ENOENT;
>> +
>> + crg->rstc = hisi_reset_init(pdev);
>> + if (!crg->rstc)
>> + return -ENOMEM;
>> +
>> + crg->clk_data = crg->funcs->register_clks(pdev);
>> + if (IS_ERR(crg->clk_data)) {
>> + hisi_reset_exit(crg->rstc);
>> + return PTR_ERR(crg->clk_data);
>> + }
>> +
>> + platform_set_drvdata(pdev, crg);
>> + return 0;
>> +}
>> +
>> +static int hi3516cv300_crg_remove(struct platform_device *pdev)
>> +{
>> + struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
>> +
>> + hisi_reset_exit(crg->rstc);
>> + crg->funcs->unregister_clks(pdev);
>> + return 0;
>> +}
>> +
>> +static struct platform_driver hi3516cv300_crg_driver = {
>> + .probe = hi3516cv300_crg_probe,
>> + .remove = hi3516cv300_crg_remove,
>> + .driver = {
>> + .name = "hi3516cv300-crg",
>> + .of_match_table = hi3516cv300_crg_match_table,
>> + },
>> +};
>> +
>> +static int __init hi3516cv300_crg_init(void)
>> +{
>> + return platform_driver_register(&hi3516cv300_crg_driver);
>> +}
>> +core_initcall(hi3516cv300_crg_init);
>> +
>> +static void __exit hi3516cv300_crg_exit(void)
>> +{
>> + platform_driver_unregister(&hi3516cv300_crg_driver);
>> +}
>> +module_exit(hi3516cv300_crg_exit);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DESCRIPTION("HiSilicon Hi3516CV300 CRG Driver");
>> diff --git a/include/dt-bindings/clock/hi3516cv300-clock.h b/include/dt-bindings/clock/hi3516cv300-clock.h
>> new file mode 100644
>> index 0000000..5ba51b8
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/hi3516cv300-clock.h
>> @@ -0,0 +1,48 @@
>> +/*
>> + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#ifndef __DTS_HI3516CV300_CLOCK_H
>> +#define __DTS_HI3516CV300_CLOCK_H
>> +
>> +/* hi3516CV300 core CRG */
>> +#define HI3516CV300_APB_CLK 0
>> +#define HI3516CV300_UART0_CLK 1
>> +#define HI3516CV300_UART1_CLK 2
>> +#define HI3516CV300_UART2_CLK 3
>> +#define HI3516CV300_SPI0_CLK 4
>> +#define HI3516CV300_SPI1_CLK 5
>> +#define HI3516CV300_FMC_CLK 6
>> +#define HI3516CV300_MMC0_CLK 7
>> +#define HI3516CV300_MMC1_CLK 8
>> +#define HI3516CV300_MMC2_CLK 9
>> +#define HI3516CV300_MMC3_CLK 10
>> +#define HI3516CV300_ETH_CLK 11
>> +#define HI3516CV300_ETH_MACIF_CLK 12
>> +#define HI3516CV300_DMAC_CLK 13
>> +#define HI3516CV300_PWM_CLK 14
>> +#define HI3516CV300_USB2_BUS_CLK 15
>> +#define HI3516CV300_USB2_OHCI48M_CLK 16
>> +#define HI3516CV300_USB2_OHCI12M_CLK 17
>> +#define HI3516CV300_USB2_OTG_UTMI_CLK 18
>> +#define HI3516CV300_USB2_HST_PHY_CLK 19
>> +#define HI3516CV300_USB2_UTMI0_CLK 20
>> +#define HI3516CV300_USB2_PHY_CLK 21
>> +
>> +/* hi3516CV300 sysctrl CRG */
>> +#define HI3516CV300_WDT_CLK 1
>> +
>> +#endif /* __DTS_HI3516CV300_CLOCK_H */
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to [email protected]
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> .
>
On 10/29, Jiancheng Xue wrote:
Should be a From: Pan Wen here?
> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
> Generator) module generates clock and reset signals used
> by other module blocks on SoC.
>
> Signed-off-by: Pan Wen <[email protected]>
And you should have signed it off? Care to resend or state that
this is incorrectly attributed to you instead of Pan Wen?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 10/29, Jiancheng Xue wrote:
> Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
> Generator) module generates clock and reset signals used
> by other module blocks on SoC.
>
> Signed-off-by: Jiancheng Xue <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
Applied to clk-hisi and merged into clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Stephen,
On 2016/11/12 8:04, Stephen Boyd wrote:
> On 10/29, Jiancheng Xue wrote:
>
> Should be a From: Pan Wen here?
>
>> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
>> Generator) module generates clock and reset signals used
>> by other module blocks on SoC.
>>
>> Signed-off-by: Pan Wen <[email protected]>
>
> And you should have signed it off? Care to resend or state that
> this is incorrectly attributed to you instead of Pan Wen?
>
Pan Wen is the main author of this patch. I just made some small modification
with agreement from him. Do I need to resend this patch if it's better to add my
signed-off?
Thanks,
Jiancheng
On 11/14, Jiancheng Xue wrote:
> Hi Stephen,
>
> On 2016/11/12 8:04, Stephen Boyd wrote:
> > On 10/29, Jiancheng Xue wrote:
> >
> > Should be a From: Pan Wen here?
> >
> >> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
> >> Generator) module generates clock and reset signals used
> >> by other module blocks on SoC.
> >>
> >> Signed-off-by: Pan Wen <[email protected]>
> >
> > And you should have signed it off? Care to resend or state that
> > this is incorrectly attributed to you instead of Pan Wen?
> >
>
> Pan Wen is the main author of this patch. I just made some small modification
> with agreement from him. Do I need to resend this patch if it's better to add my
> signed-off?
>
Sure I'll apply the resent one. But you should also make sure to
retain Pan Wen's authorship. I'll go do that when applying it.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 2016/11/15 4:03, Stephen Boyd wrote:
> On 11/14, Jiancheng Xue wrote:
>> Hi Stephen,
>>
>> On 2016/11/12 8:04, Stephen Boyd wrote:
>>> On 10/29, Jiancheng Xue wrote:
>>>
>>> Should be a From: Pan Wen here?
>>>
>>>> Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset
>>>> Generator) module generates clock and reset signals used
>>>> by other module blocks on SoC.
>>>>
>>>> Signed-off-by: Pan Wen <[email protected]>
>>>
>>> And you should have signed it off? Care to resend or state that
>>> this is incorrectly attributed to you instead of Pan Wen?
>>>
>>
>> Pan Wen is the main author of this patch. I just made some small modification
>> with agreement from him. Do I need to resend this patch if it's better to add my
>> signed-off?
>>
>
> Sure I'll apply the resent one. But you should also make sure to
> retain Pan Wen's authorship. I'll go do that when applying it.
>
OK. I have resent this patch. Please check it. Thank you, Stephen.
Regards,
Jiancheng