Hi All,
RZ/V2L is equipped with a Cortex-A55 (1.2 GHz) CPU and built-in AI
accelerator "DRP-AI" for vision, which is Renesas' original technology.
It also has a 16-bit DDR3L/DDR4 interface and a built-in 3D graphics
engine with Arm Mali-G31 and video codec (H.264).
The RZ/V2L is also package- and pin-compatible with the RZ/G2L. This
allows RZ/G2L users to easily upgrade to the RZ/V2L for additional AI
functions without needing to modify the system configuration, keeping
migration costs low.
Initial patches enables minimal peripherals on Renesas RZ/V2L SMARC EVK
and booted via initramfs/nfs. Below blocks are enabled on Renesas RZ/V2L
SMARC EVK:
- memory
- External input clock
- CPG
- Pin controller
- SCIF
- GbEthernet
- Audio Clock
Links for SoC and EVK:
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rzv2l-general-purpose-microprocessor-
equipped-renesas-original-ai-dedicated-accelerator-drp-ai-12ghz-dual
[*] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
rz-arm-based-high-end-32-64-bit-mpus/rtk9744l23s01000be-rzg2l-evaluation-board-kit
This patch series is dependent on [0] & [1]
[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
[email protected]/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/
patch/[email protected]/
Sorry for cross posting the patches to multiple subsystems, as these are
just the dt-binding patches included as part of initial bringup patches.
Changes for v2:
* Included ACK from Rob
* Fixed alignment issue
* Added place holder for GPU node
* Updated divider values for PLL2/3
Test Logs on Renesas RZ/V2L SMARC EVK:
/ # cat /proc/cpuinfo
processor : 0
BogoMIPS : 48.00
Features : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 1
BogoMIPS : 48.00
Features : fp asimd evtstrm crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
/ # cat /proc/meminfo
MemTotal: 1897380 kB
MemFree: 1811032 kB
MemAvailable: 1788712 kB
Buffers: 0 kB
Cached: 38408 kB
SwapCached: 0 kB
Active: 4 kB
Inactive: 32 kB
Active(anon): 4 kB
Inactive(anon): 32 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 38404 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 68 kB
Mapped: 1356 kB
Shmem: 0 kB
KReclaimable: 22940 kB
Slab: 33192 kB
SReclaimable: 22940 kB
SUnreclaim: 10252 kB
KernelStack: 1088 kB
PageTables: 28 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 948688 kB
Committed_AS: 664 kB
VmallocTotal: 133143461888 kB
VmallocUsed: 1396 kB
VmallocChunk: 0 kB
Percpu: 240 kB
AnonHugePages: 0 kB
ShmemHugePages: 0 kB
ShmemPmdMapped: 0 kB
FileHugePages: 0 kB
FilePmdMapped: 0 kB
CmaTotal: 131072 kB
CmaFree: 130304 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ #
/ #
/ #
/ # cat /proc/interrupts
CPU0 CPU1
11: 814 896 GICv3 27 Level arch_timer
13: 0 0 GICv3 412 Level 1004b800.serial:rx err
14: 6 0 GICv3 414 Level 1004b800.serial:rx full
15: 368 0 GICv3 415 Level 1004b800.serial:tx empty
16: 0 0 GICv3 413 Level 1004b800.serial:break
17: 11 0 GICv3 416 Level 1004b800.serial:rx ready
23: 0 0 GICv3 173 Edge error
24: 0 0 GICv3 157 Edge 11820000.dma-controller:0
25: 0 0 GICv3 158 Edge 11820000.dma-controller:1
26: 0 0 GICv3 159 Edge 11820000.dma-controller:2
27: 0 0 GICv3 160 Edge 11820000.dma-controller:3
28: 0 0 GICv3 161 Edge 11820000.dma-controller:4
29: 0 0 GICv3 162 Edge 11820000.dma-controller:5
30: 0 0 GICv3 163 Edge 11820000.dma-controller:6
31: 0 0 GICv3 164 Edge 11820000.dma-controller:7
32: 0 0 GICv3 165 Edge 11820000.dma-controller:8
33: 0 0 GICv3 166 Edge 11820000.dma-controller:9
34: 0 0 GICv3 167 Edge 11820000.dma-controller:10
35: 0 0 GICv3 168 Edge 11820000.dma-controller:11
36: 0 0 GICv3 169 Edge 11820000.dma-controller:12
37: 0 0 GICv3 170 Edge 11820000.dma-controller:13
38: 0 0 GICv3 171 Edge 11820000.dma-controller:14
39: 0 0 GICv3 172 Edge 11820000.dma-controller:15
IPI0: 251 253 Rescheduling interrupts
IPI1: 36 33 Function call interrupts
IPI2: 0 0 CPU stop interrupts
IPI3: 0 0 CPU stop (for crash dump) interrupts
IPI4: 0 0 Timer broadcast interrupts
IPI5: 0 0 IRQ work interrupts
IPI6: 0 0 CPU wake-up interrupts
Err: 0
/ #
/ #
/ #
/ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas SMARC EVK based on r9a07g054l2
family: RZ/V2L
soc_id: r9a07g054
revision: Rev 0
/ #
/ #
/ #
Cheers,
Prabhakar
Biju Das (12):
dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC
soc: renesas: Identify RZ/V2L SoC
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
dt-bindings: clock: renesas: Document RZ/V2L SoC
clk: renesas: Add support for RZ/V2L SoC
dt-bindings: pinctrl: renesas: Document RZ/V2L pinctrl
pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is
enabled
dt-bindings: dma: rz-dmac: Document RZ/V2L SoC
dt-bindings: net: renesas,etheravb: Document RZ/V2L SoC
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
arm64: dts: renesas: Add support for r9a07g044c1/r9a07g054l1-smarc.dts
.../bindings/clock/renesas,rzg2l-cpg.yaml | 14 +-
.../bindings/dma/renesas,rz-dmac.yaml | 3 +-
.../bindings/net/renesas,etheravb.yaml | 3 +-
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +-
.../bindings/power/renesas,rzg2l-sysc.yaml | 7 +-
arch/arm64/boot/dts/renesas/Makefile | 3 +
.../boot/dts/renesas/r9a07g044c1-smarc.dts | 99 ++++
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 ++++++++++++++++++
.../boot/dts/renesas/r9a07g054l1-smarc.dts | 25 +
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 +
.../boot/dts/renesas/r9a07g054l2-smarc.dts | 25 +
arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 +
.../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 2 +-
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 2 +-
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 2 +-
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g054-cpg.c | 184 +++++++
drivers/clk/renesas/rzg2l-cpg.c | 6 +
drivers/clk/renesas/rzg2l-cpg.h | 1 +
drivers/pinctrl/renesas/Kconfig | 1 +
drivers/soc/renesas/Kconfig | 5 +
drivers/soc/renesas/renesas-soc.c | 13 +
include/dt-bindings/clock/r9a07g054-cpg.h | 226 ++++++++
24 files changed, 1154 insertions(+), 19 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
create mode 100644 drivers/clk/renesas/r9a07g054-cpg.c
create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h
--
2.17.1
From: Biju Das <[email protected]>
Add DT binding documentation for SYSC controller found on RZ/V2L SoC.
SYSC controller found on the RZ/V2L SoC is almost identical to one found
on the RZ/G2L SoC's only difference being that the RZ/V2L has an
additional register to control the DRP-AI.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v1->v2
* Included ACK from ROB
---
.../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
index 84ddc772b003..bb433e75a0ee 100644
--- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
@@ -4,14 +4,14 @@
$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: Renesas RZ/G2L System Controller (SYSC)
+title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
maintainers:
- Geert Uytterhoeven <[email protected]>
description:
- The RZ/G2L System Controller (SYSC) performs system control of the LSI and
- supports following functions,
+ The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
+ and supports following functions,
- External terminal state capture function
- 34-bit address space access function
- Low power consumption control
@@ -21,6 +21,7 @@ properties:
compatible:
enum:
- renesas,r9a07g044-sysc # RZ/G2{L,LC}
+ - renesas,r9a07g054-sysc # RZ/V2L
reg:
maxItems: 1
--
2.17.1
From: Biju Das <[email protected]>
Add support for identifying the RZ/V2L (R9A07G054) SoC.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1->v2
* None
---
drivers/soc/renesas/Kconfig | 5 +++++
drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++
2 files changed, 18 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index ce16ef5c939c..15ace18968f6 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -289,6 +289,11 @@ config ARCH_R9A07G044
help
This enables support for the Renesas RZ/G2L SoC variants.
+config ARCH_R9A07G054
+ bool "ARM64 Platform support for RZ/V2L"
+ help
+ This enables support for the Renesas RZ/V2L SoC variants.
+
endif # ARM64
config RST_RCAR
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 3d7711d5178c..7eeb73768369 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -60,6 +60,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
.name = "RZ/G2L",
};
+static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
+ .name = "RZ/V2L",
+};
+
static const struct renesas_family fam_shmobile __initconst __maybe_unused = {
.name = "SH-Mobile",
.reg = 0xe600101c, /* CCCR (Common Chip Code Register) */
@@ -140,6 +144,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
.id = 0x841c447,
};
+static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
+ .family = &fam_rzv2l,
+ .id = 0x8447447,
+};
+
static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = {
.family = &fam_rcar_gen1,
};
@@ -322,6 +331,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#if defined(CONFIG_ARCH_R9A07G044)
{ .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
#endif
+#if defined(CONFIG_ARCH_R9A07G054)
+ { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l },
+#endif
#ifdef CONFIG_ARCH_SH73A0
{ .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 },
#endif
@@ -355,6 +367,7 @@ static const struct renesas_id id_prr __initconst = {
static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,bsid", .data = &id_bsid },
{ .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l },
+ { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,prr", .data = &id_prr },
{ /* sentinel */ }
};
--
2.17.1
From: Biju Das <[email protected]>
Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00,
Nov.2021).
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v1->v2
* Included ACK from ROB
---
include/dt-bindings/clock/r9a07g054-cpg.h | 226 ++++++++++++++++++++++
1 file changed, 226 insertions(+)
create mode 100644 include/dt-bindings/clock/r9a07g054-cpg.h
diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
new file mode 100644
index 000000000000..fa338a7827bd
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G054 CPG Core Clocks */
+#define R9A07G054_CLK_I 0
+#define R9A07G054_CLK_I2 1
+#define R9A07G054_CLK_G 2
+#define R9A07G054_CLK_S0 3
+#define R9A07G054_CLK_S1 4
+#define R9A07G054_CLK_SPI0 5
+#define R9A07G054_CLK_SPI1 6
+#define R9A07G054_CLK_SD0 7
+#define R9A07G054_CLK_SD1 8
+#define R9A07G054_CLK_M0 9
+#define R9A07G054_CLK_M1 10
+#define R9A07G054_CLK_M2 11
+#define R9A07G054_CLK_M3 12
+#define R9A07G054_CLK_M4 13
+#define R9A07G054_CLK_HP 14
+#define R9A07G054_CLK_TSU 15
+#define R9A07G054_CLK_ZT 16
+#define R9A07G054_CLK_P0 17
+#define R9A07G054_CLK_P1 18
+#define R9A07G054_CLK_P2 19
+#define R9A07G054_CLK_AT 20
+#define R9A07G054_OSCCLK 21
+#define R9A07G054_CLK_P0_DIV2 22
+
+/* R9A07G054 Module Clocks */
+#define R9A07G054_CA55_SCLK 0
+#define R9A07G054_CA55_PCLK 1
+#define R9A07G054_CA55_ATCLK 2
+#define R9A07G054_CA55_GICCLK 3
+#define R9A07G054_CA55_PERICLK 4
+#define R9A07G054_CA55_ACLK 5
+#define R9A07G054_CA55_TSCLK 6
+#define R9A07G054_GIC600_GICCLK 7
+#define R9A07G054_IA55_CLK 8
+#define R9A07G054_IA55_PCLK 9
+#define R9A07G054_MHU_PCLK 10
+#define R9A07G054_SYC_CNT_CLK 11
+#define R9A07G054_DMAC_ACLK 12
+#define R9A07G054_DMAC_PCLK 13
+#define R9A07G054_OSTM0_PCLK 14
+#define R9A07G054_OSTM1_PCLK 15
+#define R9A07G054_OSTM2_PCLK 16
+#define R9A07G054_MTU_X_MCK_MTU3 17
+#define R9A07G054_POE3_CLKM_POE 18
+#define R9A07G054_GPT_PCLK 19
+#define R9A07G054_POEG_A_CLKP 20
+#define R9A07G054_POEG_B_CLKP 21
+#define R9A07G054_POEG_C_CLKP 22
+#define R9A07G054_POEG_D_CLKP 23
+#define R9A07G054_WDT0_PCLK 24
+#define R9A07G054_WDT0_CLK 25
+#define R9A07G054_WDT1_PCLK 26
+#define R9A07G054_WDT1_CLK 27
+#define R9A07G054_WDT2_PCLK 28
+#define R9A07G054_WDT2_CLK 29
+#define R9A07G054_SPI_CLK2 30
+#define R9A07G054_SPI_CLK 31
+#define R9A07G054_SDHI0_IMCLK 32
+#define R9A07G054_SDHI0_IMCLK2 33
+#define R9A07G054_SDHI0_CLK_HS 34
+#define R9A07G054_SDHI0_ACLK 35
+#define R9A07G054_SDHI1_IMCLK 36
+#define R9A07G054_SDHI1_IMCLK2 37
+#define R9A07G054_SDHI1_CLK_HS 38
+#define R9A07G054_SDHI1_ACLK 39
+#define R9A07G054_GPU_CLK 40
+#define R9A07G054_GPU_AXI_CLK 41
+#define R9A07G054_GPU_ACE_CLK 42
+#define R9A07G054_ISU_ACLK 43
+#define R9A07G054_ISU_PCLK 44
+#define R9A07G054_H264_CLK_A 45
+#define R9A07G054_H264_CLK_P 46
+#define R9A07G054_CRU_SYSCLK 47
+#define R9A07G054_CRU_VCLK 48
+#define R9A07G054_CRU_PCLK 49
+#define R9A07G054_CRU_ACLK 50
+#define R9A07G054_MIPI_DSI_PLLCLK 51
+#define R9A07G054_MIPI_DSI_SYSCLK 52
+#define R9A07G054_MIPI_DSI_ACLK 53
+#define R9A07G054_MIPI_DSI_PCLK 54
+#define R9A07G054_MIPI_DSI_VCLK 55
+#define R9A07G054_MIPI_DSI_LPCLK 56
+#define R9A07G054_LCDC_CLK_A 57
+#define R9A07G054_LCDC_CLK_P 58
+#define R9A07G054_LCDC_CLK_D 59
+#define R9A07G054_SSI0_PCLK2 60
+#define R9A07G054_SSI0_PCLK_SFR 61
+#define R9A07G054_SSI1_PCLK2 62
+#define R9A07G054_SSI1_PCLK_SFR 63
+#define R9A07G054_SSI2_PCLK2 64
+#define R9A07G054_SSI2_PCLK_SFR 65
+#define R9A07G054_SSI3_PCLK2 66
+#define R9A07G054_SSI3_PCLK_SFR 67
+#define R9A07G054_SRC_CLKP 68
+#define R9A07G054_USB_U2H0_HCLK 69
+#define R9A07G054_USB_U2H1_HCLK 70
+#define R9A07G054_USB_U2P_EXR_CPUCLK 71
+#define R9A07G054_USB_PCLK 72
+#define R9A07G054_ETH0_CLK_AXI 73
+#define R9A07G054_ETH0_CLK_CHI 74
+#define R9A07G054_ETH1_CLK_AXI 75
+#define R9A07G054_ETH1_CLK_CHI 76
+#define R9A07G054_I2C0_PCLK 77
+#define R9A07G054_I2C1_PCLK 78
+#define R9A07G054_I2C2_PCLK 79
+#define R9A07G054_I2C3_PCLK 80
+#define R9A07G054_SCIF0_CLK_PCK 81
+#define R9A07G054_SCIF1_CLK_PCK 82
+#define R9A07G054_SCIF2_CLK_PCK 83
+#define R9A07G054_SCIF3_CLK_PCK 84
+#define R9A07G054_SCIF4_CLK_PCK 85
+#define R9A07G054_SCI0_CLKP 86
+#define R9A07G054_SCI1_CLKP 87
+#define R9A07G054_IRDA_CLKP 88
+#define R9A07G054_RSPI0_CLKB 89
+#define R9A07G054_RSPI1_CLKB 90
+#define R9A07G054_RSPI2_CLKB 91
+#define R9A07G054_CANFD_PCLK 92
+#define R9A07G054_GPIO_HCLK 93
+#define R9A07G054_ADC_ADCLK 94
+#define R9A07G054_ADC_PCLK 95
+#define R9A07G054_TSU_PCLK 96
+#define R9A07G054_STPAI_INITCLK 97
+#define R9A07G054_STPAI_ACLK 98
+#define R9A07G054_STPAI_MCLK 99
+#define R9A07G054_STPAI_DCLKIN 100
+#define R9A07G054_STPAI_ACLK_DRP 101
+
+/* R9A07G054 Resets */
+#define R9A07G054_CA55_RST_1_0 0
+#define R9A07G054_CA55_RST_1_1 1
+#define R9A07G054_CA55_RST_3_0 2
+#define R9A07G054_CA55_RST_3_1 3
+#define R9A07G054_CA55_RST_4 4
+#define R9A07G054_CA55_RST_5 5
+#define R9A07G054_CA55_RST_6 6
+#define R9A07G054_CA55_RST_7 7
+#define R9A07G054_CA55_RST_8 8
+#define R9A07G054_CA55_RST_9 9
+#define R9A07G054_CA55_RST_10 10
+#define R9A07G054_CA55_RST_11 11
+#define R9A07G054_CA55_RST_12 12
+#define R9A07G054_GIC600_GICRESET_N 13
+#define R9A07G054_GIC600_DBG_GICRESET_N 14
+#define R9A07G054_IA55_RESETN 15
+#define R9A07G054_MHU_RESETN 16
+#define R9A07G054_DMAC_ARESETN 17
+#define R9A07G054_DMAC_RST_ASYNC 18
+#define R9A07G054_SYC_RESETN 19
+#define R9A07G054_OSTM0_PRESETZ 20
+#define R9A07G054_OSTM1_PRESETZ 21
+#define R9A07G054_OSTM2_PRESETZ 22
+#define R9A07G054_MTU_X_PRESET_MTU3 23
+#define R9A07G054_POE3_RST_M_REG 24
+#define R9A07G054_GPT_RST_C 25
+#define R9A07G054_POEG_A_RST 26
+#define R9A07G054_POEG_B_RST 27
+#define R9A07G054_POEG_C_RST 28
+#define R9A07G054_POEG_D_RST 29
+#define R9A07G054_WDT0_PRESETN 30
+#define R9A07G054_WDT1_PRESETN 31
+#define R9A07G054_WDT2_PRESETN 32
+#define R9A07G054_SPI_RST 33
+#define R9A07G054_SDHI0_IXRST 34
+#define R9A07G054_SDHI1_IXRST 35
+#define R9A07G054_GPU_RESETN 36
+#define R9A07G054_GPU_AXI_RESETN 37
+#define R9A07G054_GPU_ACE_RESETN 38
+#define R9A07G054_ISU_ARESETN 39
+#define R9A07G054_ISU_PRESETN 40
+#define R9A07G054_H264_X_RESET_VCP 41
+#define R9A07G054_H264_CP_PRESET_P 42
+#define R9A07G054_CRU_CMN_RSTB 43
+#define R9A07G054_CRU_PRESETN 44
+#define R9A07G054_CRU_ARESETN 45
+#define R9A07G054_MIPI_DSI_CMN_RSTB 46
+#define R9A07G054_MIPI_DSI_ARESET_N 47
+#define R9A07G054_MIPI_DSI_PRESET_N 48
+#define R9A07G054_LCDC_RESET_N 49
+#define R9A07G054_SSI0_RST_M2_REG 50
+#define R9A07G054_SSI1_RST_M2_REG 51
+#define R9A07G054_SSI2_RST_M2_REG 52
+#define R9A07G054_SSI3_RST_M2_REG 53
+#define R9A07G054_SRC_RST 54
+#define R9A07G054_USB_U2H0_HRESETN 55
+#define R9A07G054_USB_U2H1_HRESETN 56
+#define R9A07G054_USB_U2P_EXL_SYSRST 57
+#define R9A07G054_USB_PRESETN 58
+#define R9A07G054_ETH0_RST_HW_N 59
+#define R9A07G054_ETH1_RST_HW_N 60
+#define R9A07G054_I2C0_MRST 61
+#define R9A07G054_I2C1_MRST 62
+#define R9A07G054_I2C2_MRST 63
+#define R9A07G054_I2C3_MRST 64
+#define R9A07G054_SCIF0_RST_SYSTEM_N 65
+#define R9A07G054_SCIF1_RST_SYSTEM_N 66
+#define R9A07G054_SCIF2_RST_SYSTEM_N 67
+#define R9A07G054_SCIF3_RST_SYSTEM_N 68
+#define R9A07G054_SCIF4_RST_SYSTEM_N 69
+#define R9A07G054_SCI0_RST 70
+#define R9A07G054_SCI1_RST 71
+#define R9A07G054_IRDA_RST 72
+#define R9A07G054_RSPI0_RST 73
+#define R9A07G054_RSPI1_RST 74
+#define R9A07G054_RSPI2_RST 75
+#define R9A07G054_CANFD_RSTP_N 76
+#define R9A07G054_CANFD_RSTC_N 77
+#define R9A07G054_GPIO_RSTN 78
+#define R9A07G054_GPIO_PORT_RESETN 79
+#define R9A07G054_GPIO_SPARE_RESETN 80
+#define R9A07G054_ADC_PRESETN 81
+#define R9A07G054_ADC_ADRST_N 82
+#define R9A07G054_TSU_PRESETN 83
+#define R9A07G054_STPAI_ARESETN 84
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
--
2.17.1
From: Biju Das <[email protected]>
Document the device tree binding for the Renesas RZ/V2L SoC.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v1->v2
* Included ACK from ROB
---
.../bindings/clock/renesas,rzg2l-cpg.yaml | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 30b2e3d0d25d..bd3af8fc616b 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,13 +4,13 @@
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
maintainers:
- Geert Uytterhoeven <[email protected]>
description: |
- On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
+ On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.
They provide the following functionalities:
@@ -22,7 +22,9 @@ description: |
properties:
compatible:
- const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ enum:
+ - renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ - renesas,r9a07g054-cpg # RZ/V2L
reg:
maxItems: 1
@@ -40,9 +42,9 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
- <dt-bindings/clock/r9a07g044-cpg.h>
+ <dt-bindings/clock/r9a07g*-cpg.h>
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
- a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
+ a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 2
'#power-domain-cells':
@@ -56,7 +58,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
- the <dt-bindings/clock/r9a07g044-cpg.h>.
+ the <dt-bindings/clock/r9a07g0*-cpg.h>.
const: 1
required:
--
2.17.1
From: Biju Das <[email protected]>
The clock structure for RZ/V2L is almost identical to RZ/G2L SoC. The only
difference being RZ/V2L has an additional registers to control clock and
reset for the DRP-AI block.
This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/V2L SMARC EVK and binds it with the RZ/G2L CPG core
driver.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1->v2
* Updated divider values for PLL2/3
---
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g054-cpg.c | 184 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.c | 6 +
drivers/clk/renesas/rzg2l-cpg.h | 1 +
5 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r9a07g054-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 32e2783cad2f..8b3b87190c8f 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -33,6 +33,7 @@ config CLK_RENESAS
select CLK_R8A779A0 if ARCH_R8A779A0
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_R9A07G044 if ARCH_R9A07G044
+ select CLK_R9A07G054 if ARCH_R9A07G054
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@@ -158,6 +159,10 @@ config CLK_R9A07G044
bool "RZ/G2L clock support" if COMPILE_TEST
select CLK_RZG2L
+config CLK_R9A07G054
+ bool "RZ/V2L clock support" if COMPILE_TEST
+ select CLK_RZG2L
+
config CLK_SH73A0
bool "SH-Mobile AG5 clock support" if COMPILE_TEST
select CLK_RENESAS_CPG_MSTP
@@ -190,7 +195,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
This is a driver for R-Car USB2 clock selector
config CLK_RZG2L
- bool "Renesas RZ/G2L family clock support" if COMPILE_TEST
+ bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST
select RESET_CONTROLLER
# Generic
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 7270e8df29b3..c77556b1be0b 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
+obj-$(CONFIG_CLK_R9A07G054) += r9a07g054-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
# Family
diff --git a/drivers/clk/renesas/r9a07g054-cpg.c b/drivers/clk/renesas/r9a07g054-cpg.c
new file mode 100644
index 000000000000..03082dca7b85
--- /dev/null
+++ b/drivers/clk/renesas/r9a07g054-cpg.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/V2L CPG driver
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/r9a07g054-cpg.h>
+
+#include "rzg2l-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R9A07G054_CLK_P0_DIV2,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_OSC_DIV1000,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL2_DIV2,
+ CLK_PLL2_DIV16,
+ CLK_PLL3,
+ CLK_PLL3_DIV2,
+ CLK_PLL3_DIV2_4,
+ CLK_PLL3_DIV2_4_2,
+ CLK_PLL3_DIV4,
+ CLK_PLL5,
+ CLK_PLL5_FOUT3,
+ CLK_PLL5_250,
+ CLK_PLL6,
+ CLK_PLL6_250,
+ CLK_P1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE,
+};
+
+/* Divider tables */
+static const struct clk_div_table dtable_1_32[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {4, 32},
+ {0, 0},
+};
+
+/* Mux clock tables */
+static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
+
+static const struct cpg_core_clk r9a07g054_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_FIXED(".osc", R9A07G054_OSCCLK, CLK_EXTAL, 1, 1),
+ DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
+ DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
+ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
+
+ DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
+ DEF_FIXED(".pll5_fout3", CLK_PLL5_FOUT3, CLK_PLL5, 1, 6),
+
+ DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
+
+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
+ DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
+
+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
+ DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
+ DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
+
+ DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
+ DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
+
+ /* Core output clk */
+ DEF_FIXED("I", R9A07G054_CLK_I, CLK_PLL1, 1, 1),
+ DEF_DIV("P0", R9A07G054_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
+ dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("P0_DIV2", R9A07G054_CLK_P0_DIV2, R9A07G054_CLK_P0, 1, 2),
+ DEF_DIV("P1", R9A07G054_CLK_P1, CLK_PLL3_DIV2_4,
+ DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G054_CLK_P1, 1, 2),
+ DEF_DIV("P2", R9A07G054_CLK_P2, CLK_PLL3_DIV2_4_2,
+ DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("M0", R9A07G054_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
+ DEF_FIXED("ZT", R9A07G054_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
+ DEF_MUX("HP", R9A07G054_CLK_HP, SEL_PLL6_2,
+ sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK),
+};
+
+static struct rzg2l_mod_clk r9a07g054_mod_clks[] = {
+ DEF_MOD("gic", R9A07G054_GIC600_GICCLK, R9A07G054_CLK_P1,
+ 0x514, 0),
+ DEF_MOD("ia55_pclk", R9A07G054_IA55_PCLK, R9A07G054_CLK_P2,
+ 0x518, 0),
+ DEF_MOD("ia55_clk", R9A07G054_IA55_CLK, R9A07G054_CLK_P1,
+ 0x518, 1),
+ DEF_MOD("dmac_aclk", R9A07G054_DMAC_ACLK, R9A07G054_CLK_P1,
+ 0x52c, 0),
+ DEF_MOD("dmac_pclk", R9A07G054_DMAC_PCLK, CLK_P1_DIV2,
+ 0x52c, 1),
+ DEF_COUPLED("eth0_axi", R9A07G054_ETH0_CLK_AXI, R9A07G054_CLK_M0,
+ 0x57c, 0),
+ DEF_COUPLED("eth0_chi", R9A07G054_ETH0_CLK_CHI, R9A07G054_CLK_ZT,
+ 0x57c, 0),
+ DEF_COUPLED("eth1_axi", R9A07G054_ETH1_CLK_AXI, R9A07G054_CLK_M0,
+ 0x57c, 1),
+ DEF_COUPLED("eth1_chi", R9A07G054_ETH1_CLK_CHI, R9A07G054_CLK_ZT,
+ 0x57c, 1),
+ DEF_MOD("scif0", R9A07G054_SCIF0_CLK_PCK, R9A07G054_CLK_P0,
+ 0x584, 0),
+ DEF_MOD("scif1", R9A07G054_SCIF1_CLK_PCK, R9A07G054_CLK_P0,
+ 0x584, 1),
+ DEF_MOD("scif2", R9A07G054_SCIF2_CLK_PCK, R9A07G054_CLK_P0,
+ 0x584, 2),
+ DEF_MOD("scif3", R9A07G054_SCIF3_CLK_PCK, R9A07G054_CLK_P0,
+ 0x584, 3),
+ DEF_MOD("scif4", R9A07G054_SCIF4_CLK_PCK, R9A07G054_CLK_P0,
+ 0x584, 4),
+ DEF_MOD("sci0", R9A07G054_SCI0_CLKP, R9A07G054_CLK_P0,
+ 0x588, 0),
+ DEF_MOD("sci1", R9A07G054_SCI1_CLKP, R9A07G054_CLK_P0,
+ 0x588, 1),
+ DEF_MOD("gpio", R9A07G054_GPIO_HCLK, R9A07G054_OSCCLK,
+ 0x598, 0),
+};
+
+static struct rzg2l_reset r9a07g054_resets[] = {
+ DEF_RST(R9A07G054_GIC600_GICRESET_N, 0x814, 0),
+ DEF_RST(R9A07G054_GIC600_DBG_GICRESET_N, 0x814, 1),
+ DEF_RST(R9A07G054_IA55_RESETN, 0x818, 0),
+ DEF_RST(R9A07G054_DMAC_ARESETN, 0x82c, 0),
+ DEF_RST(R9A07G054_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G054_ETH0_RST_HW_N, 0x87c, 0),
+ DEF_RST(R9A07G054_ETH1_RST_HW_N, 0x87c, 1),
+ DEF_RST(R9A07G054_SCIF0_RST_SYSTEM_N, 0x884, 0),
+ DEF_RST(R9A07G054_SCIF1_RST_SYSTEM_N, 0x884, 1),
+ DEF_RST(R9A07G054_SCIF2_RST_SYSTEM_N, 0x884, 2),
+ DEF_RST(R9A07G054_SCIF3_RST_SYSTEM_N, 0x884, 3),
+ DEF_RST(R9A07G054_SCIF4_RST_SYSTEM_N, 0x884, 4),
+ DEF_RST(R9A07G054_SCI0_RST, 0x888, 0),
+ DEF_RST(R9A07G054_SCI1_RST, 0x888, 1),
+ DEF_RST(R9A07G054_GPIO_RSTN, 0x898, 0),
+ DEF_RST(R9A07G054_GPIO_PORT_RESETN, 0x898, 1),
+ DEF_RST(R9A07G054_GPIO_SPARE_RESETN, 0x898, 2),
+};
+
+static const unsigned int r9a07g054_crit_mod_clks[] __initconst = {
+ MOD_CLK_BASE + R9A07G054_GIC600_GICCLK,
+ MOD_CLK_BASE + R9A07G054_IA55_CLK,
+ MOD_CLK_BASE + R9A07G054_DMAC_ACLK,
+};
+
+const struct rzg2l_cpg_info r9a07g054_cpg_info = {
+ /* Core Clocks */
+ .core_clks = r9a07g054_core_clks,
+ .num_core_clks = ARRAY_SIZE(r9a07g054_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r9a07g054_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r9a07g054_crit_mod_clks),
+
+ /* Module Clocks */
+ .mod_clks = r9a07g054_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r9a07g054_mod_clks),
+ .num_hw_mod_clks = R9A07G054_TSU_PCLK + 1,
+
+ /* Resets */
+ .resets = r9a07g054_resets,
+ .num_resets = ARRAY_SIZE(r9a07g054_resets),
+};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index edd0abe34a37..486d0656c58a 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -952,6 +952,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
.compatible = "renesas,r9a07g044-cpg",
.data = &r9a07g044_cpg_info,
},
+#endif
+#ifdef CONFIG_CLK_R9A07G054
+ {
+ .compatible = "renesas,r9a07g054-cpg",
+ .data = &r9a07g054_cpg_info,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 5729d102034b..ce657beaf160 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -203,5 +203,6 @@ struct rzg2l_cpg_info {
};
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
+extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
#endif
--
2.17.1
From: Biju Das <[email protected]>
Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L is package- and
pin-compatible with the RZ/G2L. No driver changes are required as RZ/G2L
compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v1->v2
* Included ACK from ROB
---
.../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index ef68dabcf4dc..189a0800cd1d 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas RZ/G2L combined Pin and GPIO controller
+title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
maintainers:
- Geert Uytterhoeven <[email protected]>
- Lad Prabhakar <[email protected]>
description:
- The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
+ The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO
controller.
Pin multiplexing and GPIO configuration is performed on a per-pin basis.
Each port features up to 8 pins, each of them configurable for GPIO function
@@ -20,8 +20,15 @@ description:
properties:
compatible:
- enum:
- - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
+
+ - items:
+ - enum:
+ - renesas,r9a07g054-pinctrl # RZ/V2L
+ - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L
reg:
maxItems: 1
--
2.17.1
From: Biju Das <[email protected]>
Enable RZ/G2L pinctrl driver if RZ/V2L (R9A07G054) if
ARCH_R9A07G054 is enabled.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1->v2
* None
---
drivers/pinctrl/renesas/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 9a72999084b3..89f5ca76ab83 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -38,6 +38,7 @@ config PINCTRL_RENESAS
select PINCTRL_PFC_R8A77995 if ARCH_R8A77995
select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0
select PINCTRL_RZG2L if ARCH_R9A07G044
+ select PINCTRL_RZG2L if ARCH_R9A07G054
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269
--
2.17.1
From: Biju Das <[email protected]>
Document RZ/V2L DMAC bindings. RZ/V2L DMAC is identical to one found on
the RZ/G2L SoC. No driver changes are required as generic compatible
string "renesas,rz-dmac" will be used as a fallback.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v1->v2
* Included ACK from ROB
---
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index 7a4f415d74dc..e353377084aa 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas RZ/G2L DMA Controller
+title: Renesas RZ/{G2L,V2L} DMA Controller
maintainers:
- Biju Das <[email protected]>
@@ -17,6 +17,7 @@ properties:
items:
- enum:
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
+ - renesas,r9a07g054-dmac # RZ/V2L
- const: renesas,rz-dmac
reg:
--
2.17.1
From: Biju Das <[email protected]>
Document Gigabit Ethernet IP found on RZ/V2L SoC. Gigabit Ethernet
Interface is identical to one found on the RZ/G2L SoC. No driver changes
are required as generic compatible string "renesas,rzg2l-gbeth" will be
used as a fallback.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v1->v2
* Included ACK from ROB
---
Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
index bda821065a2b..db0ad6fbad89 100644
--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
@@ -46,7 +46,8 @@ properties:
- items:
- enum:
- renesas,r9a07g044-gbeth # RZ/G2{L,LC}
- - const: renesas,rzg2l-gbeth # RZ/G2L
+ - renesas,r9a07g054-gbeth # RZ/V2L
+ - const: renesas,rzg2l-gbeth # RZ/{G2L,V2L} family
reg: true
--
2.17.1
From: Biju Das <[email protected]>
The RZ/V2L is package- and pin-compatible with the RZ/G2L. The only
difference being the RZ/V2L SoC has additional DRP-AI IP (AI
accelerator).
Add initial DTSI for RZ/V2L SoC with below SoC specific dtsi files for
supporting single core and dual core devices.
r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts
r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts
Both RZ/G2L and RZ/V2L SMARC EVK SoM are identical apart from SoC's
used hence the common dtsi files (rzg2l-smarc*.dtsi) are share between
RZ/G2L and RZ/V2L SMARC EVK. Place holders are added in device nodes to
avoid compilation errors for the devices which have not been enabled yet
on RZ/V2L SoC.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1->v2
* None
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 +++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 +
arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 +
3 files changed, 529 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
new file mode 100644
index 000000000000..5de8f343f12a
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2L SoC
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g054-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g054";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ audio_clk1: audio_clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio_clk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ssi0: ssi@10049c00 {
+ reg = <0 0x10049c00 0 0x400>;
+ #sound-dai-cells = <0>;
+ /* place holder */
+ };
+
+ spi1: spi@1004b000 {
+ reg = <0 0x1004b000 0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a07g054",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ sci0: serial@1004d000 {
+ compatible = "renesas,r9a07g054-sci", "renesas,sci";
+ reg = <0 0x1004d000 0 0x400>;
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCI0_RST>;
+ status = "disabled";
+ };
+
+ sci1: serial@1004d400 {
+ compatible = "renesas,r9a07g054-sci", "renesas,sci";
+ reg = <0 0x1004d400 0 0x400>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_SCI1_RST>;
+ status = "disabled";
+ };
+
+ canfd: can@10050000 {
+ reg = <0 0x10050000 0 0x8000>;
+ /* place holder */
+ };
+
+ i2c0: i2c@10058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058000 0 0x400>;
+ /* place holder */
+ };
+
+ i2c1: i2c@10058400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058400 0 0x400>;
+ /* place holder */
+ };
+
+ i2c3: i2c@10058c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058c00 0 0x400>;
+ /* place holder */
+ };
+
+ adc: adc@10059000 {
+ reg = <0 0x10059000 0 0x400>;
+ /* place holder */
+ };
+
+ sbc: spi@10060000 {
+ reg = <0 0x10060000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>,
+ <0 0x10070000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g054-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g054-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ pinctrl: pin-controller@11030000 {
+ compatible = "renesas,r9a07g054-pinctrl",
+ "renesas,r9a07g044-pinctrl";
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 392>;
+ clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_GPIO_RSTN>,
+ <&cpg R9A07G054_GPIO_PORT_RESETN>,
+ <&cpg R9A07G054_GPIO_SPARE_RESETN>;
+ };
+
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a07g054-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G054_DMAC_ARESETN>,
+ <&cpg R9A07G054_DMAC_RST_ASYNC>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ gpu: gpu@11840000 {
+ reg = <0x0 0x11840000 0x0 0x10000>;
+ /* place holder */
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sdhi0: mmc@11c00000 {
+ reg = <0x0 0x11c00000 0 0x10000>;
+ /* place holder */
+ };
+
+ sdhi1: mmc@11c10000 {
+ reg = <0x0 0x11c10000 0 0x10000>;
+ /* place holder */
+ };
+
+ eth0: ethernet@11c20000 {
+ compatible = "renesas,r9a07g054-gbeth",
+ "renesas,rzg2l-gbeth";
+ reg = <0 0x11c20000 0 0x10000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
+ <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
+ <&cpg CPG_CORE R9A07G054_CLK_HP>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ eth1: ethernet@11c30000 {
+ compatible = "renesas,r9a07g054-gbeth",
+ "renesas,rzg2l-gbeth";
+ reg = <0 0x11c30000 0 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mux", "fil", "arp_ns";
+ phy-mode = "rgmii";
+ clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
+ <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
+ <&cpg CPG_CORE R9A07G054_CLK_HP>;
+ clock-names = "axi", "chi", "refclk";
+ resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ phyrst: usbphy-ctrl@11c40000 {
+ reg = <0 0x11c40000 0 0x10000>;
+ /* place holder */
+ };
+
+ ohci0: usb@11c50000 {
+ reg = <0 0x11c50000 0 0x100>;
+ /* place holder */
+ };
+
+ ohci1: usb@11c70000 {
+ reg = <0 0x11c70000 0 0x100>;
+ /* place holder */
+ };
+
+ ehci0: usb@11c50100 {
+ reg = <0 0x11c50100 0 0x100>;
+ /* place holder */
+ };
+
+ ehci1: usb@11c70100 {
+ reg = <0 0x11c70100 0 0x100>;
+ /* place holder */
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ reg = <0 0x11c50200 0 0x700>;
+ /* place holder */
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ reg = <0 0x11c70200 0 0x700>;
+ /* place holder */
+ };
+
+ hsusb: usb@11c60000 {
+ reg = <0 0x11c60000 0 0x10000>;
+ /* place holder */
+ };
+
+ wdt0: watchdog@12800800 {
+ reg = <0 0x12800800 0 0x400>;
+ /* place holder */
+ };
+
+ wdt1: watchdog@12800c00 {
+ reg = <0 0x12800C00 0 0x400>;
+ /* place holder */
+ };
+
+ wdt2: watchdog@12800400 {
+ reg = <0 0x12800400 0 0x400>;
+ /* place holder */
+ };
+
+ ostm0: timer@12801000 {
+ reg = <0x0 0x12801000 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm1: timer@12801400 {
+ reg = <0x0 0x12801400 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm2: timer@12801800 {
+ reg = <0x0 0x12801800 0x0 0x400>;
+ /* place holder */
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
new file mode 100644
index 000000000000..c448cc6634c1
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g054.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g054l1", "renesas,r9a07g054";
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ };
+
+ timer {
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
new file mode 100644
index 000000000000..4d5914bc95d3
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g054.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g054l2", "renesas,r9a07g054";
+};
--
2.17.1
From: Biju Das <[email protected]>
Add basic support for RZ/V2L SMARC EVK (based on R9A07G054L2):
- memory
- External input clock
- CPG
- Pin controller
- SCIF
- GbEthernet
- Audio Clock
It shares the same carrier board with RZ/G2L with the same pin mapping.
Delete the gpio-hog nodes from pinctrl as this will be added later when
the functionality has been tested.
Signed-off-by: Biju Das <[email protected]>
Signed-off-by: Lad Prabhakar <[email protected]>
---
v1->v2
* None
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../boot/dts/renesas/r9a07g054l2-smarc.dts | 25 +++++++++++++++++++
.../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 2 +-
.../boot/dts/renesas/rzg2l-smarc-som.dtsi | 2 +-
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 2 +-
5 files changed, 29 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8e696a38c560..2daba38d1161 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -77,3 +77,4 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
new file mode 100644
index 000000000000..39ef55bfe0c3
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g054l2.dtsi"
+#include "rzg2l-smarc-som.dtsi"
+#include "rzg2l-smarc-pinfunction.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g054l2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
+};
+
+&pinctrl {
+ /delete-node/ can0-stb;
+ /delete-node/ can1-stb;
+ /delete-node/ gpio-sd0-pwr-en-hog;
+ /delete-node/ sd0-dev-sel-hog;
+ /delete-node/ sd1-pwr-en-hog;
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index 71d83e447670..2ef217445f72 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2L SMARC pincontrol parts
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 9112e79079a1..aeacd22e9eb0 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2L SMARC SOM common parts
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index 46abb29718cc..78034f36156d 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2L SMARC EVK common parts
+ * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
--
2.17.1
From: Biju Das <[email protected]>
Signed-off-by: Biju Das <[email protected]>
---
v1->v2
* None
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a07g044c1-smarc.dts | 99 +++++++++++++++++++
.../boot/dts/renesas/r9a07g054l1-smarc.dts | 25 +++++
3 files changed, 126 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1-smarc.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 2daba38d1161..8de5561a3902 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -77,4 +77,6 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c1-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
+dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l1-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts
new file mode 100644
index 000000000000..43af14ef0103
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2LC SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044c1.dtsi"
+#include "rzg2lc-smarc-som.dtsi"
+#include "rzg2lc-smarc-pinfunction.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g044c2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
+
+};
+
+&canfd {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&ehci0 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&ehci1 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&hsusb {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&i2c0 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&i2c1 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&i2c3 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&ohci0 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&ohci1 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&phyrst {
+ status = "disabled";
+};
+
+&scif2 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&sdhi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-1;
+ /delete-property/ vmmc-supply;
+ status = "disabled";
+};
+
+&spi1 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&ssi0 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ /delete-property/ pinctrl-0;
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l1-smarc.dts
new file mode 100644
index 000000000000..2d9d397cef06
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g054l1-smarc.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g054l1.dtsi"
+#include "rzg2l-smarc-som.dtsi"
+#include "rzg2l-smarc-pinfunction.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g054l1";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g054l1", "renesas,r9a07g054";
+};
+
+&pinctrl {
+ /delete-node/ can0-stb;
+ /delete-node/ can1-stb;
+ /delete-node/ gpio-sd0-pwr-en-hog;
+ /delete-node/ sd0-dev-sel-hog;
+ /delete-node/ sd1-pwr-en-hog;
+};
--
2.17.1
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Add DT binding documentation for SYSC controller found on RZ/V2L SoC.
> SYSC controller found on the RZ/V2L SoC is almost identical to one found
> on the RZ/G2L SoC's only difference being that the RZ/V2L has an
> additional register to control the DRP-AI.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar, Biju,
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00,
> Nov.2021).
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Before I queue this in renesas-clk-for-v5.18, I'm wondering if you
want to add the DRP_M, DRP_D, and DRP_A core clocks, too?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Document the device tree binding for the Renesas RZ/V2L SoC.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-clk-for-v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Enable RZ/G2L pinctrl driver if RZ/V2L (R9A07G054) if
> ARCH_R9A07G054 is enabled.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-pinctrl-for-v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Document RZ/V2L DMAC bindings. RZ/V2L DMAC is identical to one found on
> the RZ/G2L SoC. No driver changes are required as generic compatible
> string "renesas,rz-dmac" will be used as a fallback.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Document Gigabit Ethernet IP found on RZ/V2L SoC. Gigabit Ethernet
> Interface is identical to one found on the RZ/G2L SoC. No driver changes
> are required as generic compatible string "renesas,rzg2l-gbeth" will be
> used as a fallback.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Add support for identifying the RZ/V2L (R9A07G054) SoC.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar, Biju,
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Signed-off-by: Biju Das <[email protected]>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -77,4 +77,6 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
>
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
> dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
> +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c1-smarc.dtb
Please preserve sort order, and add a blank line to separate
different SoCs.
> dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
> +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l1-smarc.dtb
Sort order.
Given this patch adds boards with two different SoCs, and the two
DTS files are quite dissimilar, I think this patch should be split in
two parts.
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts
> @@ -0,0 +1,99 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G2LC SMARC EVK board
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r9a07g044c1.dtsi"
> +#include "rzg2lc-smarc-som.dtsi"
> +#include "rzg2lc-smarc-pinfunction.dtsi"
> +#include "rzg2l-smarc.dtsi"
> +
> +/ {
> + model = "Renesas SMARC EVK based on r9a07g044c2";
> + compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
"renesas,r9a07g044c1"
> +
> +};
> +
> +&canfd {
> + /delete-property/ pinctrl-0;
> + status = "disabled";
> +};
Looks like the corresponding pinctrl-names properties should be
removed, too. Else "make dtbs_check" complains.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar, Biju,
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> The clock structure for RZ/V2L is almost identical to RZ/G2L SoC. The only
> difference being RZ/V2L has an additional registers to control clock and
> reset for the DRP-AI block.
>
> This patch adds minimal clock and reset entries required to boot the
> system on Renesas RZ/V2L SMARC EVK and binds it with the RZ/G2L CPG core
> driver.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/clk/renesas/r9a07g054-cpg.c
> +const struct rzg2l_cpg_info r9a07g054_cpg_info = {
> + /* Core Clocks */
> + .core_clks = r9a07g054_core_clks,
> + .num_core_clks = ARRAY_SIZE(r9a07g054_core_clks),
> + .last_dt_core_clk = LAST_DT_CORE_CLK,
> + .num_total_core_clks = MOD_CLK_BASE,
> +
> + /* Critical Module Clocks */
> + .crit_mod_clks = r9a07g054_crit_mod_clks,
> + .num_crit_mod_clks = ARRAY_SIZE(r9a07g054_crit_mod_clks),
> +
> + /* Module Clocks */
> + .mod_clks = r9a07g054_mod_clks,
> + .num_mod_clks = ARRAY_SIZE(r9a07g054_mod_clks),
> + .num_hw_mod_clks = R9A07G054_TSU_PCLK + 1,
R9A07G054_STPAI_ACLK_DRP
> +
> + /* Resets */
> + .resets = r9a07g054_resets,
> + .num_resets = ARRAY_SIZE(r9a07g054_resets),
> +};
Given RZ/V2L is RZ/G2L + DRP-AI, and the common clock IDs are the
same, what about reusing r9a07g044-cpg.c, and just adding a separate
r9a07g054_cpg_info?
When you add DRP-AI clocks and resets later, you just have to make
sure .num_{core_clks,mod_clks,resets} are correct, similar to how
drivers/pinctrl/renesas/pfc-r8a77951.c handles common and automotive
pin groups and functions.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Document Renesas RZ/V2L pinctrl bindings. The RZ/V2L is package- and
> pin-compatible with the RZ/G2L. No driver changes are required as RZ/G2L
> compatible string "renesas,r9a07g044-pinctrl" will be used as a fallback.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-pinctrl-for-v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> Add basic support for RZ/V2L SMARC EVK (based on R9A07G054L2):
> - memory
> - External input clock
> - CPG
> - Pin controller
> - SCIF
> - GbEthernet
> - Audio Clock
>
> It shares the same carrier board with RZ/G2L with the same pin mapping.
> Delete the gpio-hog nodes from pinctrl as this will be added later when
> the functionality has been tested.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Prabhakar, Biju,
On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
<[email protected]> wrote:
> From: Biju Das <[email protected]>
>
> The RZ/V2L is package- and pin-compatible with the RZ/G2L. The only
> difference being the RZ/V2L SoC has additional DRP-AI IP (AI
> accelerator).
>
> Add initial DTSI for RZ/V2L SoC with below SoC specific dtsi files for
> supporting single core and dual core devices.
>
> r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts
> r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts
>
> Both RZ/G2L and RZ/V2L SMARC EVK SoM are identical apart from SoC's
> used hence the common dtsi files (rzg2l-smarc*.dtsi) are share between
> RZ/G2L and RZ/V2L SMARC EVK. Place holders are added in device nodes to
> avoid compilation errors for the devices which have not been enabled yet
> on RZ/V2L SoC.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> + pinctrl: pin-controller@11030000 {
pinctrl@
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v5.18 with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Fri, Jan 21, 2022 at 2:45 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar, Biju,
>
> On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> <[email protected]> wrote:
> > From: Biju Das <[email protected]>
> >
> > Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module
> > clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also
> > add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> > ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev.1.00,
> > Nov.2021).
> >
> > Signed-off-by: Biju Das <[email protected]>
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Acked-by: Rob Herring <[email protected]>
>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
>
> Before I queue this in renesas-clk-for-v5.18, I'm wondering if you
> want to add the DRP_M, DRP_D, and DRP_A core clocks, too?
>
Good point lets get everything in one shot, I'll send a v2 including
the above core clocks.
Cheers,
Prabhakar
Hi Geert,
Ouch please ignore this patch.
Now I know where I missed the v2 combining "[PATCH 01/16] dt-bindings:
arm: renesas: Document Renesas RZ/V2L SoC" and "[PATCH 02/16]
dt-bindings: arm: renesas: Document SMARC EVK". I picked a wrong
commit-id vehicle sending a v2!
This patch is intended for internal build testing atm. We are yet to
test r9a07g044c1/r9a07g054l1 on actual HW.
Sorry about the inconvenience.
Cheers,
Prabhakar
On Fri, Jan 21, 2022 at 2:47 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar, Biju,
>
> On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> <[email protected]> wrote:
> > From: Biju Das <[email protected]>
> >
> > Signed-off-by: Biju Das <[email protected]>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/Makefile
> > +++ b/arch/arm64/boot/dts/renesas/Makefile
> > @@ -77,4 +77,6 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
> >
> > dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
> > dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
> > +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c1-smarc.dtb
>
> Please preserve sort order, and add a blank line to separate
> different SoCs.
>
> > dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
> > +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l1-smarc.dtb
>
> Sort order.
>
> Given this patch adds boards with two different SoCs, and the two
> DTS files are quite dissimilar, I think this patch should be split in
> two parts.
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044c1-smarc.dts
> > @@ -0,0 +1,99 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/G2LC SMARC EVK board
> > + *
> > + * Copyright (C) 2021 Renesas Electronics Corp.
> > + */
> > +
> > +/dts-v1/;
> > +#include "r9a07g044c1.dtsi"
> > +#include "rzg2lc-smarc-som.dtsi"
> > +#include "rzg2lc-smarc-pinfunction.dtsi"
> > +#include "rzg2l-smarc.dtsi"
> > +
> > +/ {
> > + model = "Renesas SMARC EVK based on r9a07g044c2";
> > + compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
>
> "renesas,r9a07g044c1"
>
> > +
> > +};
> > +
> > +&canfd {
> > + /delete-property/ pinctrl-0;
> > + status = "disabled";
> > +};
>
> Looks like the corresponding pinctrl-names properties should be
> removed, too. Else "make dtbs_check" complains.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Hi Geert,
Thank you for the review.
On Fri, Jan 21, 2022 at 2:45 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar, Biju,
>
> On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> <[email protected]> wrote:
> > From: Biju Das <[email protected]>
> >
> > The clock structure for RZ/V2L is almost identical to RZ/G2L SoC. The only
> > difference being RZ/V2L has an additional registers to control clock and
> > reset for the DRP-AI block.
> >
> > This patch adds minimal clock and reset entries required to boot the
> > system on Renesas RZ/V2L SMARC EVK and binds it with the RZ/G2L CPG core
> > driver.
> >
> > Signed-off-by: Biju Das <[email protected]>
> > Signed-off-by: Lad Prabhakar <[email protected]>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r9a07g054-cpg.c
>
> > +const struct rzg2l_cpg_info r9a07g054_cpg_info = {
> > + /* Core Clocks */
> > + .core_clks = r9a07g054_core_clks,
> > + .num_core_clks = ARRAY_SIZE(r9a07g054_core_clks),
> > + .last_dt_core_clk = LAST_DT_CORE_CLK,
> > + .num_total_core_clks = MOD_CLK_BASE,
> > +
> > + /* Critical Module Clocks */
> > + .crit_mod_clks = r9a07g054_crit_mod_clks,
> > + .num_crit_mod_clks = ARRAY_SIZE(r9a07g054_crit_mod_clks),
> > +
> > + /* Module Clocks */
> > + .mod_clks = r9a07g054_mod_clks,
> > + .num_mod_clks = ARRAY_SIZE(r9a07g054_mod_clks),
> > + .num_hw_mod_clks = R9A07G054_TSU_PCLK + 1,
>
> R9A07G054_STPAI_ACLK_DRP
>
Agreed.
> > +
> > + /* Resets */
> > + .resets = r9a07g054_resets,
> > + .num_resets = ARRAY_SIZE(r9a07g054_resets),
> > +};
>
> Given RZ/V2L is RZ/G2L + DRP-AI, and the common clock IDs are the
> same, what about reusing r9a07g044-cpg.c, and just adding a separate
> r9a07g054_cpg_info?
>
Agreed. To clarify for clock and reset entries for common we use the
macros defined for RZ/G2L and for DRP entries we use the RZ/V2L macros
(which will be an additional member) ?
> When you add DRP-AI clocks and resets later, you just have to make
> sure .num_{core_clks,mod_clks,resets} are correct, similar to how
> drivers/pinctrl/renesas/pfc-r8a77951.c handles common and automotive
> pin groups and functions.
>
Agreed.
Cheers,
Prabhakar
Hi Prabhakar,
On Fri, Jan 21, 2022 at 5:32 PM Lad, Prabhakar
<[email protected]> wrote:
> On Fri, Jan 21, 2022 at 2:45 PM Geert Uytterhoeven <[email protected]> wrote:
> > On Mon, Jan 10, 2022 at 2:47 PM Lad Prabhakar
> > <[email protected]> wrote:
> > > From: Biju Das <[email protected]>
> > >
> > > The clock structure for RZ/V2L is almost identical to RZ/G2L SoC. The only
> > > difference being RZ/V2L has an additional registers to control clock and
> > > reset for the DRP-AI block.
> > >
> > > This patch adds minimal clock and reset entries required to boot the
> > > system on Renesas RZ/V2L SMARC EVK and binds it with the RZ/G2L CPG core
> > > driver.
> > >
> > > Signed-off-by: Biju Das <[email protected]>
> > > Signed-off-by: Lad Prabhakar <[email protected]>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/drivers/clk/renesas/r9a07g054-cpg.c
> >
> > > +const struct rzg2l_cpg_info r9a07g054_cpg_info = {
> > > + /* Core Clocks */
> > > + .core_clks = r9a07g054_core_clks,
> > > + .num_core_clks = ARRAY_SIZE(r9a07g054_core_clks),
> > > + .last_dt_core_clk = LAST_DT_CORE_CLK,
> > > + .num_total_core_clks = MOD_CLK_BASE,
> > > +
> > > + /* Critical Module Clocks */
> > > + .crit_mod_clks = r9a07g054_crit_mod_clks,
> > > + .num_crit_mod_clks = ARRAY_SIZE(r9a07g054_crit_mod_clks),
> > > +
> > > + /* Module Clocks */
> > > + .mod_clks = r9a07g054_mod_clks,
> > > + .num_mod_clks = ARRAY_SIZE(r9a07g054_mod_clks),
> > > + .num_hw_mod_clks = R9A07G054_TSU_PCLK + 1,
> >
> > R9A07G054_STPAI_ACLK_DRP
> >
> Agreed.
>
> > > +
> > > + /* Resets */
> > > + .resets = r9a07g054_resets,
> > > + .num_resets = ARRAY_SIZE(r9a07g054_resets),
> > > +};
> >
> > Given RZ/V2L is RZ/G2L + DRP-AI, and the common clock IDs are the
> > same, what about reusing r9a07g044-cpg.c, and just adding a separate
> > r9a07g054_cpg_info?
> >
> Agreed. To clarify for clock and reset entries for common we use the
> macros defined for RZ/G2L and for DRP entries we use the RZ/V2L macros
> (which will be an additional member) ?
You can have a struct with two arrays:
static const struct {
static struct rzg2l_mod_clk common[...];
#ifdef CONFIG_CLK_R9A07G054
static struct rzg2l_mod_clk drp[...];
#endif
} r9a07g054_mod_clks[] = ...
See drivers/pinctrl/renesas/pfc-r8a77951.c.
> > When you add DRP-AI clocks and resets later, you just have to make
> > sure .num_{core_clks,mod_clks,resets} are correct, similar to how
> > drivers/pinctrl/renesas/pfc-r8a77951.c handles common and automotive
> > pin groups and functions.
> >
> Agreed.
E.g. ARRAY_SIZE(r9a07g054_mod_clks.common) vs.
ARRAY_SIZE(r9a07g054_mod_clks.common) + ARRAY_SIZE(r9a07g054_mod_clks.drp).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Jan 10, 2022 at 7:47 AM Lad Prabhakar
<[email protected]> wrote:
>
> From: Biju Das <[email protected]>
>
> The RZ/V2L is package- and pin-compatible with the RZ/G2L. The only
> difference being the RZ/V2L SoC has additional DRP-AI IP (AI
> accelerator).
>
> Add initial DTSI for RZ/V2L SoC with below SoC specific dtsi files for
> supporting single core and dual core devices.
>
> r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts
> r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts
>
> Both RZ/G2L and RZ/V2L SMARC EVK SoM are identical apart from SoC's
> used hence the common dtsi files (rzg2l-smarc*.dtsi) are share between
> RZ/G2L and RZ/V2L SMARC EVK. Place holders are added in device nodes to
> avoid compilation errors for the devices which have not been enabled yet
> on RZ/V2L SoC.
>
> Signed-off-by: Biju Das <[email protected]>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v1->v2
> * None
> ---
> arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 491 +++++++++++++++++++
> arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 25 +
> arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi | 13 +
> 3 files changed, 529 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi
> create mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> new file mode 100644
> index 000000000000..5de8f343f12a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> @@ -0,0 +1,491 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/V2L SoC
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r9a07g054-cpg.h>
linux-next is failing because this header is missing:
In file included from arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi:9,
from arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts:9:
arch/arm64/boot/dts/renesas/r9a07g054.dtsi:9:10: fatal error:
dt-bindings/clock/r9a07g054-cpg.h: No such file or directory
9 | #include <dt-bindings/clock/r9a07g054-cpg.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hi Rob,
On Tue, Jan 25, 2022 at 3:00 PM Rob Herring <[email protected]> wrote:
> On Mon, Jan 10, 2022 at 7:47 AM Lad Prabhakar
> <[email protected]> wrote:
> > From: Biju Das <[email protected]>
> >
> > The RZ/V2L is package- and pin-compatible with the RZ/G2L. The only
> > difference being the RZ/V2L SoC has additional DRP-AI IP (AI
> > accelerator).
> >
> > Add initial DTSI for RZ/V2L SoC with below SoC specific dtsi files for
> > supporting single core and dual core devices.
> >
> > r9a07g054l1.dtsi => RZ/V2L R9A07G054L1 SoC specific parts
> > r9a07g054l2.dtsi => RZ/V2L R9A07G054L2 SoC specific parts
> >
> > Both RZ/G2L and RZ/V2L SMARC EVK SoM are identical apart from SoC's
> > used hence the common dtsi files (rzg2l-smarc*.dtsi) are share between
> > RZ/G2L and RZ/V2L SMARC EVK. Place holders are added in device nodes to
> > avoid compilation errors for the devices which have not been enabled yet
> > on RZ/V2L SoC.
> >
> > Signed-off-by: Biju Das <[email protected]>
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
> > @@ -0,0 +1,491 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/V2L SoC
> > + *
> > + * Copyright (C) 2021 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/clock/r9a07g054-cpg.h>
>
> linux-next is failing because this header is missing:
>
> In file included from arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi:9,
> from arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts:9:
> arch/arm64/boot/dts/renesas/r9a07g054.dtsi:9:10: fatal error:
> dt-bindings/clock/r9a07g054-cpg.h: No such file or directory
> 9 | #include <dt-bindings/clock/r9a07g054-cpg.h>
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Thanks, I have already removed the offending commits from renesas-next.
as the header is not ready yet.
Interestingly, kernel test robot reported a success for that branch...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 10-01-22, 13:46, Lad Prabhakar wrote:
> From: Biju Das <[email protected]>
>
> Document RZ/V2L DMAC bindings. RZ/V2L DMAC is identical to one found on
> the RZ/G2L SoC. No driver changes are required as generic compatible
> string "renesas,rz-dmac" will be used as a fallback.
Applied, thanks
--
~Vinod