From: Lad Prabhakar <[email protected]>
Add DT binding documentation for System Controller (SYS) found on
RZ/V2H{P} ("R9A09G057") SoC's.
SYS block contains the SYS_LSI_DEVID register which can be used to
retrieve SoC version information.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Fabrizio Castro <[email protected]>
---
Note, the reset index in example node will be update once the CPG
support is upstreamed.
---
.../soc/renesas/renesas,r9a09g057-sys.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
new file mode 100644
index 000000000000..ba30d7734ee8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H{P} System Controller (SYS)
+
+maintainers:
+ - Geert Uytterhoeven <[email protected]>
+
+description:
+ The RZ/V2H{P} SYS (System Controller) controls the overall
+ configuration of the LSI and supports the following functions,
+ - Trust zone control
+ - Extend access by specific masters to address beyond 4GB space
+ - GBETH configuration
+ - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
+ - LSI version
+ - WDT stop control
+ - General registers
+
+properties:
+ compatible:
+ const: renesas,r9a09g057-sys
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Clock from external oscillator
+
+ resets:
+ items:
+ - description: SYS_0_PRESETN reset signal
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ sys: system-controller@10430000 {
+ compatible = "renesas,r9a09g057-sys";
+ reg = <0x10430000 0x10000>;
+ clocks = <&extal_clk>;
+ resets = <&cpg 1>;
+ };
--
2.34.1
On 19/02/2024 17:09, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> Add DT binding documentation for System Controller (SYS) found on
> RZ/V2H{P} ("R9A09G057") SoC's.
>
> SYS block contains the SYS_LSI_DEVID register which can be used to
> retrieve SoC version information.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Fabrizio Castro <[email protected]>
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
Drop the node, not relevant.
> +
> + sys: system-controller@10430000 {
> + compatible = "renesas,r9a09g057-sys";
> + reg = <0x10430000 0x10000>;
> + clocks = <&extal_clk>;
> + resets = <&cpg 1>;
> + };
Best regards,
Krzysztof
Hi Krzysztof,
Thank you for the review.
On Tue, Feb 20, 2024 at 9:51 AM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 19/02/2024 17:09, Prabhakar wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Add DT binding documentation for System Controller (SYS) found on
> > RZ/V2H{P} ("R9A09G057") SoC's.
> >
> > SYS block contains the SYS_LSI_DEVID register which can be used to
> > retrieve SoC version information.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Fabrizio Castro <[email protected]>
>
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + };
>
> Drop the node, not relevant.
>
OK, I'll drop the clock node in the next version.
Cheers,
Prabhakar
Hi Prabhakar,
Thanks for your patch!
On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> Add DT binding documentation for System Controller (SYS) found on
> RZ/V2H{P} ("R9A09G057") SoC's.
RZ/V2H(P)
>
> SYS block contains the SYS_LSI_DEVID register which can be used to
> retrieve SoC version information.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Fabrizio Castro <[email protected]>
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sysyaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H{P} System Controller (SYS)
> +
> +maintainers:
> + - Geert Uytterhoeven <[email protected]>
> +
> +description:
> + The RZ/V2H{P} SYS (System Controller) controls the overall
RZ/V2H(P)
> + configuration of the LSI and supports the following functions,
> + - Trust zone control
> + - Extend access by specific masters to address beyond 4GB space
> + - GBETH configuration
> + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
> + - LSI version
> + - WDT stop control
> + - General registers
> +
> +properties:
> + compatible:
> + const: renesas,r9a09g057-sys
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Clock from external oscillator
Isn't this SYS_0_PCLK inside the CPG?
> +
> + resets:
> + items:
> + - description: SYS_0_PRESETN reset signal
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> +
> + sys: system-controller@10430000 {
> + compatible = "renesas,r9a09g057-sys";
> + reg = <0x10430000 0x10000>;
> + clocks = <&extal_clk>;
clocks = <&cpg 1>;
(I guess it will be 1 ;-)
> + resets = <&cpg 1>;
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thank you for the review.
On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <prabhakar.csengg@gmailcom> wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Add DT binding documentation for System Controller (SYS) found on
> > RZ/V2H{P} ("R9A09G057") SoC's.
>
> RZ/V2H(P)
>
> >
> > SYS block contains the SYS_LSI_DEVID register which can be used to
> > retrieve SoC version information.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > Reviewed-by: Fabrizio Castro <[email protected]>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> > @@ -0,0 +1,59 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g057-sys.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/V2H{P} System Controller (SYS)
> > +
> > +maintainers:
> > + - Geert Uytterhoeven <[email protected]>
> > +
> > +description:
> > + The RZ/V2H{P} SYS (System Controller) controls the overall
>
> RZ/V2H(P)
>
OK.
> > + configuration of the LSI and supports the following functions,
> > + - Trust zone control
> > + - Extend access by specific masters to address beyond 4GB space
> > + - GBETH configuration
> > + - Control of settings and states of SRAM/PCIe/CM33/CA55/CR8/xSPI/ADC/TSU
> > + - LSI version
> > + - WDT stop control
> > + - General registers
> > +
> > +properties:
> > + compatible:
> > + const: renesas,r9a09g057-sys
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Clock from external oscillator
>
> Isn't this SYS_0_PCLK inside the CPG?
>
As per the block diagram (figure 4.4-3), if we follow the clock source
for SYS it traces back to 24MHz Oscillator. Let me know how you want
me to describe this please.
> > +
> > + resets:
> > + items:
> > + - description: SYS_0_PRESETN reset signal
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + };
> > +
> > + sys: system-controller@10430000 {
> > + compatible = "renesas,r9a09g057-sys";
> > + reg = <0x10430000 0x10000>;
> > + clocks = <&extal_clk>;
>
> clocks = <&cpg 1>;
>
> (I guess it will be 1 ;-)
>
Yep indeed ;)
Cheers,
Prabhakar
> > + resets = <&cpg 1>;
> > + };
>
> Gr{oetje,eeting}s,
>
> Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Hi Prabhakar,
On Mon, Feb 26, 2024 at 3:01 PM Lad, Prabhakar
<[email protected]> wrote:
> On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <[email protected]> wrote:
> > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <[email protected]> wrote:
> > > From: Lad Prabhakar <[email protected]>
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> > > + clocks:
> > > + items:
> > > + - description: Clock from external oscillator
> >
> > Isn't this SYS_0_PCLK inside the CPG?
> >
> As per the block diagram (figure 4.4-3), if we follow the clock source
> for SYS it traces back to 24MHz Oscillator. Let me know how you want
> me to describe this please.
Yes, that is the diagram I was looking at.
MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK.
MAIN OSC 24 MHz is a clock input to the CPG.
MAINCLK is a CPG internal core clock.
SYS_0_PCLK is a CPG clock output, serving as the SYS module clock.
I think the standard "maxItems: 1" would be fine, and no description
is needed.
> > > +
> > > + resets:
> > > + items:
> > > + - description: SYS_0_PRESETN reset signal
Same here.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
On Mon, Feb 26, 2024 at 3:15 PM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Prabhakar,
>
> On Mon, Feb 26, 2024 at 3:01 PM Lad, Prabhakar
> <[email protected]> wrote:
> > On Mon, Feb 26, 2024 at 1:41 PM Geert Uytterhoeven <[email protected]> wrote:
> > > On Mon, Feb 19, 2024 at 5:10 PM Prabhakar <[email protected]> wrote:
> > > > From: Lad Prabhakar <[email protected]>
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
> > > > + clocks:
> > > > + items:
> > > > + - description: Clock from external oscillator
> > >
> > > Isn't this SYS_0_PCLK inside the CPG?
> > >
> > As per the block diagram (figure 4.4-3), if we follow the clock source
> > for SYS it traces back to 24MHz Oscillator. Let me know how you want
> > me to describe this please.
>
> Yes, that is the diagram I was looking at.
> MAIN OSC 24 MHz -> MAINCLK -> SYS_0_PCLK.
>
> MAIN OSC 24 MHz is a clock input to the CPG.
> MAINCLK is a CPG internal core clock.
> SYS_0_PCLK is a CPG clock output, serving as the SYS module clock.
>
Agreed.
> I think the standard "maxItems: 1" would be fine, and no description
> is needed.
>
OK, makes sense.
> > > > +
> > > > + resets:
> > > > + items:
> > > > + - description: SYS_0_PRESETN reset signal
>
> Same here.
>
Ok.
Cheers,
Prabhakar