This patch set adds basic support for the Tesla Full Self-Driving (FSD)
SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
as well as several IPs.
Patches 1 to 8 provide support for the clock controller
(which is designed similarly to Exynos SoCs).
The remaining changes provide pinmux support, initial device tree support,
and SPI, ADC, and MCT IP functionality.
Alim Akhtar (21):
dt-bindings: clock: Document FSD CMU bindings
dt-bindings: clock: Add bindings definitions for FSD CMU blocks
clk: samsung: fsd: Add initial clock support
clk: samsung: fsd: Add cmu_peric block clock information
clk: samsung: fsd: Add cmu_fsys0 clock information
clk: samsung: fsd: Add cmu_fsys1 clock information
clk: samsung: fsd: Add cmu_imem block clock information
clk: samsung: fsd: Add cmu_mfc block clock information
clk: samsung: fsd: Add cam_csi block clock information
dt-bindings: pinctrl: samsung: Add compatible for Tesla FSD SoC
pinctrl: samsung: add FSD SoC specific data
dt-bindings: add vendor prefix for Tesla
dt-bindings: arm: add Tesla FSD ARM SoC
arm64: dts: fsd: Add initial device tree support
arm64: dts: fsd: Add initial pinctrl support
arm64: defconfig: Enable Tesla FSD SoC
Documentation: bindings: Add fsd spi compatible in dt-bindings
document
spi: s3c64xx: Add spi port configuration for Tesla FSD SoC
dt-bindings: iio: adc: exynos-adc: Add ADC-V3 variant
iio: adc: exynos-adc: Add support for ADC V3 controller
arm64: dts: fsd: Add ADC device tree node
Aswani Reddy (2):
arm64: dts: fsd: Add SPI device nodes
clocksource: exynos_mct: Add support for handling three clusters
.../devicetree/bindings/arm/tesla.yaml | 25 +
.../bindings/clock/tesla,fsd-clock.yaml | 212 ++
.../bindings/iio/adc/samsung,exynos-adc.yaml | 1 +
.../bindings/pinctrl/samsung-pinctrl.txt | 1 +
.../devicetree/bindings/spi/spi-samsung.txt | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/tesla/Makefile | 3 +
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 338 +++
arch/arm64/boot/dts/tesla/fsd.dts | 156 ++
arch/arm64/boot/dts/tesla/fsd.dtsi | 805 +++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-fsd.c | 1858 +++++++++++++++++
drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
drivers/clocksource/exynos_mct.c | 6 +-
drivers/iio/adc/exynos_adc.c | 74 +-
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 71 +
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
drivers/spi/spi-s3c64xx.c | 13 +
include/dt-bindings/clock/fsd-clk.h | 146 ++
25 files changed, 3731 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml
create mode 100644 Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
create mode 100644 arch/arm64/boot/dts/tesla/Makefile
create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/tesla/fsd.dts
create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi
create mode 100644 drivers/clk/samsung/clk-fsd.c
create mode 100644 include/dt-bindings/clock/fsd-clk.h
base-commit: c9e6606c7fe92b50a02ce51dda82586ebdf99b48
--
2.17.1
Add dt-schema documentation for Tesla FSD SoC clock controller.
Cc: [email protected]
Signed-off-by: Alim Akhtar <[email protected]>
---
.../bindings/clock/tesla,fsd-clock.yaml | 212 ++++++++++++++++++
1 file changed, 212 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
new file mode 100644
index 000000000000..58f341e5004d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
@@ -0,0 +1,212 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD (Full Self-Driving) SoC clock controller
+
+maintainers:
+ - Alim Akhtar <[email protected]>
+ - [email protected]
+
+description: |
+ FSD clock controller consist of several clock management unit
+ (CMU), which generates clocks for various inteernal SoC blocks.
+ The root clock comes from external OSC clock (24 MHz).
+
+ All available clocks are defined as preprocessor macros in
+ 'dt-bindings/clock/fsd-clk.h' header.
+
+properties:
+ compatible:
+ enum:
+ - tesla,fsd-clock-cmu
+ - tesla,fsd-clock-imem
+ - tesla,fsd-clock-peric
+ - tesla,fsd-clock-fsys0
+ - tesla,fsd-clock-fsys1
+ - tesla,fsd-clock-mfc
+ - tesla,fsd-clock-cam_csi
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+
+ clock-names:
+ minItems: 1
+ maxItems: 6
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-cmu
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+
+ clock-names:
+ items:
+ - const: fin_pll
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-imem
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: IMEM TCU clock (from CMU_CMU)
+ - description: IMEM bus clock (from CMU_CMU)
+ - description: IMEM DMA clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_imem_tcuclk
+ - const: dout_cmu_imem_aclk
+ - const: dout_cmu_imem_dmaclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-peric
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: Shared0 PLL div4 clock (from CMU_CMU)
+ - description: PERIC shared1 div36 clock (from CMU_CMU)
+ - description: PERIC shared0 div3 TBU clock (from CMU_CMU)
+ - description: PERIC shared0 div20 clock (from CMU_CMU)
+ - description: PERIC shared1 div4 DMAclock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_pll_shared0_div4
+ - const: dout_cmu_peric_shared1div36
+ - const: dout_cmu_peric_shared0div3_tbuclk
+ - const: dout_cmu_peric_shared0div20
+ - const: dout_cmu_peric_shared1div4_dmaclk
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-fsys0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: Shared0 PLL div6 clock (from CMU_CMU)
+ - description: FSYS0 shared1 div4 clock (from CMU_CMU)
+ - description: FSYS0 shared0 div4 clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_pll_shared0_div6
+ - const: dout_cmu_fsys0_shared1div4
+ - const: dout_cmu_fsys0_shared0div4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-fsys1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+ - description: FSYS1 shared0 div8 clock (from CMU_CMU)
+ - description: FSYS1 shared0 div4 clock (from CMU_CMU)
+
+ clock-names:
+ items:
+ - const: fin_pll
+ - const: dout_cmu_fsys1_shared0div8
+ - const: dout_cmu_fsys1_shared0div4
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-mfc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+
+ clock-names:
+ items:
+ - const: fin_pll
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: tesla,fsd-clock-cam_csi
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24 MHz)
+
+ clock-names:
+ items:
+ - const: fin_pll
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - reg
+
+additionalProperties: false
+
+examples:
+ # Clock controller node for CMU_FSYS1
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+
+ clock_fsys1: clock-controller@16810000 {
+ compatible = "tesla,fsd-clock-fsys1";
+ reg = <0x0 0x16810000 0x0 0x3000>;
+ #clock-cells = <1>;
+
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
+ clock-names = "fin_pll",
+ "dout_cmu_fsys1_shared0div8",
+ "dout_cmu_fsys1_shared0div4";
+ };
+
+...
--
2.17.1
Clock controller driver of FSD platform is designed to have separate
instances for each particular CMU. So clock IDs in this bindings header
also start from 1 for each CMU block.
Cc: [email protected]
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
include/dt-bindings/clock/fsd-clk.h | 146 ++++++++++++++++++++++++++++
1 file changed, 146 insertions(+)
create mode 100644 include/dt-bindings/clock/fsd-clk.h
diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h
new file mode 100644
index 000000000000..9b97417ea6a1
--- /dev/null
+++ b/include/dt-bindings/clock/fsd-clk.h
@@ -0,0 +1,146 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2022 Tesla, Inc.
+ * https://www.tesla.com
+ *
+ * The constants defined in this header are being used in dts
+ * and fsd platform driver.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_FSD_H
+#define _DT_BINDINGS_CLOCK_FSD_H
+
+/* CMU */
+#define DOUT_CMU_PLL_SHARED0_DIV4 1
+#define DOUT_CMU_PERIC_SHARED1DIV36 2
+#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
+#define DOUT_CMU_PERIC_SHARED0DIV20 4
+#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
+#define DOUT_CMU_PLL_SHARED0_DIV6 6
+#define DOUT_CMU_FSYS0_SHARED1DIV4 7
+#define DOUT_CMU_FSYS0_SHARED0DIV4 8
+#define DOUT_CMU_FSYS1_SHARED0DIV8 9
+#define DOUT_CMU_FSYS1_SHARED0DIV4 10
+#define CMU_CPUCL_SWITCH_GATE 11
+#define DOUT_CMU_IMEM_TCUCLK 12
+#define DOUT_CMU_IMEM_ACLK 13
+#define DOUT_CMU_IMEM_DMACLK 14
+#define GAT_CMU_FSYS0_SHARED0DIV4 15
+#define CMU_NR_CLK 16
+
+/* PERIC */
+#define PERIC_SCLK_UART0 1
+#define PERIC_PCLK_UART0 2
+#define PERIC_SCLK_UART1 3
+#define PERIC_PCLK_UART1 4
+#define PERIC_DMA0_IPCLKPORT_ACLK 5
+#define PERIC_DMA1_IPCLKPORT_ACLK 6
+#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
+#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
+#define PERIC_PCLK_SPI0 9
+#define PERIC_SCLK_SPI0 10
+#define PERIC_PCLK_SPI1 11
+#define PERIC_SCLK_SPI1 12
+#define PERIC_PCLK_SPI2 13
+#define PERIC_SCLK_SPI2 14
+#define PERIC_PCLK_TDM0 15
+#define PERIC_PCLK_HSI2C0 16
+#define PERIC_PCLK_HSI2C1 17
+#define PERIC_PCLK_HSI2C2 18
+#define PERIC_PCLK_HSI2C3 19
+#define PERIC_PCLK_HSI2C4 20
+#define PERIC_PCLK_HSI2C5 21
+#define PERIC_PCLK_HSI2C6 22
+#define PERIC_PCLK_HSI2C7 23
+#define PERIC_MCAN0_IPCLKPORT_CCLK 24
+#define PERIC_MCAN0_IPCLKPORT_PCLK 25
+#define PERIC_MCAN1_IPCLKPORT_CCLK 26
+#define PERIC_MCAN1_IPCLKPORT_PCLK 27
+#define PERIC_MCAN2_IPCLKPORT_CCLK 28
+#define PERIC_MCAN2_IPCLKPORT_PCLK 29
+#define PERIC_MCAN3_IPCLKPORT_CCLK 30
+#define PERIC_MCAN3_IPCLKPORT_PCLK 31
+#define PERIC_PCLK_ADCIF 32
+#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
+#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
+#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
+#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
+#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
+#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
+#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
+#define PERIC_HCLK_TDM0 40
+#define PERIC_PCLK_TDM1 41
+#define PERIC_HCLK_TDM1 42
+#define PERIC_EQOS_PHYRXCLK_MUX 43
+#define PERIC_EQOS_PHYRXCLK 44
+#define PERIC_DOUT_RGMII_CLK 45
+#define PERIC_NR_CLK 46
+
+/* FSYS0 */
+#define UFS0_MPHY_REFCLK_IXTAL24 1
+#define UFS0_MPHY_REFCLK_IXTAL26 2
+#define UFS1_MPHY_REFCLK_IXTAL24 3
+#define UFS1_MPHY_REFCLK_IXTAL26 4
+#define UFS0_TOP0_HCLK_BUS 5
+#define UFS0_TOP0_ACLK 6
+#define UFS0_TOP0_CLK_UNIPRO 7
+#define UFS0_TOP0_FMP_CLK 8
+#define UFS1_TOP1_HCLK_BUS 9
+#define UFS1_TOP1_ACLK 10
+#define UFS1_TOP1_CLK_UNIPRO 11
+#define UFS1_TOP1_FMP_CLK 12
+#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
+#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
+#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
+#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
+#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
+#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
+#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
+#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
+#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
+#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
+#define FSYS0_NR_CLK 23
+
+/* FSYS1 */
+#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
+#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
+#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
+#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
+#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
+#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
+#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
+#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
+#define FSYS1_NR_CLK 9
+
+/* IMEM */
+#define IMEM_DMA0_IPCLKPORT_ACLK 1
+#define IMEM_DMA1_IPCLKPORT_ACLK 2
+#define IMEM_WDT0_IPCLKPORT_PCLK 3
+#define IMEM_WDT1_IPCLKPORT_PCLK 4
+#define IMEM_WDT2_IPCLKPORT_PCLK 5
+#define IMEM_MCT_PCLK 6
+#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
+#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
+#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
+#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
+#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
+#define IMEM_NR_CLK 12
+
+/* MFC */
+#define MFC_MFC_IPCLKPORT_ACLK 1
+#define MFC_NR_CLK 2
+
+/* CAM_CSI */
+#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
+#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
+#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
+#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
+#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
+#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
+#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
+#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
+#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
+#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
+#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
+#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
+#define CAM_CSI_NR_CLK 13
+#endif /* _DT_BINDINGS_CLOCK_FSD_H */
--
2.17.1
Add initial clock support for FSD (Full Self-Driving) SoC
which is required to bring-up platforms based on this SoC.
Cc: [email protected]
Signed-off-by: Jayati Sahu <[email protected]>
Signed-off-by: Ajay Kumar <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-fsd.c | 308 ++++++++++++++++++++++++++++++++++
drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
4 files changed, 311 insertions(+)
create mode 100644 drivers/clk/samsung/clk-fsd.c
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index c46cf11e4d0b..d66b2ede004c 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
+obj-$(CONFIG_ARCH_TESLA_FSD) += clk-fsd.o
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
new file mode 100644
index 000000000000..e47523106d9e
--- /dev/null
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Common Clock Framework support for FSD SoC.
+ *
+ * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2022 Tesla, Inc.
+ * https://www.tesla.com
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+
+#include "clk.h"
+#include <dt-bindings/clock/fsd-clk.h>
+
+/* Register Offset definitions for CMU_CMU (0x11c10000) */
+#define PLL_LOCKTIME_PLL_SHARED0 0x0
+#define PLL_LOCKTIME_PLL_SHARED1 0x4
+#define PLL_LOCKTIME_PLL_SHARED2 0x8
+#define PLL_LOCKTIME_PLL_SHARED3 0xc
+#define PLL_CON0_PLL_SHARED0 0x100
+#define PLL_CON0_PLL_SHARED1 0x120
+#define PLL_CON0_PLL_SHARED2 0x140
+#define PLL_CON0_PLL_SHARED3 0x160
+#define MUX_CMU_CIS0_CLKMUX 0x1000
+#define MUX_CMU_CIS1_CLKMUX 0x1004
+#define MUX_CMU_CIS2_CLKMUX 0x1008
+#define MUX_CMU_CPUCL_SWITCHMUX 0x100c
+#define MUX_CMU_FSYS1_ACLK_MUX 0x1014
+#define MUX_PLL_SHARED0_MUX 0x1020
+#define MUX_PLL_SHARED1_MUX 0x1024
+#define DIV_CMU_CIS0_CLK 0x1800
+#define DIV_CMU_CIS1_CLK 0x1804
+#define DIV_CMU_CIS2_CLK 0x1808
+#define DIV_CMU_CMU_ACLK 0x180c
+#define DIV_CMU_CPUCL_SWITCH 0x1810
+#define DIV_CMU_FSYS0_SHARED0DIV4 0x181c
+#define DIV_CMU_FSYS0_SHARED1DIV3 0x1820
+#define DIV_CMU_FSYS0_SHARED1DIV4 0x1824
+#define DIV_CMU_FSYS1_SHARED0DIV4 0x1828
+#define DIV_CMU_FSYS1_SHARED0DIV8 0x182c
+#define DIV_CMU_IMEM_ACLK 0x1834
+#define DIV_CMU_IMEM_DMACLK 0x1838
+#define DIV_CMU_IMEM_TCUCLK 0x183c
+#define DIV_CMU_PERIC_SHARED0DIV20 0x1844
+#define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848
+#define DIV_CMU_PERIC_SHARED1DIV36 0x184c
+#define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850
+#define DIV_PLL_SHARED0_DIV2 0x1858
+#define DIV_PLL_SHARED0_DIV3 0x185c
+#define DIV_PLL_SHARED0_DIV4 0x1860
+#define DIV_PLL_SHARED0_DIV6 0x1864
+#define DIV_PLL_SHARED1_DIV3 0x1868
+#define DIV_PLL_SHARED1_DIV36 0x186c
+#define DIV_PLL_SHARED1_DIV4 0x1870
+#define DIV_PLL_SHARED1_DIV9 0x1874
+#define GAT_CMU_CIS0_CLKGATE 0x2000
+#define GAT_CMU_CIS1_CLKGATE 0x2004
+#define GAT_CMU_CIS2_CLKGATE 0x2008
+#define GAT_CMU_CPUCL_SWITCH_GATE 0x200c
+#define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018
+#define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c
+#define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020
+#define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024
+#define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028
+#define GAT_CMU_IMEM_ACLK_GATE 0x2030
+#define GAT_CMU_IMEM_DMACLK_GATE 0x2034
+#define GAT_CMU_IMEM_TCUCLK_GATE 0x2038
+#define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040
+#define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044
+#define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048
+#define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c
+#define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054
+#define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058
+#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c
+#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060
+
+static const unsigned long cmu_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_SHARED0,
+ PLL_LOCKTIME_PLL_SHARED1,
+ PLL_LOCKTIME_PLL_SHARED2,
+ PLL_LOCKTIME_PLL_SHARED3,
+ PLL_CON0_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED3,
+ MUX_CMU_CIS0_CLKMUX,
+ MUX_CMU_CIS1_CLKMUX,
+ MUX_CMU_CIS2_CLKMUX,
+ MUX_CMU_CPUCL_SWITCHMUX,
+ MUX_CMU_FSYS1_ACLK_MUX,
+ MUX_PLL_SHARED0_MUX,
+ MUX_PLL_SHARED1_MUX,
+ DIV_CMU_CIS0_CLK,
+ DIV_CMU_CIS1_CLK,
+ DIV_CMU_CIS2_CLK,
+ DIV_CMU_CMU_ACLK,
+ DIV_CMU_CPUCL_SWITCH,
+ DIV_CMU_FSYS0_SHARED0DIV4,
+ DIV_CMU_FSYS0_SHARED1DIV3,
+ DIV_CMU_FSYS0_SHARED1DIV4,
+ DIV_CMU_FSYS1_SHARED0DIV4,
+ DIV_CMU_FSYS1_SHARED0DIV8,
+ DIV_CMU_IMEM_ACLK,
+ DIV_CMU_IMEM_DMACLK,
+ DIV_CMU_IMEM_TCUCLK,
+ DIV_CMU_PERIC_SHARED0DIV20,
+ DIV_CMU_PERIC_SHARED0DIV3_TBUCLK,
+ DIV_CMU_PERIC_SHARED1DIV36,
+ DIV_CMU_PERIC_SHARED1DIV4_DMACLK,
+ DIV_PLL_SHARED0_DIV2,
+ DIV_PLL_SHARED0_DIV3,
+ DIV_PLL_SHARED0_DIV4,
+ DIV_PLL_SHARED0_DIV6,
+ DIV_PLL_SHARED1_DIV3,
+ DIV_PLL_SHARED1_DIV36,
+ DIV_PLL_SHARED1_DIV4,
+ DIV_PLL_SHARED1_DIV9,
+ GAT_CMU_CIS0_CLKGATE,
+ GAT_CMU_CIS1_CLKGATE,
+ GAT_CMU_CIS2_CLKGATE,
+ GAT_CMU_CPUCL_SWITCH_GATE,
+ GAT_CMU_FSYS0_SHARED0DIV4_GATE,
+ GAT_CMU_FSYS0_SHARED1DIV4_CLK,
+ GAT_CMU_FSYS0_SHARED1DIV4_GATE,
+ GAT_CMU_FSYS1_SHARED0DIV4_GATE,
+ GAT_CMU_FSYS1_SHARED1DIV4_GATE,
+ GAT_CMU_IMEM_ACLK_GATE,
+ GAT_CMU_IMEM_DMACLK_GATE,
+ GAT_CMU_IMEM_TCUCLK_GATE,
+ GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE,
+ GAT_CMU_PERIC_SHARED0DIVE4_GATE,
+ GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE,
+ GAT_CMU_PERIC_SHARED1DIVE4_GATE,
+ GAT_CMU_CMU_CMU_IPCLKPORT_PCLK,
+ GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK,
+ GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU,
+ GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK,
+};
+
+static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
+};
+
+static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 2400000000, 200, 2, 0),
+};
+
+static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 2400000000, 200, 2, 0),
+};
+
+static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 1800000000, 150, 2, 0),
+};
+
+static const struct samsung_pll_clock cmu_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0,
+ PLL_CON0_PLL_SHARED0, pll_shared0_rate_table),
+ PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1,
+ PLL_CON0_PLL_SHARED1, pll_shared1_rate_table),
+ PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2,
+ PLL_CON0_PLL_SHARED2, pll_shared2_rate_table),
+ PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3,
+ PLL_CON0_PLL_SHARED3, pll_shared3_rate_table),
+};
+
+/* List of parent clocks for Muxes in CMU_CMU */
+PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" };
+PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" };
+PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" };
+PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" };
+PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" };
+PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" };
+PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" };
+PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" };
+
+static const struct samsung_mux_clock cmu_mux_clks[] __initconst = {
+ MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
+ MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
+ MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
+ MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
+ MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
+ MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
+ MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
+ MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
+ MUX_CMU_CPUCL_SWITCHMUX, 0, 1),
+ MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
+ MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
+ MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1),
+};
+
+static const struct samsung_div_clock cmu_div_clks[] __initconst = {
+ DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4),
+ DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4),
+ DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4),
+ DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4),
+ DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4),
+ DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate",
+ DIV_CMU_FSYS0_SHARED0DIV4, 0, 4),
+ DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk",
+ DIV_CMU_FSYS0_SHARED1DIV3, 0, 4),
+ DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate",
+ DIV_CMU_FSYS0_SHARED1DIV4, 0, 4),
+ DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate",
+ DIV_CMU_FSYS1_SHARED0DIV4, 0, 4),
+ DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate",
+ DIV_CMU_FSYS1_SHARED0DIV8, 0, 4),
+ DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate",
+ DIV_CMU_IMEM_ACLK, 0, 4),
+ DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate",
+ DIV_CMU_IMEM_DMACLK, 0, 4),
+ DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate",
+ DIV_CMU_IMEM_TCUCLK, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20",
+ "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk",
+ "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36",
+ "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4),
+ DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk",
+ "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4),
+ DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux",
+ DIV_PLL_SHARED0_DIV2, 0, 4),
+ DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux",
+ DIV_PLL_SHARED0_DIV3, 0, 4),
+ DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2",
+ DIV_PLL_SHARED0_DIV4, 0, 4),
+ DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3",
+ DIV_PLL_SHARED0_DIV6, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux",
+ DIV_PLL_SHARED1_DIV3, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9",
+ DIV_PLL_SHARED1_DIV36, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux",
+ DIV_PLL_SHARED1_DIV4, 0, 4),
+ DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3",
+ DIV_PLL_SHARED1_DIV9, 0, 4),
+};
+
+static const struct samsung_gate_clock cmu_gate_clks[] __initconst = {
+ GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux",
+ GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4",
+ GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3",
+ GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4",
+ GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux",
+ GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4",
+ GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3",
+ GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4",
+ GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4",
+ GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36",
+ GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
+ GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk",
+ GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk",
+ GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk",
+ GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info cmu_cmu_info __initconst = {
+ .pll_clks = cmu_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks),
+ .mux_clks = cmu_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks),
+ .div_clks = cmu_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmu_div_clks),
+ .gate_clks = cmu_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks),
+ .nr_clk_ids = CMU_NR_CLK,
+ .clk_regs = cmu_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs),
+};
+
+static void __init fsd_clk_cmu_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &cmu_cmu_info);
+}
+
+CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 83d1b03647db..e321036875f0 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1469,6 +1469,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
case pll_1450x:
case pll_1451x:
case pll_1452x:
+ case pll_142xx:
pll->enable_offs = PLL35XX_ENABLE_SHIFT;
pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT;
if (!pll->rate_table)
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index a739f2b7ae80..9ba5d7c867c5 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -38,6 +38,7 @@ enum samsung_pll_type {
pll_1460x,
pll_0822x,
pll_0831x,
+ pll_142xx,
};
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
--
2.17.1
This patch adds CMU_PERIC block clock information needed
for various IPs functions found in this block.
Cc: [email protected]
Signed-off-by: Aswani Reddy <[email protected]>
Signed-off-by: Niyas Ahmed S T <[email protected]>
Signed-off-by: Chandrasekar R <[email protected]>
Signed-off-by: Jayati Sahu <[email protected]>
Signed-off-by: Sriranjani P <[email protected]>
Signed-off-by: Ajay Kumar <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clk/samsung/clk-fsd.c | 464 +++++++++++++++++++++++++++++++++-
1 file changed, 463 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index e47523106d9e..6da20966ba99 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -9,12 +9,59 @@
*
*/
-#include <linux/clk-provider.h>
#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
#include "clk.h"
#include <dt-bindings/clock/fsd-clk.h>
+/* Gate register bits */
+#define GATE_MANUAL BIT(20)
+#define GATE_ENABLE_HWACG BIT(28)
+
+/* Gate register offsets range */
+#define GATE_OFF_START 0x2000
+#define GATE_OFF_END 0x2fff
+
+/**
+ * fsd_init_clocks - Set clocks initial configuration
+ * @np: CMU device tree node with "reg" property (CMU addr)
+ * @reg_offs: Register offsets array for clocks to init
+ * @reg_offs_len: Number of register offsets in reg_offs array
+ *
+ * Set manual control mode for all gate clocks.
+ */
+static void __init fsd_init_clocks(struct device_node *np,
+ const unsigned long *reg_offs, size_t reg_offs_len)
+{
+ void __iomem *reg_base;
+ size_t i;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ for (i = 0; i < reg_offs_len; ++i) {
+ void __iomem *reg = reg_base + reg_offs[i];
+ u32 val;
+
+ /* Modify only gate clock registers */
+ if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
+ continue;
+
+ val = readl(reg);
+ val |= GATE_MANUAL;
+ val &= ~GATE_ENABLE_HWACG;
+ writel(val, reg);
+ }
+
+ iounmap(reg_base);
+}
+
/* Register Offset definitions for CMU_CMU (0x11c10000) */
#define PLL_LOCKTIME_PLL_SHARED0 0x0
#define PLL_LOCKTIME_PLL_SHARED1 0x4
@@ -306,3 +353,418 @@ static void __init fsd_clk_cmu_init(struct device_node *np)
}
CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init);
+
+/* Register Offset definitions for CMU_PERIC (0x14010000) */
+#define PLL_CON0_PERIC_DMACLK_MUX 0x100
+#define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120
+#define PLL_CON0_PERIC_PCLK_MUX 0x140
+#define PLL_CON0_PERIC_TBUCLK_MUX 0x160
+#define PLL_CON0_SPI_CLK 0x180
+#define PLL_CON0_SPI_PCLK 0x1a0
+#define PLL_CON0_UART_CLK 0x1c0
+#define PLL_CON0_UART_PCLK 0x1e0
+#define MUX_PERIC_EQOS_PHYRXCLK 0x1000
+#define DIV_EQOS_BUSCLK 0x1800
+#define DIV_PERIC_MCAN_CLK 0x1804
+#define DIV_RGMII_CLK 0x1808
+#define DIV_RII_CLK 0x180c
+#define DIV_RMII_CLK 0x1810
+#define DIV_SPI_CLK 0x1814
+#define DIV_UART_CLK 0x1818
+#define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000
+#define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004
+#define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008
+#define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c
+#define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010
+#define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014
+#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018
+#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c
+#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020
+#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024
+#define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028
+#define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c
+#define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030
+#define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034
+#define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038
+#define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c
+#define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040
+#define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044
+#define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048
+#define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c
+#define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050
+#define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054
+#define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058
+#define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c
+#define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060
+#define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064
+#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068
+#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c
+#define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070
+#define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074
+#define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078
+#define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c
+#define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080
+#define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084
+#define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088
+#define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c
+#define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090
+#define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094
+#define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098
+#define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c
+#define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0
+#define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4
+#define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8
+#define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac
+#define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0
+#define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4
+#define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8
+#define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc
+#define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0
+#define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4
+#define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8
+#define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc
+#define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0
+#define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4
+#define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8
+#define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc
+#define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0
+#define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4
+#define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8
+#define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec
+#define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0
+#define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4
+#define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8
+#define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc
+#define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100
+#define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104
+
+static const unsigned long peric_clk_regs[] __initconst = {
+ PLL_CON0_PERIC_DMACLK_MUX,
+ PLL_CON0_PERIC_EQOS_BUSCLK_MUX,
+ PLL_CON0_PERIC_PCLK_MUX,
+ PLL_CON0_PERIC_TBUCLK_MUX,
+ PLL_CON0_SPI_CLK,
+ PLL_CON0_SPI_PCLK,
+ PLL_CON0_UART_CLK,
+ PLL_CON0_UART_PCLK,
+ MUX_PERIC_EQOS_PHYRXCLK,
+ DIV_EQOS_BUSCLK,
+ DIV_PERIC_MCAN_CLK,
+ DIV_RGMII_CLK,
+ DIV_RII_CLK,
+ DIV_RMII_CLK,
+ DIV_SPI_CLK,
+ DIV_UART_CLK,
+ GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I,
+ GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
+ GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK,
+ GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK,
+ GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK,
+ GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK,
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM,
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS,
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM,
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS,
+ GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK,
+ GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK,
+ GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK,
+ GAT_BUS_D_PERIC_IPCLKPORT_DMACLK,
+ GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK,
+ GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK,
+ GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK,
+ GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK,
+ GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK,
+ GAT_EQOS_TOP_IPCLKPORT_ACLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I,
+ GAT_EQOS_TOP_IPCLKPORT_HCLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I,
+ GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I,
+ GAT_GPIO_PERIC_IPCLKPORT_PCLK,
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D,
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P,
+ GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0,
+ GAT_PERIC_DMA0_IPCLKPORT_ACLK,
+ GAT_PERIC_DMA1_IPCLKPORT_ACLK,
+ GAT_PERIC_I2C0_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C1_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C2_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C3_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C4_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C5_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C6_IPCLKPORT_I_PCLK,
+ GAT_PERIC_I2C7_IPCLKPORT_I_PCLK,
+ GAT_PERIC_MCAN0_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN0_IPCLKPORT_PCLK,
+ GAT_PERIC_MCAN1_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN1_IPCLKPORT_PCLK,
+ GAT_PERIC_MCAN2_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN2_IPCLKPORT_PCLK,
+ GAT_PERIC_MCAN3_IPCLKPORT_CCLK,
+ GAT_PERIC_MCAN3_IPCLKPORT_PCLK,
+ GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0,
+ GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0,
+ GAT_PERIC_SMMU_IPCLKPORT_CCLK,
+ GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK,
+ GAT_PERIC_SPI0_IPCLKPORT_I_PCLK,
+ GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI,
+ GAT_PERIC_SPI1_IPCLKPORT_I_PCLK,
+ GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI,
+ GAT_PERIC_SPI2_IPCLKPORT_I_PCLK,
+ GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI,
+ GAT_PERIC_TDM0_IPCLKPORT_HCLK_M,
+ GAT_PERIC_TDM0_IPCLKPORT_PCLK,
+ GAT_PERIC_TDM1_IPCLKPORT_HCLK_M,
+ GAT_PERIC_TDM1_IPCLKPORT_PCLK,
+ GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART,
+ GAT_PERIC_UART0_IPCLKPORT_PCLK,
+ GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART,
+ GAT_PERIC_UART1_IPCLKPORT_PCLK,
+ GAT_SYSREG_PERI_IPCLKPORT_PCLK,
+};
+
+static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = {
+ FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000),
+};
+
+/* List of parent clocks for Muxes in CMU_PERIC */
+PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" };
+PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" };
+PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
+PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" };
+PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" };
+PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
+PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" };
+PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" };
+PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" };
+
+static const struct samsung_mux_clock peric_mux_clks[] __initconst = {
+ MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1),
+ MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p,
+ PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1),
+ MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1),
+ MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1),
+ MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1),
+ MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1),
+ MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1),
+ MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1),
+ MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p,
+ MUX_PERIC_EQOS_PHYRXCLK, 0, 1),
+};
+
+static const struct samsung_div_clock peric_div_clks[] __initconst = {
+ DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4),
+ DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4),
+ DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk",
+ DIV_RGMII_CLK, 0, 4),
+ DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4),
+ DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4),
+ DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6),
+ DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6),
+};
+
+static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i",
+ "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll",
+ GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk",
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk",
+ GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk",
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk",
+ GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk",
+ GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk",
+ GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk",
+ GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk",
+ GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk",
+ "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk",
+ GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk",
+ "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk",
+ GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk",
+ GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i",
+ "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i",
+ "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i",
+ "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i",
+ "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk",
+ GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk",
+ GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk",
+ GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk",
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk",
+ GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk",
+ GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk",
+ GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk",
+ GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk",
+ GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk",
+ GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk",
+ GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk",
+ GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk",
+ GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk",
+ GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk",
+ GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
+ GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk",
+ GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
+ GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk",
+ GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk",
+ GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk",
+ GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk",
+ GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk",
+ GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
+ GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk",
+ GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk",
+ GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk",
+ GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk",
+ GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info peric_cmu_info __initconst = {
+ .mux_clks = peric_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peric_mux_clks),
+ .div_clks = peric_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peric_div_clks),
+ .gate_clks = peric_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
+ .fixed_clks = peric_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks),
+ .nr_clk_ids = PERIC_NR_CLK,
+ .clk_regs = peric_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
+ .clk_name = "dout_cmu_pll_shared0_div4",
+};
+
+/**
+ * fsd_cmu_probe - Probe function for FSD platform clocks
+ * @pdev: Pointer to platform device
+ *
+ * Configure clock hierarchy for clock domains of FSD platform
+ */
+static int __init fsd_cmu_probe(struct platform_device *pdev)
+{
+ const struct samsung_cmu_info *info;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+
+ info = of_device_get_match_data(dev);
+ fsd_init_clocks(np, info->clk_regs, info->nr_clk_regs);
+ samsung_cmu_register_one(np, info);
+
+ /* Keep bus clock running, so it's possible to access CMU registers */
+ if (info->clk_name) {
+ struct clk *bus_clk;
+
+ bus_clk = clk_get(dev, info->clk_name);
+ if (IS_ERR(bus_clk)) {
+ pr_err("%s: could not find bus clock %s; err = %ld\n",
+ __func__, info->clk_name, PTR_ERR(bus_clk));
+ } else {
+ clk_prepare_enable(bus_clk);
+ }
+ }
+
+ return 0;
+}
+
+/* CMUs which belong to Power Domains and need runtime PM to be implemented */
+static const struct of_device_id fsd_cmu_of_match[] = {
+ {
+ .compatible = "tesla,fsd-clock-peric",
+ .data = &peric_cmu_info,
+ }, {
+ },
+};
+
+static struct platform_driver fsd_cmu_driver __refdata = {
+ .driver = {
+ .name = "fsd-cmu",
+ .of_match_table = fsd_cmu_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = fsd_cmu_probe,
+};
+
+static int __init fsd_cmu_init(void)
+{
+ return platform_driver_register(&fsd_cmu_driver);
+}
+core_initcall(fsd_cmu_init);
--
2.17.1
CMU_FSYS0 block has IPs like UFS, EQOS, PCIe etc, lets add
the related clock information for the same.
Cc: [email protected]
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Shradha Todi <[email protected]>
Signed-off-by: Jayati Sahu <[email protected]>
Signed-off-by: Ajay Kumar <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clk/samsung/clk-fsd.c | 302 ++++++++++++++++++++++++++++++++++
1 file changed, 302 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 6da20966ba99..8a7a668eb4be 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -713,6 +713,305 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
.clk_name = "dout_cmu_pll_shared0_div4",
};
+/* Register Offset definitions for CMU_FSYS0 (0x15010000) */
+#define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100
+#define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140
+#define PLL_CON0_EQOS_RGMII_125_MUX1 0x160
+#define DIV_CLK_UNIPRO 0x1800
+#define DIV_EQS_RGMII_CLK_125 0x1804
+#define DIV_PERIBUS_GRP 0x1808
+#define DIV_EQOS_RII_CLK2O5 0x180c
+#define DIV_EQOS_RMIICLK_25 0x1810
+#define DIV_PCIE_PHY_OSCCLK 0x1814
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008
+#define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c
+#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c
+#define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038
+#define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c
+#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040
+#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044
+#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048
+#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c
+#define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060
+#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064
+#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074
+#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090
+#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094
+#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098
+#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c
+#define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac
+#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc
+#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0
+#define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4
+
+static const unsigned long fsys0_clk_regs[] __initconst = {
+ PLL_CON0_CLKCMU_FSYS0_UNIPRO,
+ PLL_CON0_CLK_FSYS0_SLAVEBUSCLK,
+ PLL_CON0_EQOS_RGMII_125_MUX1,
+ DIV_CLK_UNIPRO,
+ DIV_EQS_RGMII_CLK_125,
+ DIV_PERIBUS_GRP,
+ DIV_EQOS_RII_CLK2O5,
+ DIV_EQOS_RMIICLK_25,
+ DIV_PCIE_PHY_OSCCLK,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I,
+ GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26,
+ GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK,
+ GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK,
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK,
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK,
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK,
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK,
+ GAT_FSYS0_CPE425_IPCLKPORT_ACLK,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I,
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I,
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P,
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC,
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC,
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK,
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK,
+ GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO,
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO,
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK,
+ GAT_FSYS0_RII_CLK_DIVGATE,
+};
+
+static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = {
+ FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000),
+ FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000),
+ FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000),
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS0 */
+PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" };
+PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" };
+PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" };
+
+static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = {
+ MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p,
+ PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1),
+ MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p,
+ PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1),
+ MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p,
+ PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1),
+};
+
+static const struct samsung_div_clock fsys0_div_clks[] __initconst = {
+ DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4),
+ DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1",
+ DIV_EQS_RGMII_CLK_125, 0, 4),
+ DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp",
+ "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4),
+ DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4),
+ DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1",
+ DIV_EQOS_RMIICLK_25, 0, 5),
+ DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1",
+ DIV_PCIE_PHY_OSCCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = {
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i",
+ "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0,
+ "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo",
+ "xtal_clk_pcie_phy",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26",
+ "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1",
+ GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i",
+ "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i",
+ "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i",
+ "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5",
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25",
+ GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll",
+ GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1",
+ "mout_fsys0_eqos_rgmii_125_mux1",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0,
+ "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll",
+ "dout_fsys0_pcie_phy_oscclk",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk",
+ "dout_fsys0_peribus_grp",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC,
+ "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc",
+ "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1",
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk",
+ GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp",
+ GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i",
+ "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
+ .mux_clks = fsys0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
+ .div_clks = fsys0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(fsys0_div_clks),
+ .gate_clks = fsys0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
+ .fixed_clks = fsys0_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks),
+ .nr_clk_ids = FSYS0_NR_CLK,
+ .clk_regs = fsys0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
+ .clk_name = "dout_cmu_fsys0_shared1div4",
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -750,6 +1049,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
{
.compatible = "tesla,fsd-clock-peric",
.data = &peric_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-fsys0",
+ .data = &fsys0_cmu_info,
}, {
},
};
--
2.17.1
Adds cmu_fsys1 block clock information which are needed
for PCIe IPs in block FSYS1.
Cc: [email protected]
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Ajay Kumar <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clk/samsung/clk-fsd.c | 175 ++++++++++++++++++++++++++++++++++
1 file changed, 175 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 8a7a668eb4be..d06afab39d37 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1012,6 +1012,178 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
.clk_name = "dout_cmu_fsys0_shared1div4",
};
+/* Register Offset definitions for CMU_FSYS1 (0x16810000) */
+#define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100
+#define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180
+#define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800
+#define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804
+#define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c
+#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c
+#define GAT_FSYS1_PHY0_OSCCLLK 0x2034
+#define GAT_FSYS1_PHY1_OSCCLK 0x2038
+#define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c
+#define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040
+#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048
+#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c
+#define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054
+#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c
+#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078
+#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088
+#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c
+#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4
+#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8
+#define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4
+#define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8
+
+static const unsigned long fsys1_clk_regs[] __initconst = {
+ PLL_CON0_ACLK_FSYS1_BUSP_MUX,
+ PLL_CON0_PCLKL_FSYS1_BUSP_MUX,
+ DIV_CLK_FSYS1_PHY0_OSCCLK,
+ DIV_CLK_FSYS1_PHY1_OSCCLK,
+ GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK,
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL,
+ GAT_FSYS1_PHY0_OSCCLLK,
+ GAT_FSYS1_PHY1_OSCCLK,
+ GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK,
+ GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK,
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK,
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK,
+ GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK,
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0,
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK,
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK,
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK,
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK,
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL,
+ GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK,
+ GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK,
+};
+
+static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = {
+ FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000),
+ FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000),
+};
+
+/* List of parent clocks for Muxes in CMU_FSYS1 */
+PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" };
+PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" };
+
+static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
+ MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p,
+ PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1),
+ MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p,
+ PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1),
+};
+
+static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
+ DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk",
+ DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4),
+ DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk",
+ DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
+ GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref",
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0",
+ "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0",
+ "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk",
+ "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll",
+ GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll",
+ GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk",
+ GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux",
+ GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux",
+ GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
+ .mux_clks = fsys1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
+ .div_clks = fsys1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
+ .gate_clks = fsys1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
+ .fixed_clks = fsys1_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks),
+ .nr_clk_ids = FSYS1_NR_CLK,
+ .clk_regs = fsys1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
+ .clk_name = "dout_cmu_fsys1_shared0div4",
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -1052,6 +1224,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-fsys0",
.data = &fsys0_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-fsys1",
+ .data = &fsys1_cmu_info,
}, {
},
};
--
2.17.1
Adds cmu_imem clock related code, imem block contains IPs
like WDT, DMA, TMU etc, these clocks are required for such
IP function.
Cc: [email protected]
Signed-off-by: Arjun K V <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Tauseef Nomani <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clk/samsung/clk-fsd.c | 283 ++++++++++++++++++++++++++++++++++
1 file changed, 283 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index d06afab39d37..dc252e63099d 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1184,6 +1184,289 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
.clk_name = "dout_cmu_fsys1_shared0div4",
};
+/* Register Offset definitions for CMU_IMEM (0x10010000) */
+#define PLL_CON0_CLK_IMEM_ACLK 0x100
+#define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120
+#define PLL_CON0_CLK_IMEM_TCUCLK 0x140
+#define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800
+#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000
+#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004
+#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008
+#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c
+#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010
+#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014
+#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018
+#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c
+#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020
+#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024
+#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028
+#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c
+#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030
+#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034
+#define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038
+#define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c
+#define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040
+#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044
+#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048
+#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c
+#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050
+#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054
+#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058
+#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c
+#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060
+#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064
+#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068
+#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c
+#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070
+#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c
+#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080
+#define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084
+#define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088
+#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c
+#define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090
+#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094
+#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098
+#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c
+#define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8
+#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac
+#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0
+#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4
+#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8
+#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc
+#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0
+#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4
+#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8
+#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc
+#define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0
+#define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4
+#define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8
+#define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc
+
+static const unsigned long imem_clk_regs[] __initconst = {
+ PLL_CON0_CLK_IMEM_ACLK,
+ PLL_CON0_CLK_IMEM_INTMEMCLK,
+ PLL_CON0_CLK_IMEM_TCUCLK,
+ DIV_OSCCLK_IMEM_TMUTSCLK,
+ GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO,
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
+ GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK,
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK,
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS,
+ GAT_IMEM_WDT0_IPCLKPORT_CLK,
+ GAT_IMEM_WDT1_IPCLKPORT_CLK,
+ GAT_IMEM_WDT2_IPCLKPORT_CLK,
+ GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM,
+ GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS,
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM,
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS,
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM,
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS,
+ GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK,
+ GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK,
+ GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK,
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK,
+ GAT_IMEM_DMA0_IPCLKPORT_ACLK,
+ GAT_IMEM_DMA1_IPCLKPORT_ACLK,
+ GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK,
+ GAT_IMEM_GIC_IPCLKPORT_CLK,
+ GAT_IMEM_INTMEM_IPCLKPORT_ACLK,
+ GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK,
+ GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK,
+ GAT_IMEM_MCT_IPCLKPORT_PCLK,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU,
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P,
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK,
+ GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK,
+ GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK,
+ GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK,
+ GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK,
+ GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK,
+ GAT_IMEM_TCU_IPCLKPORT_ACLK,
+ GAT_IMEM_WDT0_IPCLKPORT_PCLK,
+ GAT_IMEM_WDT1_IPCLKPORT_PCLK,
+ GAT_IMEM_WDT2_IPCLKPORT_PCLK,
+};
+
+PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" };
+PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" };
+PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" };
+
+static const struct samsung_mux_clock imem_mux_clks[] __initconst = {
+ MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p,
+ PLL_CON0_CLK_IMEM_TCUCLK, 4, 1),
+ MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1),
+ MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p,
+ PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1),
+};
+
+static const struct samsung_div_clock imem_div_clks[] __initconst = {
+ DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4),
+};
+
+static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
+ GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll",
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll",
+ GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll",
+ GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts",
+ "dout_imem_oscclk_imem_tmutsclk",
+ GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
+ GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0),
+ GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk",
+ GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d",
+ "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu",
+ "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll",
+ GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk",
+ GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll",
+ GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk",
+ GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk",
+ GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info imem_cmu_info __initconst = {
+ .mux_clks = imem_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(imem_mux_clks),
+ .div_clks = imem_div_clks,
+ .nr_div_clks = ARRAY_SIZE(imem_div_clks),
+ .gate_clks = imem_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
+ .nr_clk_ids = IMEM_NR_CLK,
+ .clk_regs = imem_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
+};
+
+static void __init fsd_clk_imem_init(struct device_node *np)
+{
+ samsung_cmu_register_one(np, &imem_cmu_info);
+}
+
+CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
--
2.17.1
This patch adds clock related to MFC IP.
Cc: [email protected]
Signed-off-by: Smitha T Murthy <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clk/samsung/clk-fsd.c | 121 ++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index dc252e63099d..927b310ce4a4 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1467,6 +1467,124 @@ static void __init fsd_clk_imem_init(struct device_node *np)
CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init);
+/* Register Offset definitions for CMU_MFC (0x12810000) */
+#define PLL_LOCKTIME_PLL_MFC 0x0
+#define PLL_CON0_PLL_MFC 0x100
+#define MUX_MFC_BUSD 0x1000
+#define MUX_MFC_BUSP 0x1008
+#define DIV_MFC_BUSD_DIV4 0x1800
+#define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000
+#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004
+#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008
+#define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c
+#define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010
+#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018
+#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c
+#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028
+#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c
+#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030
+#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034
+#define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038
+#define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c
+#define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040
+#define GAT_MFC_BUSD_DIV4_GATE 0x2044
+#define GAT_MFC_BUSD_GATE 0x2048
+
+static const unsigned long mfc_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_MFC,
+ PLL_CON0_PLL_MFC,
+ MUX_MFC_BUSD,
+ MUX_MFC_BUSP,
+ DIV_MFC_BUSD_DIV4,
+ GAT_MFC_CMU_MFC_IPCLKPORT_PCLK,
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM,
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS,
+ GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK,
+ GAT_MFC_MFC_IPCLKPORT_ACLK,
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D,
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P,
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK,
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK,
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK,
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK,
+ GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK,
+ GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK,
+ GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK,
+ GAT_MFC_BUSD_DIV4_GATE,
+ GAT_MFC_BUSD_GATE,
+};
+
+static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 666000000, 111, 4, 0),
+};
+
+static const struct samsung_pll_clock mfc_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll",
+ PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table),
+};
+
+PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" };
+PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" };
+PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" };
+
+static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
+ MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1),
+ MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1),
+ MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1),
+};
+
+static const struct samsung_div_clock mfc_div_clks[] __initconst = {
+ DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4),
+};
+
+static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
+ GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd",
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp",
+ GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp",
+ GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd",
+ GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd",
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp",
+ GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd",
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd",
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp",
+ GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd",
+ GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd",
+ GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll",
+ GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0),
+};
+
+static const struct samsung_cmu_info mfc_cmu_info __initconst = {
+ .pll_clks = mfc_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks),
+ .mux_clks = mfc_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
+ .div_clks = mfc_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
+ .gate_clks = mfc_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
+ .nr_clk_ids = MFC_NR_CLK,
+ .clk_regs = mfc_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -1510,6 +1628,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-fsys1",
.data = &fsys1_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-mfc",
+ .data = &mfc_cmu_info,
}, {
},
};
--
2.17.1
Adds clocks for BLK_CAM_CSI block, this is needed for CSI to work.
Cc: [email protected]
Signed-off-by: Sathyakam M <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clk/samsung/clk-fsd.c | 207 ++++++++++++++++++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 927b310ce4a4..1bed8c7eb605 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -1585,6 +1585,210 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
};
+/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */
+#define PLL_LOCKTIME_PLL_CAM_CSI 0x0
+#define PLL_CON0_PLL_CAM_CSI 0x100
+#define DIV_CAM_CSI0_ACLK 0x1800
+#define DIV_CAM_CSI1_ACLK 0x1804
+#define DIV_CAM_CSI2_ACLK 0x1808
+#define DIV_CAM_CSI_BUSD 0x180c
+#define DIV_CAM_CSI_BUSP 0x1810
+#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000
+#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014
+#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c
+#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024
+#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c
+#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034
+#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c
+#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044
+#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c
+#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054
+#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c
+#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064
+#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c
+#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074
+#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c
+#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080
+#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084
+#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088
+
+static const unsigned long cam_csi_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_CAM_CSI,
+ PLL_CON0_PLL_CAM_CSI,
+ DIV_CAM_CSI0_ACLK,
+ DIV_CAM_CSI1_ACLK,
+ DIV_CAM_CSI2_ACLK,
+ DIV_CAM_CSI_BUSD,
+ DIV_CAM_CSI_BUSP,
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC,
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK,
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D,
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P,
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK,
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK,
+};
+
+static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 12, 0),
+};
+
+static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
+ PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
+ PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
+};
+
+PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" };
+
+static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = {
+ MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1),
+};
+
+static const struct samsung_div_clock cam_csi_div_clks[] __initconst = {
+ DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4),
+ DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4),
+ DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4),
+};
+
+static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
+ GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp",
+ GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd",
+ GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+ GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
+ "dout_cam_csi_busd",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p",
+ "dout_cam_csi_busp",
+ GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp",
+ GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd",
+ GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info cam_csi_cmu_info __initconst = {
+ .pll_clks = cam_csi_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks),
+ .mux_clks = cam_csi_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks),
+ .div_clks = cam_csi_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks),
+ .gate_clks = cam_csi_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks),
+ .nr_clk_ids = CAM_CSI_NR_CLK,
+ .clk_regs = cam_csi_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs),
+};
+
/**
* fsd_cmu_probe - Probe function for FSD platform clocks
* @pdev: Pointer to platform device
@@ -1631,6 +1835,9 @@ static const struct of_device_id fsd_cmu_of_match[] = {
}, {
.compatible = "tesla,fsd-clock-mfc",
.data = &mfc_cmu_info,
+ }, {
+ .compatible = "tesla,fsd-clock-cam_csi",
+ .data = &cam_csi_cmu_info,
}, {
},
};
--
2.17.1
Add compatible for Tesla Full Self-Driving SoC. The
pinctrl hardware IP is similar to what found on most of the
exynos series of SoC, so this new compatible is added in
samsung pinctrl binding.
Cc: [email protected]
Signed-off-by: Alim Akhtar <[email protected]>
---
Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index b8b475967ff9..ba972998a0e4 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -24,6 +24,7 @@ Required Properties:
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
- "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller.
+ - "tesla,fsd-pinctrl": for Tesla FSD SoC compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
--
2.17.1
This patch adds Tesla FSD SoC specific data to enable pinctrl.
FSD SoC has similar pinctrl controller as found in the most
samsung/exynos SoCs.
Cc: [email protected]
Signed-off-by: Ajay Kumar <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
.../pinctrl/samsung/pinctrl-exynos-arm64.c | 71 +++++++++++++++++++
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
3 files changed, 74 insertions(+)
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 6b77fd24571e..b9175b4911ac 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -646,3 +646,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
.ctrl = exynosautov9_pin_ctrl,
.num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
};
+
+/*
+ * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
+ * gpio/pin-mux/pinconfig controllers.
+ */
+
+/* pin banks of FSD pin-controller 0 (FSYS) */
+static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c),
+ EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10),
+};
+
+/* pin banks of FSD pin-controller 1 (PERIC) */
+static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00),
+ EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18),
+ EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24),
+ EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28),
+ EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
+ EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c),
+ EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50),
+};
+
+/* pin banks of FSD pin-controller 2 (PMU) */
+static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = {
+ EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
+};
+
+const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
+ {
+ /* pin-controller instance 0 FSYS0 data */
+ .pin_banks = fsd_pin_banks0,
+ .nr_banks = ARRAY_SIZE(fsd_pin_banks0),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin-controller instance 1 PERIC data */
+ .pin_banks = fsd_pin_banks1,
+ .nr_banks = ARRAY_SIZE(fsd_pin_banks1),
+ .eint_gpio_init = exynos_eint_gpio_init,
+ .suspend = exynos_pinctrl_suspend,
+ .resume = exynos_pinctrl_resume,
+ }, {
+ /* pin-controller instance 2 PMU data */
+ .pin_banks = fsd_pin_banks2,
+ .nr_banks = ARRAY_SIZE(fsd_pin_banks2),
+ },
+};
+
+const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
+ .ctrl = fsd_pin_ctrl,
+ .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
+};
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 23f355ae9ca0..4b348c038f7a 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1268,6 +1268,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
.data = &exynos850_of_data },
{ .compatible = "samsung,exynosautov9-pinctrl",
.data = &exynosautov9_of_data },
+ { .compatible = "tesla,fsd-pinctrl",
+ .data = &fsd_of_data },
#endif
#ifdef CONFIG_PINCTRL_S3C64XX
{ .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 547968a31aed..43d8a8a139c3 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -341,6 +341,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
+extern const struct samsung_pinctrl_of_match_data fsd_of_data;
extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
--
2.17.1
Add device tree bindings for the Tesla FSD ARM SoC.
Cc: [email protected]
Signed-off-by: Alim Akhtar <[email protected]>
---
.../devicetree/bindings/arm/tesla.yaml | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml
diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml b/Documentation/devicetree/bindings/arm/tesla.yaml
new file mode 100644
index 000000000000..9f89cde76c85
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tesla.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/tesla.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla Full Self Driving(FSD) platforms device tree bindings
+
+maintainers:
+ - Alim Akhtar <[email protected]>
+ - [email protected]
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: FSD SoC board
+ items:
+ - const: tesla,fsd
+
+additionalProperties: true
+
+...
--
2.17.1
Add initial device tree support for "Full Self-Driving" (FSD) SoC
This SoC contain three clusters of four cortex-a72 CPUs and various
peripheral IPs.
Cc: [email protected]
Signed-off-by: Arjun K V <[email protected]>
Signed-off-by: Aswani Reddy <[email protected]>
Signed-off-by: Ajay Kumar <[email protected]>
Signed-off-by: Sriranjani P <[email protected]>
Signed-off-by: Chandrasekar R <[email protected]>
Signed-off-by: Shashank Prashar <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
MAINTAINERS | 8 +
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/tesla/Makefile | 3 +
arch/arm64/boot/dts/tesla/fsd.dts | 140 ++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 715 +++++++++++++++++++++++++++++
6 files changed, 873 insertions(+)
create mode 100644 arch/arm64/boot/dts/tesla/Makefile
create mode 100644 arch/arm64/boot/dts/tesla/fsd.dts
create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index fb18ce7168aa..02d56909c5e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2726,6 +2726,14 @@ S: Maintained
F: Documentation/devicetree/bindings/media/tegra-cec.txt
F: drivers/media/cec/platform/tegra/
+ARM/TESLA FSD SoC SUPPORT
+M: Alim Akhtar <[email protected]>
+M: [email protected]
+L: [email protected] (moderated for non-subscribers)
+L: [email protected]
+S: Maintained
+F: arch/arm64/boot/dts/tesla*
+
ARM/TETON BGA MACHINE SUPPORT
M: "Mark F. Brown" <[email protected]>
L: [email protected] (moderated for non-subscribers)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 54e3910e8b9b..bb8a047c2359 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -267,6 +267,12 @@ config ARCH_TEGRA
help
This enables support for the NVIDIA Tegra SoC family.
+config ARCH_TESLA_FSD
+ bool "ARMv8 based Tesla platform"
+ select ARCH_EXYNOS
+ help
+ Support for ARMv8 based Tesla platforms.
+
config ARCH_SPRD
bool "Spreadtrum SoC platform"
help
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 639e01a4d855..1ba04e31a438 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -27,6 +27,7 @@ subdir-y += rockchip
subdir-y += socionext
subdir-y += sprd
subdir-y += synaptics
+subdir-y += tesla
subdir-y += ti
subdir-y += toshiba
subdir-y += xilinx
diff --git a/arch/arm64/boot/dts/tesla/Makefile b/arch/arm64/boot/dts/tesla/Makefile
new file mode 100644
index 000000000000..a9818cda6b08
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_TESLA_FSD) += \
+ fsd.dtb
diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts
new file mode 100644
index 000000000000..e9bbd3284de9
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/fsd.dts
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Tesla FSD board device tree source
+ *
+ * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2021 Tesla, Inc.
+ * https://www.tesla.com
+ */
+
+/dts-v1/;
+#include "fsd.dtsi"
+
+/ {
+ model = "Tesla Full Self-Driving (FSD) SoC";
+ compatible = "tesla,fsd";
+
+ aliases {
+ serial0 = &serial_0;
+ serial1 = &serial_1;
+ };
+
+ chosen {
+ stdout-path = &serial_0;
+ linux,initrd-start = <0xE0000000>;
+ linux,initrd-end = <0xE4F00000>;
+ bootargs = "console=ttySAC0,115200n8
+ earlycon=exynos4210,0x14180000 root=/dev/ram0
+ init=/linuxrc";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+};
+
+&fin_pll {
+ clock-frequency = <24000000>;
+};
+
+&serial_0 {
+ status = "okay";
+};
+
+&serial_1 {
+ status = "okay";
+};
+
+&clock_cmu {
+ status = "okay";
+};
+
+&clock_imem {
+ status = "okay";
+};
+
+&clock_peric {
+ status = "okay";
+};
+
+&smmu_isp {
+ status = "okay";
+};
+
+&clock_fsys0 {
+ status = "okay";
+};
+
+&clock_fsys1 {
+ status = "okay";
+};
+
+&smmu_peric {
+ status = "okay";
+};
+
+&smmu_imem {
+ status = "okay";
+};
+
+&smmu_fsys0 {
+ status = "okay";
+};
+
+&hsi2c_0 {
+ status = "okay";
+};
+
+&hsi2c_1 {
+ status = "okay";
+};
+
+&hsi2c_2 {
+ status = "okay";
+};
+
+&hsi2c_3 {
+ status = "okay";
+};
+
+&hsi2c_4 {
+ status = "okay";
+};
+
+&hsi2c_5 {
+ status = "okay";
+};
+
+&hsi2c_6 {
+ status = "okay";
+};
+
+&hsi2c_7 {
+ status = "okay";
+};
+
+&pwm_0 {
+ status = "okay";
+};
+
+&pwm_1 {
+ status = "okay";
+};
+
+&mdma0 {
+ status = "okay";
+};
+
+&mdma1 {
+ status = "okay";
+};
+
+&pdma0 {
+ status = "okay";
+};
+
+&pdma1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
new file mode 100644
index 000000000000..47cd9f20566e
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -0,0 +1,715 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Tesla Full Self-Driving SoC device tree source
+ *
+ * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2022 Tesla, Inc.
+ * https://www.tesla.com
+ */
+
+#include <dt-bindings/clock/fsd-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "tesla,fsd";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ watchdog0 = &watchdog_0;
+ watchdog1 = &watchdog_1;
+ watchdog2 = &watchdog_2;
+ hsi2c0 = &hsi2c_0;
+ hsi2c1 = &hsi2c_1;
+ hsi2c2 = &hsi2c_2;
+ hsi2c3 = &hsi2c_3;
+ hsi2c4 = &hsi2c_4;
+ hsi2c5 = &hsi2c_5;
+ hsi2c6 = &hsi2c_6;
+ hsi2c7 = &hsi2c_7;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpucl0_0>;
+ };
+ core1 {
+ cpu = <&cpucl0_1>;
+ };
+ core2 {
+ cpu = <&cpucl0_2>;
+ };
+ core3 {
+ cpu = <&cpucl0_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpucl1_0>;
+ };
+ core1 {
+ cpu = <&cpucl1_1>;
+ };
+ core2 {
+ cpu = <&cpucl1_2>;
+ };
+ core3 {
+ cpu = <&cpucl1_3>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpucl2_0>;
+ };
+ core1 {
+ cpu = <&cpucl2_1>;
+ };
+ core2 {
+ cpu = <&cpucl2_2>;
+ };
+ core3 {
+ cpu = <&cpucl2_3>;
+ };
+ };
+ };
+
+ /* Cluster 0 */
+ cpucl0_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x000>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl0_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x001>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl0_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x002>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl0_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x003>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ /* Cluster 1 */
+ cpucl1_0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl1_1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl1_2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl1_3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ /* Cluster 2 */
+ cpucl2_0: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl2_1: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x201>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl2_2: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x202>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpucl2_3: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x0 0x203>;
+ enable-method = "psci";
+ clock-frequency = <2400000000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2_0>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP: cpu-sleep {
+ idle-state-name = "c2";
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <30>;
+ exit-latency-us = <75>;
+ min-residency-us = <300>;
+ status = "okay";
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
+ <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
+ <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
+ <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_on = <0xC4000003>;
+ cpu_suspend = <0xC4000001>;
+ cpu_off = <0x84000002>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ fin_pll: clock {
+ compatible = "fixed-clock";
+ clock-output-names = "fin_pll";
+ #clock-cells = <0>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
+ dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
+
+ gic: interrupt-controller@10400000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
+ <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
+ };
+
+ smmu_isp: iommu@12100000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x12100000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <11>;
+ interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
+ /* Per context non-secure context interrupts, 0-7 interrupts */
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
+ status = "disabled";
+ };
+
+ smmu_imem: iommu@10200000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x10200000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <7>;
+ interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */
+ /* Per context non-secure context interrupts, 0-3 interrupts */
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
+ status = "disabled";
+ };
+
+ smmu_peric: iommu@14900000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x14900000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <5>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
+ /* Per context non-secure context interrupts, 0-1 interrupts */
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
+ status = "disabled";
+ };
+
+ smmu_fsys0: iommu@15450000 {
+ compatible = "arm,mmu-500";
+ reg = <0x0 0x15450000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <5>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
+ /* Performance counter interrupts */
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */
+ /* Per context non-secure context interrupts, 0-1 interrupts */
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
+ status = "disabled";
+ };
+
+ clock_cmu: clock-controller@11C10000 {
+ compatible = "tesla,fsd-clock-cmu";
+ reg = <0x0 0x11C10000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ status = "disabled";
+ };
+
+ clock_imem: clock-controller@10010000 {
+ compatible = "tesla,fsd-clock-imem";
+ reg = <0x0 0x10010000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
+ <&clock_cmu DOUT_CMU_IMEM_ACLK>,
+ <&clock_cmu DOUT_CMU_IMEM_DMACLK>;
+ clock-names = "fin_pll",
+ "dout_cmu_imem_tcuclk",
+ "dout_cmu_imem_aclk",
+ "dout_cmu_imem_dmaclk";
+ status = "disabled";
+ };
+
+ clock_peric: clock-controller@14010000 {
+ compatible = "tesla,fsd-clock-peric";
+ reg = <0x0 0x14010000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
+ <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
+ clock-names = "fin_pll",
+ "dout_cmu_pll_shared0_div4",
+ "dout_cmu_peric_shared1div36",
+ "dout_cmu_peric_shared0div3_tbuclk",
+ "dout_cmu_peric_shared0div20",
+ "dout_cmu_peric_shared1div4_dmaclk";
+ status = "disabled";
+ };
+
+ clock_fsys0: clock-controller@15010000 {
+ compatible = "tesla,fsd-clock-fsys0";
+ reg = <0x0 0x15010000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
+ <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
+ <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
+ clock-names = "fin_pll",
+ "dout_cmu_pll_shared0_div6",
+ "dout_cmu_fsys0_shared1div4",
+ "dout_cmu_fsys0_shared0div4";
+ status = "disabled";
+ };
+
+ clock_fsys1: clock-controller@16810000 {
+ compatible = "tesla,fsd-clock-fsys1";
+ reg = <0x0 0x16810000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
+ <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
+ clock-names = "fin_pll",
+ "dout_cmu_fsys1_shared0div8",
+ "dout_cmu_fsys1_shared0div4";
+ status = "disabled";
+ };
+
+ clock_mfc: clock-controller@12810000 {
+ compatible = "tesla,fsd-clock-mfc";
+ reg = <0x0 0x12810000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ status = "disabled";
+ };
+
+ clock_csi: clock-controller@12610000 {
+ compatible = "tesla,fsd-clock-cam_csi";
+ reg = <0x0 0x12610000 0x0 0x3000>;
+ #clock-cells = <1>;
+ clocks = <&fin_pll>;
+ clock-names = "fin_pll";
+ status = "disabled";
+ };
+
+ mdma0: mdma@10100000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x10100000 0x0 0x1000>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_imem 0x800 0x0>;
+ status = "disabled";
+ };
+
+ mdma1: mdma@10110000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x10110000 0x0 0x1000>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_imem 0x801 0x0>;
+ status = "disabled";
+ };
+
+ pdma0: pdma@14280000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x14280000 0x0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_peric 0x2 0x0>;
+ status = "disabled";
+ };
+
+ pdma1: pdma@14290000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x14290000 0x0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
+ clock-names = "apb_pclk";
+ iommus = <&smmu_peric 0x1 0x0>;
+ status = "disabled";
+ };
+
+ mct: mct@10040000 {
+ compatible = "samsung,exynos4210-mct";
+ reg = <0x0 0x10040000 0x0 0x800>;
+ interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
+ clock-names = "fin_pll", "mct";
+ };
+
+ serial_0: serial@14180000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x0 0x14180000 0x0 0x100>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 0>, <&pdma1 1>;
+ dma-names = "tx", "rx";
+ clocks = <&clock_peric PERIC_PCLK_UART0>,
+ <&clock_peric PERIC_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ serial_1: serial@14190000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x0 0x14190000 0x0 0x100>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 2>, <&pdma1 3>;
+ dma-names = "tx", "rx";
+ clocks = <&clock_peric PERIC_PCLK_UART1>,
+ <&clock_peric PERIC_SCLK_UART1>;
+ clock-names = "uart", "clk_uart_baud0";
+ status = "disabled";
+ };
+
+ pmu_system_controller: system-controller@11400000 {
+ compatible = "samsung,exynos7-pmu", "syscon";
+ reg = <0x0 0x11400000 0x0 0x5000>;
+ };
+
+ watchdog_0: watchdog@100A0000 {
+ compatible = "samsung,exynos7-wdt";
+ reg = <0x0 0x100A0000 0x0 0x100>;
+ interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ clocks = <&fin_pll>;
+ clock-names = "watchdog";
+ interrupt-mode = <1>;
+ };
+
+ watchdog_1: watchdog@100B0000 {
+ compatible = "samsung,exynos7-wdt";
+ reg = <0x0 0x100B0000 0x0 0x100>;
+ interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ clocks = <&fin_pll>;
+ clock-names = "watchdog";
+ interrupt-mode = <1>;
+ };
+
+ watchdog_2: watchdog@100C0000 {
+ compatible = "samsung,exynos7-wdt";
+ reg = <0x0 0x100C0000 0x0 0x100>;
+ interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+ samsung,syscon-phandle = <&pmu_system_controller>;
+ clocks = <&fin_pll>;
+ clock-names = "watchdog";
+ interrupt-mode = <1>;
+ };
+
+ pwm_0: pwm@14100000 {
+ compatible = "samsung,exynos4210-pwm";
+ reg = <0x0 0x14100000 0x0 0x100>;
+ samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+ #pwm-cells = <3>;
+ clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
+ clock-names = "timers";
+ status = "disabled";
+ };
+
+ pwm_1: pwm@14110000 {
+ compatible = "samsung,exynos4210-pwm";
+ reg = <0x0 0x14110000 0x0 0x100>;
+ samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+ #pwm-cells = <3>;
+ clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
+ clock-names = "timers";
+ status = "disabled";
+ };
+
+ hsi2c_0: hsi2c@14200000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14200000 0x0 0x1000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c0_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_1: hsi2c@14210000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14210000 0x0 0x1000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c1_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_2: hsi2c@14220000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14220000 0x0 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c2_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_3: hsi2c@14230000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14230000 0x0 0x1000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c3_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_4: hsi2c@14240000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14240000 0x0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c4_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_5: hsi2c@14250000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14250000 0x0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c5_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_6: hsi2c@14260000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14260000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c6_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+
+ hsi2c_7: hsi2c@14270000 {
+ compatible = "samsung,exynos7-hsi2c";
+ reg = <0x0 0x14270000 0x0 0x1000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hs_i2c7_bus>;
+ clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
+ clock-names = "hsi2c";
+ status = "disabled";
+ };
+ };
+};
--
2.17.1
Add initial pin configuration nodes for FSD SoC.
Cc: [email protected]
Signed-off-by: Shashank Prashar <[email protected]>
Signed-off-by: Aswani Reddy <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 338 +++++++++++++++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++
2 files changed, 360 insertions(+)
create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
new file mode 100644
index 000000000000..ec8d944af636
--- /dev/null
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Tesla Full Self-Driving SoC device tree source
+ *
+ * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
+ * https://www.samsung.com
+ * Copyright (c) 2017-2021 Tesla, Inc.
+ * https://www.tesla.com
+ */
+
+#include <dt-bindings/pinctrl/samsung.h>
+
+&pinctrl_fsys0 {
+
+ gpf0: gpf0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf1: gpf1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf6: gpf6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf4: gpf4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf5: gpf5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&pinctrl_peric {
+
+ gpc8: gpc8 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf2: gpf2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpf3: gpf3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb1: gpb1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb4: gpb4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb5: gpb5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb6: gpb6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpb7: gpb7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpd3: gpd3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg0: gpg0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg1: gpg1 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg2: gpg2 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg3: gpg3 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg4: gpg4 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg5: gpg5 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg6: gpg6 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpg7: gpg7 {
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pwm0_out: pwm0-out {
+ samsung,pins = "gpb6-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+ };
+
+ pwm1_out: pwm1-out {
+ samsung,pins = "gpb6-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
+ };
+
+ hs_i2c0_bus: hs-i2c0-bus {
+ samsung,pins = "gpb0-0", "gpb0-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c1_bus: hs-i2c1-bus {
+ samsung,pins = "gpb0-2", "gpb0-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c2_bus: hs-i2c2-bus {
+ samsung,pins = "gpb0-4", "gpb0-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c3_bus: hs-i2c3-bus {
+ samsung,pins = "gpb0-6", "gpb0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c4_bus: hs-i2c4-bus {
+ samsung,pins = "gpb1-0", "gpb1-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c5_bus: hs-i2c5-bus {
+ samsung,pins = "gpb1-2", "gpb1-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c6_bus: hs-i2c6-bus {
+ samsung,pins = "gpb1-4", "gpb1-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ hs_i2c7_bus: hs-i2c7-bus {
+ samsung,pins = "gpb1-6", "gpb1-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart0_data: uart0-data {
+ samsung,pins = "gpb7-0", "gpb7-1";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = "gpb7-4", "gpb7-5";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+
+ spi2_bus: spi2-bus {
+ samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
+ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
+ };
+};
+
+&pinctrl_pmu {
+
+ gpq0: gpq0 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 47cd9f20566e..811186e5ba4d 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -29,6 +29,9 @@
hsi2c5 = &hsi2c_5;
hsi2c6 = &hsi2c_6;
hsi2c7 = &hsi2c_7;
+ pinctrl0 = &pinctrl_fsys0;
+ pinctrl1 = &pinctrl_peric;
+ pinctrl2 = &pinctrl_pmu;
};
cpus {
@@ -711,5 +714,24 @@
clock-names = "hsi2c";
status = "disabled";
};
+
+ pinctrl_fsys0: pinctrl@15020000 {
+ compatible = "tesla,fsd-pinctrl";
+ reg = <0x0 0x15020000 0x0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_peric: pinctrl@141F0000 {
+ compatible = "tesla,fsd-pinctrl";
+ reg = <0x0 0x141F0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pinctrl_pmu: pinctrl@114F0000 {
+ compatible = "tesla,fsd-pinctrl";
+ reg = <0x0 0x114F0000 0x0 0x1000>;
+ };
};
};
+
+#include "fsd-pinctrl.dtsi"
--
2.17.1
This patch enables the Tesla FSD SoC in arm64 defconfig.
Cc: [email protected]
Signed-off-by: Alim Akhtar <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f2e2b9bdd702..6e6f26eb54ab 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -54,6 +54,7 @@ CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_INTEL_SOCFPGA=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TESLA_FSD=y
CONFIG_ARCH_SPRD=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_THUNDER2=y
--
2.17.1
This patch adds spi controller dt-binding compatible information for
Tesla Full Self-Driving SoC.
Cc: [email protected]
Signed-off-by: Adithya K V <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
Documentation/devicetree/bindings/spi/spi-samsung.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 49028a4f5df1..3af2408454b4 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -11,6 +11,7 @@ Required SoC Specific Properties:
- samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
- samsung,exynos5433-spi: for exynos5433 compatible controllers
- samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
+ - tesla,fsd-spi: spi controller support for Tesla Full Self-Driving SoC
- reg: physical base address of the controller and length of memory mapped
region.
--
2.17.1
This patch adds compatible and port configuration for
spi controller for Tesla Full Self-Driving SoC.
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Aswani Reddy <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/spi/spi-s3c64xx.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 8755cd85e83c..8d0c1f03ab7a 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1442,6 +1442,16 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
};
+static struct s3c64xx_spi_port_config fsd_spi_port_config = {
+ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
+ .rx_lvl_offset = 15,
+ .tx_st_done = 25,
+ .high_speed = true,
+ .clk_from_cmu = true,
+ .clk_ioclk = false,
+ .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
+};
+
static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
{
.name = "s3c2443-spi",
@@ -1472,6 +1482,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
{ .compatible = "samsung,exynos5433-spi",
.data = (void *)&exynos5433_spi_port_config,
},
+ { .compatible = "tesla,fsd-spi",
+ .data = (void *)&fsd_spi_port_config,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
--
2.17.1
From: Aswani Reddy <[email protected]>
This patch add device tree node for SPI IPs and needed
GPIO pin configurations needed for SPI IP
Cc: [email protected]
Signed-off-by: Aswani Reddy <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
arch/arm64/boot/dts/tesla/fsd.dts | 12 +++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 57 ++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts
index e9bbd3284de9..7f3bb6212e50 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dts
+++ b/arch/arm64/boot/dts/tesla/fsd.dts
@@ -138,3 +138,15 @@
&pdma1 {
status = "okay";
};
+
+&spi_0 {
+ status = "okay";
+};
+
+&spi_1 {
+ status = "okay";
+};
+
+&spi_2 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 811186e5ba4d..7e687c6f74f6 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -32,6 +32,9 @@
pinctrl0 = &pinctrl_fsys0;
pinctrl1 = &pinctrl_peric;
pinctrl2 = &pinctrl_pmu;
+ spi0 = &spi_0;
+ spi1 = &spi_1;
+ spi2 = &spi_2;
};
cpus {
@@ -731,6 +734,60 @@
compatible = "tesla,fsd-pinctrl";
reg = <0x0 0x114F0000 0x0 0x1000>;
};
+
+ spi_0: spi@14140000 {
+ compatible = "tesla,fsd-spi";
+ reg = <0x0 0x14140000 0x0 0x100>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 4>, <&pdma1 5>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric PERIC_PCLK_SPI0>,
+ <&clock_peric PERIC_SCLK_SPI0>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_bus>;
+ num-cs = <1>;
+ status = "disabled";
+ };
+
+ spi_1: spi@14150000 {
+ compatible = "tesla,fsd-spi";
+ reg = <0x0 0x14150000 0x0 0x100>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 6>, <&pdma1 7>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric PERIC_PCLK_SPI1>,
+ <&clock_peric PERIC_SCLK_SPI1>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_bus>;
+ num-cs = <1>;
+ status = "disabled";
+ };
+
+ spi_2: spi@14160000 {
+ compatible = "tesla,fsd-spi";
+ reg = <0x0 0x14160000 0x0 0x100>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma1 8>, <&pdma1 9>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock_peric PERIC_PCLK_SPI2>,
+ <&clock_peric PERIC_SCLK_SPI2>;
+ clock-names = "spi", "spi_busclk0";
+ samsung,spi-src-clk = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_bus>;
+ num-cs = <1>;
+ status = "disabled";
+ };
};
};
--
2.17.1
This patch adds a new compatible string for exynos's ADC-V3 variant.
Cc: [email protected]
Signed-off-by: Tamseel Shams <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
.../devicetree/bindings/iio/adc/samsung,exynos-adc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
index 81c87295912c..9303053759ca 100644
--- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
@@ -14,6 +14,7 @@ properties:
enum:
- samsung,exynos-adc-v1 # Exynos5250
- samsung,exynos-adc-v2
+ - samsung,exynos-adc-v3
- samsung,exynos3250-adc
- samsung,exynos4212-adc # Exynos4212 and Exynos4412
- samsung,exynos7-adc
--
2.17.1
Exynos's ADC-V3 has some difference in registers set, number of
programmable channels (16 channel) etc. This patch adds support for ADC-V3
controller version.
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Tamseel Shams <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/iio/adc/exynos_adc.c | 74 +++++++++++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 3b3868aa2533..61752e798fd6 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -55,6 +55,11 @@
#define ADC_V2_INT_ST(x) ((x) + 0x14)
#define ADC_V2_VER(x) ((x) + 0x20)
+/* ADC_V3 register definitions */
+#define ADC_V3_DAT(x) ((x) + 0x08)
+#define ADC_V3_DAT_SUM(x) ((x) + 0x0C)
+#define ADC_V3_DBG_DATA(x) ((x) + 0x1C)
+
/* Bit definitions for ADC_V1 */
#define ADC_V1_CON_RES (1u << 16)
#define ADC_V1_CON_PRSCEN (1u << 14)
@@ -92,6 +97,7 @@
/* Bit definitions for ADC_V2 */
#define ADC_V2_CON1_SOFT_RESET (1u << 2)
+#define ADC_V2_CON1_SOFT_NON_RESET (1u << 1)
#define ADC_V2_CON2_OSEL (1u << 10)
#define ADC_V2_CON2_ESEL (1u << 9)
@@ -100,6 +106,7 @@
#define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
#define ADC_V2_CON2_ACH_MASK 0xF
+#define MAX_ADC_V3_CHANNELS 16
#define MAX_ADC_V2_CHANNELS 10
#define MAX_ADC_V1_CHANNELS 8
#define MAX_EXYNOS3250_ADC_CHANNELS 2
@@ -164,6 +171,7 @@ struct exynos_adc_data {
void (*exit_hw)(struct exynos_adc *info);
void (*clear_irq)(struct exynos_adc *info);
void (*start_conv)(struct exynos_adc *info, unsigned long addr);
+ irqreturn_t (*adc_isr)(int irq, void *dev_id);
};
static void exynos_adc_unprepare_clk(struct exynos_adc *info)
@@ -484,6 +492,59 @@ static const struct exynos_adc_data exynos7_adc_data = {
.start_conv = exynos_adc_v2_start_conv,
};
+static void exynos_adc_v3_init_hw(struct exynos_adc *info)
+{
+ u32 con2;
+
+ writel(ADC_V2_CON1_SOFT_RESET, ADC_V2_CON1(info->regs));
+
+ writel(ADC_V2_CON1_SOFT_NON_RESET, ADC_V2_CON1(info->regs));
+
+ con2 = ADC_V2_CON2_C_TIME(6);
+ writel(con2, ADC_V2_CON2(info->regs));
+
+ /* Enable interrupts */
+ writel(1, ADC_V2_INT_EN(info->regs));
+}
+
+static void exynos_adc_v3_exit_hw(struct exynos_adc *info)
+{
+ u32 con2;
+
+ con2 = readl(ADC_V2_CON2(info->regs));
+ con2 &= ~ADC_V2_CON2_C_TIME(7);
+ writel(con2, ADC_V2_CON2(info->regs));
+
+ /* Disable interrupts */
+ writel(0, ADC_V2_INT_EN(info->regs));
+}
+
+static irqreturn_t exynos_adc_v3_isr(int irq, void *dev_id)
+{
+ struct exynos_adc *info = (struct exynos_adc *)dev_id;
+ u32 mask = info->data->mask;
+
+ info->value = readl(ADC_V3_DAT(info->regs)) & mask;
+
+ if (info->data->clear_irq)
+ info->data->clear_irq(info);
+
+ complete(&info->completion);
+
+ return IRQ_HANDLED;
+}
+
+static const struct exynos_adc_data exynos_adc_v3_adc_data = {
+ .num_channels = MAX_ADC_V3_CHANNELS,
+ .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
+
+ .init_hw = exynos_adc_v3_init_hw,
+ .exit_hw = exynos_adc_v3_exit_hw,
+ .clear_irq = exynos_adc_v2_clear_irq,
+ .start_conv = exynos_adc_v2_start_conv,
+ .adc_isr = exynos_adc_v3_isr,
+};
+
static const struct of_device_id exynos_adc_match[] = {
{
.compatible = "samsung,s3c2410-adc",
@@ -518,6 +579,9 @@ static const struct of_device_id exynos_adc_match[] = {
}, {
.compatible = "samsung,exynos7-adc",
.data = &exynos7_adc_data,
+ }, {
+ .compatible = "samsung,exynos-adc-v3",
+ .data = &exynos_adc_v3_adc_data,
},
{},
};
@@ -719,6 +783,12 @@ static const struct iio_chan_spec exynos_adc_iio_channels[] = {
ADC_CHANNEL(7, "adc7"),
ADC_CHANNEL(8, "adc8"),
ADC_CHANNEL(9, "adc9"),
+ ADC_CHANNEL(10, "adc10"),
+ ADC_CHANNEL(11, "adc11"),
+ ADC_CHANNEL(12, "adc12"),
+ ADC_CHANNEL(13, "adc13"),
+ ADC_CHANNEL(14, "adc14"),
+ ADC_CHANNEL(15, "adc15"),
};
static int exynos_adc_remove_devices(struct device *dev, void *c)
@@ -885,8 +955,8 @@ static int exynos_adc_probe(struct platform_device *pdev)
mutex_init(&info->lock);
- ret = request_irq(info->irq, exynos_adc_isr,
- 0, dev_name(&pdev->dev), info);
+ ret = request_irq(info->irq, info->data->adc_isr ? info->data->adc_isr :
+ exynos_adc_isr, 0, dev_name(&pdev->dev), info);
if (ret < 0) {
dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
info->irq);
--
2.17.1
This patch adds ADC device tree node and enables the same
on fsd platform.
Cc: [email protected]
Signed-off-by: Tamseel Shams <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
arch/arm64/boot/dts/tesla/fsd.dts | 4 ++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 11 +++++++++++
2 files changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts
index 7f3bb6212e50..dd6c75fc3221 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dts
+++ b/arch/arm64/boot/dts/tesla/fsd.dts
@@ -150,3 +150,7 @@
&spi_2 {
status = "okay";
};
+
+&adc {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 7e687c6f74f6..058a9d381aed 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -788,6 +788,17 @@
num-cs = <1>;
status = "disabled";
};
+
+ adc: adc@141A0000 {
+ compatible = "samsung,exynos-adc-v3";
+ reg = <0x0 0x141A0000 0x0 0x100>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_peric PERIC_PCLK_ADCIF>;
+ clock-names = "adc";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ status = "disabled";
+ };
};
};
--
2.17.1
From: Aswani Reddy <[email protected]>
This patch adds support for handling thress clusters
(upto 12 CPUs)
Cc: [email protected]
Signed-off-by: Aswani Reddy <[email protected]>
Signed-off-by: Alim Akhtar <[email protected]>
---
drivers/clocksource/exynos_mct.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 5e3e96d3d1b9..ba3af940a687 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -78,6 +78,10 @@ enum {
MCT_L5_IRQ,
MCT_L6_IRQ,
MCT_L7_IRQ,
+ MCT_L8_IRQ,
+ MCT_L9_IRQ,
+ MCT_L10_IRQ,
+ MCT_L11_IRQ,
MCT_NR_IRQS,
};
@@ -89,7 +93,7 @@ static int mct_irqs[MCT_NR_IRQS];
struct mct_clock_event_device {
struct clock_event_device evt;
unsigned long base;
- char name[10];
+ char name[11];
};
static void exynos4_mct_write(unsigned int value, unsigned long offset)
--
2.17.1
Add vendor prefix for the Tesla (https://www.tesla.com)
Cc: [email protected]
Signed-off-by: Alim Akhtar <[email protected]>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 66d6432fd781..af71d00f1092 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1189,6 +1189,8 @@ patternProperties:
description: Shenzhen Techstar Electronics Co., Ltd.
"^terasic,.*":
description: Terasic Inc.
+ "^tesla,.*":
+ description: Tesla, Inc.
"^tfc,.*":
description: Three Five Corp
"^thine,.*":
--
2.17.1
On 13/01/2022 13:11, Alim Akhtar wrote:
> Add compatible for Tesla Full Self-Driving SoC. The
> pinctrl hardware IP is similar to what found on most of the
> exynos series of SoC, so this new compatible is added in
> samsung pinctrl binding.
>
> Cc: [email protected]
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> index b8b475967ff9..ba972998a0e4 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> @@ -24,6 +24,7 @@ Required Properties:
> - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
> - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
> - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller.
> + - "tesla,fsd-pinctrl": for Tesla FSD SoC compatible pin-controller.
>
Please rebase this on my latest Samsung pinctrl dtschema patches. You
also need a tesla vendor prefix patch (separate).
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch set adds basic support for the Tesla Full Self-Driving (FSD)
> SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
> as well as several IPs.
>
> Patches 1 to 8 provide support for the clock controller
> (which is designed similarly to Exynos SoCs).
>
> The remaining changes provide pinmux support, initial device tree support,
> and SPI, ADC, and MCT IP functionality.
Does FSD have some version number? The FDS, especially in compatibles,
looks quite generic, so what will happen if a newer SoC comes later? You
would have:
- tesla,fsd-pinctrl
- tesla,fsd-xxxx-pinctrl (where xxxx could be some new version)
This will be extra confusing, because fsd-pinctrl looks like the generic
one, while it is specific...
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> Add device tree bindings for the Tesla FSD ARM SoC.
>
> Cc: [email protected]
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> .../devicetree/bindings/arm/tesla.yaml | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml b/Documentation/devicetree/bindings/arm/tesla.yaml
> new file mode 100644
> index 000000000000..9f89cde76c85
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tesla.yaml
> @@ -0,0 +1,25 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/tesla.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tesla Full Self Driving(FSD) platforms device tree bindings
> +
> +maintainers:
> + - Alim Akhtar <[email protected]>
> + - [email protected]
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> +
> + - description: FSD SoC board
> + items:
> + - const: tesla,fsd
Either this is a SoC or a board compatible... Cannot be both.
> +
> +additionalProperties: true
> +
> +...
>
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> Add dt-schema documentation for Tesla FSD SoC clock controller.
>
> Cc: [email protected]
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> .../bindings/clock/tesla,fsd-clock.yaml | 212 ++++++++++++++++++
> 1 file changed, 212 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
> new file mode 100644
> index 000000000000..58f341e5004d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
> @@ -0,0 +1,212 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tesla FSD (Full Self-Driving) SoC clock controller
> +
> +maintainers:
> + - Alim Akhtar <[email protected]>
> + - [email protected]
> +
> +description: |
> + FSD clock controller consist of several clock management unit
> + (CMU), which generates clocks for various inteernal SoC blocks.
> + The root clock comes from external OSC clock (24 MHz).
> +
> + All available clocks are defined as preprocessor macros in
> + 'dt-bindings/clock/fsd-clk.h' header.
> +
> +properties:
> + compatible:
> + enum:
> + - tesla,fsd-clock-cmu
> + - tesla,fsd-clock-imem
> + - tesla,fsd-clock-peric
> + - tesla,fsd-clock-fsys0
> + - tesla,fsd-clock-fsys1
> + - tesla,fsd-clock-mfc
> + - tesla,fsd-clock-cam_csi
> +
> + clocks:
> + minItems: 1
> + maxItems: 6
> +
> + clock-names:
> + minItems: 1
> + maxItems: 6
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: tesla,fsd-clock-cmu
> +
Nitpick: Drop the white-spaces between if-then. It's easier to spot the
if-blocks if they are together.
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (24 MHz)
> +
Drop this whitespace as well.
Rest looks good to me, except the discussion about the compatible.
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> Add initial clock support for FSD (Full Self-Driving) SoC
> which is required to bring-up platforms based on this SoC.
>
> Cc: [email protected]
> Signed-off-by: Jayati Sahu <[email protected]>
> Signed-off-by: Ajay Kumar <[email protected]>
> Signed-off-by: Pankaj Dubey <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-fsd.c | 308 ++++++++++++++++++++++++++++++++++
> drivers/clk/samsung/clk-pll.c | 1 +
> drivers/clk/samsung/clk-pll.h | 1 +
> 4 files changed, 311 insertions(+)
> create mode 100644 drivers/clk/samsung/clk-fsd.c
>
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index c46cf11e4d0b..d66b2ede004c 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o
> obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
> +obj-$(CONFIG_ARCH_TESLA_FSD) += clk-fsd.o
It should be rather it's own CONFIG_TESLA_FSD_CLK option, just like
other Exynos designs. This keeps unified approach with existing Samsung
clock Kconfig.
> obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
> obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
> obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
> diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
> new file mode 100644
> index 000000000000..e47523106d9e
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-fsd.c
> @@ -0,0 +1,308 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Common Clock Framework support for FSD SoC.
> + *
> + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
> + * https://www.samsung.com
> + * Copyright (c) 2017-2022 Tesla, Inc.
> + * https://www.tesla.com
> + *
Drop the line break with empty * comment.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +
> +#include "clk.h"
> +#include <dt-bindings/clock/fsd-clk.h>
dt-bindings headers before local clk.h.
> +
> +/* Register Offset definitions for CMU_CMU (0x11c10000) */
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch adds CMU_PERIC block clock information needed
> for various IPs functions found in this block.
Here and in all other commits, please do not use "This patch". Instead:
https://elixir.bootlin.com/linux/v5.13/source/Documentation/process/submitting-patches.rst#L89
>
> Cc: [email protected]
> Signed-off-by: Aswani Reddy <[email protected]>
> Signed-off-by: Niyas Ahmed S T <[email protected]>
> Signed-off-by: Chandrasekar R <[email protected]>
> Signed-off-by: Jayati Sahu <[email protected]>
> Signed-off-by: Sriranjani P <[email protected]>
> Signed-off-by: Ajay Kumar <[email protected]>
> Signed-off-by: Pankaj Dubey <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> drivers/clk/samsung/clk-fsd.c | 464 +++++++++++++++++++++++++++++++++-
> 1 file changed, 463 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
> index e47523106d9e..6da20966ba99 100644
> --- a/drivers/clk/samsung/clk-fsd.c
> +++ b/drivers/clk/samsung/clk-fsd.c
> @@ -9,12 +9,59 @@
> *
> */
>
> -#include <linux/clk-provider.h>
> #include <linux/of.h>
> +#include <linux/clk.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
Please order the includes alphabetically.
>
> #include "clk.h"
> #include <dt-bindings/clock/fsd-clk.h>
>
> +/* Gate register bits */
> +#define GATE_MANUAL BIT(20)
> +#define GATE_ENABLE_HWACG BIT(28)
> +
> +/* Gate register offsets range */
> +#define GATE_OFF_START 0x2000
> +#define GATE_OFF_END 0x2fff
> +
> +/**
> + * fsd_init_clocks - Set clocks initial configuration
> + * @np: CMU device tree node with "reg" property (CMU addr)
> + * @reg_offs: Register offsets array for clocks to init
> + * @reg_offs_len: Number of register offsets in reg_offs array
> + *
> + * Set manual control mode for all gate clocks.
> + */
> +static void __init fsd_init_clocks(struct device_node *np,
> + const unsigned long *reg_offs, size_t reg_offs_len)
The same as exynos_arm64_init_clocks - please re-use instead of duplicating.
> +{
> + void __iomem *reg_base;
> + size_t i;
> +
> + reg_base = of_iomap(np, 0);
> + if (!reg_base)
> + panic("%s: failed to map registers\n", __func__);
> +
> + for (i = 0; i < reg_offs_len; ++i) {
> + void __iomem *reg = reg_base + reg_offs[i];
> + u32 val;
> +
> + /* Modify only gate clock registers */
> + if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
> + continue;
> +
> + val = readl(reg);
> + val |= GATE_MANUAL;
> + val &= ~GATE_ENABLE_HWACG;
> + writel(val, reg);
> + }
> +
> + iounmap(reg_base);
> +}
> +
(...)
> +/**
> + * fsd_cmu_probe - Probe function for FSD platform clocks
> + * @pdev: Pointer to platform device
> + *
> + * Configure clock hierarchy for clock domains of FSD platform
> + */
> +static int __init fsd_cmu_probe(struct platform_device *pdev)
> +{
> + const struct samsung_cmu_info *info;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> +
> + info = of_device_get_match_data(dev);
> + fsd_init_clocks(np, info->clk_regs, info->nr_clk_regs);
> + samsung_cmu_register_one(np, info);
> +
> + /* Keep bus clock running, so it's possible to access CMU registers */
> + if (info->clk_name) {
> + struct clk *bus_clk;
> +
> + bus_clk = clk_get(dev, info->clk_name);
> + if (IS_ERR(bus_clk)) {
> + pr_err("%s: could not find bus clock %s; err = %ld\n",
> + __func__, info->clk_name, PTR_ERR(bus_clk));
> + } else {
> + clk_prepare_enable(bus_clk);
> + }
> + }
> +
> + return 0;
> +}
Please re-use exynos_arm64_register_cmu(). This will also solve my
previous comment about exynos_arm64_init_clocks().
> +
> +/* CMUs which belong to Power Domains and need runtime PM to be implemented */
> +static const struct of_device_id fsd_cmu_of_match[] = {
> + {
> + .compatible = "tesla,fsd-clock-peric",
> + .data = &peric_cmu_info,
> + }, {
> + },
> +};
> +
> +static struct platform_driver fsd_cmu_driver __refdata = {
> + .driver = {
> + .name = "fsd-cmu",
> + .of_match_table = fsd_cmu_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = fsd_cmu_probe,
> +};
> +
> +static int __init fsd_cmu_init(void)
> +{
> + return platform_driver_register(&fsd_cmu_driver);
> +}
> +core_initcall(fsd_cmu_init);
>
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch adds Tesla FSD SoC specific data to enable pinctrl.
> FSD SoC has similar pinctrl controller as found in the most
> samsung/exynos SoCs.
>
> Cc: [email protected]
> Signed-off-by: Ajay Kumar <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 71 +++++++++++++++++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
> 3 files changed, 74 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index 6b77fd24571e..b9175b4911ac 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -646,3 +646,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
> .ctrl = exynosautov9_pin_ctrl,
> .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
> };
> +
> +/*
> + * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
> + * gpio/pin-mux/pinconfig controllers.
> + */
> +
> +/* pin banks of FSD pin-controller 0 (FSYS) */
> +static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04),
> + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08),
> + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c),
> + EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10),
> +};
> +
> +/* pin banks of FSD pin-controller 1 (PERIC) */
> +static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00),
> + EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18),
> + EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24),
> + EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28),
> + EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
> + EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c),
> + EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50),
> +};
> +
> +/* pin banks of FSD pin-controller 2 (PMU) */
> +static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = {
> + EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
> +};
> +
> +const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
> + {
> + /* pin-controller instance 0 FSYS0 data */
> + .pin_banks = fsd_pin_banks0,
> + .nr_banks = ARRAY_SIZE(fsd_pin_banks0),
No wake-up interrupts (eint_wkup_init)? It's fine not to have them but
just looks incomplete.
In general looks ok, except discussion about compatibles.
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> Add vendor prefix for the Tesla (https://www.tesla.com)
>
> Cc: [email protected]
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(
This should be the first patch in the series.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> Add initial device tree support for "Full Self-Driving" (FSD) SoC
> This SoC contain three clusters of four cortex-a72 CPUs and various
> peripheral IPs.
>
> Cc: [email protected]
> Signed-off-by: Arjun K V <[email protected]>
> Signed-off-by: Aswani Reddy <[email protected]>
> Signed-off-by: Ajay Kumar <[email protected]>
> Signed-off-by: Sriranjani P <[email protected]>
> Signed-off-by: Chandrasekar R <[email protected]>
> Signed-off-by: Shashank Prashar <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> MAINTAINERS | 8 +
> arch/arm64/Kconfig.platforms | 6 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/tesla/Makefile | 3 +
> arch/arm64/boot/dts/tesla/fsd.dts | 140 ++++++
> arch/arm64/boot/dts/tesla/fsd.dtsi | 715 +++++++++++++++++++++++++++++
> 6 files changed, 873 insertions(+)
> create mode 100644 arch/arm64/boot/dts/tesla/Makefile
> create mode 100644 arch/arm64/boot/dts/tesla/fsd.dts
> create mode 100644 arch/arm64/boot/dts/tesla/fsd.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fb18ce7168aa..02d56909c5e2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2726,6 +2726,14 @@ S: Maintained
> F: Documentation/devicetree/bindings/media/tegra-cec.txt
> F: drivers/media/cec/platform/tegra/
>
> +ARM/TESLA FSD SoC SUPPORT
> +M: Alim Akhtar <[email protected]>
> +M: [email protected]
> +L: [email protected] (moderated for non-subscribers)
> +L: [email protected]
> +S: Maintained
> +F: arch/arm64/boot/dts/tesla*
> +
+Cc Arnd,
Please Cc all SoC maintainers in new sub-architecture submissions, so
Olof and Arnd.
> ARM/TETON BGA MACHINE SUPPORT
> M: "Mark F. Brown" <[email protected]>
> L: [email protected] (moderated for non-subscribers)
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 54e3910e8b9b..bb8a047c2359 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -267,6 +267,12 @@ config ARCH_TEGRA
> help
> This enables support for the NVIDIA Tegra SoC family.
>
> +config ARCH_TESLA_FSD
> + bool "ARMv8 based Tesla platform"
> + select ARCH_EXYNOS
How similar it is? I think it is better to duplicate Exynos
selections/options here, instead of selecting entire ARCH. If this would
require "depends on ARCH_EXYNOS || ARCH_TESLA_FSD" everywhere in the
drivers, it's a hint that it is not a separate SoC but it is an Exynos,
so it might not need a new sub-architecture.
> + help
> + Support for ARMv8 based Tesla platforms.
> +
> config ARCH_SPRD
> bool "Spreadtrum SoC platform"
> help
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 639e01a4d855..1ba04e31a438 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -27,6 +27,7 @@ subdir-y += rockchip
> subdir-y += socionext
> subdir-y += sprd
> subdir-y += synaptics
> +subdir-y += tesla
> subdir-y += ti
> subdir-y += toshiba
> subdir-y += xilinx
> diff --git a/arch/arm64/boot/dts/tesla/Makefile b/arch/arm64/boot/dts/tesla/Makefile
> new file mode 100644
> index 000000000000..a9818cda6b08
> --- /dev/null
> +++ b/arch/arm64/boot/dts/tesla/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_TESLA_FSD) += \
> + fsd.dtb
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts
> new file mode 100644
> index 000000000000..e9bbd3284de9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/tesla/fsd.dts
No, this is not a fsd.dts, but some board. You call FSD a SoC, so this
should have different name.
> @@ -0,0 +1,140 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Tesla FSD board device tree source
> + *
> + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
> + * https://www.samsung.com
> + * Copyright (c) 2017-2021 Tesla, Inc.
> + * https://www.tesla.com
> + */
> +
> +/dts-v1/;
> +#include "fsd.dtsi"
> +
> +/ {
> + model = "Tesla Full Self-Driving (FSD) SoC";
Wrong model, this is DTS, not DTSI.
> + compatible = "tesla,fsd";
Missing compatible for board.
> +
> + aliases {
> + serial0 = &serial_0;
> + serial1 = &serial_1;
> + };
> +
> + chosen {
> + stdout-path = &serial_0;
> + linux,initrd-start = <0xE0000000>;
> + linux,initrd-end = <0xE4F00000>;
> + bootargs = "console=ttySAC0,115200n8
> + earlycon=exynos4210,0x14180000 root=/dev/ram0
> + init=/linuxrc";
These are not bootargs matching SoC. earlycon is purely a debug option.
console is duplicating stdout-path. root and init are also not a part of
DTSI or DTS.
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x2 0x00000000>;
> + };
> +};
> +
> +&fin_pll {
> + clock-frequency = <24000000>;
> +};
> +
> +&serial_0 {
> + status = "okay";
> +};
> +
> +&serial_1 {
> + status = "okay";
> +};
> +
> +&clock_cmu {
> + status = "okay";
> +};
> +
> +&clock_imem {
> + status = "okay";
> +};
> +
> +&clock_peric {
> + status = "okay";
> +};
The labels/overrides are with weird order... looks like a mess. Anyway,
clocks should be always enabled, why board has to enable them?
> +
> +&smmu_isp {
> + status = "okay";
> +};
> +
> +&clock_fsys0 {
> + status = "okay";
> +};
> +
> +&clock_fsys1 {
> + status = "okay";
> +};
> +
> +&smmu_peric {
> + status = "okay";
The same as clocks.
> +};
> +
> +&smmu_imem {
> + status = "okay";
> +};
> +
> +&smmu_fsys0 {
> + status = "okay";
> +};
> +
> +&hsi2c_0 {
> + status = "okay";
This looks wrong. There is nothing attached.
> +};
> +
> +&hsi2c_1 {
> + status = "okay";
Same here and other I2C.
> +};
> +
> +&hsi2c_2 {
> + status = "okay";
> +};
> +
> +&hsi2c_3 {
> + status = "okay";
> +};
> +
> +&hsi2c_4 {
> + status = "okay";
> +};
> +
> +&hsi2c_5 {
> + status = "okay";
> +};
> +
> +&hsi2c_6 {
> + status = "okay";
> +};
> +
> +&hsi2c_7 {
> + status = "okay";
> +};
> +
> +&pwm_0 {
> + status = "okay";
Nope, nope.
> +};
> +
> +&pwm_1 {
> + status = "okay";
> +};
> +
> +&mdma0 {
> + status = "okay";
Can you imagine SoC with disabled DMA?
> +};
> +
> +&mdma1 {
> + status = "okay";
> +};
> +
> +&pdma0 {
> + status = "okay";
> +};
> +
> +&pdma1 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
> new file mode 100644
> index 000000000000..47cd9f20566e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -0,0 +1,715 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Tesla Full Self-Driving SoC device tree source
> + *
> + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
> + * https://www.samsung.com
> + * Copyright (c) 2017-2022 Tesla, Inc.
> + * https://www.tesla.com
> + */
> +
> +#include <dt-bindings/clock/fsd-clk.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "tesla,fsd";
Same compatible as board - nope.
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + watchdog0 = &watchdog_0;
> + watchdog1 = &watchdog_1;
> + watchdog2 = &watchdog_2;
I think watchdogs do not need/use aliases.
> + hsi2c0 = &hsi2c_0;
> + hsi2c1 = &hsi2c_1;
> + hsi2c2 = &hsi2c_2;
> + hsi2c3 = &hsi2c_3;
> + hsi2c4 = &hsi2c_4;
> + hsi2c5 = &hsi2c_5;
> + hsi2c6 = &hsi2c_6;
> + hsi2c7 = &hsi2c_7;
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpucl0_0>;
> + };
> + core1 {
> + cpu = <&cpucl0_1>;
> + };
> + core2 {
> + cpu = <&cpucl0_2>;
> + };
> + core3 {
> + cpu = <&cpucl0_3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpucl1_0>;
> + };
> + core1 {
> + cpu = <&cpucl1_1>;
> + };
> + core2 {
> + cpu = <&cpucl1_2>;
> + };
> + core3 {
> + cpu = <&cpucl1_3>;
> + };
> + };
> +
> + cluster2 {
> + core0 {
> + cpu = <&cpucl2_0>;
> + };
> + core1 {
> + cpu = <&cpucl2_1>;
> + };
> + core2 {
> + cpu = <&cpucl2_2>;
> + };
> + core3 {
> + cpu = <&cpucl2_3>;
> + };
> + };
> + };
> +
> + /* Cluster 0 */
> + cpucl0_0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x000>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl0_1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x001>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl0_2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x002>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl0_3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x003>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + /* Cluster 1 */
> + cpucl1_0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl1_1: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl1_2: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x102>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl1_3: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x103>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + /* Cluster 2 */
> + cpucl2_0: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl2_1: cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x201>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl2_2: cpu@202 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x202>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpucl2_3: cpu@203 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0 0x203>;
> + enable-method = "psci";
> + clock-frequency = <2400000000>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_SLEEP: cpu-sleep {
> + idle-state-name = "c2";
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <30>;
> + exit-latency-us = <75>;
> + min-residency-us = <300>;
> + status = "okay";
No need for status.
> + };
> + };
> +
> + L2_0: l2-cache0 {
lowercase letters in label.
> + compatible = "cache";
You miss here some properties. Does your DTSI/DTS pass dtschema validation?
> + };
> + };
> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
> + <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
> + <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
> + <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
> + };
> +
> + psci {
> + compatible = "arm,psci";
> + method = "smc";
> + cpu_on = <0xC4000003>;
> + cpu_suspend = <0xC4000001>;
> + cpu_off = <0x84000002>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
Not sure - don't you need CPU mask?
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + fin_pll: clock {
> + compatible = "fixed-clock";
> + clock-output-names = "fin_pll";
> + #clock-cells = <0>;
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
> + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> +
> + gic: interrupt-controller@10400000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
> + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
> + };
> +
> + smmu_isp: iommu@12100000 {
> + compatible = "arm,mmu-500";
> + reg = <0x0 0x12100000 0x0 0x10000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <11>;
> + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
> + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
> + /* Performance counter interrupts */
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
> + /* Per context non-secure context interrupts, 0-7 interrupts */
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
> + status = "disabled";
> + };
> +
> + smmu_imem: iommu@10200000 {
> + compatible = "arm,mmu-500";
> + reg = <0x0 0x10200000 0x0 0x10000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <7>;
> + interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
> + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
> + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
> + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
> + /* Performance counter interrupts */
> + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
> + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
> + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */
> + /* Per context non-secure context interrupts, 0-3 interrupts */
> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
> + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
> + <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
> + status = "disabled";
> + };
> +
> + smmu_peric: iommu@14900000 {
> + compatible = "arm,mmu-500";
> + reg = <0x0 0x14900000 0x0 0x10000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <5>;
> + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
> + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
> + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
> + /* Performance counter interrupts */
> + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
> + /* Per context non-secure context interrupts, 0-1 interrupts */
> + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
> + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
> + status = "disabled";
> + };
> +
> + smmu_fsys0: iommu@15450000 {
> + compatible = "arm,mmu-500";
> + reg = <0x0 0x15450000 0x0 0x10000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <5>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
> + /* Performance counter interrupts */
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */
> + /* Per context non-secure context interrupts, 0-1 interrupts */
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
> + status = "disabled";
> + };
> +
> + clock_cmu: clock-controller@11C10000 {
> + compatible = "tesla,fsd-clock-cmu";
> + reg = <0x0 0x11C10000 0x0 0x3000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>;
> + clock-names = "fin_pll";
> + status = "disabled";
This explains why DTS has to enable basic SoC features... why do you
disable your clock controllers?
> + };
> +
> + clock_imem: clock-controller@10010000 {
> + compatible = "tesla,fsd-clock-imem";
> + reg = <0x0 0x10010000 0x0 0x3000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
> + <&clock_cmu DOUT_CMU_IMEM_ACLK>,
> + <&clock_cmu DOUT_CMU_IMEM_DMACLK>;
> + clock-names = "fin_pll",
> + "dout_cmu_imem_tcuclk",
> + "dout_cmu_imem_aclk",
> + "dout_cmu_imem_dmaclk";
> + status = "disabled";
> + };
> +
> + clock_peric: clock-controller@14010000 {
> + compatible = "tesla,fsd-clock-peric";
> + reg = <0x0 0x14010000 0x0 0x3000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
> + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
> + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
> + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
> + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
> + clock-names = "fin_pll",
> + "dout_cmu_pll_shared0_div4",
> + "dout_cmu_peric_shared1div36",
> + "dout_cmu_peric_shared0div3_tbuclk",
> + "dout_cmu_peric_shared0div20",
> + "dout_cmu_peric_shared1div4_dmaclk";
> + status = "disabled";
> + };
> +
> + clock_fsys0: clock-controller@15010000 {
> + compatible = "tesla,fsd-clock-fsys0";
> + reg = <0x0 0x15010000 0x0 0x3000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
> + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
> + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
> + clock-names = "fin_pll",
> + "dout_cmu_pll_shared0_div6",
> + "dout_cmu_fsys0_shared1div4",
> + "dout_cmu_fsys0_shared0div4";
> + status = "disabled";
> + };
> +
> + clock_fsys1: clock-controller@16810000 {
> + compatible = "tesla,fsd-clock-fsys1";
> + reg = <0x0 0x16810000 0x0 0x3000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>,
> + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
> + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
> + clock-names = "fin_pll",
> + "dout_cmu_fsys1_shared0div8",
> + "dout_cmu_fsys1_shared0div4";
> + status = "disabled";
> + };
> +
> + clock_mfc: clock-controller@12810000 {
> + compatible = "tesla,fsd-clock-mfc";
> + reg = <0x0 0x12810000 0x0 0x3000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>;
> + clock-names = "fin_pll";
> + status = "disabled";
> + };
> +
> + clock_csi: clock-controller@12610000 {
> + compatible = "tesla,fsd-clock-cam_csi";
> + reg = <0x0 0x12610000 0x0 0x3000>;
> + #clock-cells = <1>;
> + clocks = <&fin_pll>;
> + clock-names = "fin_pll";
> + status = "disabled";
> + };
> +
> + mdma0: mdma@10100000 {
Node name: just dma to be generic. Schema does not enforce it but might
at some point.
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x0 0x10100000 0x0 0x1000>;
> + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
> + clock-names = "apb_pclk";
> + iommus = <&smmu_imem 0x800 0x0>;
> + status = "disabled";
> + };
> +
> + mdma1: mdma@10110000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x0 0x10110000 0x0 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
> + clock-names = "apb_pclk";
> + iommus = <&smmu_imem 0x801 0x0>;
> + status = "disabled";
> + };
> +
> + pdma0: pdma@14280000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x0 0x14280000 0x0 0x1000>;
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
> + clock-names = "apb_pclk";
> + iommus = <&smmu_peric 0x2 0x0>;
> + status = "disabled";
> + };
> +
> + pdma1: pdma@14290000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x0 0x14290000 0x0 0x1000>;
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
> + clock-names = "apb_pclk";
> + iommus = <&smmu_peric 0x1 0x0>;
> + status = "disabled";
> + };
> +
> + mct: mct@10040000 {
> + compatible = "samsung,exynos4210-mct";
> + reg = <0x0 0x10040000 0x0 0x800>;
> + interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
> + clock-names = "fin_pll", "mct";
> + };
> +
> + serial_0: serial@14180000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x0 0x14180000 0x0 0x100>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&pdma1 0>, <&pdma1 1>;
> + dma-names = "tx", "rx";
> + clocks = <&clock_peric PERIC_PCLK_UART0>,
> + <&clock_peric PERIC_SCLK_UART0>;
> + clock-names = "uart", "clk_uart_baud0";
> + status = "disabled";
> + };
> +
> + serial_1: serial@14190000 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x0 0x14190000 0x0 0x100>;
> + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&pdma1 2>, <&pdma1 3>;
> + dma-names = "tx", "rx";
> + clocks = <&clock_peric PERIC_PCLK_UART1>,
> + <&clock_peric PERIC_SCLK_UART1>;
> + clock-names = "uart", "clk_uart_baud0";
> + status = "disabled";
> + };
> +
> + pmu_system_controller: system-controller@11400000 {
> + compatible = "samsung,exynos7-pmu", "syscon";
> + reg = <0x0 0x11400000 0x0 0x5000>;
> + };
> +
> + watchdog_0: watchdog@100A0000 {
lowercase hex addresses. Here, in reg below and all other nodes.
> + compatible = "samsung,exynos7-wdt";
> + reg = <0x0 0x100A0000 0x0 0x100>;
> + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
> + samsung,syscon-phandle = <&pmu_system_controller>;
> + clocks = <&fin_pll>;
> + clock-names = "watchdog";
> + interrupt-mode = <1>;
This property looks unsupported. Did you run dtschema checks?
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> Add initial pin configuration nodes for FSD SoC.
>
> Cc: [email protected]
> Signed-off-by: Shashank Prashar <[email protected]>
> Signed-off-by: Aswani Reddy <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 338 +++++++++++++++++++++
> arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++
> 2 files changed, 360 insertions(+)
> create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>
> diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> new file mode 100644
> index 000000000000..ec8d944af636
> --- /dev/null
> +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
> @@ -0,0 +1,338 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Tesla Full Self-Driving SoC device tree source
> + *
> + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
> + * https://www.samsung.com
> + * Copyright (c) 2017-2021 Tesla, Inc.
> + * https://www.tesla.com
> + */
> +
> +#include <dt-bindings/pinctrl/samsung.h>
> +
> +&pinctrl_fsys0 {
> +
No need for empty line.
> + gpf0: gpf0 {
FYI:
It's ok now, but the nodes will have to be renamed to "xxx-gpio-bank" later.
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf1: gpf1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf6: gpf6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf4: gpf4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf5: gpf5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_peric {
> +
No need for empty line.
> + gpc8: gpc8 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf2: gpf2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf3: gpf3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd0: gpd0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb0: gpb0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb1: gpb1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb4: gpb4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb5: gpb5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb6: gpb6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb7: gpb7 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd1: gpd1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd2: gpd2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd3: gpd3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg0: gpg0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg1: gpg1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg2: gpg2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg3: gpg3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg4: gpg4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg5: gpg5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg6: gpg6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg7: gpg7 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + pwm0_out: pwm0-out {
All pin configuretion node names with "-pins" suffix. Upcoming dtschema
will require this.
> + samsung,pins = "gpb6-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> + };
> +
> + pwm1_out: pwm1-out {
> + samsung,pins = "gpb6-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
> + };
> +
> + hs_i2c0_bus: hs-i2c0-bus {
> + samsung,pins = "gpb0-0", "gpb0-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + hs_i2c1_bus: hs-i2c1-bus {
> + samsung,pins = "gpb0-2", "gpb0-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + hs_i2c2_bus: hs-i2c2-bus {
> + samsung,pins = "gpb0-4", "gpb0-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + hs_i2c3_bus: hs-i2c3-bus {
> + samsung,pins = "gpb0-6", "gpb0-7";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + hs_i2c4_bus: hs-i2c4-bus {
> + samsung,pins = "gpb1-0", "gpb1-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + hs_i2c5_bus: hs-i2c5-bus {
> + samsung,pins = "gpb1-2", "gpb1-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + hs_i2c6_bus: hs-i2c6-bus {
> + samsung,pins = "gpb1-4", "gpb1-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + hs_i2c7_bus: hs-i2c7-bus {
> + samsung,pins = "gpb1-6", "gpb1-7";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + uart0_data: uart0-data {
> + samsung,pins = "gpb7-0", "gpb7-1";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + uart1_data: uart1-data {
> + samsung,pins = "gpb7-4", "gpb7-5";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + spi0_bus: spi0-bus {
> + samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + spi1_bus: spi1-bus {
> + samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +
> + spi2_bus: spi2-bus {
> + samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
> + };
> +};
> +
> +&pinctrl_pmu {
> +
No need for empty line.
> + gpq0: gpq0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch adds spi controller dt-binding compatible information for
> Tesla Full Self-Driving SoC.
>
> Cc: [email protected]
> Signed-off-by: Adithya K V <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> Documentation/devicetree/bindings/spi/spi-samsung.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Please rebase on upcoming Samsung SPI dtschema patches.
> diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
> index 49028a4f5df1..3af2408454b4 100644
> --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
> @@ -11,6 +11,7 @@ Required SoC Specific Properties:
> - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
> - samsung,exynos5433-spi: for exynos5433 compatible controllers
> - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
> + - tesla,fsd-spi: spi controller support for Tesla Full Self-Driving SoC
Compatible - same discussions/questions as with other ones.
>
> - reg: physical base address of the controller and length of memory mapped
> region.
>
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch adds spi controller dt-binding compatible information for
> Tesla Full Self-Driving SoC.
>
> Cc: [email protected]
> Signed-off-by: Adithya K V <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> Documentation/devicetree/bindings/spi/spi-samsung.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Also: subject prefix:
spi: dt-bindings: samsung:
> diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
> index 49028a4f5df1..3af2408454b4 100644
> --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
> +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
> @@ -11,6 +11,7 @@ Required SoC Specific Properties:
> - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
> - samsung,exynos5433-spi: for exynos5433 compatible controllers
> - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
> + - tesla,fsd-spi: spi controller support for Tesla Full Self-Driving SoC
>
> - reg: physical base address of the controller and length of memory mapped
> region.
>
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch adds compatible and port configuration for
> spi controller for Tesla Full Self-Driving SoC.
>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Aswani Reddy <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> drivers/spi/spi-s3c64xx.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index 8755cd85e83c..8d0c1f03ab7a 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -1442,6 +1442,16 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
> .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> };
>
> +static struct s3c64xx_spi_port_config fsd_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .high_speed = true,
> + .clk_from_cmu = true,
> + .clk_ioclk = false,
> + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> +};
> +
> static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
> {
> .name = "s3c2443-spi",
> @@ -1472,6 +1482,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
> { .compatible = "samsung,exynos5433-spi",
> .data = (void *)&exynos5433_spi_port_config,
> },
> + { .compatible = "tesla,fsd-spi",
> + .data = (void *)&fsd_spi_port_config,
> + },
Looks good, except the discussion about too generic compatible.
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> From: Aswani Reddy <[email protected]>
>
> This patch add device tree node for SPI IPs and needed
> GPIO pin configurations needed for SPI IP
>
> Cc: [email protected]
> Signed-off-by: Aswani Reddy <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> arch/arm64/boot/dts/tesla/fsd.dts | 12 +++++++
> arch/arm64/boot/dts/tesla/fsd.dtsi | 57 ++++++++++++++++++++++++++++++
> 2 files changed, 69 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch adds a new compatible string for exynos's ADC-V3 variant.
>
> Cc: [email protected]
> Signed-off-by: Tamseel Shams <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> .../devicetree/bindings/iio/adc/samsung,exynos-adc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
> index 81c87295912c..9303053759ca 100644
> --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
> @@ -14,6 +14,7 @@ properties:
> enum:
> - samsung,exynos-adc-v1 # Exynos5250
> - samsung,exynos-adc-v2
> + - samsung,exynos-adc-v3
Please use SoC-specific compatible. IP block versions are tricky because:
1. Documentation/datasheet mentioning which SoC has which block version
are not public.
2. Neither are public the datasheets for ADC blocks.
3. The versioning of IP blocks can be inaccurate.
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> This patch adds ADC device tree node and enables the same
> on fsd platform.
>
> Cc: [email protected]
> Signed-off-by: Tamseel Shams <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> arch/arm64/boot/dts/tesla/fsd.dts | 4 ++++
> arch/arm64/boot/dts/tesla/fsd.dtsi | 11 +++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dts b/arch/arm64/boot/dts/tesla/fsd.dts
> index 7f3bb6212e50..dd6c75fc3221 100644
> --- a/arch/arm64/boot/dts/tesla/fsd.dts
> +++ b/arch/arm64/boot/dts/tesla/fsd.dts
> @@ -150,3 +150,7 @@
> &spi_2 {
> status = "okay";
> };
> +
> +&adc {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
> index 7e687c6f74f6..058a9d381aed 100644
> --- a/arch/arm64/boot/dts/tesla/fsd.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -788,6 +788,17 @@
> num-cs = <1>;
> status = "disabled";
> };
> +
> + adc: adc@141A0000 {
lowercase hex numbers please.
> + compatible = "samsung,exynos-adc-v3";
> + reg = <0x0 0x141A0000 0x0 0x100>;
> + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clock_peric PERIC_PCLK_ADCIF>;
> + clock-names = "adc";
> + #io-channel-cells = <1>;
> + io-channel-ranges;
> + status = "disabled";
This does not pass dtschema. NAK.
> + };
> };
> };
>
>
Best regards,
Krzysztof
On 13/01/2022 13:11, Alim Akhtar wrote:
> From: Aswani Reddy <[email protected]>
>
> This patch adds support for handling thress clusters
> (upto 12 CPUs)
>
> Cc: [email protected]
> Signed-off-by: Aswani Reddy <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> drivers/clocksource/exynos_mct.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
> index 5e3e96d3d1b9..ba3af940a687 100644
> --- a/drivers/clocksource/exynos_mct.c
> +++ b/drivers/clocksource/exynos_mct.c
> @@ -78,6 +78,10 @@ enum {
> MCT_L5_IRQ,
> MCT_L6_IRQ,
> MCT_L7_IRQ,
> + MCT_L8_IRQ,
> + MCT_L9_IRQ,
> + MCT_L10_IRQ,
> + MCT_L11_IRQ,
I think this should be variable, based on SoC compatible. The mistake
was done already when adding Exynos5420 support by Linaro/Samsung, but
at least let's correct it now.
Older MCTs/SoCs do not support 12 local interrupts, so they do not need
and should not register so many interrupts.
Best regards,
Krzysztof
On Thu, Jan 13, 2022 at 2:16 PM Krzysztof Kozlowski
<[email protected]> wrote:
> > ARM/TETON BGA MACHINE SUPPORT
> > M: "Mark F. Brown" <[email protected]>
> > L: [email protected] (moderated for non-subscribers)
> > diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> > index 54e3910e8b9b..bb8a047c2359 100644
> > --- a/arch/arm64/Kconfig.platforms
> > +++ b/arch/arm64/Kconfig.platforms
> > @@ -267,6 +267,12 @@ config ARCH_TEGRA
> > help
> > This enables support for the NVIDIA Tegra SoC family.
> >
> > +config ARCH_TESLA_FSD
> > + bool "ARMv8 based Tesla platform"
> > + select ARCH_EXYNOS
>
> How similar it is? I think it is better to duplicate Exynos
> selections/options here, instead of selecting entire ARCH. If this would
> require "depends on ARCH_EXYNOS || ARCH_TESLA_FSD" everywhere in the
> drivers, it's a hint that it is not a separate SoC but it is an Exynos,
> so it might not need a new sub-architecture.
Agreed, the SoC family options mainly exist so we can quickly enable or
disable drivers based on what a kernel is built for. If most of the drivers
for this SoC are shared with Exynos, I think having a single option is
sufficient, but it may be worth pointing out both in the help text.
If we want to have a separate option (mainly to help users find it), maybe
a 'depends on ARCH_EXYNOS' would be better. How many uses of
ARCH_TESLA_FSD are there?
Arnd
On Thu, Jan 13, 2022 at 4:32 AM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 13/01/2022 13:11, Alim Akhtar wrote:
> > This patch set adds basic support for the Tesla Full Self-Driving (FSD)
> > SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
> > as well as several IPs.
> >
> > Patches 1 to 8 provide support for the clock controller
> > (which is designed similarly to Exynos SoCs).
> >
> > The remaining changes provide pinmux support, initial device tree support,
> > and SPI, ADC, and MCT IP functionality.
>
> Does FSD have some version number? The FDS, especially in compatibles,
> looks quite generic, so what will happen if a newer SoC comes later? You
> would have:
> - tesla,fsd-pinctrl
> - tesla,fsd-xxxx-pinctrl (where xxxx could be some new version)
>
> This will be extra confusing, because fsd-pinctrl looks like the generic
> one, while it is specific...
The public sources from Tesla on github uses "turbo,trav" here, but
that's also not a versioned name. The platform itself (hw3/hw31 -- 3.1
I presume?) has numbering, but that's system and not SoC:
https://github.com/teslamotors/linux/tree/tesla-4.14-hw3/arch/arm64/boot/dts/turbo
It would be easy to do "fsd2" for naming/numbering if needed for
future versions, for example. I'm not so worried about this,
especially if there's no corresponding internal version numbering that
this would map naturally to.
-Olof
On Thu, 13 Jan 2022 17:41:21 +0530, Alim Akhtar wrote:
> Add dt-schema documentation for Tesla FSD SoC clock controller.
>
> Cc: [email protected]
> Signed-off-by: Alim Akhtar <[email protected]>
> ---
> .../bindings/clock/tesla,fsd-clock.yaml | 212 ++++++++++++++++++
> 1 file changed, 212 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/clock/tesla,fsd-clock.example.dts:19:18: fatal error: dt-bindings/clock/fsd-clk.h: No such file or directory
19 | #include <dt-bindings/clock/fsd-clk.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/clock/tesla,fsd-clock.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1579595
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
Hi Alim,
I love your patch! Yet something to improve:
[auto build test ERROR on v5.16]
[also build test ERROR on next-20220113]
[cannot apply to clk/clk-next robh/for-next pinctrl-samsung/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Alim-Akhtar/dt-bindings-clock-Document-FSD-CMU-bindings/20220113-211129
base: df0cc57e057f18e44dac8e6c18aba47ab53202f9
config: arm64-randconfig-r014-20220113 (https://download.01.org/0day-ci/archive/20220114/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/7edcfae09ff2aa85ae39f2240b13ea17eac8be94
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Alim-Akhtar/dt-bindings-clock-Document-FSD-CMU-bindings/20220113-211129
git checkout 7edcfae09ff2aa85ae39f2240b13ea17eac8be94
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
In file included from arch/arm64/boot/dts/tesla/fsd.dtsi:11,
from arch/arm64/boot/dts/tesla/fsd.dts:12:
>> scripts/dtc/include-prefixes/dt-bindings/clock/fsd-clk.h:12: error: unterminated #ifndef
12 | #ifndef _DT_BINDINGS_CLOCK_FSD_H
|
vim +12 scripts/dtc/include-prefixes/dt-bindings/clock/fsd-clk.h
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi Krzysztof,
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:02 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]
>Subject: Re: [PATCH 00/23] Add support for Tesla Full Self-Driving (FSD) SoC
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> This patch set adds basic support for the Tesla Full Self-Driving
>> (FSD) SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
>> as well as several IPs.
>>
>> Patches 1 to 8 provide support for the clock controller (which is
>> designed similarly to Exynos SoCs).
>>
>> The remaining changes provide pinmux support, initial device tree
>> support, and SPI, ADC, and MCT IP functionality.
>
>Does FSD have some version number? The FDS, especially in compatibles,
>looks quite generic, so what will happen if a newer SoC comes later? You
>would have:
> - tesla,fsd-pinctrl
> - tesla,fsd-xxxx-pinctrl (where xxxx could be some new version)
>
>This will be extra confusing, because fsd-pinctrl looks like the generic one,
>while it is specific...
>
AFAIK, there is no version for FSD SoC (like we see on Exynos or any other SoC)
In case something comes in future, may be just adopt as Olof suggested in the other thread like fsd2 etc..
>Best regards,
>Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 5:57 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected]
>Subject: Re: [PATCH 10/23] dt-bindings: pinctrl: samsung: Add compatible for
>Tesla FSD SoC
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> Add compatible for Tesla Full Self-Driving SoC. The pinctrl hardware
>> IP is similar to what found on most of the exynos series of SoC, so
>> this new compatible is added in samsung pinctrl binding.
>>
>> Cc: [email protected]
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>> b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>> index b8b475967ff9..ba972998a0e4 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>> @@ -24,6 +24,7 @@ Required Properties:
>> - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
>> - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
>> - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-
>controller.
>> + - "tesla,fsd-pinctrl": for Tesla FSD SoC compatible pin-controller.
>>
>
>Please rebase this on my latest Samsung pinctrl dtschema patches. You also
>need a tesla vendor prefix patch (separate).
>
Sure will rebase when sending v2, your latest patches are in Linux-next or still in your tree?
>
>Best regards,
>Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:11 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected]
>Subject: Re: [PATCH 01/23] dt-bindings: clock: Document FSD CMU bindings
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> Add dt-schema documentation for Tesla FSD SoC clock controller.
>>
>> Cc: [email protected]
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> .../bindings/clock/tesla,fsd-clock.yaml | 212 ++++++++++++++++++
>> 1 file changed, 212 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
>> b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
>> new file mode 100644
>> index 000000000000..58f341e5004d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml
>> @@ -0,0 +1,212 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id:
>> +https://protect2.fireeye.com/v1/url?k=7e607c7a-1f1d943d-7e61f735-74fe
>> +485fff30-a4acf0e03cbf256d&q=1&e=05b30de9-b535-49f7-9359-
>77edd951da07&
>> +u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fclock%2Ftesla%2Cfsd-
>clock.y
>> +aml%23
>> +$schema:
>> +https://protect2.fireeye.com/v1/url?k=5c769dcb-3d0b758c-5c771684-74fe
>> +485fff30-b4007a892a5a3e44&q=1&e=05b30de9-b535-49f7-9359-
>77edd951da07&
>> +u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>> +
>> +title: Tesla FSD (Full Self-Driving) SoC clock controller
>> +
>> +maintainers:
>> + - Alim Akhtar <[email protected]>
>> + - [email protected]
>> +
>> +description: |
>> + FSD clock controller consist of several clock management unit
>> + (CMU), which generates clocks for various inteernal SoC blocks.
>> + The root clock comes from external OSC clock (24 MHz).
>> +
>> + All available clocks are defined as preprocessor macros in
>> + 'dt-bindings/clock/fsd-clk.h' header.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - tesla,fsd-clock-cmu
>> + - tesla,fsd-clock-imem
>> + - tesla,fsd-clock-peric
>> + - tesla,fsd-clock-fsys0
>> + - tesla,fsd-clock-fsys1
>> + - tesla,fsd-clock-mfc
>> + - tesla,fsd-clock-cam_csi
>> +
>> + clocks:
>> + minItems: 1
>> + maxItems: 6
>> +
>> + clock-names:
>> + minItems: 1
>> + maxItems: 6
>> +
>> + "#clock-cells":
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: tesla,fsd-clock-cmu
>> +
>
>Nitpick: Drop the white-spaces between if-then. It's easier to spot the if-
>blocks if they are together.
>
Thanks will fix in next version
>> + then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: External reference clock (24 MHz)
>> +
>
>Drop this whitespace as well.
>
Noted
>Rest looks good to me, except the discussion about the compatible.
>
Have replied to the original question thread.
>
>Best regards,
>Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:20 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected];
>Jayati Sahu <[email protected]>; Ajay Kumar
><[email protected]>
>Subject: Re: [PATCH 03/23] clk: samsung: fsd: Add initial clock support
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> Add initial clock support for FSD (Full Self-Driving) SoC which is
>> required to bring-up platforms based on this SoC.
>>
>> Cc: [email protected]
>> Signed-off-by: Jayati Sahu <[email protected]>
>> Signed-off-by: Ajay Kumar <[email protected]>
>> Signed-off-by: Pankaj Dubey <[email protected]>
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> drivers/clk/samsung/Makefile | 1 +
>> drivers/clk/samsung/clk-fsd.c | 308
>++++++++++++++++++++++++++++++++++
>> drivers/clk/samsung/clk-pll.c | 1 +
>> drivers/clk/samsung/clk-pll.h | 1 +
>> 4 files changed, 311 insertions(+)
>> create mode 100644 drivers/clk/samsung/clk-fsd.c
>>
>> diff --git a/drivers/clk/samsung/Makefile
>> b/drivers/clk/samsung/Makefile index c46cf11e4d0b..d66b2ede004c 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -18,6 +18,7 @@ obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-
>exynos-audss.o
>> obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o
>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
>> obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
>> +obj-$(CONFIG_ARCH_TESLA_FSD) += clk-fsd.o
>
>It should be rather it's own CONFIG_TESLA_FSD_CLK option, just like other
>Exynos designs. This keeps unified approach with existing Samsung clock
>Kconfig.
>
Ok, will add a separate config for this
>> obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
>> obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
>> obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o diff --git
>> a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c new
>> file mode 100644 index 000000000000..e47523106d9e
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-fsd.c
>> @@ -0,0 +1,308 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Common Clock Framework support for FSD SoC.
>> + *
>> + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
>> + * https://www.samsung.com
>> + * Copyright (c) 2017-2022 Tesla, Inc.
>> + * https://www.tesla.com
>> + *
>
>Drop the line break with empty * comment.
Will fix in next version
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/of.h>
>> +
>> +#include "clk.h"
>> +#include <dt-bindings/clock/fsd-clk.h>
>
>dt-bindings headers before local clk.h.
>
Noted, thanks
>> +
>> +/* Register Offset definitions for CMU_CMU (0x11c10000) */
>
>
>
>Best regards,
>Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:25 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected];
>Aswani Reddy <[email protected]>; Niyas Ahmed S T
><[email protected]>; Chandrasekar R <[email protected]>;
>Jayati Sahu <[email protected]>; Sriranjani P
><[email protected]>; Ajay Kumar <[email protected]>
>Subject: Re: [PATCH 04/23] clk: samsung: fsd: Add cmu_peric block clock
>information
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> This patch adds CMU_PERIC block clock information needed for various
>> IPs functions found in this block.
>
>Here and in all other commits, please do not use "This patch". Instead:
>https://protect2.fireeye.com/v1/url?k=5ec41fe1-015f26dc-5ec594ae-
>0cc47a31309a-72c796795ac37ef5&q=1&e=2a1e171b-f066-48ff-95a7-
>12605dbbf8a9&u=https%3A%2F%2Felixir.bootlin.com%2Flinux%2Fv5.13%2Fso
>urce%2FDocumentation%2Fprocess%2Fsubmitting-patches.rst%23L89
>
Noted
>>
>> Cc: [email protected]
>> Signed-off-by: Aswani Reddy <[email protected]>
>> Signed-off-by: Niyas Ahmed S T <[email protected]>
>> Signed-off-by: Chandrasekar R <[email protected]>
>> Signed-off-by: Jayati Sahu <[email protected]>
>> Signed-off-by: Sriranjani P <[email protected]>
>> Signed-off-by: Ajay Kumar <[email protected]>
>> Signed-off-by: Pankaj Dubey <[email protected]>
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> drivers/clk/samsung/clk-fsd.c | 464
>> +++++++++++++++++++++++++++++++++-
>> 1 file changed, 463 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-fsd.c
>> b/drivers/clk/samsung/clk-fsd.c index e47523106d9e..6da20966ba99
>> 100644
>> --- a/drivers/clk/samsung/clk-fsd.c
>> +++ b/drivers/clk/samsung/clk-fsd.c
>> @@ -9,12 +9,59 @@
>> *
>> */
>>
>> -#include <linux/clk-provider.h>
>> #include <linux/of.h>
>> +#include <linux/clk.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_device.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/platform_device.h>
>
>Please order the includes alphabetically.
>
Sure will fix this
>>
>> #include "clk.h"
>> #include <dt-bindings/clock/fsd-clk.h>
>>
>> +/* Gate register bits */
>> +#define GATE_MANUAL BIT(20)
>> +#define GATE_ENABLE_HWACG BIT(28)
>> +
>> +/* Gate register offsets range */
>> +#define GATE_OFF_START 0x2000
>> +#define GATE_OFF_END 0x2fff
>> +
>> +/**
>> + * fsd_init_clocks - Set clocks initial configuration
>> + * @np: CMU device tree node with "reg" property
>(CMU addr)
>> + * @reg_offs: Register offsets array for clocks to init
>> + * @reg_offs_len: Number of register offsets in reg_offs array
>> + *
>> + * Set manual control mode for all gate clocks.
>> + */
>> +static void __init fsd_init_clocks(struct device_node *np,
>> + const unsigned long *reg_offs, size_t reg_offs_len)
>
>The same as exynos_arm64_init_clocks - please re-use instead of duplicating.
>
Will re-base on latest tree to have these common functions
>> +{
>> + void __iomem *reg_base;
>> + size_t i;
>> +
>> + reg_base = of_iomap(np, 0);
>> + if (!reg_base)
>> + panic("%s: failed to map registers\n", __func__);
>> +
>> + for (i = 0; i < reg_offs_len; ++i) {
>> + void __iomem *reg = reg_base + reg_offs[i];
>> + u32 val;
>> +
>> + /* Modify only gate clock registers */
>> + if (reg_offs[i] < GATE_OFF_START || reg_offs[i] >
>GATE_OFF_END)
>> + continue;
>> +
>> + val = readl(reg);
>> + val |= GATE_MANUAL;
>> + val &= ~GATE_ENABLE_HWACG;
>> + writel(val, reg);
>> + }
>> +
>> + iounmap(reg_base);
>> +}
>> +
>
>(...)
>
>> +/**
>> + * fsd_cmu_probe - Probe function for FSD platform clocks
>> + * @pdev: Pointer to platform device
>> + *
>> + * Configure clock hierarchy for clock domains of FSD platform */
>> +static int __init fsd_cmu_probe(struct platform_device *pdev) {
>> + const struct samsung_cmu_info *info;
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> +
>> + info = of_device_get_match_data(dev);
>> + fsd_init_clocks(np, info->clk_regs, info->nr_clk_regs);
>> + samsung_cmu_register_one(np, info);
>> +
>> + /* Keep bus clock running, so it's possible to access CMU registers */
>> + if (info->clk_name) {
>> + struct clk *bus_clk;
>> +
>> + bus_clk = clk_get(dev, info->clk_name);
>> + if (IS_ERR(bus_clk)) {
>> + pr_err("%s: could not find bus clock %s; err = %ld\n",
>> + __func__, info->clk_name, PTR_ERR(bus_clk));
>> + } else {
>> + clk_prepare_enable(bus_clk);
>> + }
>> + }
>> +
>> + return 0;
>> +}
>
>Please re-use exynos_arm64_register_cmu(). This will also solve my previous
>comment about exynos_arm64_init_clocks().
>
ok
>> +
>> +/* CMUs which belong to Power Domains and need runtime PM to be
>> +implemented */ static const struct of_device_id fsd_cmu_of_match[] = {
>> + {
>> + .compatible = "tesla,fsd-clock-peric",
>> + .data = &peric_cmu_info,
>> + }, {
>> + },
>> +};
>> +
>> +static struct platform_driver fsd_cmu_driver __refdata = {
>> + .driver = {
>> + .name = "fsd-cmu",
>> + .of_match_table = fsd_cmu_of_match,
>> + .suppress_bind_attrs = true,
>> + },
>> + .probe = fsd_cmu_probe,
>> +};
>> +
>> +static int __init fsd_cmu_init(void)
>> +{
>> + return platform_driver_register(&fsd_cmu_driver);
>> +}
>> +core_initcall(fsd_cmu_init);
>>
>
>
>Best regards,
>Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:28 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected]
>Subject: Re: [PATCH 12/23] dt-bindings: add vendor prefix for Tesla
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> Add vendor prefix for the Tesla (https://www.tesla.com)
>>
>> Cc: [email protected]
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>> 1 file changed, 2 insertions(
>
>This should be the first patch in the series.
>
>Reviewed-by: Krzysztof Kozlowski <[email protected]>
>
Thanks, will put this as first patch in this series
>
>Best regards,
>Krzysztof
>-----Original Message-----
>From: Mark Brown [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:29 PM
>To: Alim Akhtar <[email protected]>
>Cc: [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected]; linux-
>[email protected]; Aswani Reddy <[email protected]>
>Subject: Re: [PATCH 18/23] spi: s3c64xx: Add spi port configuration for
Tesla
>FSD SoC
>
>On Thu, Jan 13, 2022 at 05:41:38PM +0530, Alim Akhtar wrote:
>
>> + { .compatible = "tesla,fsd-spi",
>> + .data = (void *)&fsd_spi_port_config,
>> + },
>
>This needs a DT bindings update to match.
Thanks for point it out, will update in v2.
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:55 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected];
>Adithya K V <[email protected]>
>Subject: Re: [PATCH 17/23] Documentation: bindings: Add fsd spi compatible
>in dt-bindings document
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> This patch adds spi controller dt-binding compatible information for
>> Tesla Full Self-Driving SoC.
>>
>> Cc: [email protected]
>> Signed-off-by: Adithya K V <[email protected]>
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> Documentation/devicetree/bindings/spi/spi-samsung.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>
>Also: subject prefix:
>spi: dt-bindings: samsung:
>
Ok, will update and rebase on your upcoming dt schema patch set.
>> diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt
>> b/Documentation/devicetree/bindings/spi/spi-samsung.txt
>> index 49028a4f5df1..3af2408454b4 100644
>> --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
>> +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
>> @@ -11,6 +11,7 @@ Required SoC Specific Properties:
>> - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
>> - samsung,exynos5433-spi: for exynos5433 compatible controllers
>> - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
>> + - tesla,fsd-spi: spi controller support for Tesla Full
>> + Self-Driving SoC
>>
>> - reg: physical base address of the controller and length of memory mapped
>> region.
>>
>
>
>Best regards,
>Krzysztof
On 14/01/2022 06:41, Alim Akhtar wrote:
> Hi Krzysztof,
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: Thursday, January 13, 2022 6:02 PM
>> To: Alim Akhtar <[email protected]>; linux-arm-
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; linux-samsung-
>> [email protected]; [email protected]
>> Subject: Re: [PATCH 00/23] Add support for Tesla Full Self-Driving (FSD) SoC
>>
>> On 13/01/2022 13:11, Alim Akhtar wrote:
>>> This patch set adds basic support for the Tesla Full Self-Driving
>>> (FSD) SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
>>> as well as several IPs.
>>>
>>> Patches 1 to 8 provide support for the clock controller (which is
>>> designed similarly to Exynos SoCs).
>>>
>>> The remaining changes provide pinmux support, initial device tree
>>> support, and SPI, ADC, and MCT IP functionality.
>>
>> Does FSD have some version number? The FDS, especially in compatibles,
>> looks quite generic, so what will happen if a newer SoC comes later? You
>> would have:
>> - tesla,fsd-pinctrl
>> - tesla,fsd-xxxx-pinctrl (where xxxx could be some new version)
>>
>> This will be extra confusing, because fsd-pinctrl looks like the generic one,
>> while it is specific...
>>
> AFAIK, there is no version for FSD SoC (like we see on Exynos or any other SoC)
> In case something comes in future, may be just adopt as Olof suggested in the other thread like fsd2 etc..
>> Best regards,
>> Krzysztof
The naming is still confusing. The SoC is FSD, compatible is "fsd" but
entire sub-architecture is also FSD called. Therefore it looks like
creating entire sub-architecture for only one SoC, which actually in
multiple pieces is or looks like Samsung Exynos (designed by Samsung,
using several blocks from Exynos SoC).
Best regards,
Krzysztof
On 14/01/2022 06:44, Alim Akhtar wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: Thursday, January 13, 2022 5:57 PM
>> To: Alim Akhtar <[email protected]>; linux-arm-
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; linux-samsung-
>> [email protected]; [email protected]; [email protected]
>> Subject: Re: [PATCH 10/23] dt-bindings: pinctrl: samsung: Add compatible for
>> Tesla FSD SoC
>>
>> On 13/01/2022 13:11, Alim Akhtar wrote:
>>> Add compatible for Tesla Full Self-Driving SoC. The pinctrl hardware
>>> IP is similar to what found on most of the exynos series of SoC, so
>>> this new compatible is added in samsung pinctrl binding.
>>>
>>> Cc: [email protected]
>>> Signed-off-by: Alim Akhtar <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>> b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>> index b8b475967ff9..ba972998a0e4 100644
>>> --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>> @@ -24,6 +24,7 @@ Required Properties:
>>> - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
>>> - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
>>> - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-
>> controller.
>>> + - "tesla,fsd-pinctrl": for Tesla FSD SoC compatible pin-controller.
>>>
>>
>> Please rebase this on my latest Samsung pinctrl dtschema patches. You also
>> need a tesla vendor prefix patch (separate).
>>
> Sure will rebase when sending v2, your latest patches are in Linux-next or still in your tree?
The SPI (v3) and pinctrl (v2) dtschema patches are on mailing lists.
They seem to be done, so after merge window they will make to
linux-next. If you want earlier, grab them from mailing list or from
branches:
https://github.com/krzk/linux/tree/n/dt-bindings-samsung-spi-schema-v3
https://github.com/krzk/linux/tree/n/dt-bindings-samsung-pinctrl-schema-v2
Best regards,
Krzysztof
Hi Arnd and Krzysztof
>-----Original Message-----
>From: Arnd Bergmann [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 7:54 PM
>To: Krzysztof Kozlowski <[email protected]>
>Cc: Alim Akhtar <[email protected]>; Linux ARM <linux-arm-
>[email protected]>; Linux Kernel Mailing List <linux-
>[email protected]>; SoC Team <[email protected]>; linux-clk <linux-
>[email protected]>; DTML <[email protected]>; Olof Johansson
><[email protected]>; Linus Walleij <[email protected]>; Catalin Marinas
><[email protected]>; Rob Herring <[email protected]>; Sylwester
>Nawrocki <[email protected]>; moderated list:ARM/SAMSUNG
>EXYNOS ARM ARCHITECTURES <[email protected]>; Pankaj
>Dubey <[email protected]>; [email protected]; Arjun K V
><[email protected]>; Aswani Reddy <[email protected]>;
>Ajay Kumar <[email protected]>; Sriranjani P
><[email protected]>; Chandrasekar R <[email protected]>;
>Shashank Prashar <[email protected]>; Arnd Bergmann
><[email protected]>
>Subject: Re: [PATCH 14/23] arm64: dts: fsd: Add initial device tree support
>
>On Thu, Jan 13, 2022 at 2:16 PM Krzysztof Kozlowski
><[email protected]> wrote:
>> > ARM/TETON BGA MACHINE SUPPORT
>> > M: "Mark F. Brown" <[email protected]>
>> > L: [email protected] (moderated for non-subscribers)
>> > diff --git a/arch/arm64/Kconfig.platforms
>> > b/arch/arm64/Kconfig.platforms index 54e3910e8b9b..bb8a047c2359
>> > 100644
>> > --- a/arch/arm64/Kconfig.platforms
>> > +++ b/arch/arm64/Kconfig.platforms
>> > @@ -267,6 +267,12 @@ config ARCH_TEGRA
>> > help
>> > This enables support for the NVIDIA Tegra SoC family.
>> >
>> > +config ARCH_TESLA_FSD
>> > + bool "ARMv8 based Tesla platform"
>> > + select ARCH_EXYNOS
>>
>> How similar it is? I think it is better to duplicate Exynos
>> selections/options here, instead of selecting entire ARCH. If this
>> would require "depends on ARCH_EXYNOS || ARCH_TESLA_FSD"
>everywhere in
>> the drivers, it's a hint that it is not a separate SoC but it is an
>> Exynos, so it might not need a new sub-architecture.
>
>Agreed, the SoC family options mainly exist so we can quickly enable or
>disable drivers based on what a kernel is built for. If most of the drivers for
>this SoC are shared with Exynos, I think having a single option is sufficient, but
>it may be worth pointing out both in the help text.
>
>If we want to have a separate option (mainly to help users find it), maybe a
>'depends on ARCH_EXYNOS' would be better. How many uses of
>ARCH_TESLA_FSD are there?
>
It is true that FSD shares few IPs with Exynos and it dose contains Telsa specific IPs/ PCIe/some of the PHYs/ GPUs (different then Exynos) etc. to name a few.
And drivers for those will be posted in upcoming phases by Samsung, Telsa etc.
AFA architecture is concerns both Exynos and FSD has completely different architecture (at least at HW level).
In my opinion, it is make sense to have a separate option for FSD.
And as Arnd suggested "'depends on ARCH_EXYNOS" may be the way forward.
> Arnd
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Friday, January 14, 2022 1:20 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected]
>Subject: Re: [PATCH 10/23] dt-bindings: pinctrl: samsung: Add compatible for
>Tesla FSD SoC
>
>On 14/01/2022 06:44, Alim Akhtar wrote:
>>
>>
>>> -----Original Message-----
>>> From: Krzysztof Kozlowski [mailto:[email protected]]
>>> Sent: Thursday, January 13, 2022 5:57 PM
>>> To: Alim Akhtar <[email protected]>; linux-arm-
>>> [email protected]; [email protected]
>>> Cc: [email protected]; [email protected];
>>> [email protected]; [email protected]; [email protected];
>>> [email protected];
>>> [email protected]; [email protected]; linux-samsung-
>>> [email protected]; [email protected]; [email protected]
>>> Subject: Re: [PATCH 10/23] dt-bindings: pinctrl: samsung: Add
>>> compatible for Tesla FSD SoC
>>>
>>> On 13/01/2022 13:11, Alim Akhtar wrote:
>>>> Add compatible for Tesla Full Self-Driving SoC. The pinctrl hardware
>>>> IP is similar to what found on most of the exynos series of SoC, so
>>>> this new compatible is added in samsung pinctrl binding.
>>>>
>>>> Cc: [email protected]
>>>> Signed-off-by: Alim Akhtar <[email protected]>
>>>> ---
>>>> Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>>> b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>>> index b8b475967ff9..ba972998a0e4 100644
>>>> --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>>> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
>>>> @@ -24,6 +24,7 @@ Required Properties:
>>>> - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
>>>> - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
>>>> - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible
>>>> pin-
>>> controller.
>>>> + - "tesla,fsd-pinctrl": for Tesla FSD SoC compatible pin-controller.
>>>>
>>>
>>> Please rebase this on my latest Samsung pinctrl dtschema patches. You
>>> also need a tesla vendor prefix patch (separate).
>>>
>> Sure will rebase when sending v2, your latest patches are in Linux-next or
>still in your tree?
>
>The SPI (v3) and pinctrl (v2) dtschema patches are on mailing lists.
>They seem to be done, so after merge window they will make to linux-next. If
>you want earlier, grab them from mailing list or from
>branches:
>https://protect2.fireeye.com/v1/url?k=78372ba7-27ac12a5-7836a0e8-
>0cc47a31381a-987e4f8740569613&q=1&e=8e15033d-ca15-4f1f-b463-
>adce6ebe65ef&u=https%3A%2F%2Fgithub.com%2Fkrzk%2Flinux%2Ftree%2F
>n%2Fdt-bindings-samsung-spi-schema-v3
>https://protect2.fireeye.com/v1/url?k=32fb0ddf-6d6034dd-32fa8690-
>0cc47a31381a-a7fe8cfb89319cf3&q=1&e=8e15033d-ca15-4f1f-b463-
>adce6ebe65ef&u=https%3A%2F%2Fgithub.com%2Fkrzk%2Flinux%2Ftree%2F
>n%2Fdt-bindings-samsung-pinctrl-schema-v2
>
Thanks Krzysztof, will take them for addressing FSD comments.
>
>Best regards,
>Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:03 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected]
>Subject: Re: [PATCH 13/23] dt-bindings: arm: add Tesla FSD ARM SoC
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> Add device tree bindings for the Tesla FSD ARM SoC.
>>
>> Cc: [email protected]
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> .../devicetree/bindings/arm/tesla.yaml | 25 +++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml
>> b/Documentation/devicetree/bindings/arm/tesla.yaml
>> new file mode 100644
>> index 000000000000..9f89cde76c85
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/tesla.yaml
>> @@ -0,0 +1,25 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
>> +---
>> +$id:
>> +https://protect2.fireeye.com/v1/url?k=2f0fac44-70949546-2f0e270b-0cc4
>> +7a312ab0-50c826f7b1999a5f&q=1&e=bcbf277f-4e93-4705-8f6a-
>2beaa7eb31e2&
>> +u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Farm%2Ftesla.yaml%23
>> +$schema:
>> +https://protect2.fireeye.com/v1/url?k=d8493fe2-87d206e0-d848b4ad-0cc4
>> +7a312ab0-f4e5046adc7da972&q=1&e=bcbf277f-4e93-4705-8f6a-
>2beaa7eb31e2&
>> +u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>> +
>> +title: Tesla Full Self Driving(FSD) platforms device tree bindings
>> +
>> +maintainers:
>> + - Alim Akhtar <[email protected]>
>> + - [email protected]
>> +
>> +properties:
>> + $nodename:
>> + const: '/'
>> + compatible:
>> + oneOf:
>> +
>> + - description: FSD SoC board
>> + items:
>> + - const: tesla,fsd
>
>Either this is a SoC or a board compatible... Cannot be both.
>
Actually we call this as fsd board, so let me add accordingly compatible (fsd-baord) for board.
Thanks
>> +
>> +additionalProperties: true
>> +
>> +...
>>
>
>
>Best regards,
>Krzysztof
On 14/01/2022 17:57, Alim Akhtar wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: Thursday, January 13, 2022 6:03 PM
>> To: Alim Akhtar <[email protected]>; linux-arm-
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; linux-samsung-
>> [email protected]; [email protected]; [email protected]
>> Subject: Re: [PATCH 13/23] dt-bindings: arm: add Tesla FSD ARM SoC
>>
>> On 13/01/2022 13:11, Alim Akhtar wrote:
>>> Add device tree bindings for the Tesla FSD ARM SoC.
>>>
>>> Cc: [email protected]
>>> Signed-off-by: Alim Akhtar <[email protected]>
>>> ---
>>> .../devicetree/bindings/arm/tesla.yaml | 25 +++++++++++++++++++
>>> 1 file changed, 25 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/arm/tesla.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml
>>> b/Documentation/devicetree/bindings/arm/tesla.yaml
>>> new file mode 100644
>>> index 000000000000..9f89cde76c85
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/tesla.yaml
>>> @@ -0,0 +1,25 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
>>> +---
>>> +$id:
>>> +https://protect2.fireeye.com/v1/url?k=2f0fac44-70949546-2f0e270b-0cc4
>>> +7a312ab0-50c826f7b1999a5f&q=1&e=bcbf277f-4e93-4705-8f6a-
>> 2beaa7eb31e2&
>>> +u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Farm%2Ftesla.yaml%23
>>> +$schema:
>>> +https://protect2.fireeye.com/v1/url?k=d8493fe2-87d206e0-d848b4ad-0cc4
>>> +7a312ab0-f4e5046adc7da972&q=1&e=bcbf277f-4e93-4705-8f6a-
>> 2beaa7eb31e2&
>>> +u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>>> +
>>> +title: Tesla Full Self Driving(FSD) platforms device tree bindings
>>> +
>>> +maintainers:
>>> + - Alim Akhtar <[email protected]>
>>> + - [email protected]
>>> +
>>> +properties:
>>> + $nodename:
>>> + const: '/'
>>> + compatible:
>>> + oneOf:
>>> +
>>> + - description: FSD SoC board
>>> + items:
>>> + - const: tesla,fsd
>>
>> Either this is a SoC or a board compatible... Cannot be both.
>>
> Actually we call this as fsd board, so let me add accordingly compatible (fsd-baord) for board.
> Thanks
It's confusing and probably not accurate. In your series fsd is three
things in the same time: an architecture, a SoC and a board (DTS). The
last two should definitely be different. You probably have some eval
board (how it is called also in Tesla open source git) or some specific
product board.
I cannot judge how different this is from Exynos subarchitecture -
looking at patches it is not different - so I could understand a FSD
sub-arch with only one SoC.
Best regards,
Krzysztof
Hi!
> This patch set adds basic support for the Tesla Full Self-Driving (FSD)
> SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
> as well as several IPs.
I'm not thrilled by their naming. Intel does not produce "Intel
Fastest in world SoC", and this chip is not actually suitable for
autonomous driving :-(.
Pavel
--
http://www.livejournal.com/~pavelmachek
On Thu, Jan 13, 2022 at 1:24 PM Alim Akhtar <[email protected]> wrote:
> This patch adds compatible and port configuration for
> spi controller for Tesla Full Self-Driving SoC.
>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Aswani Reddy <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
Note to self: now that I see that the Samsung "S3C" SPI controller,
which I was thinking of as "some kind of early 2000s legacy" is used
by the very latest silicon I bumped up fixing it to use GPIO descriptors
a bit on my TODO list.
Yours,
Linus Walleij
On Thu, Jan 13, 2022 at 1:24 PM Alim Akhtar <[email protected]> wrote:
> Add vendor prefix for the Tesla (https://www.tesla.com)
>
> Cc: [email protected]
> Signed-off-by: Alim Akhtar <[email protected]>
That's an interesting new SoC vendor...
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Thu, Jan 13, 2022 at 1:24 PM Alim Akhtar <[email protected]> wrote:
> This patch adds Tesla FSD SoC specific data to enable pinctrl.
> FSD SoC has similar pinctrl controller as found in the most
> samsung/exynos SoCs.
>
> Cc: [email protected]
> Signed-off-by: Ajay Kumar <[email protected]>
> Signed-off-by: Alim Akhtar <[email protected]>
Looks good to me once Krysztof is happy with this I expect to get the
pin control portions from him by a pull request.
FWIW
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Thu, 13 Jan 2022 14:32:12 +0100
Krzysztof Kozlowski <[email protected]> wrote:
> On 13/01/2022 13:11, Alim Akhtar wrote:
> > This patch adds a new compatible string for exynos's ADC-V3 variant.
> >
> > Cc: [email protected]
> > Signed-off-by: Tamseel Shams <[email protected]>
> > Signed-off-by: Alim Akhtar <[email protected]>
Please cc [email protected] for next version...
> > ---
> > .../devicetree/bindings/iio/adc/samsung,exynos-adc.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
> > index 81c87295912c..9303053759ca 100644
> > --- a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
> > +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
> > @@ -14,6 +14,7 @@ properties:
> > enum:
> > - samsung,exynos-adc-v1 # Exynos5250
> > - samsung,exynos-adc-v2
> > + - samsung,exynos-adc-v3
>
> Please use SoC-specific compatible. IP block versions are tricky because:
> 1. Documentation/datasheet mentioning which SoC has which block version
> are not public.
> 2. Neither are public the datasheets for ADC blocks.
> 3. The versioning of IP blocks can be inaccurate.
>
>
> Best regards,
> Krzysztof
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Jonathan
>-----Original Message-----
>From: Jonathan Cameron [mailto:[email protected]]
>Sent: Sunday, January 16, 2022 4:50 PM
>To: Alim Akhtar <[email protected]>
>Cc: [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected]; linux-
>[email protected]; Tamseel Shams <[email protected]>
>Subject: Re: [PATCH 21/23] iio: adc: exynos-adc: Add support for ADC V3
>controller
>
>On Thu, 13 Jan 2022 17:41:41 +0530
>Alim Akhtar <[email protected]> wrote:
>
>> Exynos's ADC-V3 has some difference in registers set, number of
>> programmable channels (16 channel) etc. This patch adds support for
>> ADC-V3 controller version.
>>
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> Signed-off-by: Tamseel Shams <[email protected]>
>> Signed-off-by: Alim Akhtar <[email protected]>
>
>Hi Alim,
>
>A few minor suggestions below. I'm not seeing a binding update though...
>
>I'd also suggest that it would be more appropriate to break this out as a
>separate mini series from the main support so that it can be reviewed and
>merge separately. It's not ideal when a list just gets patch 21 of
>23 with no cover letter etc sent to it.
>
Thanks for the detailed review, I agree, will send as a separate patch set
only related with ADC support.
And addressing rest of your comments in this patch.
>Jonathan
>
>> ---
>> drivers/iio/adc/exynos_adc.c | 74
>> +++++++++++++++++++++++++++++++++++-
>> 1 file changed, 72 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/iio/adc/exynos_adc.c
>> b/drivers/iio/adc/exynos_adc.c index 3b3868aa2533..61752e798fd6 100644
>> --- a/drivers/iio/adc/exynos_adc.c
>> +++ b/drivers/iio/adc/exynos_adc.c
>> @@ -55,6 +55,11 @@
>> #define ADC_V2_INT_ST(x) ((x) + 0x14)
>> #define ADC_V2_VER(x) ((x) + 0x20)
>>
>> +/* ADC_V3 register definitions */
>> +#define ADC_V3_DAT(x) ((x) + 0x08)
>> +#define ADC_V3_DAT_SUM(x) ((x) + 0x0C)
>> +#define ADC_V3_DBG_DATA(x) ((x) + 0x1C)
>> +
>> /* Bit definitions for ADC_V1 */
>> #define ADC_V1_CON_RES (1u << 16)
>> #define ADC_V1_CON_PRSCEN (1u << 14)
>> @@ -92,6 +97,7 @@
>>
>> /* Bit definitions for ADC_V2 */
>> #define ADC_V2_CON1_SOFT_RESET (1u << 2)
>> +#define ADC_V2_CON1_SOFT_NON_RESET (1u << 1)
>>
>> #define ADC_V2_CON2_OSEL (1u << 10)
>> #define ADC_V2_CON2_ESEL (1u << 9)
>> @@ -100,6 +106,7 @@
>> #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
>> #define ADC_V2_CON2_ACH_MASK 0xF
>>
>> +#define MAX_ADC_V3_CHANNELS 16
>> #define MAX_ADC_V2_CHANNELS 10
>> #define MAX_ADC_V1_CHANNELS 8
>> #define MAX_EXYNOS3250_ADC_CHANNELS 2
>
>Given we have a mixture of required an unrequired elements in this
structure
>it might be a good idea to add some documentation. Kernel-doc for the
>whole structure preferred. Note this isn't necessarily something that
needs
>to be in this patch given the lack of docs predates this and with the
change to
>make
>adc_isr() required that I suggest below things aren't made worse by this
>patch.
>
>> @@ -164,6 +171,7 @@ struct exynos_adc_data {
>> void (*exit_hw)(struct exynos_adc *info);
>> void (*clear_irq)(struct exynos_adc *info);
>> void (*start_conv)(struct exynos_adc *info, unsigned long addr);
>> + irqreturn_t (*adc_isr)(int irq, void *dev_id);
>> };
>>
>> static void exynos_adc_unprepare_clk(struct exynos_adc *info) @@
>> -484,6 +492,59 @@ static const struct exynos_adc_data exynos7_adc_data =
>{
>> .start_conv = exynos_adc_v2_start_conv,
>> };
>>
>> +static void exynos_adc_v3_init_hw(struct exynos_adc *info) {
>> + u32 con2;
>> +
>> + writel(ADC_V2_CON1_SOFT_RESET, ADC_V2_CON1(info->regs));
>> +
>> + writel(ADC_V2_CON1_SOFT_NON_RESET, ADC_V2_CON1(info-
>>regs));
>> +
>> + con2 = ADC_V2_CON2_C_TIME(6);
>> + writel(con2, ADC_V2_CON2(info->regs));
>> +
>> + /* Enable interrupts */
>> + writel(1, ADC_V2_INT_EN(info->regs)); }
>> +
>> +static void exynos_adc_v3_exit_hw(struct exynos_adc *info) {
>> + u32 con2;
>> +
>> + con2 = readl(ADC_V2_CON2(info->regs));
>> + con2 &= ~ADC_V2_CON2_C_TIME(7);
>> + writel(con2, ADC_V2_CON2(info->regs));
>> +
>> + /* Disable interrupts */
>> + writel(0, ADC_V2_INT_EN(info->regs)); }
>> +
>> +static irqreturn_t exynos_adc_v3_isr(int irq, void *dev_id) {
>> + struct exynos_adc *info = (struct exynos_adc *)dev_id;
>
>Shouldn't need the cast as cast from void * to another pointer is always
valid
>in C without the explicit cast.
>
>> + u32 mask = info->data->mask;
>> +
>> + info->value = readl(ADC_V3_DAT(info->regs)) & mask;
>> +
>> + if (info->data->clear_irq)
>> + info->data->clear_irq(info);
>
>Don't need this currently as v3_isr() is always matched with clear_isr()
being
>provided. Having the check implies otherwise which is probably not a good
>thing to do until some future device support (maybe) needs it.
>
>> +
>> + complete(&info->completion);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static const struct exynos_adc_data exynos_adc_v3_adc_data = {
>> + .num_channels = MAX_ADC_V3_CHANNELS,
>> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
>> +
>> + .init_hw = exynos_adc_v3_init_hw,
>> + .exit_hw = exynos_adc_v3_exit_hw,
>> + .clear_irq = exynos_adc_v2_clear_irq,
>> + .start_conv = exynos_adc_v2_start_conv,
>> + .adc_isr = exynos_adc_v3_isr,
>> +};
>> +
>> static const struct of_device_id exynos_adc_match[] = {
>> {
>> .compatible = "samsung,s3c2410-adc", @@ -518,6 +579,9 @@
>static
>> const struct of_device_id exynos_adc_match[] = {
>> }, {
>> .compatible = "samsung,exynos7-adc",
>> .data = &exynos7_adc_data,
>> + }, {
>> + .compatible = "samsung,exynos-adc-v3",
>> + .data = &exynos_adc_v3_adc_data,
>> },
>> {},
>> };
>> @@ -719,6 +783,12 @@ static const struct iio_chan_spec
>exynos_adc_iio_channels[] = {
>> ADC_CHANNEL(7, "adc7"),
>> ADC_CHANNEL(8, "adc8"),
>> ADC_CHANNEL(9, "adc9"),
>> + ADC_CHANNEL(10, "adc10"),
>> + ADC_CHANNEL(11, "adc11"),
>> + ADC_CHANNEL(12, "adc12"),
>> + ADC_CHANNEL(13, "adc13"),
>> + ADC_CHANNEL(14, "adc14"),
>> + ADC_CHANNEL(15, "adc15"),
>> };
>>
>> static int exynos_adc_remove_devices(struct device *dev, void *c) @@
>> -885,8 +955,8 @@ static int exynos_adc_probe(struct platform_device
>> *pdev)
>>
>> mutex_init(&info->lock);
>>
>> - ret = request_irq(info->irq, exynos_adc_isr,
>> - 0, dev_name(&pdev->dev), info);
>> + ret = request_irq(info->irq, info->data->adc_isr ?
info->data->adc_isr
>:
>> + exynos_adc_isr, 0, dev_name(&pdev->dev),
>info);
>
>I'd rather see the slightly larger change of providing adc_isr for existing
parts
>and the conditional part here going away.
>
>Jonathan
>
>
>> if (ret < 0) {
>> dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
>> info->irq);
>-----Original Message-----
>From: Jonathan Cameron [mailto:[email protected]]
>Sent: Monday, January 17, 2022 3:17 PM
>To: Krzysztof Kozlowski <[email protected]>
>Cc: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected]; Tamseel Shams
><[email protected]>
>Subject: Re: [PATCH 20/23] dt-bindings: iio: adc: exynos-adc: Add ADC-V3
>variant
>
>On Thu, 13 Jan 2022 14:32:12 +0100
>Krzysztof Kozlowski <[email protected]> wrote:
>
>> On 13/01/2022 13:11, Alim Akhtar wrote:
>> > This patch adds a new compatible string for exynos's ADC-V3 variant.
>> >
>> > Cc: [email protected]
>> > Signed-off-by: Tamseel Shams <[email protected]>
>> > Signed-off-by: Alim Akhtar <[email protected]>
>
>Please cc [email protected] for next version...
>
Noted, will separate out these patches from the original series and send.
Thanks
>> > ---
>> > .../devicetree/bindings/iio/adc/samsung,exynos-adc.yaml | 1 +
>> > 1 file changed, 1 insertion(+)
>> >
>> > diff --git
>> > a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
>> > b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
>> > index 81c87295912c..9303053759ca 100644
>> > ---
>> > a/Documentation/devicetree/bindings/iio/adc/samsung,exynos-adc.yaml
>> > +++ b/Documentation/devicetree/bindings/iio/adc/samsung,exynos-
>adc.y
>> > +++ aml
>> > @@ -14,6 +14,7 @@ properties:
>> > enum:
>> > - samsung,exynos-adc-v1 # Exynos5250
>> > - samsung,exynos-adc-v2
>> > + - samsung,exynos-adc-v3
>>
>> Please use SoC-specific compatible. IP block versions are tricky because:
>> 1. Documentation/datasheet mentioning which SoC has which block
>> version are not public.
>> 2. Neither are public the datasheets for ADC blocks.
>> 3. The versioning of IP blocks can be inaccurate.
>>
>>
>> Best regards,
>> Krzysztof
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> [email protected]
>> https://protect2.fireeye.com/v1/url?k=9dd88c77-fca326ff-9dd90738-74fe4
>> 860018a-343cb1b0388f1560&q=1&e=61045889-dd66-417f-b142-
>9e85b39f1676&u=
>> http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-
>kern
>> el
Hi Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Friday, January 14, 2022 11:00 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected]
>Subject: Re: [PATCH 13/23] dt-bindings: arm: add Tesla FSD ARM SoC
>
>On 14/01/2022 17:57, Alim Akhtar wrote:
>>
>>
>>> -----Original Message-----
>>> From: Krzysztof Kozlowski [mailto:[email protected]]
>>> Sent: Thursday, January 13, 2022 6:03 PM
>>> To: Alim Akhtar <[email protected]>; linux-arm-
>>> [email protected]; [email protected]
>>> Cc: [email protected]; [email protected];
>>> [email protected]; [email protected]; [email protected];
>>> [email protected];
>>> [email protected]; [email protected]; linux-samsung-
>>> [email protected]; [email protected]; [email protected]
>>> Subject: Re: [PATCH 13/23] dt-bindings: arm: add Tesla FSD ARM SoC
>>>
>>> On 13/01/2022 13:11, Alim Akhtar wrote:
>>>> Add device tree bindings for the Tesla FSD ARM SoC.
>>>>
>>>> Cc: [email protected]
>>>> Signed-off-by: Alim Akhtar <[email protected]>
>>>> ---
>>>> .../devicetree/bindings/arm/tesla.yaml | 25 +++++++++++++++++++
>>>> 1 file changed, 25 insertions(+)
>>>> create mode 100644
>Documentation/devicetree/bindings/arm/tesla.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml
>>>> b/Documentation/devicetree/bindings/arm/tesla.yaml
>>>> new file mode 100644
>>>> index 000000000000..9f89cde76c85
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/arm/tesla.yaml
>>>> @@ -0,0 +1,25 @@
>>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2
>>>> +---
>>>> +$id:
>>>> +https://protect2.fireeye.com/v1/url?k=2f0fac44-70949546-2f0e270b-0c
>>>> +c4
>>>> +7a312ab0-50c826f7b1999a5f&q=1&e=bcbf277f-4e93-4705-8f6a-
>>> 2beaa7eb31e2&
>>>>
>+u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Farm%2Ftesla.yaml%23
>>>> +$schema:
>>>> +https://protect2.fireeye.com/v1/url?k=d8493fe2-87d206e0-d848b4ad-
>0c
>>>> +c4
>>>> +7a312ab0-f4e5046adc7da972&q=1&e=bcbf277f-4e93-4705-8f6a-
>>> 2beaa7eb31e2&
>>>> +u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
>>>> +
>>>> +title: Tesla Full Self Driving(FSD) platforms device tree bindings
>>>> +
>>>> +maintainers:
>>>> + - Alim Akhtar <[email protected]>
>>>> + - [email protected]
>>>> +
>>>> +properties:
>>>> + $nodename:
>>>> + const: '/'
>>>> + compatible:
>>>> + oneOf:
>>>> +
>>>> + - description: FSD SoC board
>>>> + items:
>>>> + - const: tesla,fsd
>>>
>>> Either this is a SoC or a board compatible... Cannot be both.
>>>
>> Actually we call this as fsd board, so let me add accordingly compatible (fsd-
>baord) for board.
>> Thanks
>
>It's confusing and probably not accurate. In your series fsd is three things in
>the same time: an architecture, a SoC and a board (DTS). The last two should
>definitely be different. You probably have some eval board (how it is called
>also in Tesla open source git) or some specific product board.
>
Understood, let me clear this confusion in the patchset-2 where fsd board will have its own compatible and
of course SoC will have its own (shared with fsd architecture) compatible.
>I cannot judge how different this is from Exynos subarchitecture - looking at
>patches it is not different - so I could understand a FSD sub-arch with only one
>SoC.
>
I understand, it is a bit difficult to visualize it with the current patch set.
As discuss on the other thread, FSD is different, more over the vendor is different, internal design is different.
>
>Best regards,
>Krzysztof
Hi Krzysztof
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Thursday, January 13, 2022 6:50 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected];
>Shashank Prashar <[email protected]>; Aswani Reddy
><[email protected]>
>Subject: Re: [PATCH 15/23] arm64: dts: fsd: Add initial pinctrl support
>
>On 13/01/2022 13:11, Alim Akhtar wrote:
>> Add initial pin configuration nodes for FSD SoC.
>>
>> Cc: [email protected]
>> Signed-off-by: Shashank Prashar <[email protected]>
>> Signed-off-by: Aswani Reddy <[email protected]>
>> Signed-off-by: Alim Akhtar <[email protected]>
>> ---
>> arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 338
>+++++++++++++++++++++
>> arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++
>> 2 files changed, 360 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>> b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>> new file mode 100644
>> index 000000000000..ec8d944af636
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>> @@ -0,0 +1,338 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Tesla Full Self-Driving SoC device tree source
>> + *
>> + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
>> + * https://www.samsung.com
>> + * Copyright (c) 2017-2021 Tesla, Inc.
>> + * https://www.tesla.com
>> + */
>> +
>> +#include <dt-bindings/pinctrl/samsung.h>
>> +
>> +&pinctrl_fsys0 {
>> +
>
>No need for empty line.
>
Noted
>> + gpf0: gpf0 {
>
>FYI:
>It's ok now, but the nodes will have to be renamed to "xxx-gpio-bank" later.
>
Have rebased my v2 on your pinmux schema update, so these and below comments are addressed.
Thanks
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf1: gpf1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf6: gpf6 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf4: gpf4 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf5: gpf5 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +};
>> +
>> +&pinctrl_peric {
>> +
>
>No need for empty line.
>
>> + gpc8: gpc8 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf2: gpf2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpf3: gpf3 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpd0: gpd0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb0: gpb0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb1: gpb1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb4: gpb4 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb5: gpb5 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb6: gpb6 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpb7: gpb7 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpd1: gpd1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpd2: gpd2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpd3: gpd3 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg0: gpg0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg1: gpg1 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg2: gpg2 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg3: gpg3 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg4: gpg4 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg5: gpg5 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg6: gpg6 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + gpg7: gpg7 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + };
>> +
>> + pwm0_out: pwm0-out {
>
>All pin configuretion node names with "-pins" suffix. Upcoming dtschema will
>require this.
>
>> + samsung,pins = "gpb6-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
>> + };
>> +
>> + pwm1_out: pwm1-out {
>> + samsung,pins = "gpb6-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
>> + };
>> +
>> + hs_i2c0_bus: hs-i2c0-bus {
>> + samsung,pins = "gpb0-0", "gpb0-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + hs_i2c1_bus: hs-i2c1-bus {
>> + samsung,pins = "gpb0-2", "gpb0-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + hs_i2c2_bus: hs-i2c2-bus {
>> + samsung,pins = "gpb0-4", "gpb0-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + hs_i2c3_bus: hs-i2c3-bus {
>> + samsung,pins = "gpb0-6", "gpb0-7";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + hs_i2c4_bus: hs-i2c4-bus {
>> + samsung,pins = "gpb1-0", "gpb1-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + hs_i2c5_bus: hs-i2c5-bus {
>> + samsung,pins = "gpb1-2", "gpb1-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + hs_i2c6_bus: hs-i2c6-bus {
>> + samsung,pins = "gpb1-4", "gpb1-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + hs_i2c7_bus: hs-i2c7-bus {
>> + samsung,pins = "gpb1-6", "gpb1-7";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + uart0_data: uart0-data {
>> + samsung,pins = "gpb7-0", "gpb7-1";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + uart1_data: uart1-data {
>> + samsung,pins = "gpb7-4", "gpb7-5";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + spi0_bus: spi0-bus {
>> + samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + spi1_bus: spi1-bus {
>> + samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +
>> + spi2_bus: spi2-bus {
>> + samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3";
>> + samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
>> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
>> + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
>> + };
>> +};
>> +
>> +&pinctrl_pmu {
>> +
>
>No need for empty line.
>
>> + gpq0: gpq0 {
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>
>
>
>
>Best regards,
>Krzysztof
On 17/01/2022 14:44, Alim Akhtar wrote:
> Hi Krzysztof
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski [mailto:[email protected]]
>> Sent: Thursday, January 13, 2022 6:50 PM
>> To: Alim Akhtar <[email protected]>; linux-arm-
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; linux-samsung-
>> [email protected]; [email protected]; [email protected];
>> Shashank Prashar <[email protected]>; Aswani Reddy
>> <[email protected]>
>> Subject: Re: [PATCH 15/23] arm64: dts: fsd: Add initial pinctrl support
>>
>> On 13/01/2022 13:11, Alim Akhtar wrote:
>>> Add initial pin configuration nodes for FSD SoC.
>>>
>>> Cc: [email protected]
>>> Signed-off-by: Shashank Prashar <[email protected]>
>>> Signed-off-by: Aswani Reddy <[email protected]>
>>> Signed-off-by: Alim Akhtar <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 338
>> +++++++++++++++++++++
>>> arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++
>>> 2 files changed, 360 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>> b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>> new file mode 100644
>>> index 000000000000..ec8d944af636
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>> @@ -0,0 +1,338 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Tesla Full Self-Driving SoC device tree source
>>> + *
>>> + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
>>> + * https://www.samsung.com
>>> + * Copyright (c) 2017-2021 Tesla, Inc.
>>> + * https://www.tesla.com
>>> + */
>>> +
>>> +#include <dt-bindings/pinctrl/samsung.h>
>>> +
>>> +&pinctrl_fsys0 {
>>> +
>>
>> No need for empty line.
>>
> Noted
>
>>> + gpf0: gpf0 {
>>
>> FYI:
>> It's ok now, but the nodes will have to be renamed to "xxx-gpio-bank" later.
>>
> Have rebased my v2 on your pinmux schema update, so these and below comments are addressed.
> Thanks
>
OK, but have in mind that -gpio-bank suffix is not needed now. This
depends on support in the pinctrl driver, which will be applied after
the merge window to different tree or branches than DTS is going to.
Therefore if I apply your DTS with "-gpio-bank" to my next/dt64, the
kernel won't find GPIo banks and won't properly boot. The linux-next
will be fine, just my next/dt64 won't be.
If you're fine with it - use "-gpio-bank" suffix. If you prefer my
next/dt64 to have a fully working Tesla SoC DTS, then stick to old node
naming and let's replace it later.
Best regards,
Krzysztof
On Mon, Jan 17, 2022 at 2:26 PM Alim Akhtar <[email protected]> wrote:
>
> >I cannot judge how different this is from Exynos subarchitecture - looking at
> >patches it is not different - so I could understand a FSD sub-arch with only one
> >SoC.
> >
> I understand, it is a bit difficult to visualize it with the current patch set.
> As discuss on the other thread, FSD is different, more over the vendor is different, internal design is different.
Is it based on another SoC design then? Most new SoCs are derived from
some other
one, so it makes sense to put it into the same family. E.g. the Apple
M1 takes bits from
both Exynos and PA-Semi SoCs but has more newly added components than
either one.
I would argue that if this SoC shares the pinctrl, clock, spi, adc,
and timer implementation
with Exynos, we should consider it part of the Exynos family,
regardless of what other
blocks may exist next to those.
Arnd
On 17/01/2022 15:14, Arnd Bergmann wrote:
> On Mon, Jan 17, 2022 at 2:26 PM Alim Akhtar <[email protected]> wrote:
>>
>>> I cannot judge how different this is from Exynos subarchitecture - looking at
>>> patches it is not different - so I could understand a FSD sub-arch with only one
>>> SoC.
>>>
>> I understand, it is a bit difficult to visualize it with the current patch set.
>> As discuss on the other thread, FSD is different, more over the vendor is different, internal design is different.
>
> Is it based on another SoC design then? Most new SoCs are derived from
> some other
> one, so it makes sense to put it into the same family. E.g. the Apple
> M1 takes bits from
> both Exynos and PA-Semi SoCs but has more newly added components than
> either one.
It seems Apple M1 shares only few bits with SoC. I am aware of only UART
driver as directly re-usable.
>
> I would argue that if this SoC shares the pinctrl, clock, spi, adc,
> and timer implementation
Plus: UART, watchdog, PWM, I2C, I2S, USB PHY, DWC3 USB (in Exynos
flavor), UFS (also in Exynos-looking flavor), MFC (video codec), some
similarities in DW PCIe, TMU (thermal). Looking at DTS there are
differences but just few comparing to most of shared blocks.
Additionally SoC BSP (and maybe SoC itself...) was actually developed or
co-developed by Samsung, judging by copyrights in the BSP code. Even the
original DTSI has:
TURBO TRAV SoC device tree source
Copyright (c) 2017 Samsung Electronics Co., Ltd.
Tesla could still customize it a lot, but it is a strong hint that most
of it came from Samsung LSI and shares with existing Samsung designs.
Have in mind that recent Exynos chips are significantly different than
early ARMv7 or ARMv8 designs and we still consider them part of Exynos
family.
> with Exynos, we should consider it part of the Exynos family,
> regardless of what other
> blocks may exist next to those.
Yes. I don't see the benefit of keeping it outside of Exynos. It will
sprinkle "depends on ARCH_EXYNOS || ARCH_FSD" all over (or depend on
Exynos like you suggested).
Best regards,
Krzysztof
On Sun, Jan 16, 2022 at 1:23 AM Pavel Machek <[email protected]> wrote:
>
> Hi!
>
> > This patch set adds basic support for the Tesla Full Self-Driving (FSD)
> > SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
> > as well as several IPs.
>
> I'm not thrilled by their naming. Intel does not produce "Intel
> Fastest in world SoC"
If you say so. :)
> , and this chip is not actually suitable for
> autonomous driving :-(.
And AMD's Infinity Fabric isn't.... infinite. Things have names.
That discussion seems off-topic for this patchset. It references a
marketing name used by the company, and as such it makes sense to be
able to cross-reference:
https://www.tesla.com/support/full-self-driving-computer
Tesla seems to have moved away from the initial "Hardware 3" naming
scheme, so using this naming seems as good as any.
-Olof
On Mon, Jan 17, 2022 at 7:00 AM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 17/01/2022 15:14, Arnd Bergmann wrote:
> > On Mon, Jan 17, 2022 at 2:26 PM Alim Akhtar <[email protected]> wrote:
> >>
> >>> I cannot judge how different this is from Exynos subarchitecture - looking at
> >>> patches it is not different - so I could understand a FSD sub-arch with only one
> >>> SoC.
> >>>
> >> I understand, it is a bit difficult to visualize it with the current patch set.
> >> As discuss on the other thread, FSD is different, more over the vendor is different, internal design is different.
> >
> > Is it based on another SoC design then? Most new SoCs are derived from
> > some other
> > one, so it makes sense to put it into the same family. E.g. the Apple
> > M1 takes bits from
> > both Exynos and PA-Semi SoCs but has more newly added components than
> > either one.
I think it's a misnomer to call SoCs like these "based on each other".
What often happens is that a manufacturer reuses IPs between designs
since they're there, they're available and they work and there's
little reason to redo it, etc.
For cases such as a vendor building a custom SoC for a specific
customer (which, from the looks of this patchset seems to be the case
-- this is not something I say with insider information :-), it makes
sense to reuse IP blocks in the same way. It's actually a competitive
benefit of the vendor to have silicon-proven IPs in this manner.
Does this mean that this custom-built product is a part of a product
family? I don't think that's the primary conclusion I would make --
it's more complex than that. And it also doesn't make all that much of
a difference whether it's considered a family member or not. I would
be very surprised if this SoC had a Samsung marketing name, since to
my knowledge it's not sold to any other customer.
If all we're arguing here about is a toplevel compatible and a Kconfig
variable, then I don't see a need to spend a whole lot of time on this
-- as long as it's not a change that ends up proliferating the whole
source tree. I.e. if you want to create a new sub-arch, make sure it
selects or depends on EXYNOS so you don't need to sprinkle a lot of
"EXYNOS" -> "EXYNOS || TESLA" edits in the tree (as per below in the
email).
Same with the DT bindings. Can you just augment to make the tesla
vendor prefix an allowed one for the exynos bindings where it makes
sense? Toplevel board (and SoC) compats can of course still be
independent.
> It seems Apple M1 shares only few bits with SoC. I am aware of only UART
> driver as directly re-usable.
>
> >
> > I would argue that if this SoC shares the pinctrl, clock, spi, adc,
> > and timer implementation
>
> Plus: UART, watchdog, PWM, I2C, I2S, USB PHY, DWC3 USB (in Exynos
> flavor), UFS (also in Exynos-looking flavor), MFC (video codec), some
> similarities in DW PCIe, TMU (thermal). Looking at DTS there are
> differences but just few comparing to most of shared blocks.
>
> Additionally SoC BSP (and maybe SoC itself...) was actually developed or
> co-developed by Samsung, judging by copyrights in the BSP code. Even the
> original DTSI has:
>
> TURBO TRAV SoC device tree source
> Copyright (c) 2017 Samsung Electronics Co., Ltd.
>
>
> Tesla could still customize it a lot, but it is a strong hint that most
> of it came from Samsung LSI and shares with existing Samsung designs.
>
> Have in mind that recent Exynos chips are significantly different than
> early ARMv7 or ARMv8 designs and we still consider them part of Exynos
> family.
>
> > with Exynos, we should consider it part of the Exynos family,
> > regardless of what other
> > blocks may exist next to those.
>
> Yes. I don't see the benefit of keeping it outside of Exynos. It will
> sprinkle "depends on ARCH_EXYNOS || ARCH_FSD" all over (or depend on
> Exynos like you suggested).
Depend or select (but select is a slippery slope so might be better
avoided) seems like a pretty good option here to me.
-Olof
On Mon 2022-01-17 12:53:48, Olof Johansson wrote:
> On Sun, Jan 16, 2022 at 1:23 AM Pavel Machek <[email protected]> wrote:
> >
> > Hi!
> >
> > > This patch set adds basic support for the Tesla Full Self-Driving (FSD)
> > > SoC. This SoC contains three clusters of four Cortex-A72 CPUs,
> > > as well as several IPs.
> >
> > I'm not thrilled by their naming. Intel does not produce "Intel
> > Fastest in world SoC"
>
> If you say so. :)
>
> > , and this chip is not actually suitable for
> > autonomous driving :-(.
>
> And AMD's Infinity Fabric isn't.... infinite. Things have names.
>
> That discussion seems off-topic for this patchset. It references a
> marketing name used by the company, and as such it makes sense to be
> able to cross-reference:
> https://www.tesla.com/support/full-self-driving-computer
>
> Tesla seems to have moved away from the initial "Hardware 3" naming
> scheme, so using this naming seems as good as any.
I'd prefer to call it Tesla HW3. Even wikipedia has that name, no need
to do false advertising for Tesla, and we'll have good names for
HW2.5 and HW4 if it comes out. We normally use codenames, not
marketing names.
Best regards,
Pavel
--
http://www.livejournal.com/~pavelmachek
>-----Original Message-----
>From: Krzysztof Kozlowski [mailto:[email protected]]
>Sent: Monday, January 17, 2022 7:20 PM
>To: Alim Akhtar <[email protected]>; linux-arm-
>[email protected]; [email protected]
>Cc: [email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; linux-samsung-
>[email protected]; [email protected]; [email protected];
>'Shashank Prashar' <[email protected]>; 'Aswani Reddy'
><[email protected]>
>Subject: Re: [PATCH 15/23] arm64: dts: fsd: Add initial pinctrl support
>
>On 17/01/2022 14:44, Alim Akhtar wrote:
>> Hi Krzysztof
>>
>>> -----Original Message-----
>>> From: Krzysztof Kozlowski [mailto:[email protected]]
>>> Sent: Thursday, January 13, 2022 6:50 PM
>>> To: Alim Akhtar <[email protected]>; linux-arm-
>>> [email protected]; [email protected]
>>> Cc: [email protected]; [email protected];
>>> [email protected]; [email protected]; [email protected];
>>> [email protected];
>>> [email protected]; [email protected]; linux-samsung-
>>> [email protected]; [email protected]; [email protected];
>>> Shashank Prashar <[email protected]>; Aswani Reddy
>>> <[email protected]>
>>> Subject: Re: [PATCH 15/23] arm64: dts: fsd: Add initial pinctrl
>>> support
>>>
>>> On 13/01/2022 13:11, Alim Akhtar wrote:
>>>> Add initial pin configuration nodes for FSD SoC.
>>>>
>>>> Cc: [email protected]
>>>> Signed-off-by: Shashank Prashar <[email protected]>
>>>> Signed-off-by: Aswani Reddy <[email protected]>
>>>> Signed-off-by: Alim Akhtar <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 338
>>> +++++++++++++++++++++
>>>> arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++
>>>> 2 files changed, 360 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>>> b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>>> new file mode 100644
>>>> index 000000000000..ec8d944af636
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
>>>> @@ -0,0 +1,338 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>>> + * Tesla Full Self-Driving SoC device tree source
>>>> + *
>>>> + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
>>>> + * https://www.samsung.com
>>>> + * Copyright (c) 2017-2021 Tesla, Inc.
>>>> + * https://www.tesla.com
>>>> + */
>>>> +
>>>> +#include <dt-bindings/pinctrl/samsung.h>
>>>> +
>>>> +&pinctrl_fsys0 {
>>>> +
>>>
>>> No need for empty line.
>>>
>> Noted
>>
>>>> + gpf0: gpf0 {
>>>
>>> FYI:
>>> It's ok now, but the nodes will have to be renamed to "xxx-gpio-bank"
>later.
>>>
>> Have rebased my v2 on your pinmux schema update, so these and below
>comments are addressed.
>> Thanks
>>
>
>OK, but have in mind that -gpio-bank suffix is not needed now. This depends
>on support in the pinctrl driver, which will be applied after the merge window
>to different tree or branches than DTS is going to.
>Therefore if I apply your DTS with "-gpio-bank" to my next/dt64, the kernel
>won't find GPIo banks and won't properly boot. The linux-next will be fine,
>just my next/dt64 won't be.
>
Thanks, got it, for now let me send v2 on linux-next (as of today).
As required I will rebase to your next/dt64 and send again.
Which also means that my v2 will not be based on your new pinmux schema.
Probably we will move to that after the merge window.
>If you're fine with it - use "-gpio-bank" suffix. If you prefer my
>next/dt64 to have a fully working Tesla SoC DTS, then stick to old node naming
>and let's replace it later.
>
>Best regards,
>Krzysztof