2022-10-30 07:34:34

by Marijn Suijten

Subject: [PATCH 02/10] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2

Use the generic pin functions specifically for sdc2.

Signed-off-by: Marijn Suijten <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index a3ae765d9781..b98b881ebe7e 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1074,6 +1074,10 @@ sdhc_2: mmc@8804000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr", "cpu-sdhc";

+ pinctrl-0 = <&sdc2_on_state>;
+ pinctrl-1 = <&sdc2_off_state>;
+ pinctrl-names = "default", "sleep";
+
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM6350_CX>;
@@ -1316,6 +1320,46 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;

+ sdc2_off_state: sdc2-off-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_on_state: sdc2-on-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ drive-strength = <10>;
+ bias-pull-up;
+ };
+ };
+
qup_uart9_default: qup-uart9-default-state {
pins = "gpio25", "gpio26";
function = "qup13_f2";
--
2.38.1

2022-10-31 09:38:11

by Luca Weiss

Subject: Re: [PATCH 02/10] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2

On Sun Oct 30, 2022 at 8:32 AM CET, Marijn Suijten wrote:
> Use the generic pin functions specifically for sdc2.
>
> Signed-off-by: Marijn Suijten <[email protected]>

Reviewed-by: Luca Weiss <[email protected]>
Tested-by: Luca Weiss <[email protected]> # sm7225-fairphone-fp4

Regards
Luca

> ---
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index a3ae765d9781..b98b881ebe7e 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1074,6 +1074,10 @@ sdhc_2: mmc@8804000 {
> <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> interconnect-names = "sdhc-ddr", "cpu-sdhc";
>
> + pinctrl-0 = <&sdc2_on_state>;
> + pinctrl-1 = <&sdc2_off_state>;
> + pinctrl-names = "default", "sleep";
> +
> qcom,dll-config = <0x0007642c>;
> qcom,ddr-config = <0x80040868>;
> power-domains = <&rpmhpd SM6350_CX>;
> @@ -1316,6 +1320,46 @@ tlmm: pinctrl@f100000 {
> #interrupt-cells = <2>;
> gpio-ranges = <&tlmm 0 0 157>;
>
> + sdc2_off_state: sdc2-off-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + sdc2_on_state: sdc2-on-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> + };
> +
> qup_uart9_default: qup-uart9-default-state {
> pins = "gpio25", "gpio26";
> function = "qup13_f2";
> --
> 2.38.1

2022-10-31 21:44:23

by Konrad Dybcio

Subject: Re: [PATCH 02/10] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2

On 30.10.2022 08:32, Marijn Suijten wrote:
> Use the generic pin functions specifically for sdc2.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index a3ae765d9781..b98b881ebe7e 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1074,6 +1074,10 @@ sdhc_2: mmc@8804000 {
> <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> interconnect-names = "sdhc-ddr", "cpu-sdhc";
>
> + pinctrl-0 = <&sdc2_on_state>;
> + pinctrl-1 = <&sdc2_off_state>;
> + pinctrl-names = "default", "sleep";
> +
> qcom,dll-config = <0x0007642c>;
> qcom,ddr-config = <0x80040868>;
> power-domains = <&rpmhpd SM6350_CX>;
> @@ -1316,6 +1320,46 @@ tlmm: pinctrl@f100000 {
> #interrupt-cells = <2>;
> gpio-ranges = <&tlmm 0 0 157>;
>
> + sdc2_off_state: sdc2-off-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + sdc2_on_state: sdc2-on-state {
> + clk-pins {
> + pins = "sdc2_clk";
> + drive-strength = <16>;
> + bias-disable;
> + };
> +
> + cmd-pins {
> + pins = "sdc2_cmd";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> +
> + data-pins {
> + pins = "sdc2_data";
> + drive-strength = <10>;
> + bias-pull-up;
> + };
> + };
> +
> qup_uart9_default: qup-uart9-default-state {
> pins = "gpio25", "gpio26";
> function = "qup13_f2";

2022-11-02 21:12:36

by Krzysztof Kozlowski

Subject: Re: [PATCH 02/10] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2

On 30/10/2022 03:32, Marijn Suijten wrote:
> Use the generic pin functions specifically for sdc2.
>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++


Acked-by: Krzysztof Kozlowski <[email protected]>


Best regards,
Krzysztof