From: Hou Zhiqiang <[email protected]>
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
- compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Biwen Li <[email protected]>
---
drivers/irqchip/irq-ls-extirq.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-ls-extirq.c b/drivers/irqchip/irq-ls-extirq.c
index 4d1179fed77c..564e6de0bd8e 100644
--- a/drivers/irqchip/irq-ls-extirq.c
+++ b/drivers/irqchip/irq-ls-extirq.c
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
+// Copyright 2019-2020 NXP
#define pr_fmt(fmt) "irq-ls-extirq: " fmt
@@ -183,6 +184,9 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent)
priv->bit_reverse = (revcr != 0);
}
+ if (of_device_is_compatible(node, "fsl,ls1043a-extirq"))
+ priv->bit_reverse = true;
+
domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node,
&extirq_domain_ops, priv);
if (!domain)
@@ -195,3 +199,5 @@ ls_extirq_of_init(struct device_node *node, struct device_node *parent)
}
IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq", ls_extirq_of_init);
+IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq", ls_extirq_of_init);
+IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq", ls_extirq_of_init);
--
2.17.1
From: Biwen Li <[email protected]>
Add interrupt line for RTC node on ls208xa-rdb
Signed-off-by: Biwen Li <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
index d0d670227ae2..4b71c4fcb35f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
@@ -3,7 +3,7 @@
* Device Tree file for Freescale LS2080A RDB Board.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini <[email protected]>
*
@@ -56,6 +56,8 @@
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
+ /* IRQ_RTC_B -> IRQ06, active low */
+ interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
From: Biwen Li <[email protected]>
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 27 ++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0246d975a206..dff3ee84c294 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu <[email protected]>
*/
@@ -314,6 +314,31 @@
compatible = "fsl,ls1046a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1570000 0x10000>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
};
crypto: crypto@1700000 {
--
2.17.1
From: Biwen Li <[email protected]>
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e1..f75aa2ce4e2b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini <[email protected]>
*
@@ -154,6 +154,37 @@
little-endian;
};
+ isc: syscon@1f70000 {
+ compatible = "fsl,ls2080a-isc", "syscon";
+ reg = <0x0 0x1f70000 0x0 0x10000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f70000 0x10000>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
+ };
+
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
--
2.17.1
From: Biwen Li <[email protected]>
Fix interrupt line for RTC node on lx2160ardb
Signed-off-by: Biwen Li <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 54fe8cd3a711..f3bab76797fb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -2,7 +2,7 @@
//
// Device Tree file for LX2160ARDB
//
-// Copyright 2018 NXP
+// Copyright 2018-2020 NXP
/dts-v1/;
@@ -151,8 +151,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
- // IRQ10_B
- interrupts = <0 150 0x4>;
+ /* IRQ_RTC_B -> IRQ08, active low */
+ interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
On 2020-10-26 09:06, Rasmus Villemoes wrote:
> On 26/10/2020 09.44, Marc Zyngier wrote:
>> On 2020-10-26 08:01, Biwen Li wrote:
>>> From: Hou Zhiqiang <[email protected]>
>>>
>>> Add an new IRQ chip declaration for LS1043A and LS1088A
>>> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
>>> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
>>
>> Three things:
>> - This commit message doesn't describe the bit_reverse change
>
> Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't
> mention anything about bit reversal for the scfg registers - they don't
> seem to have the utter nonsense that is SCFG_SCFGREVCR, but perhaps,
> instead of removing it, that has just become a hard-coded part of the
> IP.
>
> Also, IANAL etc., but
>
>>> +// Copyright 2019-2020 NXP
>
> really? Seems to be a bit of a stretch.
>
> At the very least, cc'ing the original author and only person to ever
> touch that file would have been appreciated.
Huh. Well spotted. That's definitely not on.
NXP people, please talk to your legal department.
M.
--
Jazz is not dead. It just smells funny...
From: Biwen Li <[email protected]>
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 27 ++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 5c2e370f6316..38a6d951ecc5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
* Mingkai Hu <[email protected]>
*/
@@ -311,6 +311,31 @@
compatible = "fsl,ls1043a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1570000 0x10000>;
+
+ extirq: interrupt-controller@1ac {
+ compatible = "fsl,ls1043a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1ac 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
};
crypto: crypto@1700000 {
--
2.17.1
From: Hou Zhiqiang <[email protected]>
Add interrupt line for RTC node, which is low level active.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index d53ccc56bb63..60acdf0b689e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2019-2020 NXP
*
* Mingkai Hu <[email protected]>
*/
@@ -74,6 +75,8 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
+ /* IRQ_RTC_B -> IRQ05, active low */
+ interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.17.1
From: Biwen Li <[email protected]>
Update bindings for Layerscape external irqs,
support more SoCs(LS1043A, LS1046A, LS1088A,
LS208xA, LX216xA)
Signed-off-by: Biwen Li <[email protected]>
---
.../bindings/interrupt-controller/fsl,ls-extirq.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
index f0ad7801e8cf..90ef8917ac02 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt
@@ -1,6 +1,7 @@
* Freescale Layerscape external IRQs
-Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting
+Some Layerscape SOCs (LS1021A, LS1043A, LS1046A
+LS1088A, LS208xA, LX216xA) support inverting
the polarity of certain external interrupt lines.
The device node must be a child of the node representing the
@@ -8,12 +9,16 @@ Supplemental Configuration Unit (SCFG).
Required properties:
- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
+ "fsl,ls1043a-extirq": for LS1043A, LS1046A.
+ "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
+
- #interrupt-cells: Must be 2. The first element is the index of the
external interrupt line. The second element is the trigger type.
- #address-cells: Must be 0.
- interrupt-controller: Identifies the node as an interrupt controller
- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
- the SCFG.
+ the SCFG or the External Interrupt Control Register (IRQCR) in
+ the ISC.
- interrupt-map: Specifies the mapping from external interrupts to GIC
interrupts.
- interrupt-map-mask: Must be <0xffffffff 0>.
--
2.17.1
From: Biwen Li <[email protected]>
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 33 ++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 169f4742ae3b..12fe8f079c28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1088A family SoC.
*
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Harninder Rai <[email protected]>
*
@@ -206,6 +206,37 @@
little-endian;
};
+ isc: syscon@1f70000 {
+ compatible = "fsl,ls1088a-isc", "syscon";
+ reg = <0x0 0x1f70000 0x0 0x10000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f70000 0x10000>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
+ };
+
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
--
2.17.1
On 2020-10-26 08:01, Biwen Li wrote:
> From: Hou Zhiqiang <[email protected]>
>
> Add an new IRQ chip declaration for LS1043A and LS1088A
> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
Three things:
- This commit message doesn't describe the bit_reverse change
- Please add a cover letter
- Sending the same series again after 4 days is not OK, specially when
the initial one was during the merge window.
Thanks,
M.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
> Signed-off-by: Biwen Li <[email protected]>
> ---
> drivers/irqchip/irq-ls-extirq.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/irqchip/irq-ls-extirq.c
> b/drivers/irqchip/irq-ls-extirq.c
> index 4d1179fed77c..564e6de0bd8e 100644
> --- a/drivers/irqchip/irq-ls-extirq.c
> +++ b/drivers/irqchip/irq-ls-extirq.c
> @@ -1,4 +1,5 @@
> // SPDX-License-Identifier: GPL-2.0
> +// Copyright 2019-2020 NXP
>
> #define pr_fmt(fmt) "irq-ls-extirq: " fmt
>
> @@ -183,6 +184,9 @@ ls_extirq_of_init(struct device_node *node, struct
> device_node *parent)
> priv->bit_reverse = (revcr != 0);
> }
>
> + if (of_device_is_compatible(node, "fsl,ls1043a-extirq"))
> + priv->bit_reverse = true;
> +
> domain = irq_domain_add_hierarchy(parent_domain, 0, priv->nirq, node,
> &extirq_domain_ops, priv);
> if (!domain)
> @@ -195,3 +199,5 @@ ls_extirq_of_init(struct device_node *node, struct
> device_node *parent)
> }
>
> IRQCHIP_DECLARE(ls1021a_extirq, "fsl,ls1021a-extirq",
> ls_extirq_of_init);
> +IRQCHIP_DECLARE(ls1043a_extirq, "fsl,ls1043a-extirq",
> ls_extirq_of_init);
> +IRQCHIP_DECLARE(ls1088a_extirq, "fsl,ls1088a-extirq",
> ls_extirq_of_init);
--
Jazz is not dead. It just smells funny...
On 26/10/2020 09.44, Marc Zyngier wrote:
> On 2020-10-26 08:01, Biwen Li wrote:
>> From: Hou Zhiqiang <[email protected]>
>>
>> Add an new IRQ chip declaration for LS1043A and LS1088A
>> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
>> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
>
> Three things:
> - This commit message doesn't describe the bit_reverse change
Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't
mention anything about bit reversal for the scfg registers - they don't
seem to have the utter nonsense that is SCFG_SCFGREVCR, but perhaps,
instead of removing it, that has just become a hard-coded part of the IP.
Also, IANAL etc., but
>> +// Copyright 2019-2020 NXP
really? Seems to be a bit of a stretch.
At the very least, cc'ing the original author and only person to ever
touch that file would have been appreciated.
Rasmus
On 2020-10-26 15:06, Leo Li wrote:
>> -----Original Message-----
>> From: Marc Zyngier <[email protected]>
>> Sent: Monday, October 26, 2020 4:23 AM
>> To: Rasmus Villemoes <[email protected]>
>> Cc: Biwen Li (OSS) <[email protected]>; [email protected];
>> [email protected]; [email protected]; Leo Li <[email protected]>;
>> Z.q. Hou <[email protected]>; [email protected];
>> [email protected]; [email protected]; linux-
>> [email protected]; Jiafei Pan <[email protected]>; Xiaobo Xie
>> <[email protected]>; [email protected]; Biwen Li
>> <[email protected]>
>> Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A
>> external
>> interrupt
>>
>> On 2020-10-26 09:06, Rasmus Villemoes wrote:
>> > On 26/10/2020 09.44, Marc Zyngier wrote:
>> >> On 2020-10-26 08:01, Biwen Li wrote:
>> >>> From: Hou Zhiqiang <[email protected]>
>> >>>
>> >>> Add an new IRQ chip declaration for LS1043A and LS1088A
>> >>> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
>> >>> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
>> >>
>> >> Three things:
>> >> - This commit message doesn't describe the bit_reverse change
>> >
>> > Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't
>> > mention anything about bit reversal for the scfg registers - they
>> > don't seem to have the utter nonsense that is SCFG_SCFGREVCR, but
>> > perhaps, instead of removing it, that has just become a hard-coded
>> > part of the IP.
>> >
>> > Also, IANAL etc., but
>> >
>> >>> +// Copyright 2019-2020 NXP
>> >
>> > really? Seems to be a bit of a stretch.
>> >
>> > At the very least, cc'ing the original author and only person to ever
>> > touch that file would have been appreciated.
>>
>> Huh. Well spotted. That's definitely not on.
>> NXP people, please talk to your legal department.
>
> We do have an internal policy to require developer adding/updating NXP
> copyright on non-trivial changes. I'm not sure if this change should
> be considered trivial, but adding copyright claim on a file without
> prior copyright claims could causing confusion like in this case.
The copyright exists implicitly, and doesn't require a copyright claim
in the file itself. Please talk to your legal department.
> One
> potential solution is to add a more specific description on the NXP
> change together with the copyright claim. But maybe an easier
> solution is to add Rasmus your Copyright claim first if you are ok
> with it.
That's for Rasmus to decide whether he wants to add such a claim,
given that it exists implicitly. Adding copyright claims for any
odd change you make isn't acceptable either (your changes are already
unambiguously identified in git).
For the time being, I'm not taking any NXP patch carrying additional
copyright update until this is clarified.
M.
--
Jazz is not dead. It just smells funny...
> -----Original Message-----
> From: Marc Zyngier <[email protected]>
> Sent: Monday, October 26, 2020 4:23 AM
> To: Rasmus Villemoes <[email protected]>
> Cc: Biwen Li (OSS) <[email protected]>; [email protected];
> [email protected]; [email protected]; Leo Li <[email protected]>;
> Z.q. Hou <[email protected]>; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]; Jiafei Pan <[email protected]>; Xiaobo Xie
> <[email protected]>; [email protected]; Biwen Li
> <[email protected]>
> Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
> interrupt
>
> On 2020-10-26 09:06, Rasmus Villemoes wrote:
> > On 26/10/2020 09.44, Marc Zyngier wrote:
> >> On 2020-10-26 08:01, Biwen Li wrote:
> >>> From: Hou Zhiqiang <[email protected]>
> >>>
> >>> Add an new IRQ chip declaration for LS1043A and LS1088A
> >>> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
> >>> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
> >>
> >> Three things:
> >> - This commit message doesn't describe the bit_reverse change
> >
> > Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't
> > mention anything about bit reversal for the scfg registers - they
> > don't seem to have the utter nonsense that is SCFG_SCFGREVCR, but
> > perhaps, instead of removing it, that has just become a hard-coded
> > part of the IP.
> >
> > Also, IANAL etc., but
> >
> >>> +// Copyright 2019-2020 NXP
> >
> > really? Seems to be a bit of a stretch.
> >
> > At the very least, cc'ing the original author and only person to ever
> > touch that file would have been appreciated.
>
> Huh. Well spotted. That's definitely not on.
> NXP people, please talk to your legal department.
We do have an internal policy to require developer adding/updating NXP copyright on non-trivial changes. I'm not sure if this change should be considered trivial, but adding copyright claim on a file without prior copyright claims could causing confusion like in this case. One potential solution is to add a more specific description on the NXP change together with the copyright claim. But maybe an easier solution is to add Rasmus your Copyright claim first if you are ok with it.
Regards,
Leo
> > -----Original Message-----
> > From: Marc Zyngier <[email protected]>
> > Sent: Monday, October 26, 2020 4:23 AM
> > To: Rasmus Villemoes <[email protected]>
> > Cc: Biwen Li (OSS) <[email protected]>; [email protected];
> > [email protected]; [email protected]; Leo Li <[email protected]>;
> > Z.q. Hou <[email protected]>; [email protected];
> > [email protected]; [email protected]; linux-
> > [email protected]; Jiafei Pan <[email protected]>; Xiaobo Xie
> > <[email protected]>; [email protected]; Biwen Li
> > <[email protected]>
> > Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A
> > external interrupt
> >
> > On 2020-10-26 09:06, Rasmus Villemoes wrote:
> > > On 26/10/2020 09.44, Marc Zyngier wrote:
> > >> On 2020-10-26 08:01, Biwen Li wrote:
> > >>> From: Hou Zhiqiang <[email protected]>
> > >>>
> > >>> Add an new IRQ chip declaration for LS1043A and LS1088A
> > >>> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
> > >>> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
> > >>
> > >> Three things:
> > >> - This commit message doesn't describe the bit_reverse change
> > >
> > > Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't
> > > mention anything about bit reversal for the scfg registers - they
> > > don't seem to have the utter nonsense that is SCFG_SCFGREVCR, but
> > > perhaps, instead of removing it, that has just become a hard-coded
> > > part of the IP.
> > >
> > > Also, IANAL etc., but
> > >
> > >>> +// Copyright 2019-2020 NXP
> > >
> > > really? Seems to be a bit of a stretch.
> > >
> > > At the very least, cc'ing the original author and only person to
> > > ever touch that file would have been appreciated.
> >
> > Huh. Well spotted. That's definitely not on.
> > NXP people, please talk to your legal department.
>
> We do have an internal policy to require developer adding/updating NXP
> copyright on non-trivial changes. I'm not sure if this change should be
> considered trivial, but adding copyright claim on a file without prior copyright
> claims could causing confusion like in this case. One potential solution is to
> add a more specific description on the NXP change together with the copyright
> claim. But maybe an easier solution is to add Rasmus your Copyright claim
> first if you are ok with it.
Yes, added a wrong Copyright.
>
> Regards,
> Leo
> Subject: Re: [RESEND 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A external
> interrupt
>
> On 26/10/2020 09.44, Marc Zyngier wrote:
> > On 2020-10-26 08:01, Biwen Li wrote:
> >> From: Hou Zhiqiang <[email protected]>
> >>
> >> Add an new IRQ chip declaration for LS1043A and LS1088A
> >> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A
> >> - compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
> >
> > Three things:
> > - This commit message doesn't describe the bit_reverse change
>
> Yeah, please elaborate on that, as the RM for 1043 or 1046 doesn't mention
> anything about bit reversal for the scfg registers - they don't seem to have the
> utter nonsense that is SCFG_SCFGREVCR, but perhaps, instead of removing it,
> that has just become a hard-coded part of the IP.
Yeah, you are right, I will update it in v2.
>
> Also, IANAL etc., but
>
> >> +// Copyright 2019-2020 NXP
>
> really? Seems to be a bit of a stretch.
>
> At the very least, cc'ing the original author and only person to ever touch that
> file would have been appreciated.
Okay, it's my fault, I will update it, thanks.
>
> Rasmus